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L9950 L9950XP
Door actuator driver
Features

One full bridge for 6A load (Ron=150 m ) Two half bridges for 3A load (Ron=300 m ) Two half bridges for 1.5A load (Ron=800 m ) One highside driver for 6A load (Ron=100 m ) Four highside drivers for 1.5 A load (Ron=800 m ) Programmable softstart function to drive loads with higher inrush currents (i.e. current >6 A,>3 A,>1.5 A) Very low current consumption in standby mode (IS < 6 A typ; ICC <25 A typ; Tj 85 C) All outputs short circuit protected Current monitor output for 300 m, 150 m and 100 m highside drivers All outputs over temperature protected Open load diagnostic for all outputs Overload diagnostic for all outputs Seperated half bridges for door lock motor PWM control of all outputs Charge pump output for reverse polarity protection
PowerSO-36
PowerSSO-36
Applications

Door actuator driver with bridges for door lock and safe lock, mirror axis control, mirror fold and highside driver for mirror defroster and four 10W-light bulbs.
Description
The L9950 and L9950XP are microcontroller driven multifunctional door actuator driver for automotive applications.Up to five DC motors and five grounded resistive loads can be driven with six half bridges and five highside drivers. The integrated standard serial peripheral interface (SPI) controls all operation modes (forward, reverse, brake and high impedance). All diagnostic informations are available via SPI.
Table 1.
Device summary
Order codes Package Part number (tube) PowerSO-36 PowerSSO-36 L9950 L9950XP Part number (tape and reel) L9950TR L9950XPTR
June 2009
Doc ID 10311 Rev 10
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www.st.com 1
Contents
L9950 - L9950XP
Contents
1 2 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 2.2 2.3 2.4 2.5 2.6 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 10 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 SPI - electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 Dual power supply: VS and VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Inductive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Diagnostic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Overvoltage and under voltage detection . . . . . . . . . . . . . . . . . . . . . . . . . 21 Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 21 Open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Over load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Current monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 PWM inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Cross current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Programmable soft start function to drive loads with higher inrush current . 22
4
Functional description of the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.1 4.2 4.3 4.4 4.5 4.6 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Chip Select Not (CSN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Serial Data In (DI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Serial Data Out (DO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Serial clock (CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Input data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
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Contents
4.7 4.8
Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5 6
Packages thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.1 6.2 6.3 6.4 6.5 ECOPACK(R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 PowerSO-36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 PowerSSO-36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 PowerSO-36 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 PowerSSO-36 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
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List of tables
L9950 - L9950XP
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Overvoltage and under voltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Current monitor output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Charge pump output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 OUT1 - OUT11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Delay time from standby to active mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Inputs: CSN, CLK, PWM1/2 and DI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 DI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 DO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 DO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 CSN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 SPI - input data and status registers 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 SPI - input data and status registers 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 PowerSO-36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 PowerSSO-36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
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List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 SPI - transfer timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 SPI - input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 SPI - DO valid data delay time and valid time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 SPI - DO enable and disable time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 SPI - driver turn-on/off timing, minimum csn hi time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 SPI - timing of status bit 0 (fault condition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Example of programmable soft start function for inductive loads . . . . . . . . . . . . . . . . . . . . 23 Packages thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 PowerSO-36 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 PowerSSO-36 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 PowerSO-36 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 PowerSO-36 tape and reel shipment (suffix "TR") . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 PowerSSO-36 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 PowerSSO-36 tape and reel shipment (suffix "TR") . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
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Block diagram and pin description
L9950 - L9950XP
1
Block diagram and pin description
Figure 1. Block diagram
Reverse Polarity Protection VBAT
* Note: Value of capacitor has to be choosen carefully to limit the VS voltage below absolute maximum ratings in case of an unexpected freewheeling condition of inductive loads (e.g. TSD, POR)
100k
*
VREG
100F 100nF
EMC Optimization
VS
CP OUT1
10k
xy-Mirror Motors M M M Lock Safe Lock M Folder M Exterior Light Footstep Light Safety Light Turn Indicator Defroster
VCC
100
Charge Pump
VCC
OUT2 OUT3
+ 10
100nF
Driver Interface & Diagnostic
OUT4 OUT5 OUT6
SPI Interface
** 1k ** 1k ** 1k ** 1k **1k
DI DO CLK CSN
OUT7 OUT8 OUT9 OUT10 OUT11
PWM1
C
**1k
CM / PWM2
MUX
5 GND ** Note: Resistors between C and L9950 are recommended to limit currents
for negative voltage transients at VBAT (e.g. ISO type 1 pulse) + Note: Using a ferrite instead of 10ohm will additionally improve EMC behavior
Table 2.
Pin
Pin definitions and functions
Symbol Function Ground. Reference potential. Important: for the capability of driving the full current at the outputs all pins of GND must be externally connected. Highside driver output 11. The output is built by a highside switch and is intended for resistive loads, hence the internal reverse diode from GND to the output is missing. For ESD reason a diode to GND is present but the energy which can be dissipated is limited. The highside driver is a power DMOS transistor with an internal parasitic reverse diode from the output to VS (bulk-drain-diode). The output is over-current and open load protected. Important: for the capability of driving the full current at the outputs both pins of OUT11 must be externally connected.
1, 18, 19, 36
GND
2, 35
OUT11
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L9950 - L9950XP Table 2.
Pin
Block diagram and pin description Pin definitions and functions (continued)
Symbol Function Hal bridge output 1,2,3. The output is built by a highside and a lowside switch, which are internally connected. The output stage of both switches is a power DMOS transistor. Each driver has an internal parasitic reverse diode (bulk-drain-diode: highside driver from output to VS, lowside driver from GND to output). This output is over-current and open load protected. Power supply voltage (external reverse protection required. For this input a ceramic capacitor as close as possible to GND is recommended. Important: for the capability of driving the full current at the outputs all pins of VS must be externally connected. Serial data input. The input requires CMOS logic levels and receives serial data from the microcontroller. The data is an 24bit control word and the least significant bit (LSB, bit 0) is transferred first.
3 4 5
OUT1 OUT2 OUT3
6, 7, 14, 15, 23, 24, 25, 28, 29, 32
VS
8
DI
9
Current monitor output/PWM2 input. Depending on the selected multiplexer bits of Input Data Register this output sources an image of the instant current through the CM/PWM2 corresponding highside driver with a ratio of 1/10.000. This pin is bidirectional. The microcontroller can overdrive the current monitor signal to provide a second PWM input for the outputs OUT9 and OUT10. Chip select not input/test mode. This input is low active and requires CMOS logic levels. The serial data transfer between L9950 and micro controller is enabled by pulling the input CSN to low level. If an input voltage of more than 7.5V is applied to CSN pin the L9950 will be switched into a test mode. Serial data output. The diagnosis data is available via the SPI and this tristate output. The output will remain in tristate, if the chip is not selected by the input CSN (CSN = high). Logic supply voltage. For this input a ceramic capacitor as close as possible to GND is recommended. Serial clock input. This input controls the internal shift register of the SPI and requires CMOS logic levels. Half bridge output 4,5,6: see OUT1 (pin 3). Important: for the capability of driving the full current at the outputs both pins of OUT4 (OUT5, respectively) must be externally connected. Charge pump output. This output is provided to drive the gate of an external n-channel power MOS used for reverse polarity protection
10
CSN
11
DO
12
VCC
13
CLK OUT4 OUT5 OUT6 CP
16,17, 20,21, 22
26
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Block diagram and pin description Table 2.
Pin
L9950 - L9950XP
Pin definitions and functions (continued)
Symbol Function PWM1 input. This input signal can be used to control the drivers OUT1-OUT8 and OUT11 by an external PWM signal. Highside driver output 7,8,9,10. The output is built by a highside switch and is intended for resistive loads, hence the internal reverse diode from GND to the output is missing. For ESD reason a diode to GND is present but the energy which can be dissipated is limited. The highside driver is a power DMOS transistor with an internal parasitic reverse diode from the output to VS (bulk-drain-diode). The output is over-current and open load protected.
27
PWM1
30 31 33 34
OUT7, OUT8, OUT9, OUT10
Figure 2.
Configuration diagram (top view)
GND 1 OUT11 2 OUT1 3 OUT2 4 OUT3 5 VS 6 VS 7 DI 8 CM/PWM2 9 CSN 10 DO 11 VCC 12 CLK 13 VS 14 VS 15 OUT4 16 OUT4 17 GND 18
36 GND
Power SO36
35 OUT11 34 OUT10 33 OUT9 32 VS 31 OUT8 30 OUT7 29 VS
Chip
28 VS 27 PWM1 26 CP 25 VS 24 VS 23 VS 22 OUT6 21 OUT5 20 OUT5 19 GND
Leadframe
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Electrical specifications
2
2.1
Electrical specifications
Absolute maximum ratings
Stressing the device above the rating listed in the "Absolute maximum ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality document. Table 3. Absolute maximum ratings
Symbol VS VCC VDI, VDO, VCLK, VCSN, Vpwm1 VCM VCP IOUT1,2,3,6,7,8,9,10 IOUT4,5,11 Parameter DC supply voltage Single pulse tmax < 400 ms Stabilized supply voltage, logic supply Digital input/output voltage Current monitor output Charge pump output Output current Output current Value -0.3 to 28 40 -0.3 to 5.5 -0.3 to VCC + 0.3 -0.3 to VCC + 0.3 -25 to VS + 11 5 10 Unit V V V V V V A A
2.2
ESD protection
Table 4. ESD protection
Parameter All pins Output pins: OUT1 - OUT11
1. HBM according to CDF-AEC-Q100-002. 2. HBM with all unzapped pins grounded.
Value 4 (1) 8
(2)
Unit kV kV
2.3
Thermal data
Table 5.
Symbol Tj
Thermal data
Parameter Operating junction temperature Value -40 to 150 Unit C
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Electrical specifications
L9950 - L9950XP
2.4
Temperature warning and thermal shutdown
Table 6.
Symbol TjTW ON TjTW OFF
Temperature warning and thermal shutdown
Parameter Temperature warning threshold junction temperature Temperature warning threshold junction temperature Tj increasing Tj decreasing Min. 130 Tj increasing Tj decreasing 150 Typ. 5 5 Max. 150 170 Unit C C K C C K
TjTW HYS Temperature warning hysteresis TjSD ON TjSD OFF Thermal shutdown threshold junction temperature Thermal shutdown threshold junction temperature
TjSD HYS Thermal shutdown hysteresis
2.5
Electrical characteristics
VS = 8 to 16 V, VCC = 4.5 to 5.3 V, Tj = - 40 to 150 C, unless otherwise specified. The voltages are referred to GND and currents are assumed positive, when the current flows into the pin. Table 7.
Symbol VS
Supply
Parameter Operating supply voltage range VS DC supply current VS = 16 V, VCC = 5.3 V active mode OUT1 - OUT11 floating VS = 16 V, VCC = 0 V standby mode OUT1 - OUT11 floating Ttest =-40 C, 25 C VS = 16 V, VCC = 5.3 V CSN = VCC , active mode VS = 16 V, VCC = 5.3 V CSN = VCCstandby mode OUT1 - OUT11 floating Ttest =-40 C, 25 C VS = 16 V, VCC = 5.3 V CSN = VCC standby mode OUT1 - OUT11 floating Ttest =-40 C, 25 C Test condition Min. 7 Typ. Max. 28 Unit V
-
7
20
mA
IS VS quiescent supply current
-
4
12
A
VCC DC supply current ICC
-
1
3
mA
VCC quiescent supply current
-
25
50
A
IS + ICC
Sum quiescent supply current
-
31
75
A
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L9950 - L9950XP Table 8.
Symbol
Electrical specifications Overvoltage and under voltage detection
Parameter Test condition VS increasing VS decreasing VSUV ON - VSUV OFF VS increasing VS decreasing VSOV OFF - VSOV ON VCC increasing VCC decreasing VPOR OFF - VPOR ON Min. 5.9 5.5 18 17.5 3.1 Typ. 0.5 1 0.3 Max. 7.2 6.5 24.5 22 4.4 Unit V V V V V V V V V
VSUV ON VS UV-threshold voltage VSUV OFF VS UV-threshold voltage VSUV hyst VS UV-hysteresis VSOV OFF VS OV-threshold voltage VSOV ON VS OV-threshold voltage VSOV hyst VS OV-hysteresis VPOR OFF Power-on-reset threshold VPOR ON Power-on-reset threshold VPOR hyst Power-on-reset hysteresis
Table 9.
Symbol VCM ICM,r
Current monitor output
Parameter Test condition Min. 0 1----------------10.000 Typ. Max. 4 Unit V -
Functional voltage range VCC = 5 V Current monitor output ratio: ICM / IOUT1,4,5,6,11 0 V VCM 4 V, VCC=5 V
ICM acc
0 V VCM 3.8 V, VCC = 5 V, IOut,min=500 mA, Current monitor accuracy IOut4,5,11,max = 5.9 A IOut1,6,max = 2.9 A (FS = full scale= 600 A)
-
4% + 1%FS
8% + 2%FS
-
Table 10.
Symbol
Charge pump output
Parameter Charge pump output voltage Charge pump output current Test condition VS = 8 V, ICP = -60 A Min. 6 8 10 95 Typ. 150 Max. 13 13 13 300 Unit V V V A
VCP
VS = 10 V, ICP = -80 A VS 12 V, ICP = -100 A
ICP
VCP = VS+10 V, VS =13.5 V
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Electrical specifications Table 11.
Symbol
L9950 - L9950XP
OUT1 - OUT11
Parameter Test condition VS = 13.5 V, Tj = 25 C, IOUT1,6 = 1.5A Min. 3 1.5 6 Typ. 300 450 300 800 1250 800 150 225 150 800 1250 800 100 150 100 Max. 400 600 400 1100 1700 1100 200 300 200 1100 1700 1100 150 200 150 5 2.5 10 Unit m m m m m m m m m m m m m m m A A A
rON OUT1, rON OUT6
On-resistance to supply or GND
VS = 13.5 V, Tj = 125 C, IOUT1,6 = 1.5 A VS = 8.0 V, Tj = 25 C, IOUT1,6 = 1.5 A VS = 13.5 V, Tj = 25 C, IOUT2,3 = 0.8A
rON OUT2, rON OUT3
On-resistance to supply or GND
VS = 13.5 V, Tj = 125 C, IOUT2,3 = 0.8 A VS = 8.0 V, Tj = 25 C, IOUT2,3 = 0.8 A VS = 13.5 V, Tj = 25 C, IOUT4,5 = 3.0 A
rON OUT4, rON OUT5
On-resistance to supply or GND
VS = 13.5 V, Tj = 125 C, IOUT4,5 = 3.0 A VS = 8.0 V, Tj = 25 C, IOUT4,5 = 3.0 A VS = 13.5 V, Tj = 25 C, IOUT7,8,9,10 = -0.8 A
rON OUT7, rON OUT8, rON OUT9 , rON OUT10
On-resistance to supply
VS = 13.5 V, Tj = 125 C, IOUT7,8,9,10 = -0.8 A VS = 8.0 V, Tj = 25 C, IOUT7,8,9,10 = -0.8 A VS = 13.5 V, Tj = 25 C, IOUT11 = - 3.0 A
rON OUT11
On-resistance to supply
VS = 13.5 V, Tj = 125 C, IOUT11 = - 3.0A VS = 8.0 V, Tj = 25 C, IOUT11 = - 3.0 A
|IOUT1|, |IOUT6| |IOUT2|, |IOUT3| |IOUT4|, |IOUT5| |IOUT7|, |IOUT8|, |IOUT9|, |IOUT10|
Output current limitation to supply or GND Output current limitation to supply or GND Output current limitation to supply or GND Output current limitation to GND
Sink and source, VS=13.5V Sink and source, VS = 13.5V Sink and source, VS = 13.5V
Source, VS = 13.5V
1.5
-
2.5
A
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L9950 - L9950XP Table 11.
Symbol |IOUT11|
Electrical specifications OUT1 - OUT11 (continued)
Parameter Output current limitation to GND Output delay time, highside driver on Output delay time, highside driver off Output delay time, lowside driver on Output delay time, lowside driver off Test condition Source, VS = 13.5V VS = 13.5 V, corresponding lowside driver is not active VS = 13.5 V VS = 13.5 V, corresponding highside driver is not active VS = 13.5 V Min. 6 Typ. Max. 10 Unit A
td ON H
20
40
80
s
td OFF H
50
150
300
s
td ON L
15
30
70
s
td OFF L tD HL tD LH
80 0 -40 0 -40 5 15 60 30
150 200 200 -2 -15 110 -15 30 40 150 70
300 400 400 -5 0 180 0 80 60 300 150
s s s A A A A mA mA mA mA
Cross current protection time, td ON L - td OFF H, source to sink Cross current protection time, td ON H - td OFF L sink to source VOUT1-11=0 V, standby mode VOUT1-11=0 V, active mode VOUT1-6 = VS, standby mode VOUT1-6 = VS, active mode
IQLH
Switched-off output current highside drivers of OUT1-11
IQLL
Switched-off output current lowside drivers of OUT1-6 Open load detection current of OUT1 Open load detection current of OUT2, OUT3 Open load detection current of OUT4 and OUT5 Open load detection current of OUT6 Open load detection current of OUT7, OUT8, OUT9, OUT10 Open load detection current of OUT11 Minimum duration of open load condition to set the status bit Minimum duration of overcurrent condition to switch off the driver
IOLD1 IOLD23 IOLD45 IOLD6
IOLD78910
15
40
60
mA
IOLD11
30
150
300
mA
tdOL
500
-
3000
s
tISC
10
-
100
s
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Electrical specifications Table 11.
Symbol
L9950 - L9950XP
OUT1 - OUT11 (continued)
Parameter Test condition VS =13.5 V Iload = 1.5 A VS = 13.5 V Iload = -0.8 A VS = 13.5 V Iload = 3.0 A VS = 13.5 V Iload = 3.0 A Min. 0.1 0.09 0.1 0.1 Typ. 0.2 0.2 0.2 0.2 Max. 0.4 0.4 0.4 0.4 Unit V/s V/s V/s V/s
dVOUT16/dt Slew rate of OUT1,OUT6 dVOUT23/dt, Slew rate of OUT2/3 and dVOUT78910/dt OUT7-OUT10 dVOUT45/dt Slew rate of OUT4, OUT5 dVOUT11/dt Slew rate of OUT11
2.6
SPI - electrical characteristics
VS = 8 to 16 V, VCC = 4.5 to 5.3 V, Tj = - 40 to 150 C, unless otherwise specified. The voltages are referred to GND and currents are assumed positive, when the current flows into the pin. Table 12.
Symbol tset
Delay time from standby to active mode
Parameter Delay time Test condition Switching from standby to active mode. Time until output drivers are enabled after CSN going to high. Min. Typ. 160 Max. 300 Unit s
Table 13.
Symbol VinL VinH VinHyst ICSN in ICLK in IDI in IPWM1 in Cin
Inputs: CSN, CLK, PWM1/2 and DI
Parameter Input low level Input high level Input hysteresis Pull up current at input CSN Pull down current at input CLK Pull down current at input DI Pull down current at input PWM1 Input capacitance at input CSN, CLK, DI and PWM1/2 Test condition VCC = 5 V VCC = 5 V VCC = 5 V VCSN = 3.5 V VCC = 5 V VCLK = 1.5 V VDI = 1.5 V VPWM = 1.5 V VCC = 0 to 5.3 V Min. 1.5 0.5 -40 10 10 10 Typ. 2.0 3.0 -20 25 25 25 10 Max. 3.5 -8 50 50 50 15 Unit V V V A A A A pF
Note:
Value of input capacity is not measured in production test. Parameter guaranteed by design.
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L9950 - L9950XP Table 14.
Symbol tCLK tCLKH tCLKL tset CSN tset CLK tset DI thold time tr in tf in
Electrical specifications DI timing
Parameter Clock period Clock high time Clock low time CSN setup time, CSN low before rising edge of CLK CLK setup time, CLK high before rising edge of CSN DI setup time DI hold time Rise time of input signal DI, CLK, CSN Fall time of input signal DI, CLK, CSN Test condition VCC = 5 V VCC = 5 V VCC = 5 V VCC = 5 V VCC = 5 V VCC = 5 V VCC = 5 V VCC = 5 V VCC = 5 V Min. 1000 400 400 400 400 200 200 Typ. Max. 100 100 Unit ns ns ns ns ns ns ns ns ns
Note:
DI timing parameters tested in production by a passed/failed test: Tj=-40 C/+25 C: SPI communication @2 MHZ. Tj=+125 C: SPI communication @1.25 MHZ. Table 15.
Symbol VDOL VDOH IDOLK CDO(1)
DO
Parameter Output low level Output high level Tristate leakage current Tristate input capacitance Test condition VCC = 5 V, ID = -2 mA VCC = 5 V, ID = 2 mA VCSN = VCC, 0 V < VDO < VCC VCSN = VCC, 0 V < VCC < 5.3 V Min. Typ. 0.2 Max. 0.4 10 15 Unit V V A pF
VCC -0.4 VCC-0.2 -10 10
1. Value of input capacity is not measured in production test. Parameter guaranteed by design.
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Electrical specifications Table 16.
Symbol tr DO tf DO ten DO tri L tdis DO L tri ten DO tri H tdis DO H tri td DO
L9950 - L9950XP
DO timing
Parameter DO rise time DO fall time DO enable time from tristate to low level DO disable time from low level to tristate Test condition CL = 100 pF, Iload = -1 mA CL = 100 pF, Iload = 1 mA CL = 100 pF, Iload = 1 mA pull-up load to VCC CL = 100 pF, Iload = 4 mA pull-up load to VCC Min. Typ. 80 50 100 380 100 380 50 Max. Unit 140 100 250 450 250 450 250 ns ns ns ns ns ns ns
DO enable time CL =100 pF, Iload = -1 mA from tristate to high level pull-down load to GND DO disable time CL = 100 pF, Iload = -4 mA from high level to tristate pull-down load to GND DO delay time VDO < 0.3 VCC, VDO > 0.7 VCC, CL = 100 pF
Table 17.
Symbol tCSN_HI,stb tCSN_HI,min
CSN timing
Parameter Test condition Min. Typ. 20 2 Max. 50 4 Unit s s
Minimum CSN HI time, Transfer of SPI command switching from standby mode to Input Register Maximum CSN HI time, active mode Transfer of SPI command to input register
Figure 3.
SPI - transfer timing diagram
CSN high to low: DO enabled
CSN
time
CLK
0
1
2
3
4
5
6
7
X
X
18 19
20 21 22 23
0
1
DI: data will be accepted on the rising edge of CLK signal
time
0 1
DI
0
1
2
3
4
5
6
7
X
X
18 19
20 21 22 23
DO: data will change on the falling edge of CLK signal
time
0 1
DO
0
1
2
3
4
5
6
7
X
X
18 19
20 21 22
23
fault bit
CSN low to high: actual data is transfered to output power switches old data new data
time
Input Data Register
time
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L9950 - L9950XP Figure 4. SPI - input timing
Electrical specifications
CSN t t t
0.8 VCC 0.2 VCC
set CSN CLKH se t CLK
CLK t
set DI
0.8 VCC 0.2 VCC t
hold DI
t
CLKL
0.8 VCC DI Valid Valid 0.2 VCC
Figure 5.
SPI - DO valid data delay time and valid time
t f in t r in 0.8 VCC 0.5 VCC 0.2 VCC t r DO
CLK
DO (low to high) t d DO DO (high to low) t f DO
0.8 VCC 0.2 VCC
0.8 VCC 0.2 VCC
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Electrical specifications Figure 6. SPI - DO enable and disable time
tf in tr in
L9950 - L9950XP
CSN
0.8 VCC 50% 0.2 VCC
DO pull-up load to VCC C L = 100 pF
50%
ten DO tri L t dis DO L tri
DO pull-down load to GND C L = 100 pF ten DO tri H t dis DO H tri
50%
Figure 7.
SPI - driver turn-on/off timing, minimum csn hi time
CSN low to high: data from shift register is transferred to output power switches
t r in
tCSN_HI,min
t f in
CSN
80% 50% 20% tdOFF
output current of a driver
ON state
OFF state
80% 50% 20%
t OFF tdON t ON output current of a driver 80% 50% 20%
OFF state
ON state
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L9950 - L9950XP Figure 8. SPI - timing of status bit 0 (fault condition)
Electrical specifications
CSN high to low and CLK stays low: status information of data bit 0 (fault condition) is transfered to DO
CSN time CLK time DI time
DI: data is not accepted
DO
0 time
DO: status information of data bit 0 (fault condition) will stay as long as CSN is low
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Application information
L9950 - L9950XP
3
3.1
Application information
Dual power supply: VS and VCC
The power supply voltage VS supplies the half bridges and the highside drivers. An internal charge-pump is used to drive the highside switches. The logic supply voltage VCC (stabilized 5 V) is used for the logic part and the SPI of the device. Due to the independent logic supply voltage the control and status information will not be lost, if there are temporary spikes or glitches on the power supply voltage. In case of poweron (VCC increases from under voltage to VPOR OFF = 4.2 V) the circuit is initialized by an internally generated power on reset (POR). If the voltage VCC decreases under the minimum threshold (VPOR ON = 3.4 V), the outputs are switched to tristate (high impedance) and the status registers are cleared.
3.2
Standby mode
The standby mode of the L9950 is activated by clearing the bit 23 of the Input Data Register 0. All latched data will be cleared and the inputs and outputs are switched to high impedance. In the standby mode the current at VS (VCC) is less than 6 A (50 A) for CSN = high (DO in tristate). By switching the VCC voltage a very low quiescent current can be achieved. If bit 23 is set, the device will be switched to active mode.
3.3
Inductive loads
Each half bridge is built by an internally connected highside and a lowside power DMOS transistor. Due to the built-in reverse diodes of the output transistors, inductive loads can be driven at the outputs OUT1 to OUT6 without external free wheeling diodes. The highside drivers OUT7 to OUT11 are intended to drive resistive loads. Hence only a limited energy (E<1 mJ) can be dissipated by the internal ESD diodes in freewheeling condition. For inductive loads (L>100 H) an external free wheeling diode connected to GND and the corresponding output is needed.
3.4
Diagnostic functions
All diagnostic functions (over/open load, power supply over-/undervoltage, temperature warning and thermal shutdown) are internally filtered and the condition has to be valid for at least 32 s (open load: 1 ms, respectively) before the corresponding status bit in the status registers will be set. The filters are used to improve the noise immunity of the device. Open load and temperature warning function are intended for information purpose and will not change the state of the output drivers. On contrary, the overload and thermal shutdown condition will disable the corresponding driver (overload) or all drivers (thermal shutdown), respectively. Without setting the over-current recovery bits in the Input Data register, the microcontroller has to clear the over-current status bits to reactivate the corresponding drivers.
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Application information
3.5
Overvoltage and under voltage detection
If the power supply voltage VS rises above the overvoltage threshold VSOV OFF (typical 21 V), the outputs OUT1 to OUT11 are switched to high impedance state to protect the load. When the voltage VS drops below the under voltage threshold VSUV OFF (UV switch OFF voltage), the output stages are switched to the high impedance to avoid the operation of the power devices without sufficient gate driving voltage (increased power dissipation). If the supply voltage VS recovers to normal operating voltage the outputs stages return to the programmed state (input register 0: bit 20=0). If the under voltage/overvoltage recovery disable bit is set, the automatic turn-on of the drivers is deactivated. The microcontroller needs to clear the status bits to reactivate the drivers. It is recommended to set bit 20 to avoid a possible high current oscillation in case of a shorted output to GND and low battery voltage.
3.6
Temperature warning and thermal shutdown
If junction temperature rises above Tj TW a temperature warning flag is set and is detectable via the SPI. If junction temperature increases above the second threshold Tj SD, the thermal shutdown bit will be set and power DMOS transistors of all output stages are switched off to protect the device. In order to reactivate the output stages the junction temperature must decrease below Tj SD - Tj SD HYS and the thermal shutdown bit has to be cleared by the microcontroller.
3.7
Open-load detection
The open load detection monitors the load current in each activated output stage. If the load current is below the open load detection threshold for at least 1 ms (tdOL) the corresponding open load bit is set in the status register. Due to mechanical/electrical inertia of typical loads a short activation of the outputs (e.g. 3ms) can be used to test the open load status without changing the mechanical/electrical state of the loads.
3.8
Over load detection
In case of an over-current condition a flag is set in the status register in the same way as open load detection. If the over-current signal is valid for at least tISC = 32 s, the overcurrent flag is set and the corresponding driver is switched off to reduce the power dissipation and to protect the integrated circuit. If the over-current recovery bit of the output is zero the microcontroller has to clear the status bits to reactivate the corresponding driver.
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Application information
L9950 - L9950XP
3.9
Current monitor
The current monitor output sources a current image at the current monitor output which has a fixed ratio (1/10000) of the instantaneous current of the selected highside driver. The bits 18 and 19 of the Input Data Register 0 control which of the outputs OUT1, OUT4, OUT5, OUT6 and OUT11 will be multiplexed to the current monitor output. The current monitor output allows a more precise analysis of the actual state of the load rather than the detection of an open or overload condition. For example this can be used to detect the motor state (starting, free running, stalled). Moreover, it is possible to regulate the power of the defroster more precise by measuring the load current. The current monitor output is bidirectional (c.f. PWM inputs).
3.10
PWM inputs
Each driver has a corresponding PWM enable bit which can be programmed by the SPI interface. If the PWM enable bit is set, the output is controlled by the logically AND combination of the PWM signal and the output control bit in Input Data Register. The outputs OUT1-OUT8 and OUT11 are controlled by the PWM1 input and the outputs OUT9/10 are controlled by the bidirectional input CM/PMW2. For example, the two PWM inputs can be used to dim two lamps independently by external PWM signals.
3.11
Cross current protection
The six half brides of the device are cross current protected by an internal delay time. If one driver (LS or HS) is turned off the activation of the other driver of the same half bridge will be automatically delayed by the cross current protection time. After the cross current protection time is expired the slew rate limited switch off phase of the driver will be changed to a fast turn-off phase and the opposite driver is turned on with slew rate limitation. Due to this behavior it is always guaranteed that the previously activated driver is totally turned off before the opposite driver will start to conduct.
3.12
Programmable soft start function to drive loads with higher inrush current
Loads with start-up currents higher than the over-current limits (e.g. inrush current of lamps, start current of motors and cold resistance of heaters) can be driven by using the programmable soft start function (i.e. overcurrent recovery mode). Each driver has a corresponding over-current recovery bit. If this bit is set, the device will automatically switchon the outputs again after a programmable recovery time. The duty cycle in over-current condition can be programmed by the SPI interface to be about 12% or 25%. The PWM modulated current will provide sufficient average current to power up the load (e.g. heat up the bulb) until the load reaches operating condition. The device itself cannot distinguish between a real overload and a non linear load like a light bulb. A real overload condition can only be qualified by time. As an example the microcontroller can switch on light bulbs by setting the over-current Recovery bit for the first 50ms. After clearing the recovery bit the output will be automatically disabled if the overload condition still exits.
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L9950 - L9950XP Figure 9.
Application information Example of programmable soft start function for inductive loads
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Functional description of the SPI
L9950 - L9950XP
4
4.1
Functional description of the SPI
Serial Peripheral Interface (SPI)
This device uses a standard SPI to communicate with a microcontroller. The SPI can be driven by a microcontroller with its SPI peripheral running in following mode: CPOL = 0 and CPHA = 0. For this mode, input data is sampled by the low to high transition of the clock CLK, and output data is changed from the high to low transition of CLK. This device is not limited to microcontroller with a build-in SPI. Only three CMOS-compatible output pins and one input pin will be needed to communicate with the device. A fault condition can be detected by setting CSN to low. If CSN = 0, the DO pin will reflect the status bit 0 (fault condition) of the device which is a logical or of all bits in the status registers 0 and 1. The microcontroller can poll the status of the device without the need of a full SPI communication cycle.
Note:
In contrast to the SPI standard the least significant bit (LSB) will be transferred first (see Figure 3).
4.2
Chip Select Not (CSN)
The input pin is used to select the serial interface of this device. When CSN is high, the output pin (DO) will be in high impedance state. A low signal will activate the output driver and a serial communication can be started. The state when CSN is going low until the rising edge of CSN will be called a communication frame. If the CSN input pin is driven above 7.5V, the L9950 will go into a test mode. In the test mode the DO will go from tri state to active mode.
4.3
Serial Data In (DI)
The input pin is used to transfer data serial into the device. The data applied to the DI will be sampled at the rising edge of the CLK signal and shifted into an internal 24 bit shift register. At the rising edge of the CSN signal the contents of the shift register will be transferred to Data Input Register. The writing to the selected Data Input Register is only enabled if exactly 24 bits are transmitted within one communication frame (i.e. CSN low). If more or less clock pulses are counted within one frame the complete frame will be ignored. This safety function is implemented to avoid an activation of the output stages by a wrong communication frame.
Note:
Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel operation of the SPI bus by controlling the CSN signal of the connected ICs is recommended.
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Functional description of the SPI
4.4
Serial Data Out (DO)
The data output driver is activated by a logical low level at the CSN input and will go from high impedance to a low or high level depending on the status bit 0 (fault condition). The first rising edge of the CLK input after a high to low transition of the CSN pin will transfer the content of the selected status register into the data out shift register. Each subsequent falling edge of the CLK will shift the next bit out.
4.5
Serial clock (CLK)
The CLK input is used to synchronize the input and output serial bit streams. The data input (DI) is sampled at the rising edge of the CLK and the data output (DO) will change with the falling edge of the CLK signal.
4.6
Input data register
The device has two input registers. The first bit (bit 0) at the DI input is used to select one of the two Input Registers. All bits are first shifted into an input shift register. After the rising edge of CSN the contents of the input shift register will be written to the selected Input Data Register only if a frame of exact 24 data bits are detected. Depending on bit 0 the contents of the selected status register will be transferred to DO during the current communication frame. Bit 1-17 controls the behavior of the corresponding driver. If bit 23 is zero, the device will go into the standby mode. The bits 18 and 19 are used to control the current monitor multiplexer. Bit 22 is used to reset all status bits in both status registers. The bits in the status registers will be cleared after the current communication frame (rising edge of CSN).
4.7
Status register
This devices uses two status registers to store and to monitor the state of the device. Bit 0 is used as a fault bit and is a logical NOR combination of bits 1-22 in both status registers. The state of this bit can be polled by the microcontroller without the need of a full SPI communication cycle. If one of the over-current bits is set, the corresponding driver will be disabled. If the over-current recovery bit of the output is not set the microcontroller has to clear the over-current bit to enable the driver. If the thermal shutdown bit is set, all drivers will go into a high impedance state. Again the microcontroller has to clear the bit to enable the drivers.
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Functional description of the SPI
L9950 - L9950XP
4.8
Test mode
The test mode can be entered by rising the CSN input to a voltage higher than 7.0 V. In the test mode the inputs CLK, DI, PWM1/2 and the internal 2 MHz CLK can be multiplexed to data output DO for testing purpose. Furthermore the over-current thresholds are reduced by a factor of 4 to allow EWS testing at lower current. For EWS testing a special test pad is available to measure the internal bandgap voltage, the TW and TSD thresholds. The internal logic prevents that the Hi-Side and Lo-Side driver of the same half-bridge can be switched on at the same time. In the test mode this combination is used to multiplex the desired signals according to following table: Table 18. Test mode
DO No error DI CLK INT_CLK PWM1 PWM2 LS3 HS3 LS4 HS4 LS5 HS5 ! (both HI) both HI ! (both HI) both HI ! (both HI) both HI ! (both HI) both HI ! (both HI) ! (both HI) both HI both HI ! (both HI) ! (both HI) both HI both HI ! (both HI) ! (both HI) ! (both HI) ! (both HI) both HI both HI both HI both HI Test pad 5A Iref Tsens1 Tsens2 Tsens3 Tsens4 Tsens5 Tsens6 Vbandgap
LS1 HS1 LS2 HS2 LS3 HS3 ! (both HI) both HI ! (both HI) both HI ! (both HI) both HI ! (both HI) ! (both HI) both HI both HI ! (both HI) ! (both HI) ! (both HI) ! (both HI) ! (both HI) ! (both HI) both HI both HI
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L9950 - L9950XP Table 19.
Bit Name Comment If Enable Bit is set the device will be switched in active mode. If Enable Bit is cleared device go into standby mode and all bits are cleared. After poweron reset device starts in standby mode. If Reset Bit is set both status registers will be cleared after rising edge of CSN input.
Functional description of the SPI SPI - input data and status registers 0
Input register 0 (write) Name Status register 0 (read) Comment A broken VCC or SPI connection of the L9950 can be detected by the microcontroller, because all 24 bits low or high is not a valid frame.
23
Enable bit
Always 1
22
Reset bit
OC recovery duty cycle 21 0: 12% 1: 25%
In case of an overvoltage or VS overvoltage undervoltage event the corresponding bit is set and the outputs are deactivated. If This bit defines in VS voltage recovers to normal combination with the overoperating conditions outputs current recovery bit (Input VS undervoltage are reactivated automatically Register 1) the duty cycle (if Bit 20 of status register 0 is in over-current condition not set). of an activated driver. In case of an thermal shutdown all outputs are switched off. The microcontroller has to clear the TSD bit by setting the Reset Bit to reactivate the outputs. This bit is for information purpose only. It can be used for a thermal management by the microcontroller to avoid a thermal shutdown.
20
If this bit is set the microcontroller has to Overvoltage/Un clear the status register dervoltage after recovery disable undervoltage/overvoltage event to enable the outputs. Depending on combination of bit 18 and 19 the current image (1/10.000) of the selected HS output will be multiplexed to the CM output: Bit 19 0 1 Bit 18 0 0 1 1 Output OUT11 OUT1/OUT 6 OUT5 OUT4
Thermal shutdown
19
Temperature warning
18
Current monitor select bits
0 1
Not ready bit
HS driver of OUT1 is only selected if HS driver OUT1 is switched on and HS driver OUT6 is not activated.
After switching the device from standby mode to active mode an internal timer is started to allow charge pump to settle before the outputs can be activated. This bit is cleared automatically after start up time has finished. Since this bit is controlled by internal clock it can be used for synchronizing testing events (e.g. measuring filter times).
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Functional description of the SPI Table 19.
Bit Name 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 OUT11 - HS on/off OUT10 - HS on/off OUT9 - HS on/off OUT8 - HS on/off OUT7 - HS on/off OUT6 - HS on/off OUT6 - LS on/off OUT5 - HS on/off OUT5 - LS on/off OUT4 - HS on/off OUT4 - LS on/off OUT3 - HS on/off OUT3 - LS on/off OUT2 - HS on/off OUT2 - LS on/off OUT1 - HS on/off OUT1 - LS on/off 0 If a bit is set the selected output driver is switched on. If the corresponding PWM enable bit is set (Input Register 1) the driver is only activated if PWM1 (PWM2) input signal is high. The outputs of OUT1-OUT6 are half bridges. If the bits of HSand LS driver of the same half bridge are set, the internal logic prevents that both drivers of this output stage can be switched on simultaneously in order to avoid a high internal current from VS to GND. In test mode (CSN>7.5 V) this bit combinations are used to multiplex internal signals to the DO output. Comment Name OUT11 - HS over-current OUT10 - HS over-current OUT9 - HS over-current OUT8 - HS over-current OUT7 - HS over-current OUT6 - HS over-current OUT6 - LS over-current OUT5 - HS over-current OUT5 - LS over-current OUT4 - HS over-current OUT4 - LS over-current OUT3 - HS over-current OUT3 - LS over-current OUT2 - HS over-current OUT2 - LS over-current OUT1 - HS over-current OUT1 - LS over-current No error bit
L9950 - L9950XP
SPI - input data and status registers 0 (continued)
Input register 0 (write) Status register 0 (read) Comment
In case of an over-current event the corresponding status bit is set and the output driver is disabled. If the overcurrent Recovery Enable bit is set (Input Register 1) the output will be automatically reactivated after a delay time resulting in a PWM modulated current with a programmable duty cycle (Bit 21). If the over-current recovery bit is not set the microcontroller has to clear the over-current bit (Reset Bit) to reactivate the output driver.
0
A logical NOR combination of all bits 1 to 22 in both status registers.
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L9950 - L9950XP Table 20.
Bit
Functional description of the SPI SPI - input data and status registers 1
Input register 1 (write) Name Comment If Enable bit is set the device will be switched in active mode. If Enable Bit is cleared device go into standby mode and all bits are cleared. After poweron reset device starts in standby mode. Status register 1 (read) Name Comment A broken VCC or SPI connection of the L9950 can be detected by the microcontroller, because all 24 bits low or high is not a valid frame. In case of an overvoltage or undervoltage event the corresponding bit is set and the outputs are deactivated. If VS voltage recovers to normal operating conditions outputs are reactivated automatically.
23
Enable bit
Always 1
22
OUT11 OC Recovery Enable OUT10 OC Recovery Enable
VS overvoltage
21
VS undervoltage
20
OUT9 OC Recovery Enable
19
OUT8 OC Recovery Enable
In case of an over-current event the over-current status bit (Status Register 0) is set and the output is switched off. If the over-current Recovery Enable bit is set the output will be automatically reactivated after a delay time resulting in a PWM modulated current with a programmable duty cycle (Bit 21 of Input Data Register 0). Depending on occurrence of Overcurrent Event and internal clock phase it is possible that one recovery cycle is executed even if this bit is set to zero.
In case of an thermal shutdown all outputs are switched off. The Thermal shutdown microcontroller has to clear the TSD bit by setting the Reset Bit to reactivate the outputs. This bit is for information purpose only. It can be used for a thermal management by the microcontroller to avoid a thermal shutdown. After switching the device from standby mode to active mode an internal timer is started to allow charge pump to settle before the outputs can be activated. This bit is cleared automatically after start up time has finished. Since this bit is controlled by internal clock it can be used for synchronizing testing events(e.g. measuring filter times).
Temperature warning
18
OUT7 OC Recovery enable
Not ready bit
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Functional description of the SPI Table 20.
Bit
L9950 - L9950XP
SPI - input data and status registers 1 (continued)
Input register 1 (write) Status register 1 (read) Name OUT11 - HS open load OUT10 - HS open load OUT9 - HS open load OUT8 - HS open load OUT7 - HS open load OUT6 - HS open load OUT6 - LS open load OUT5 - HS open load OUT5 - LS open load OUT4 - HS open load OUT4 - LS open load OUT3 - HS open load OUT3 - LS open load OUT2 -HS open load OUT2- LS open load OUT1 - HS open load OUT1 - LS open load A logical NOR combination of all bits 1 to 22 in both status registers. Comment The open load detection monitors the load current in each activated output stage. If the load current is below the open load detection threshold for at least 1 ms (tdOL) the corresponding open load bit is set. Due to mechanical/electrical inertia of typical loads a short activation of the outputs (e.g. 3 ms) can be used to test the open load status without changing the mechanical/electrical state of the loads. Comment
Name OUT6 OC Recovery Enable OUT5 OC Recovery Enable OUT4 OC Recovery Enable OUT3 OC Recovery Enable OUT2 OC Recovery Enable OUT1 OC Recovery Enable OUT11 PWM1 Enable OUT10 PWM2 Enable OUT9 PWM2 Enable OUT8 PWM1 Enable OUT7 PWM1 Enable OUT6 PWM1 Enable OUT4 PWM1 Enable OUT4 PWM1 Enable OUT3 PWM1 Enable OUT4 PWM1 Enable OUT4 PWM1 Enable
17
16
15
14
After 50 ms the bit can be cleared. If over-current condition still exists, a wrong load can be assumed.
13
12
11 10 9 8 7 6 5 4 3 2 1
If the PWM1/2 Enable Bit is set and the output is enabled (Input Register 0) the output is switched on if PWM1/2 input is high and switched off if PWM1/2 input is low. OUT9 and OUT10 is controlled by PWM2 input all other outputs are controlled by PWM1 input.
The open load detection monitors the load current in each activated output stage. If the load current is below the open load detection threshold for at least 1 ms (tdOL) the corresponding open load bit is set. Due to mechanical/electrical inertia of typical loads a short activation of the outputs (e.g. 3 ms) can be used to test the open load status without changing the mechanical/electrical state of the loads.
0
1
No Error bit
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Packages thermal data
5
Packages thermal data
Figure 10. Packages thermal data
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Package and packing information
L9950 - L9950XP
6
6.1
Package and packing information
ECOPACK(R)
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark.
6.2
PowerSO-36 package information
Figure 11. PowerSO-36 package dimensions
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L9950 - L9950XP Table 21. PowerSO-36 mechanical data
Package and packing information
Millimeters Symbol Min. A a1 a2 a3 b c D* D1 E E1 * E2 E3 e e3 G H h L M N R s 0.10 0 0.22 0.23 15.80 9.40 13.90 10.90 5.80 0 15.50 0.8 Typ. 0.65 11.05 Max. 3.60 0.30 3.30 0.10 0.38 0.32 16.00 9.80 14.5 11.10 2.90 6.20 0.10 15.90 1.10 1.10 10 deg 8 deg
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Package and packing information
L9950 - L9950XP
6.3
PowerSSO-36 package information
Figure 12. PowerSSO-36 package dimensions
Table 22.
PowerSSO-36 mechanical data
Millimeters Min. 2.15 2.15 0 0.18 0.23 10.10 7.4 10.1 0 Typ. 0.5 8.5 2.3 Max. 2.45 2.35 0.10 0.36 0.32 10.50 7.6 0.1 0.06 10.5 0.4 8
Symbol A A2 a1 b c D(1) E e e3 F G G1 H h k
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L9950 - L9950XP Table 22.
Package and packing information PowerSSO-36 mechanical data (continued)
Millimeters Min. 0.55 4.3 6.9 Typ. 4.3 1.2 0.8 2.9 3.65 1 Max. 0.85 10 5.2 7.5
Symbol L M N O Q S T U X Y
1. "D" and "E" do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.15 mm per side (0.006").
6.4
PowerSO-36 packing information
Figure 13. PowerSO-36 tube shipment (no suffix)
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Package and packing information Figure 14. PowerSO-36 tape and reel shipment (suffix "TR")
L9950 - L9950XP
TAPE DIMENSIONS A0 B0 K0 K1 F P1 W 15.20 0.1 16.60 0.1 3.90 0.1 3.50 0.1 11.50 0.1 24.00 0.1 24.00 0.3
REEL DIMENSIONS
Base qty Bulk qty A (max) B (min) C (0.2) D (min) G (+2 / -0) N (min) T (max) 600 600 330 1.5 13 20.2 24.4 60 30.4
All dimensions are in mm.
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Package and packing information
6.5
PowerSSO-36 packing information
Figure 15. PowerSSO-36 tube shipment (no suffix)
Base qty Bulk qty Tube length (0.5) A B C (0.1) All dimensions are in mm.
A
C
B
49 1225 532 3.5 13.8 0.6
Figure 16. PowerSSO-36 tape and reel shipment (suffix "TR")
REEL DIMENSIONS
Base qty Bulk qty A (max) B (min) C (0.2) F G (+2 / -0) N (min) T (max) TAPE DIMENSIONS According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 Tape width Tape hole spacing Component spacing Hole diameter Hole diameter Hole position Compartment depth Hole spacing All dimensions are in mm. W P0 (0.1) P D (0.05) D1 (min) F (0.1) K (max) P1 (0.1) 24 4 12 1.55 1.5 11.5 2.85 2
1000 1000 330 1.5 13 20.2 24.4 100 30.4
End
Start Top cover tape No components Components 500mm min No components
500mm min Empty components pockets sealed with cover tape. User direction of feed
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Revision history
L9950 - L9950XP
7
Revision history
Table 23.
Date Apr-2004 Jun-2004 Jul-2004 Jun-2005 Jul-2005
Document revision history
Revision 1 2 3 4 5 First Issue Changed maturity from product preview to final; Changed values in the Table 4: ESD protection Minor changes PowerSSO-36 package insertion Figure 1 modification Features modification; Table 7 modification (ICC; IS + ICC); Figure 10 modification; IQLL modification. Document restructured and reformatted. Added PowerSO-36 packing information and PowerSSO-36 packing information. Updated Table 22: PowerSSO-36 mechanical data. Changed Section : Application on cover page Changed Section 6.1: ECOPACK(R) Table 22: PowerSSO-36 mechanical data: - Changed A (max) value from 2.50 to 2.45 - Changed A2 (max) value from 2.40 to 2.35 - Changed L (max) value from 0.90 to 0.85 Description of changes
Sep-2005
6
14-Nov-2007 05-Nov-2008 30-Mar-2009
7 8 9
09-Jun-2009
10
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