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SPT7937
12-BIT, 28 MSPS, 170 mW A/D CONVERTER
FEATURES
* * * * * * * Monolithic 28 MSPS Analog-to-Digital Converter 170 mW Power Dissipation On-Chip Track-and-Hold Single +5 V Power Supply TTL/CMOS Outputs 5 pF Input Capacitance Selectable +3 V or +5 V Logic I/O
APPLICATIONS
* All High-Speed Applications Where Low Power Dissipation Is Required * Video Imaging * Medical Imaging * IR Imaging * Digital Communications
GENERAL DESCRIPTION
The SPT7937 is a 12-bit monolithic, low-cost, low-power analog-to-digital converter capable of minimum sample rates of 28 MSPS. The SPT7937 has incorporated proprietary parallel SAR circuit design and CMOS processing technologies to achieve its advanced performance.The onchip track-and-hold function assures very good dynamic performance without the need for external components. Power dissipation is extremely low at only 170 mW typical at 28 MSPS with a power supply of +5.0 V. The digital outputs are +3 V or +5 V, and are user selectable. Inputs and outputs are TTL/CMOS compatible to interface with TTL/ CMOS logic systems. Output data format is straight binary. The SPT7937 is available in a 28-lead SSOP package over the industrial temperature range.
BLOCK DIAGRAM
ADC Section 1 AIN 1:18 Mux T/H
AutoZero CMP
13-Bit SAR 13
13
D12 Out of Range D11 (MSB) D10
P1 P2 CLK In Timing P17 and Control P18
DAC D9 ADC Section 2 13 13-Bit 18:1 Mux/ Error Correction D8 D7 D6 D5 D4 D3 D2 D1 Reference Ladder DO (LSB)
. . .
. . .
. . .
. . .
ADC Section 17 ADC Section 18 T/H
AutoZero CMP
13
13-Bit SAR 13 DAC
13
VRHF
VRHS
VRLS
VRLF
Signal Processing Technologies, Inc.
4755 Forge Road, Colorado Springs, Colorado 80907, USA Phone: (719) 528-2300 FAX: (719) 528-2370 Website: http://www.spt.com E-Mail: sales@spt.com
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 C
Supply Voltages AVDD ......................................................................... +6 V DVDD ......................................................................... +6 V OVDD ......................................................................... +6 V Input Voltages Analog Input .................................... -0.7 V to VDD +0.7 V CLK Input ................................................................... VDD AVDD - DVDD ...................................................... 100 mV AGND - DGND .................................................. 100 mV Output Digital Outputs ....................................................... 10 mA Temperature Operating Temperature ............................. -40 to +85 C Junction Temperature ......................................... +175 C Lead Temperature, (soldering 10 seconds) ........ +300 C Storage Temperature ............................... -65 to +150 C
Note: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications.
ELECTRICAL SPECIFICATIONS
T A=TMIN to TMAX, V DD =+5.0 V, S=28 MSPS, V IN =0 to 4 V, V RHS=4.0 V, VRLS=0.0 V, unless otherwise specified. PARAMETERS Resolution DC Accuracy Integral Nonlinearity Differential Nonlinearity No Missing Codes Analog Input Input Voltage Range Input Capacitance Input Bandwidth Input Impedance -Full-Scale Error1 +Full-Scale Error1 Conversion Characteristics Maximum Conversion Rate Minimum Conversion Rate Pipeline Delay (Latency) Aperture Delay Time (TAP) Aperture Jitter Time Clock Duty Cycle Over-Voltage Recovery Time2 Dynamic Performance Effective Number of Bits IN = 3.58 MHz IN = 10 MHz Reference Input Resistance Voltage Range3 VRHS VRLS VRHS - VRLS
1 The
TEST CONDITIONS
TEST LEVEL
MIN 12
SPT7937 TYP
MAX
UNITS Bits
V V VI VI V V V V VI V IV V V V 28 1 VRLS
1.75 0.9 Guaranteed VRHS 5.0 250 35 1.0 0.12
LSB LSB
V pF MHz k LSB %FS MHz MHz
14 1.0 5.0 40 60 36
Clock Cycles
ns ps (RMS) % ns
V VI VI IV IV V 350 3.0 0.0 1.0
10.3 10.0 500 650 VDD 2.0 5.0
Bits Bits V V V
4.0
full-scale range spans the reference ladder sense pins, VRHS and VRLS. Refer to the Voltage Reference section for discussion. to internal architecture, over-voltage recovery time is less than one clock cycle (i.e., 25 ns at CLK = 40 MHz). 3 For optimum performance, the full-scale voltage range (VRHS-VRLS) should be between 3 V to 5 V.
2 Due
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ELECTRICAL SPECIFICATIONS
T A =TMIN to TMAX, V DD =+5.0 V, S=28 MSPS, V IN =0 to 4 V, V RHS=4.0 V, VRLS=0.0 V, unless otherwise specified. PARAMETERS Dynamic Performance Signal-to-Noise Ratio (without Harmonics) IN = 3.58 MHz IN = 10 MHz Harmonic Distortion IN = 3.58 MHz IN = 10 MHz Signal-to-Noise and Distortion (SINAD) IN = 3.58 MHz IN = 10 MHz Spurious Free Dynamic Range IN = 10 MHz Differential Phase Differential Gain Inputs Logic 1 Voltage Logic 0 Voltage Maximum Input Current Low Maximum Input Current High Input Capacitance Digital Outputs Logic 1 Voltage Logic 0 Voltage CLK to Output Delay Time (tD) Power Supply Requirements Voltages OVDD VDD Currents IDD Power Dissipation Power Supply Rejection Ratio IOH = 0.5 mA IOL = 1.6 mA TEST CONDITIONS TEST LEVEL MIN SPT7937 TYP MAX UNITS
V VI V VI
61
65 63 -73 -72
dB dB dB dB
-63.5
V VI V V V VI VI VI VI V VI VI IV IV IV VI VI V
60
64 62 73 0.6 0.5
dB dB dB Degree % V V A A pF V V ns V V mA mW dB
2.0 -10 -10 5 VDD - 0.5 0.4 15 3.0 4.75 5.0 5.25 40 200 0.8 +10 +10
5.0 34 170 60
TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition.
TEST LEVEL I II III IV V VI
TEST PROCEDURE 100% production tested at the specified temperature. 100% production tested at TA = +25 C, and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 100% production tested at TA = +25 C. Parameter is guaranteed over specified temperature range.
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Figure 1a - Timing Diagram
1 2 3 9 4 5 6 7 8 10 11 12 13 14 15 16 17
ANALOG IN
CLOCK IN
INVALID
VALID
DATA OUTPUT
1
2
3
Figure 1b - Timing Diagram
tCLK tC tCH CLOCK IN tCL
DATA OUTPUT Data O tD
Data 1
Data 2
Data 3
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TYPICAL PERFORMANCE CHARACTERISTICS
THD, SNR, SINAD vs Input Frequency
75
THD, SNR, SINAD vs Sample Rate
90
70
80
THD, SNR, SINAD (dB)
THD
65
THD, SNR, SINAD (dB)
THD
70
SNR
60
SNR
60
SINAD
55
SINAD
50
50
40
45 0 5 10 15 20
30 0 1 5 10 20 30 40 50
Input Frequency (MHz)
Sample Rate (MSPS)
THD, SNR, SINAD vs Temperature
85
SFDR vs Temperature
85
80
80
THD, SNR, SINAD (dB)
THD
70
SFDR (dB)
75
75
70
65
65
SNR
60
60
SINAD
55 -55 -40 0 25 70 85 125
55 -55 -40 0 25 70 85 125
Temperature (C)
Temperature (C)
Input Bandwidth
0 30
IDD vs Sample Rate
Output Fundamental (dBm)
-5
25
-10
20
-15
IDD (mA)
15
-20
10
-25
5
-30 100
0 200 300 400 500 1000 10-1 100 101 102
Frequency (MHz)
Sample Rate (MSPS)
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Figure 2 - Typical Interface Circuit
CLK IN
OGND DGND CLK
+
OTR D11 D10 D9
Out of Range Bit MSB
U1 DGND
VINR
SPT7937
+A5
+
AVDD
D8 D7 D6 D5 D4 D3 D2 D1 D0 OVDD
1 LSB
(DUT)
AIN +A5
U1
+
VIN RGND VRHS VRHF VRLF VRLS
28
TK11240B
Ext VREF (+4 V)
DVDD2
FB
+
+D3/5V +A5 + 10 F +A5 AGND
+D3/5V +D3/5 + 10 F +D3/5 DGND
Notes: 1) Unless otherwise specified, all non-polarized capacitors are 0.01 microfarad surface-mount chip capacitors. They need to be placed as close to the pin as possible 2) All polarized capacitors are 4.7 to 10 microfarad tantalum surface-mount capacitors 3) FB is a ferrite bead. Place FB as close to the DUT as possible 4) U1 is TOKO regulator TK11240B (4.0 V)
TYPICAL INTERFACE CIRCUIT
Very few external components are required to achieve the stated device performance. Figure 2 shows the typical interface requirements when using the SPT7937 in normal circuit operation. The following sections provide descriptions of the major functions and outline critical performance criteria to consider for achieving the optimal device performance.
POWER SUPPLIES AND GROUNDING
SPT suggests that both the digital (DVDD) and the analog (AVDD) supply voltages on the SPT7937 be derived from a single analog supply as shown in figure 2. A separate digital supply should be used for the digital output driver supply (OVDD) and all interface circuitry. SPT suggests using this power supply configuration to prevent a possible latch-up condition on power up. In addition, the power supplies must be powered up before the analog input is applied.
SPT
Interfacing Logic
DVDD
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OPERATING DESCRIPTION
The general architecture for the CMOS ADC is shown in the block diagram. The design contains 18 identical successive approximation ADC sections (all operating in parallel), an 18-phase clock generator, a 13-bit 18:1 digital output multiplexer, correction logic, and a voltage reference generator which provides common reference levels for each ADC section. The high sample rate is achieved by using multiple SAR ADC sections in parallel, each of which samples the input signal in sequence. Each ADC uses 18 clock cycles to complete a conversion. The clock cycles are allocated as follows: Table II - Clock Cycles Clock 1 2 3 4 5-17 18 Operation Reference zero sampling Auto-zero comparison Auto-calibrate comparison Input sample 13-bit SAR conversion Data transfer
VOLTAGE REFERENCE
The SPT7937 requires the use of a single external voltage reference for driving the high side of the reference ladder. It must be within the range of 3 V to 5 V. The lower side of the ladder is typically tied to AGND (0.0 V), but can be run up to 2.0 V with a second reference. The analog input voltage fullscale range will track the total voltage difference measured between the ladder sense lines, VRHS and VRLS. For optimum performance the full-scale voltage range (VRHS-VRLS) should be between 3 V to 5 V. Force and sense taps are provided to ensure accurate and stable setting of the upper and lower ladder sense line voltages across part-to-part and temperature variations. By using the configuration shown in figure 3, offset and gain errors of less than 2 LSB can be obtained.
Figure 3 - Ladder Force/Sense Circuit
1 AGND
+ -
2
VRHF
3
VRHS
SPT
7
+ -
The 18-phase clock, which is derived from the input clock, synchronizes these events. The timing signals for adjacent ADC sections are shifted by one clock cycle so that the analog input is sampled on every cycle of the input clock by exactly one ADC section. After 18 clock periods, the timing cycle repeats. The latency from analog input sample to the corresponding digital output is 14 clock cycles. * Since only 18 comparators are used, a huge power savings is realized. * The auto-zero operation is done using a closed loop system that uses multiple samples of the comparator's response to a reference zero. * The auto-calibrate operation, which calibrates the gain of the MSB reference and the LSB reference, is also done with a closed loop system. Multiple samples of the gain error are integrated to produce a calibration voltage for each ADC section. * Capacitive displacement currents, which can induce sampling error, are minimized since only one comparator samples the input during a clock cycle. * The total input capacitance is very low since sections of the converter which are not sampling the signal are isolated from the input by transmission gates.
4 5
N/C VRLS
6
VRLF
7
VIN
All capacitors are 0.01 F
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Figure 4 - Simplified Reference Ladder Drive Circuit Without Force/Sense Circuit
+4.0 V External Reference VRHS (+3.91 V)
ANALOG INPUT
VIN is the analog input. The input voltage range is from VRLS to VRHS (typically 4.0 V) and will scale proportionally with respect to the voltage reference. (See the Voltage Reference section.) The drive requirements for the analog inputs are very minimal when compared to most other converters due to the SPT7937's extremely low input capacitance of only 5 pF and very high input resistance in excess of 35 k.
21 mV
R/2
R
R
R
R=30 (typ) All capacitors are 0.01 F
R
The analog input should be protected through a series resistor and diode clamping circuit as shown in figure 5. To prevent possible latch-up condition, the power supplies must be powered up before the input is applied. Figure 5 - Recommended Input Protection Circuit
+V AVDD
R
R VRLS (0.075 V) VRLF (AGND) 0.0 V
50 mV
R/2
D1
Buffer
47 D2
ADC
In cases in which wider variations in offset and gain can be tolerated, VRef can be tied directly to VRHF and AGND can be tied directly to VRLF as shown in figure 4. Decouple force and sense lines to AGND with a 0.01 F capacitor (chip cap preferred) to minimize high-frequency noise injection. If this simplified configuration is used, the following considerations should be taken into account: The reference ladder circuit shown in figure 4 is a simplified representation of the actual reference ladder with force and sense taps shown. Due to the actual internal structure of the ladder, the voltage drop from VRHF to VRHS is not equivalent to the voltage drop from VRLF to VRLS. Typically, the top side voltage drop for VRHF to VRHS will equal: VRHF - VRHS = 0.5% of (VRHF - VRLF) (typical), and the bottom side voltage drop for VRLS to VRLF will equal: VRLS - VRLF = 1.25% of (VRHF - VRLF) (typical). Figure 4 shows an example of expected voltage drops for a specific case. VREF of 4.0 V is applied to VRHF and VRLF is tied to AGND. A 21 mV drop is seen at VRHS (= 3.79 V) and a 50 mV increase is seen at VRLS (= 0.050 V).
-V D1 = D2 = Hewlett Packard HP5712 or equivalent
CALIBRATION
The SPT7937 uses a user-transparent, auto-calibration scheme to ensure 12-bit accuracy over time and temperature. Gain and offset errors are continually adjusted to 12-bit accuracy during device operation. Upon power up, the SPT7937 begins its calibration algorithm. In order to achieve the calibration accuracy required, the offset and gain adjustment step size is a fraction of a 12bit LSB. Since the calibration algorithm is an oversampling process, a minimum of 10,000 clock cycles are required. This results in a minimum calibration time upon power-up of 357 sec (for a 28 MHz clock). Once calibrated, the SPT7937 remains calibrated over time and temperature. Since the calibration cycles are initiated on the rising edge of the clock, the clock must be continuously applied for the SPT7937 to remain in calibration.
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Figure 6 - On-Chip Protection Circuit
VDD
120
DIGITAL OUTPUTS
Analog
120
The digital outputs (D0-D12) are driven by a separate supply (OVDD) ranging from +3 V to +5 V. This feature makes it possible to drive the SPT7937's TTL/CMOS-compatible outputs with the user's logic system supply. The format of the output data (D0-D11) is straight binary. (See table III.) The outputs are latched on the rising edge of CLK. Table III - Output Data Information
ANALOG INPUT +F.S. + 1/2 LSB +F.S. -1/2 LSB +1/2 F.S. +1/2 LSB 0.0 V OVERRANGE D12 1 0 0 0 0 OUTPUT CODE D11-D0 11 1111 1111 11 1111 111O OO OOOO OOOO 00 0000 000O 00 0000 0000
Pad
(O indicates the flickering bit between logic 0 and 1).
INPUT PROTECTION
All I/O pads are protected with an on-chip protection circuit shown in figure 6. This circuit provides ESD robustness to 3.5 kV and prevents latch-up under severe discharge conditions without degrading analog transition times.
OVERRANGE OUTPUT
The Overrange Output (D12) is an indication that the analog input signal has exceeded the positive full scale input voltage by 1 LSB. When this condition occurs, D12 will switch to logic 1. All other data outputs (D0 to D11) will remain at logic 1 as long as D12 remains at logic 1. This feature makes it possible to include the SPT7937 in higher resolution systems.
CLOCK INPUT
The SPT7937 is driven from a single-ended TTL-input clock. Because the pipelined architecture operates on the rising edge of the clock input, the device can operate over a wide range of input clock duty cycles without degrading the dynamic performance.
EVALUATION BOARD
The EB7937 evaluation board is available to aid designers in demonstrating the full performance of the SPT7937. This board includes a reference circuit, clock driver circuit, output data latches and an on-board reconstruction of the digital data. An application note (AN7937) describing the operation of this board, as well as information on the testing of the SPT7937, is also available. Contact the factory for price and availability.
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PACKAGE OUTLINE
28-Lead SSOP
INCHES SYMBOL A B
28
MILLIMETERS MIN 10.07 0.05 0.25 0.09 1.68 0.63 7.65 5.20 MAX 10.33 0.21 0.65 typ 0.38 0.20 1.78 0.95 7.90 5.38
MIN 0.397 0.002 0.010 0.004 0.066 0.025 0.301 0.205
MAX 0.407 0.008 0.0256 typ 0.015 0.008 0.070 0.037 0.311 0.212
C D IH E F G
1
H I
A F B C D E
H
G
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PIN ASSIGNMENTS
OVDD D0 (LSB) D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 (MSB) D12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 DVDD2 VRLS VRLF VRHF VRHS RGND VIN VINR AGND AVDD DVDD1 CLK DGND OGND
PIN FUNCTIONS
Name OVDD D0-D11 D12 OGND DGND CLK DVDD1 DVDD2 AVDD AGND VINR VIN RGND VRHS VRHF VRLS VRLF Function Digital Output Driver Supply Data Output, Bits 0 - Bit 11 Out of Range Digital Output Driver Ground Digital Ground Input Clock Digital VDD Digital VDD; must be tied to DVDD1 Analog VDD Analog Ground Analog Input Return Analog Input, Full Scale from VRLS to VRHS Analog Ground Shield (Junction Isolated) Reference High Sense Reference High Force (VRHFAVDD) Reference Low Sense Reference Low Force
28L SSOP
21 20 19 18 17 16 15
ORDERING INFORMATION
PART NUMBER SPT7937SIR TEMPERATURE RANGE -40 to +85 C PACKAGE TYPE 28L SSOP
Signal Processing Technologies, Inc. reserves the right to change products and specifications without notice. Permission is hereby expressly granted to copy this literature for informational purposes only. Copying this material for any other use is strictly prohibited. WARNING - LIFE SUPPORT APPLICATIONS POLICY - SPT products should not be used within Life Support Systems without the specific written consent of SPT. A Life Support System is a product or system intended to support or sustain life which, if it fails, can be reasonably expected to result in significant personal injury or death. Signal Processing Technologies believes that ultrasonic cleaning of its products may damage the wire bonding, leading to device failure. It is therefore not recommended, and exposure of a device to such a process will void the product warranty.
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