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TDA7429
DIGITALLY CONTROLLED AUDIO PROCESSOR WITH SURROUND SOUND MATRIX
1

FEATURES
3 STEREO INPUTS INPUT ATTENUATION CONTROL IN 0.5dB STEP TREBLE MIDDLE AND BASS CONTROL THREE SURROUND MODES ARE AVAILABLE - MUSIC: 4 SELECTABLE RESPONSES - MOVIE AND SIMULATED: 256 SELECTABLE RESPONSES
Figure 1. Package
SDIP42
TQFP44

Table 1. Order Codes
Part Number TDA7429S TDA7429T TDA7429T13TR Package SDIP42 TQFP44
FOUR SPEAKERS ATTENUATORS: - 4 INDEPENDENT SPEAKERS CONTROL IN 1dB STEPS FOR BALANCE FACILITY - INDEPENDENT MUTE FUNCTION
ALL FUNCTIONS PROGRAMMABLE VIA SERIAL BUS
2
DESCRIPTION
The TDA7429 is volume tone (bass middle and treble) balance (Left/Right) processors for quality audio applications in TV and Hi-Fi systems. Figure 2. Pin Connection (TQFP44)
so Ob
let
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LP1 HP1 HP2. 1 2 3 4 5 6 7 8 9 10 11
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PS1 PS2 43 42
so Ob R_IN4 R_IN3 R_IN2 40 39 VS 38 37 36 35 34 R_IN1 CREF PS4
It reproduces surround sound by using programmable phase shifters and a signal matrix. Control of all the functions is accomplished by serial bus. The AC signal setting is obtained by resistor networks and switches combined with operational amplifiers. Thanks to the used BIPOLAR/CMOS Technology, Low Distortion, Low Noise and DC stepping are obtained.
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ro P
uc d
Tape & Reel
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44
41
PS3
LP
33 32 31 30 29 28 27 26 25 24 23 12 BASS_RO 13 BASS_RI 14 MIDDLE_LO 15 MIDDLE_LI 16 MIDDLE_RO 17 MIDDLE_RI 18 TREBLE_R 19 TREBLE_L 20 AGND 21 SDA 22 SCL
MONITOR_R MONITOR_L L_IN1 L_IN2 L_IN3 L_IN4 AUXOUT_L AUXOUT_R L_OUT R_OUT DIG_GND
REAROUT REARIN VAR_L BASSO_L VAR_R BASSO_R BASS_LO BASS_LI
D96AU532
June 2004
REV. 6 1/22
TDA7429
Figure 3. PIN CONNECTION (SDIP42)
PS4 PS3 PS2 PS1 LP LP1 HP1 HP2 REAROUT REARIN VAR_L BASSO_L VAR_R BASSO_R BASS_LO BASS_LI BASS_RO BASS_RI MIDDLE_LO MIDDLE_LI MIDDLE_RO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
D97AU623
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
VS CREF R_IN3 R_IN2 R_IN1 MONITOR_R MONITOR_L L_IN1 L_IN2 L_IN3 AUXOUT_L AUXOUT_R L_OUT R_OUT DIG_GND SCL SDA AGND TREBLE_L TREBLE_R MIDDLE_RI
Table 2. Absolute Maximum Ratings
Symbol VS Tamb Tstg Operating Supply Voltage Operating Ambient Temperature Storage Temperature Range Parameter
Table 3. Quick Reference Data
Symbol VS VCL THD S/N SC Supply Voltage
Parameter
Max Input Signal Handling
Total Harmonic Distortion V = 0.1Vrms f = 1KHz Signal to Noise Ratio Vout = 1Vrms (mode = OFF) Channel Separation f = 1KHz Treble Control (2dB step) Middle Control (2dB step) Bass Control (2dB step) Balance Control 1dB step (LCH, RCH) Mute Attenuation -14 -14 -14 -79
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Symbol Rth j-pin
let
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11
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Unit V C C
Value
0 to 70 -55 to 150
Min. 7 2
Typ. 9
Max. 10.2
Unit V VRMS
0.01 106 90
0.1
% dB dB
14 14 14 0 100
dB dB dB dB dB
Table 4. Thermal Data
Parameter Thermal Resistance Junction-pins Value 85 Unit C/W
2/22
TDA7429
Figure 4. TEST CIRCUIT (TDA7429S)
2.2F 2.2F 2.2F 0.47F BASSO_R 22nF PS4 14 1 VAR_R 13 BASSO_L 12 VAR_L 11 REAROUT 9 REARIN 10 R_IN3 40 0.47F R_IN2 39 38 36 R_IN1 0.47F
22nF
PS3
2
MONITOR_L L_IN1 0.47F
4.7nF
PS2
3
35
100nF
PS1
4
34
L_IN2
0.47F
1.2nF
LP
5
33
L_IN3
0.47F
5.6nF
LP1
6 42 23
VS 10F 22F 100nF
5.6nF
TREBLE_R
5.6nF
TREBLE_L
24
100nF MONITOR_R 22nF 37
41
CREF
220nF 100nF 15 BASS_LO 100nF 16 BASS_LI
MIDDLE_LO
19
18nF MIDDLE_LI 22nF MIDDLE_RO 21 20
2.7K
17
BASS_RO
100nF
18nF
2.7K
MIDDLE_RI
22 32 31 30 29 R_OUT 28 DIG_GND 27 SCL 26 SDA 25 AGND HP2 8 HP1 680nF 7
18
AUXOUT_L AUXOUT_R L_OUT
D97AU626
Figure 5. TEST CIRCUIT (TDA7429T)
2.2F 2.2F
BASSO-R 22nF PS4 9 40
VAR-R 8
BASSO-L 7
22nF
PS3
41
4.7nF
PS2
42
100nF
1.2nF
5.6nF
let so Ob
5.6nF 5.6nF 100nF 22nF 18nF 2.7K 18nF 2.7K
ro P e
PS1 43 LP 44 LP1 1 TREBLE-R 18 TREBLE-L 19 33 MIDDLE-LO 14 MIDDLE-LI 15
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ct
s) (
6
VAR-L
REAROUT
so Ob 2.2F 0.47F REARIN R-IN4 4 5 37
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0.47F R-IN3 36 0.47F R-IN2
ro P
BASS_RI
100nF
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5.6K 5.6K
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35 34 32
R-IN1
0.47F
MONITOR_L L-IN1 0.47F
31
30
L-IN2
0.47F
29
L-IN3
0.47F
28 39
L-IN4 VS 10F
0.47F
100nF 22F
38
CREF
MONITOR_R
220nF 100nF 10 BASS-LO 100nF 11 BASS-LI 100nF
5.6K
22nF MIDDLE-RO 16
12
BASS-RO
100nF 17 27 AUXOUT-L 26 AUXOUT-R 25 L-OUT 24 R-OUT 23 DIG-GND 22 SCL 21 SDA 20 AGND HP2 3 HP1 680nF 2 13 BASS-RI
MIDDLE-RI
5.6K
D96AU533
3/22
MIDDLE-LI
MONITOR L PS1 43 RPS2 FIX RPS3 RPS4 RM RB 30K 42 41 19 15 10 7 6 14 11 40 PS2
LP1
HP1 PS3 PS4
HP2 TREBLE-L BASS-LI BASS-LO BASSO-L VAR-L
ro P e
0.47F RPS1
31
32
31.5dB 1 control
2
3
L-IN1
50K
0.47F
30 PS1 90Hz OFF SURR REC ATT 79dB CONTROL PS2 4KHz PS3 400Hz PS4 400Hz
RLP1 RHP1
MIDDLE-LO
let so Ob
28 SIM 3BAND MUSIC + MOVIE/ MUSIC OFF MOVIE/SIM MIXING AMP TREBLE MIDDLE BASS
REAR
s) t(
L-IN4
+
MUTE
FIX
50K + L-R
+
0.47F
34
I2C BUS DECODER + LATCHES
R-IN1
50K LPF 9KHz SURR EFFECT CONTROL MIXING AMP TREBLE MIDDLE BASS
0.47F
35
R-IN2
FIX
FIX VAR + 3BAND REAR SURR REC ATT
50K
so Ob -
0.47F
36 OFF
R-IN3
50K
0.47F
37 Vref 50K 44 LP REARIN 4 5
R-IN4
50K
te le
31.5dB control 18
SUPPLY
RM 17 16 13
RB 12
MUTE 79dB CONTROL BASSO-R BASS-RI 9 8
30K
33
39
20
38
MONITOR R CREF REAROUT 22F 2.2F 1.2nF
VS
TREBLE-R
VAR-R
D96AU513
AGND
MIDDLE-RI
ro P
5.6nF
18nF
22nF
MIDDLE-RO
100nF 2.7K 5.6K
100nF
THE SWITCHES POSITION MATCHES THE RESET CONDITION
BASS-RO
2.2F
+
0.47F
SURR
VAR
-
4/22
100nF 4.7nF 2.2F 22nF 22nF 5.6nF 100nF 2.7K 18nF 5.6K 22nF 100nF 27
TDA7429
5.6nF
680nF
L-IN2
uc d
50K
AUXOUT-L
Figure 6. Block Diagram (TDA7429T)
0.47F
29
L-IN3
R5
79dB CONTROL SPKR ATT MUTE
50K
R6
25
L-OUT
22 21 23
SCL SDA DIG GND
SPKR ATT
24
R-OUT MUTE 79dB CONTROL
26
AUXOUT-R
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MIDDLE_LI
MONITOR_L PS1 4 RPS2 FIX RPS3 RPS4 RM RB 30K 3 2 24 20 15 12 11 19 16 1 PS2
LP1
HP1 PS3 PS4 TREBLE_L
HP2 BASS_LI BASS_LO BASSO_L VAR_L
ro P e
100nF 4.7nF MIDDLE_LO 2.2F 22nF 22nF 5.6nF 100nF 2.7K 18nF 5.6K 22nF 100nF
let so Ob
RPS1
5.6nF
680nF
0.47F
36
35
31.5dB control
6
7
8
L_IN1
50K
0.47F PS1 90Hz OFF SURR REC ATT 79dB CONTROL PS2 4KHz PS3 400Hz PS4 400Hz
34
RLP1 RHP1
L_IN2
32
AUXOUT_L
Figure 7. Block Diagram (TDA7429S)
uc d
50K
0.47F
33
R5
79dB CONTROL VAR FIX FIX VAR SPKR ATT + MUTE
L_IN3 SURR REAR
R6
50K SIM 3BAND MUSIC + MOVIE/ MUSIC OFF MOVIE/SIM MIXING AMP TREBLE MIDDLE BASS
-
30
s) t(
MUTE
L_OUT
+
+
L-R
+
27 26 I2C BUS DECODER + LATCHES 28
SCL SDA DIG GND
0.47F LPF 9KHz SURR EFFECT CONTROL MIXING AMP TREBLE MIDDLE
38
BASS FIX
R_IN1
50K
so Ob -
0.47F
+ 3BAND REAR SURR REC ATT
SPKR ATT
39 OFF
29
R_OUT MUTE 79dB CONTROL
R_IN2
50K
0.47F
40 Vref 50K 5 LP REARIN 9 10
R_IN3
31 RM RB 30K MUTE
AUXOUT_R
te le
50K
31.5dB control 23
SUPPLY
37
42
25
41
22
21
18
17
79dB CONTROL BASSO_R
14
13 VAR_R
D97AU624A
AGND
CREF
MONITOR_R REAROUT 22F 2.2F 1.2nF
VS
TREBLE_R
BASS_RI
MIDDLE_RI
ro P
5.6nF 18nF 22nF 2.7K
MIDDLE_RO
100nF 5.6K
100nF
THE SWITCHES POSITION MATCHES THE RESET CONDITION
BASS_RO
2.2F
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TDA7429
5/22
TDA7429
Table 5. Electrical Characteristcs (refer to the test circuit Tamb = 25C, VS = 9V, R L = 10K, Vin = 1Vrms; RG = 600, all controls flat (G = 0dB), L+R CTRL = +4dB, MODE = OFF; f = 1KHz unless otherwise specified).
Symbol SUPPLY VS IS SVR Supply Voltage Supply Current Ripple Rejection LCH / RCH out, Mode = OFF 7 10 60 9 18 80 10.2 26 V mA dB Parameter Test Condition Min. Typ. Max. Unit
INPUT STAGE RIN VCL CRANGE AVMIN AVMAX ASTEP Input Resistance Clipping Level Control Range Min. Attenuation Max. Attenuation Step Resolution -1 31 THD = 0.3% 35 2 50 2.5 31.5 0 31.5 0.5 1 65 K Vrms dB
BASS CONTROL Gb BSTEP RB Control Range Step Resolution Internal Feedback Resistance Max. Boost/cut
MIDDLE CONTROL Gm MSTEP RM Control Range Step Resolution Internal Feedback Resistance
Max. Boost/cut
TREBLE CONTROL Gt TSTEP Control Range
Step Resolution
let so Ob
CRANGE SSTEP RPS10 RPS11 RPS12 RPS13 RPS20
EFFECT CONTROL
Control Range
Pr e
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11.5 1
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1
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1 3
32
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dB
dB dB
14.0 2
16.0
dB dB K
32
44
56
11.5
14.0 2 25
16.0 3 32.5
dB dB K
17.5
Max. Boost/cut
13.0 1
14.0 2
15.0 3
dB dB
-21 0.5 1
-6 1.5
dB dB
Step Resolution
SURROUBND SOUBND MATRIX PHASE Phase Shifter 1: D1 = 0, D0 = 0 Phase Shifter 1: D1 = 0, D0 = 1 Phase Shifter 1: D1 = 1, D0 = 0 Phase Shifter 1: D1 = 1, D0 = 1 Phase Shifter 2: D3 = 0, D2 = 0 8.3 10 12.6 26.4 4 11.8 14.1 17.9 37.3 5.6 15.2 18.3 23.3 48.85 7.2 K K K K K
6/22
TDA7429
Symbol Parameter Test Condition Min. Typ. Max. Unit
SURROUND SOUND MATRIX TEST CONDITION (Phase Resistor Selection D0=0, D1=1, D2=0. D3=1, D4=0, D5=1, D6=0, D7=1 RPS21 RPS22 RPS23 RPS30 RPS31 RPS32 RPS33 RPS40 RPS41 RPS42 RPS43 GOFF DGOFF GMOV Phase Shifter 2: D3 = 0, D2 = 1 Phase Shifter 2: D3 = 1, D2 = 0 Phase Shifter 2: D3 = 1, D2 = 1 Phase Shifter 3: D5 = 0, D4 = 0 Phase Shifter 3: D5 = 0, D4 = 1 Phase Shifter 3: D5 = 1, D4 = 0 Phase Shifter 3: D5 = 1, D4 = 1 Phase Shifter 4: D7 = 0, D6 = 0 Phase Shifter 4: D7 = 0, D6 = 1 Phase Shifter 4: D7 = 1, D6 = 0 Phase Shifter 4: D7 = 1, D6 = 1 In-phase Gain (OFF) LR In-phase Gain Difference (OFF) In-phase Gain (Movie) Mode OFF, Input signal of 1kHz, 1.4 Vp-p, Rin Rout , Lin Lout Mode OFF, Input signal of 1kHz, 1.4 Vp-p, Rin Rout , Lin Lout Movie mode, Effect Ctrl = -6dB 1kHz, 1.4 Vp-p, Rin Rout , Lin Lout Movie mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p (Rin Rout) - (Lin Lout) Music mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p (Rin Rout) , (Lin Lout) Music mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p (Rin Rout) , (Lin Lout) Simulated Mode, Effect Ctrl = -6dB Input signal of 250Hz, 1.4 Vp-p, Rin and Lin Lout Simulated Mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p, Rin and Lin Lout Simulated Mode, Effect Ctrl = -6dB Input signal of 3.6kHz, 1.4 Vp-p, Rin and Lin Lout Simulated Mode, Effect Ctrl = -6dB Input signal of 250Hz, 1.4 Vp-p, Rin and Lin Rout 4.8 6 12.9 8.5 10.2 12.7 27.4 8.5 10.2 12.7 27.4 -1 -1 6.8 8.4 18.3 12.1 14.5 18.1 39.1 12.1 14.5 18.1 39.1 8.7 10.9 23.7 15.6 18.7 23.3 50.75 15.6 18.7 23.3 K K K K K K K K K K
DGMOV
LR In-phase Gain Difference (Movie) In-phase Gain (Music)
GMUS
DGMUS
LR In-phase Gain Difference (Music) Simulated L Output 1
LMON1
so Ob
LMON2 LMON3 RMON1
let
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Pr te le
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0 0 8 0
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1 1
50.75
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K dB dB dB
dB
7
dB
0
dB
4.5
dB
Simulated L Output 2
-4.0
dB
Simulated L Output 3
7.0
dB
Simulated R Output 1
- 4.5
dB
7/22
TDA7429
Symbol RMON2 Parameter Simulated R Output 2 Test Condition Simulated Mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p, Rin and Lin Rout Simulated Mode, Effect Ctrl = -6dB Input signal of 3.6kHz, 1.4 Vp-p, Rin and Lin Rout 7 42 7 Min. Typ. 3.8 Max. Unit dB
RMON3
Simulated R Output 3
- 20
dB
RLP1 RHPI RLPF
Low Pass Filter Resistance High Pass Filter Resistance LP Pin Impedance
10 60 10
13 78 13
K K K
SPEAKER & AUX ATTENUATORS CRANGE SSTEP EA Control Range Step Resolution Attenuation set error Av = 0 to -20dB Av = -20 to -79dB VDC AMUTE RVEA DC Steps Output Mute Condition Input Impedance adjacent att. steps -0.5 -1.5 -3 -3 +70 79 1 0 0 1.5 dB
1.5
AUDIO OUTPUTS NO(OFF) NO(MOV) NO(Mus) Output Noise (OFF) Output Noise (Movie) Output Noise (Music) Output Mute, Flat BW = 20Hz to 20KHz Mode = Movie BW = 20Hz to 20KHz
NO(MON) Output Noise (Simulated) d SC VOCL ROUT VOUT Distorsion
Channel Separation Clipping Level
so Ob
d SC VOCL ROUT VOUT
Output Resistance DC Voltage Level
let
od Pr e
ct u
s) (
Mode = Music BW = 20Hz to 20KHz Mode Simulated BW = 20Hz to 20KHz Av = 0 ; Vin = 1Vrms 70 d = 0.3% 2 25
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so
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21
Pr
od
0 100 30 4 5 30 30 30 0.01 90 2.5 50 3.8
uc
2 3
s) t(
dB dB dB
mV dB
39
K
Vrms Vrms Vrms Vrms Vrms 0.1 % dB Vrms 85 V
MONITOR OUTPUTS Distorsion Channel Separation Clipping Level Output Resistance DC Voltage Level d = 0.3% Av = 0 ; Vin = 1Vrms 70 2 20 0.01 90 2.5 50 4.5 85 0.1 % dB Vrms V
8/22
TDA7429
Symbol BUS INPUTS VIL VIH IIN VO Input Low Voltage Input High Voltage Input Current Output Voltage SDA Acknowledge IO = 1.6mA 3 -5 +5 0.4 1 V V mA V Parameter Test Condition Min. Typ. Max. Unit
3
I2C BUS INTERFACE
Data transmission from microprocessor to the TDA7429 and viceversa takes place through the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected). 3.1 Data Validity As shown in fig. 8, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. 3.2 Start and Stop Conditions As shown in fig.9 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. 3.3 Byte Format Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. 3.4 Acknowledge The master (mP) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 10). The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line during this clock pulse. The audioprocessor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer.
let so Ob
3.5 Transmission without Acknowledge Avoiding to detect the acknowledge of the audioprocessor, the P can use a simpler transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking.
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9/22
TDA7429
Figure 8. Data validity on the I2C bus
SDA
SCL DATA LINE STABLE, DATA VALID CHANGE DATA ALLOWED
D99AU1031
Figure 9. Timing Diagram of I2C bus
SCL I2CBUS SDA
D99AU1032
START
STOP
Figure 10. Acknowledge on the I2C bus
SCL
1
2
3
7
SDA MSB
s) 4 SOFTWARE SPECIFICATION ct( du ro P ete ol bs O
4.1 Interface Protocol The interface protocol comprises:

START
D99AU1033
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8
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9
s) t(
ACKNOWLEDGMENT FROM RECEIVER
A start condition (S) A subaddress bytes A stop condition (P)
A chip address byte, containing the TDA7429 address A sequence of data (N byte + achnowledge)
Figure 11.
CHIP ADDRESS MSB S 1 0 0 0 0 0 A LSB 0 ACK MSB B
SUBADDRESS LSB DATA ACK MSB
DATA 1 to DATA n LSB DATA ACK P
D95AU226A
10/22
TDA7429
5
EXAMPLES
5.1 No Incremental Bus The TDA7429 receives a start condition, the correct chip address, a subaddress with the MSB = 0 (no incremental bus), N-datas (all these datas concern the subaddress selected), a stop condition. Figure 12.
CHIP ADDRESS MSB S 1 0 0 0 0 0 A LSB 0 ACK MSB 0 X X SUBADDRESS LSB X D3 D2 D1 D0 ACK MSB DATA DATA LSB ACK P
D95AU306
5.2 Incremental Bus The TDA7429 receives a start condition, the correct chip address, a subaddress with the MSB = 1 (incremental bus): now it is in a loop condition with an autoincrease of the subaddress whereas SUBADDRESS from "1XXX1010" to "1XXX1111" of DATA are ignored.The DATA 1 concern thesubaddress sent, and the DATA 2 concern the subaddress sent plus one in the loop etc, and at the end it receivers the stop condition. Figure 13.
CHIP ADDRESS MSB S 1 0 0 0 0 0 A LSB 0 ACK MSB 1 X X SUBADDRESS LSB MSB
DATA 1 to DATA n
X D3 D2 D1 D0 ACK
D95AU307
6
DATA BYTES
Address = 80(HEX) 6.1 Function Selection
Table 6. The first byte (Subaddress)
MSB
let so Ob
B B B B B B B B B B X X X X X X X X X X
D7
D6
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D5 X X X X X X X X X X D4 X X X X X X X X X X
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D3 0 0 0 0 0 0 0 0 1 1
s) t(
D2 0 0 0 0 1 1 1 1 0 0
so Ob LSB D1 0 0 1 1 0 0 1 1 0 0 D0 0 1 0 1 0 1 0 1 0 1
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DATA
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s) t(
ACK
LSB P
SUBADDRESS INPUT ATTENUATION SURROUND & OUT & EFFECT CONTROL PHASE RESISTOR BASS & NATURAL BASE MIDDLE & TREBLE SPEAKER ATTENUATION "L" SPEAKER ATTENUATION "R" AUX ATTENUATION "L" AUX ATTENUATION"R" INPUT MULTIPLEXER, & AUX OUT
B = 1 incremental bus; active B = 0 no incremental bus; X = indifferent 0,1
11/22
TDA7429
Table 7. INPUT ATTENUATION SELECTION
MSB D7 X X X X X X X X D6 D5 D4 D3 D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 LSB D0 0 1 0 1 0 1 0 1 INPUT ATTENUATION 0.5 dB STEPS 0 -0.5 -1 -1.5 -2 -2.5 -3 -3.5
4 dB STEPS X X X X X X X X 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0
INPUT ATTENUATION = 0 ~ -31.5dB
let so Ob
Table 8.
D7 X D6 0 X 1
ro P e
D5
uc d
D4
s) t(
D3
1
so Ob -
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ro P
uc d
0 -4 -8 -12 -16 -20 -24 -28
s) t(
D2
D1
D0
REAR SWITCH REARIN, REAROUT PIN ACTIVE NO REARIN, REAROUT PIN
12/22
TDA7429
Table 9. SURROUND SELECTION
MSB D7 X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D6 D5 D4 D3 D2 D1 0 0 1 1 LSB D0 0 1 0 1 SURROUND MODE SIMULATED MUSIC OFF MOVIE OUT VAR FIX EFFECT CONTROL -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 -16 -17 -18 -19 -20 -21
0 1
Table 10. PHASE RESISTOR SELECTION
MSB D7 D6 D5 D4
so Ob
0 0 1 1
let
Pr e
0 0 1 1
du o
0 1 0 1
ct
s) (
D3 0 0 1 1
so Ob D2 D1 0 0 1 1
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LSB D0 0 1 0 1
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s) t(
0 1 0 1
0 1 0 1
SURROUND PHASE RESISTOR PHASE SHIFT 1 (K) 12 14 18 37 PHASE SHIFT 2 (K) 6 7 8 18 PHASE SHIFT 3 (K) 12 14 18 39 PHASE SHIFT 4 (K) 12 14 18 39
13/22
TDA7429
Table 11. BASS SELECTION
MSB D7 X X X X X X X X X X X X X X X X D6 X X X X X X X X X X X X X X X X D5 X X X X X X X X X X X X X X X X D4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 D1 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 LSB D0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 BASS 2 dB STEPS -14 -12 -10 -8 -6 -4 -2 0 0 2 4 6 8 10 12 14
Table 12. SPEAKER/AUX ATT. R & L SELECTION
MSB D7 X X X X X X X X X X X X X X X X X X X X 0 0 D6 D5 D4 D3 D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1
so Ob
let
0 0 0 0 0 0 1 1 1 1
Pr e
0 0 0 0 1 1 1 1 0 0 0 1
od
uc
0 0 1 1 0 0 1 1 0 0 1 X
s) t(
0 1 0 1 0 1 0 1 0 1 X X
so Ob -
te le
LSB D0 0 1 0 1 0 1 0 1
ro P
uc d
-1 -2 -3 -4 -5 -6 -7
s) t(
SPEAKER/AUX ATT 1 dB STEPS 0
8 dB STEPS 0 -8 -16 -24 -32 -40 -48 -56 -64 -72 MUTE
X = INDIFFERENT 0,1 SPEAKER/AUX ATTENUATION = 0dB ~ -79dB
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TDA7429
Table 13. MIDDLE & TREBLE SELECTION
MSB D7 D6 D5 D4 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 D1 0 0 1 1 0 0 1 1 1 1 0 0 1 1 LSB D0 0 1 0 1 0 1 0 1 1 0 1 0 1 MIDDLE 2 dB STEPS -14 -12 -10 -8 -6 -4 -2 0 0
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0
0 0 1 1
0 1 0
let so Ob
od Pr e
0 1 1 1 1 0 0 1 1 0 0
0
uc
1 0 1 0 1 1 0 1 0 1 0 1 0
s) t(
Ob -
so
te le
0
0
Pr
0 1 0
od
uc
s) t(
2 4 6 8
10 12 14 TREBLE 2 dB STEPS -14 -12 -10 -8 -6 -4 -2 0 0 2 4 6 8 10 12 14
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TDA7429
Table 14. INPUT/RECOUT L & R SELECTION
MSB D7 X X X X D6 D5 D4 D3 D2 0 0 1 1 D1 0 1 0 1 LSB D0 0 0 0 0 INPUT MULTIPLEXER IN2 IN3 IN4 IN1 AUX OUT "L" X X X X 0 0 1 1 0 1 0 1 0 0 0 0 VER 1 (3BAND) VER 2 (SURR) VER 3 (REAR) FIX AUX OUT "R" X X X X 0 0 1 1 0 1 0 1 0 0 0 0
VER 1 (3BAND)
Table 15.
POWER ON RESET BASS & MIDDLE TREBLE
SURROUND & OUT CONTROL+ EFFECT CONTROL SPEAKER/AUX ATTENUATION L &R
INPUT ATTENUATION + REAR SWITCH NATURAL BASE INPUT
Figure 14. PIN: VOUT REF
so Ob
let
VS
ro P e
25K
du
ct
s) (
so Ob -
te le
ro P
uc d
FIX
VER 2 (SURR) VER 3 (REAR)
s) t(
2dB 0dB
OFF + FIX + MAX ATTENUATION MUTE
MAX ATTENUATION + ON OFF IN1
Figure 15. PIN: TREBLE-L, TREBLE-R
VS
20A
20A
GND GND 10K GND
D95AU309 D95AU233A
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TDA7429
Figure 16. PIN: HP1 Figure 19. PIN: L-IN, R-IN, L-IN2, R-IN2, L-IN3, R-IN3, L-IN4, R-IN4,
LP1
VS 10K
VS 20A
60K GND
D94AU198
50K GND
HP2
VREF
D94AU200
Figure 17. PIN: HP2
Figure 20. PIN: LP1
VS
VS 20A 5.5K 60K GND
D94AU199
HP1
5.5K
Figure 18. PIN: VAR-L, VAR-R,
let so Ob
VS GND Vref
Pr e
SW
od
ct u
s) (
so Ob -
te le
GND
ro P
10K
uc d
s) t(
20A
HP1
D94AU211
Figure 21. PIN: CREF
VS
20A
20K 42K
20A
30K
D95AU227
20K
D95AU336
GND
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TDA7429
Figure 22. PIN: SCL, SDA Figure 25. PIN: L-OUT, R-OUT, MONITOR-L, MONITOR-R REAROUT, BASSO-L, BASSO-R, AUXOUT_L, AUXOUT_R
VS 20A 20A
GND
D94AU205
GND
D95AU230
Figure 23. PIN: PS1, PS2, PS3, PS4, LP
Figure 26. PIN: BASS-LI, BASS-RI, MIDDLE-LI, MIDDLE-RI,
VS
VS
20A
GND
Figure 24. PIN: REARIN
let so Ob
VS GND Vref
Pr e
SW
od
ct u
D95AU308
s) (
so Ob -
te le
ro P
uc d
20A
s) t(
GND
BASS-LO
45K : Bass or 25K : MIDDLE
D95AU231A
BASS-RO,MIDDLE-LO,MIDDLE-RO
Figure 27. PIN: BASS-LO, BASS-RO, MIDDLELO, MIDDLE-RO,
VS
20A
20A
(*) GND
50K
BASS-LI,BASS-RI,MIDDLE-LI,MIDDLE-RI
D95AU232
D95AU229
(*) 45K : Bass 25K : MIDDLE
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TDA7429
Figure 28. TQFP44 (10 x 10) Mechanical Data & Package Dimensions
mm DIM. MIN. A A1 A2 B C D D1 D3 E E1 E3 e L L1 k 0.45 11.80 9.80 0.05 1.35 0.30 0.09 11.80 9.80 12.00 10.00 8.00 12.00 10.00 8.00 0.80 0.60 1.00 0.75 0.018 12.20 10.20 0.464 0.386 1.40 0.37 TYP. MAX. 1.60 0.15 1.45 0.45 0.20 12.20 10.20 0.002 0.053 0.012 0.004 0.464 0.386 0.472 0.394 0.315 0.472 0.394 0.315 0.031 0.024 0.039 0.030 0.480 0.401 0.055 0.015 MIN. TYP. MAX. 0.063 0.006 0.057 0.018 0.008 0.480 0.401 inch
OUTLINE AND MECHANICAL DATA
TQFP44 (10 x 10 x 1.4mm)
0(min.), 3.5(typ.), 7(max.)
D D1
33 34
let so Ob
B
Pr e
44 1
od
ct u
s) (
23 22
so Ob -
te le
ro P
uc d
s) t(
A A2 A1
0.10mm .004 Seating Plane
E1
12 11
E
B C L K
e
TQFP4410
0076922 D
19/22
TDA7429
Figure 29. SDIP42 Mechanical Data & Package Dimensions
DIM. MIN. A A1 A2 B B1 c D E E1 e e1 e2 e3 L 2.54 0.51 3.05 0.38 0.89 0.23 36.58 15.24 12.70
mm TYP. MAX. 5.08 0.020 3.81 0.46 1.02 0.25 36.83 4.57 0.56 1.14 0.38 37.08 16.00 13.72 1.778 15.24 18.54 1.52 3.30 3.56 0.10 14.48 0.120 MIN.
inch TYP. MAX. 0.20
OUTLINE AND MECHANICAL DATA
0.150
0.180
0.0149 0.0181 0.0220 0.035 0.040 0.045
0.0090 0.0098 0.0150 1.440 0.60 0.50 0.540 0.070 0.60 0.730 0.060 0.130 0.140 1.450 1.460 0.629 0.570
let so Ob
42 1
od Pr e
B
B1
e
L
ct u
D
A1
A2
A
s) (
so Ob -
te le
SDIP42 (0.600")
ro P
uc d
s) t(
E E1
e1 e2
c E 22
.015 0,38 Gage Plane
21
SDIP42
e3 e2
20/22
TDA7429
Table 16. Revision History
Date January 2004 June 2004 Revision 5 6 Description of Changes First Issue in EDOCS DMS Changed the Style-sheet in compliance to the new "Corporate Technical Pubblications Design Guide"
let so Ob
ro P e
uc d
s) t(
so Ob -
te le
ro P
uc d
s) t(
21/22
TDA7429
let so Ob
ro P e
uc d
s) t(
so Ob -
te le
ro P
uc d
s) t(
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com
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