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Preliminary Datasheet Version 1.02, March 2009
ICB1FL03G Smart Ballast Control IC for Fluorescent Lamp Ballasts
Industrial & Multimarket
ICB1FL03G Revision History: Previous Version: Page 2009-03 V 1.01 V 1.02
Subjects (major changes since last revision)
Edition 2009-03 Published by Infineon Technologies AG 81726 Munich, Germany (c) 2009 Infineon Technologies AG. All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
ICB1FL03G
Smart Ballast Control IC for Fluorescent Lamp Ballasts
Product Highlights
* Lowest Count of external Components * HV-Driver with coreless Transformer Technology * Improved Reliability and minimized Spread due to digital and optimized analog control functions
PG-DSO-18-2
PG-DSO-18-1
Features PFC
* * * * Discontinuous Conduction Mode PFC Integrated Compensation of PFC Control Loop Adjustable PFC Current Limitation Adjustable PFC Bus Voltage
Description
The Smart Ballast IC is designed to control a Fluorescent Lamp Ballast including a Discontinuous Conduction Mode Power Factor Correction (PFC), a lamp Inverter Control and a High Voltage Level Shift Half-Bridge Driver. Features Lamp Ballast Inverter The application requires a minimum of external * Supports Restart after Lamp Removal and End-of- components. There are integrated low pass filters and an Life Detection even in serial Multi-Lamp Topologies internal compensation for the PFC voltage loop control. * End-of-Life (EOL) detected by adjustable Preheating time is adjustable by a single resistor only in Thresholds of sensed lamp voltage the range between 0 and 2000ms. In the same way the * Rectifier Effect detected by ratio of Amplitude of preheating frequency and run frequency are set by Lamp Voltage resistors only. The control concept covers requirements * Detection of different capacitive Mode Operations for T5 lamp ballasts such as detection of end-of-life and * Adjustable Inverter Overcurrent Shutdown detection of capacitive mode operation and other * Self-adaption of Ignition Time from 40ms to 235ms protection measures in serial multilamp topologies. * Parameters adjustable by Resistors only ICB1FL03G is easy to use and easy to design and * Pb-free lead plating; RoHS compliant therefore a basis for a cost effective solution for * Halogen-free mould compound, WEEE compliant fluorescent lamp ballasts.
R41 C5 L10 C1 D1...4 C4 R1 R2 90 ... 270 VAC PE C3 C2
GND VCC
R42 R43
L1 D5
R34 R13 R14 ICB1FL03G
PFCZCD
R35 Q2
HSGD HSVCC HSGND PFCGD PFCVS
K2 C17 C15 L2
K1
LVS
R26
Q1
R15 R16
R11 C10 R3 R12 R18 R19 C11 R20 D9 C12
PFCCS RFRUN RFPH
LSGD LSCS RTPH RES
C14 R27
Q3 C16 C18 K6
C24
D6 R61
K5 R36
D7
R21R22R23 C13 C61 SMD
R30
R24R25
D8
D61 C19 SMD-Z
Type ICB1FL03G
Package PG-DSO-18-2
Preliminary Datasheet Version 1.02
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ICB1FL03G
Table of Contents 1 1.1 1.2 2 3 3.1 3.2 3.3 3.4 3.5 3.6 4 5 6 6.1 6.2 6.3 6.3.1 6.3.2 6.3.2.1 6.3.2.2 6.3.2.3 6.3.2.4 6.3.2.5 6.3.3 6.3.3.1 6.3.3.2 6.3.3.3 6.3.3.4 6.3.3.5 6.3.3.6 7 7.1 7.2 7.3 8
Page
Pin Configuration and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Pin Configuration PG-DSO-18-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Typical operating levels during start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 PFC Preconverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Typical operating levels during start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Detection of End-of-Life and Rectifier Effect . . . . . . . . . . . . . . . . . . . . . . . .14 Detection of capacitive mode operating conditions . . . . . . . . . . . . . . . . . . .15 Interruption of Operation and Restart after Lamp Removal . . . . . . . . . . . . .16 State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Power Supply Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 PFC Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 PFC Current Sense (PFCCS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 PFC Zero Current Detector (PFCZCD) . . . . . . . . . . . . . . . . . . . . . . . .23 PFC Bus Voltage Sense (PFCVS) . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 PFC PWM Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 PFC Gate Drive (PFCGD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Inverter Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Inverter Control (RFRUN, RFPH, RTPH) . . . . . . . . . . . . . . . . . . . . . .25 Inverter Low Side Current Sense (LSCS) . . . . . . . . . . . . . . . . . . . . . .25 Restart after Lamp Removal (RES) . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Lamp Voltage Sense (LVS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Inverter Low Side Gate Drive (LSGD) . . . . . . . . . . . . . . . . . . . . . . . . .27 Inverter High Side Gate Drive (HSGD) . . . . . . . . . . . . . . . . . . . . . . . .28 Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Operating Behaviour of a Ballast for a single Fluorescent Lamp . . . . . . . . .29 Design Equations of a Ballast Application . . . . . . . . . . . . . . . . . . . . . . . . . .30 Multilamp Ballast Topologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
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Pin Configuration and Description
1
1.1
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Pin Configuration and Description
Pin Configuration PG-DSO-18-2
Symbol LSCS LSGD VCC GND PFCGD PFCCS PFCVS RFRUN RFPH RTPH RES LVS n.c. n.e. n.e. HSGND HSVCC HSGD HSGND Function Low side current sense (inverter) Low side gate drive (inverter) Supply voltage Controller ground PFC gate drive PFC current sense PFC voltage sense Set R for run frequency Set R for preheating frequency Set R for preheating time Restart after lamp removal Lamp voltage sense Not connected Not existing Not existing High side ground High side supply voltage High side gate drive High side ground
1.2
Pin Description
PFCZCD PFC zero current detector
LSCS (Low side current sense, Pin 1) This pin is directly connected to the shunt resistor which is located between the Source terminal of the low-side MOSFET of the inverter and ground. Internal clamping structures and filtering measures allow for sensing the Source current of the low-side inverter MOSFET without additional filter components. There is a first threshold of 0,8V, which provides a couple of increasing steps of frequency during ignition mode, if exceeded by the sensed current signal for a time longer than 250ns. If the sensed current signal exceeds a second threshold of 1,6V for longer than 400ns during all operating modes, a latched shut down of the IC will be the result. LSGD (Low side gate drive, Pin 2) The Gate of the low-side MOSFET in a half-bridge inverter topology is controlled by this pin. There is an active L-level during UVLO (undervoltage lockout) and a limitation of the max. H-level at 11V during normal operation. Turning on the MOSFET softly (with reduced diDRAIN/dt), the Gate drive voltage rises within 220ns from L-level to H-level. The fall time of the Gate drive voltage is less than 50ns in order to turn off quickly. This measure produces different switching speeds during turn-on and turn-off as it is usually achieved with a diode in parallel to a resistor in the Gate drive loop. It is recommended to use a resistor of about 15Ohm between drive pin and Gate in order to avoid oscillations and in order to shift the power dissipation of discharging the Gate capacitance into this resistor. The dead time between LSGD signal and HSGD signal is 1800ns typically. VCC (Supply voltage, Pin 3) This pin provides the power supply of the ground related section of the IC. There is a turn-on threshold at 14V and an UVLO threshold at 10,5V. Upper supply voltage level is 17,5V. There is an internal zener diode clamping Vcc at 16V (2mA typically). The zener current is internally limited to 5mA max. For higher current levels an external zener diode is required. Current consumption during UVLO and during fault mode is less than 150A. A ceramic capacitor close to the supply and GND pin is required in order to act as a lowimpedance power source for Gate drive and logic signal currents. GND (Ground, Pin 4) This pin is connected to ground and represents the ground level of the IC for supply voltage, Gate drive and sense signals.
LSCS LSGD VCC GND PFCGD PFCCS PFCZCD PFCVS RFRUN RFPH
1 2 3
20 19 18
N.C. HSGD HSVCC HSGND
ICB1FL03G
4 5 6 7 8 9 10
17 16 15 14 13 12 11
N.C. LVS RES RTPH
PG-DSO-18-2 (300mil)
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ICB1FL03G
Pin Configuration and Description
PFCGD (PFC gate drive, Pin 5) The Gate of the MOSFET in the PFC preconverter designed in boost topology is controlled by this pin. There is an active L-level during UVLO and a limitation of the max. H-level at 11V during normal operation. Turning on the MOSFET softly (with a reduced diDRAIN/ dt), the Gate drive voltage rises within 220ns from Llevel to H-level. The fall time of the Gate voltage is less than 50ns in order to turn off quickly. A resistor of about 15 between drive pin and Gate in order to avoid oscillations and in order to shift the power dissipation of discharging the Gate capacitance into this resistor is recommended. The PFC section of the IC controls a boost converter as a PFC preconverter in discontinuous conduction mode (DCM). Typically the control starts with Gate drive pulses with an on-time of 1s increasing up to 24s and a off-time of 40s. As soon as a sufficient ZCD (zero current detector) signal is available, the operating mode changes from a fixed frequent operation to an operation with variable frequency. During rated and medium load conditions we get an operation with critical conduction mode (CritCM), that means triangular shaped currents in the boost converter choke without gaps when reaching the zero level and variable operating frequency. During light load (detected by the internal error amplifier) we get an operation with discontinuous conduction mode (DCM), that means triangular shaped currents in the boost converter choke with gaps when reaching the zero level and variable operating frequency in order to avoid steps in the consumed line current. PFCCS (PFC current sense, Pin 6) The voltage drop across a shunt resistor located between Source of the PFC MOSFET and GND is sensed with this pin. If the level exceeds a threshold of 1V for longer than 260ns the PFC Gate drive is turned off as long as the ZCD (zero current detector) enables a new cycle. If there is no ZCD signal available within 40s after turn-off of the PFC Gate drive, a new cycle is initiated from an internal start-up timer. PFCZCD (PFC zero current detection, Pin 7) This pin senses the point of time when the current through the boost inductor becomes zero during offtime of the PFC MOSFET in order to initiate a new cycle. The moment of interest appears when the voltage of the separate ZCD winding changes from positive to negative level which represents a voltage of zero at the inductor windings and therefore the end of current flow from lower input voltage level to higher output voltage level. There is a threshold with hysteresis, for increasing voltage a level of 1,5V, for decreasing voltage a level of 0,5V, that detects the change of inductor voltage. A resistor connected between ZCD winding and sense input limits the sink and source current of the sense pin, when the voltage of the ZCD winding exceeds the internal clamping levels (6,3V and -2,9V @ 4mA) of the IC. If the sensed level of the ZCD winding is not sufficient (e.g. during start-up), an internal start-up timer will initiate a new cycle every 40s after turn-off of the PFC Gate drive. PFCVS (PFC voltage sense, Pin 8) The intermediate circuit voltage (bus voltage) at the smoothing capacitor is sensed by a resistive divider at this pin. The internal reference voltage for rated bus voltage is 2,5V. There are further thresholds at 0,375V (15% of rated bus voltage), 1,83V (73% of rated bus voltage) and 2,725V (109% of rated bus voltage) for detecting open control loop, undervoltage and overvoltage. RFRUN (Set R for run frequency, Pin 9) A resistor from this pin to ground sets the operating frequency of the inverter during run mode. Typical run frequency range is 20kHz to 100kHz. The set resistor RRFRUN can be calculated based on the run frequency fRUN according to the equation R RFRUN 8 = 5 10 Hz ---------------------------f RUN
RFPH (Set R for preheating frequency, Pin 10) A resistor from this pin to ground sets together with the resistor at pin 9 the operating frequency of the inverter during preheat mode. Typical preheat frequency range is run frequency (as a minimum) to 150kHz. The set resistor RRFPH can be calculated based on the preheat frequency fPH and the resistor RRFRUN according to the equation: R RFRUN R = ------------------------------------------------RFPH f PH R RFRUN ---------------------------------------- - 1 8 5 10 Hz The total value of both resistors RRFPH and RRFRUN switched in parallel should not be less than 3,3kOhm. RTPH (Set R for preheating time, Pin 11) A resistor from this pin to ground sets the preheating time of the inverter during preheat mode. A set resistor range from zero to 18kOhm corresponds to a range of preheating time from zero to 2000ms subdivided in 127 steps. RES (Restart after lamp removal, Pin 12) A source current out of this pin via resistor and filament to ground monitors the existence of the low-side filament of the fluorescent lamp for restart after lamp
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ICB1FL03G
Pin Configuration and Description
removal. A capacitor from this pin directly to ground eliminates a superimposed AC voltage that is generated as a voltage drop across the low-side filament. During typical start-up with connected filaments of the lamp a current source IRES3 (20A) is active as long as Vcc> 10,5V and VRES< VRESC1 (1,6V). An open Lowside filament is detected, when VRES> VRESC1. Such a condition will prevent the start-up of the IC. In addition the comparator threshold is set to VRESC2 (1,3V) and the current source changes to IRES4 (17A). Now the system is waiting for a voltage level lower than VRESC2 at the RES-Pin that indicates a connected low-side filament, which will enable the start-up of the IC. An open high-side filament is detected when there is no sink current ILVSsink (15A) into the LVS-Pin before the VCC start-up threshold is reached. Under these conditions the current source at the RES-Pin is IRES1 (41A) as long as Vcc> 10,5V and VRES< VRESC1 (1,6V) and the current source is IRES2 (34A) when the threshold has changed to VRESC2 (1,3V). In this way the detection of the high-side filament is mirrored to the levels on the RES-Pin. Finally there is a delay function implemented at the RES-Pin. When a fault condition happens e.g. by an end-of-life criteria the inverter is turned-off. In some topologies a transient AC lamp voltage may occur immediately after shut down of the Gate drives which could be interpreted as a lamp removal. In order to generate a delay for the detection of a lamp removal the capacitor at the RES-Pin is charged by the IRES3 (20A) current source up to the threshold VRESC1 (1,6V) and discharged by an internal resistor RRESdisch , which operates in parallel to the external sense resistor at this pin, to the threshold VRESC3 (0,375V). The total delay amounts to 32 of these cycles, which corresponds to a delay time between 30ms to 100ms dependent on capacitor value. In addition this pin is applied to sense capacitive mode operation by use of a further capacitor connected from this pin to the nod of the high-side MOSFET's Source terminal and the low-side MOSFET's Drain terminal. The sense capacitor and the filter capacitor are acting as a capacitive voltage divider that allows for detecting voltage slopes versus timing sequence and therefore indicating capacitive mode operation. A typical ratio of the capacitive divider is 410V/2,2V which results in the capacitor values e.g. of 10nF and 53pF (56pF). LVS (Lamp voltage sense, Pin 13) Before the IC enters the softstart mode this pin has to sense a sink current above 26A (max) which is fed via resistors from the bus voltage across the high-side filament of the fluorescent lamp in order to monitor the existence of the filament for restart after lamp removal. Together with RES (pin 12) the IC can monitor the lamp removal of totally 2 lamps in series. During run mode the lamp voltage is sensed by the AC current fed into this pin via resistors. Exceeding one of the two thresholds of either +215A or -215A cycle by cycle for longer than 610s, the interpretation of this event is a failure due to EOL1 (end-of-life). A rectifier effect (EOL2) is assumed if the ratio of the sequence of positive and negative amplitudes is above 1,15 or below 0,85 for longer than 500ms. A failure due to EOL1 or EOL2 changes the operating mode from run mode into a latched fault mode that stops the operation until a reset occurs by lamp removal or by cycle of power. EOL1 and EOL2 require an AC current with zerocrossings at LVS-Pin for a reliable detection. A DC current at LVS-Pin results in a definite turn-off action acc. to EOL1 only if the sensed current exceeds the threshold ILVSEOLDC= +/-175A (typically). If the functionality of this pin is not required it can be disabled by connecting this pin to ground. Not Connected (Pin 14) This pin is internally not connected. HSGND (High side ground, Pin 17) This pin is connected to the Source terminal of the high-side MOSFET, which is also the nod of high-side and low-side MOSFET. This pin represents the floating ground level of the high-side driver and high-side supply. HSVCC (High side supply voltage, Pin 18) This pin provides the power supply of the high-side ground related section of the IC. An external capacitor between pin 15 and 16 acts like a floating battery which has to be recharged cycle by cycle via high voltage diode from low-side supply voltage during on-time of the low-side MOSFET. There is an UVLO threshold with hysteresis that enables high-side section at 10,1V and disables it at 8,4V. HSGD (High side gate drive, Pin 19) The Gate of the high-side MOSFET in a half-bridge inverter topology is controlled by this pin. There is an active L-level during UVLO and a limitation of the max. H-level at 11V during normal operation. The switching characteristics are the same as described for LSGD (pin 2). It is recommended to use a resistor of about 15Ohm between drive pin and Gate in order to avoid oscillations and in order to shift the power dissipation of discharging the Gate capacitance into this resistor. The dead time between LSGD signal and HSGD signal is 1800ns typically. HSGND (High side ground, Pin 20) This pin is internally connected with pin 17.
Preliminary Datasheet Version 1.02
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2
Figure 1
dac4 Peak Rectification ILVS HS
1
5V Other Modes Run Mode 5,0V Coreless T.
T2 D2 I OSC G1 T1 D1 T2 T1 OP Bias Cell 1 dac7 R1 S2 OP O SC Bias Cell 2 LS
1
H = on L = off
HSVCC
1 G1
OFF_ H
18 19 17 3
I1 = 5A
POWE R_DOWN_L
VPEAK(N+1) VPEAK(N)
VPEAK(N)
C2 N Z1
EOLOFF_L
& G2
=
S1
HSGD
2,0V
N+2 VPEAK(N+1)
DQ G3 EN
Oscillator
13
N+1 Q
r vef
LVS
HSGD VCC
T2 D2 G1 D1 T1 Z1
IL VS 0 220ns t 2,5V
RFRUN & G6
D2
EN=L => S tatus Latched
> 1,15.........=> Q = H = 0,85..1,15=> Q = L < 0,85........=> Q = H
Iosc HSGND
fosc
VGAT E slope control Z1 =12V
D1 1 G5
D3
T1
VCC LSGD
1 G4
C3
C1
+215A 2,5V
END-OF-LIFE E OLACTIVE_H S3 OP Bias Cell 3 LVS dac7 RFPH
LINSERT_H
Block Diagram
15A slope control
C4
Preheat Mode Other Modes
2
GND
Preliminary Datasheet Version 1.02
dac7, dac4 = GND during run mode, otherwise transient voltage levels (0..2,5V) VGATE Z1 =12V 0 220ns t VCO Softstart and Preheat Mode T2 Other Modes
T1 LS HS DSC OP PHE ND_H 5s B lank Bia s Ce ll1
VCC
-215A
9
2,0V 5,0V PWM inverter
INV_OC 400ns B lank
RFRUN
LVS
4
LSGD 1,6V
C1
10
1
1 S1
RFPH
Simplified Blockdiagram of ICB1FL03G
LSCS
C2
Av= 2.5
1
1,8s Dead time
250ns B lank IGN-LIM
OP1
8-Bit ADC
DIGITAL LOOP CONTROL END-OF-LIFE 1 CAPACITIVE LOAD 2
S Q
END-OF-LIFE 2 CAPACITIVE LOAD 1 OPEN FILAMENT VBUS OVERVOLTAGE
Up & Down Counte r min.du ration of effect: 5 00ms R1 min.duration of effect: 610s RTPH C1 dac 7 PFCGDIN
FAULT LATCH R Q
8
1
2 35ms after en d of p reheat mode
R1
PFC_PWM_IN
R2
VREF = 2,50V OPERATION ABOVE RUN FREQUENCY PREHEAT_TIMER VCC
1 C1 & POWER_DOWN_L
INVPWM VCC
1
0,8V INVCLIM
11
INVERTER OVERCURRENT
min.du ratio n of e ffect: 400ns 1 LVS_L Int. Supply
RTPH
C1
5s Blank
VBUS OVERVOLTAGE
VTH1= 2,725V VTH2= 2,625V
T2 G1 5V 5s B lank T1 UVLO
D2
VTH= 1,83V
OFF_H LAMP _INSERT_ H UVLO _L OPEN_LOOP_L
C2
5s Blank
VBUS UNDERVOLTAGE
PFCGD
D1
5
VGATE slope control Z1 =12V
Z1
8
ERROR_LOGIC
LVS OPEN_FILAMENT CA PLOAD1 DQ G1
PFCVS
VTH = 0,375V
C3
5s Blank
VBUS OPEN LOOP DETECT PFC_VS
VT H1=14,0V VT H2=10,5V
C2
VDD_good_H & G3 OFF_ H
0 220ns
t
PFCGD
PFCCS
VT H=10,5V POWERSUPPLY PFC PWM & Control
26 0ns Blank PFC_CLIM C1
Z1 16V @2mA
6
1.0V
PHEND_H dac4 dac7 PFCGDIN PFC_ PWM_IN DSC P FC_ZCD C2 DSC OSC D3
12
INV 1 DQ
RES
VD S CAP LOAD1
G3 T1 C2 DQ G2 LS GDIN_H HSGDIN_H
5,0V I3= 20A; VRES< 1,6V; VCC> 10,5V; ILVS > 15A; or during run mode I1= 41A; VRES< 1,6V; VCC> 10,5V; ILVS< 15A; I4= 17A; VRES> 1,6V; VCC> 10,5V; ILVS> 15A; 3,2V I2= 34A; VRES> 1,6V; VCC> 10,5V; ILVS < 15A; C1 I5= 41A & 0A alternating for 32 cycles as a delay; Capacitive Load Detection
5,0V
R1 D1 D1
1,6V
C3
5 s Blank
PFCZCD
D2
1,3V VD S CAP LOAD2
7
POWER_DOWN_L
C4
5 s Blank
Lamp insert detection for VRES < 1,6V during power down.
Bandgap SPI Digital Vref=2.5V for sequential Test Master control Mode Clock
MCLOCK_SPI
CA PLOAD2
0,375V 0,24V
Start-up timer off-time 40s PFCPWM
VTH1=1,5V VTH 2=0,5V
R2
C5
5 s Blank
PFCCS
54k
T1
Delay generator for activating lamp removal after fault latch is set.
ICB1FL03G
Block Diagram
March 2009
CAPLOAD-RES
LAMP_INSERT_H
ICB1FL03G
Functional Description
3
3.1
Functional Description
Typical operating levels during start-up
The control of the ballast should be able to start the operation within less than 100ms. Therefore the current consumption of the IC is less than 150A during UVLO. With a small start-up capacitor (about 1F) and a power supply, that feeds within 100s (charge pump of the inverter) the IC can cover this feature. As long as the Vcc is less than 10,5V, the current consumption is typically 80A. Above a Vcc voltage level of 10,5V the IC checks whether the lamp(s) are assembled by detecting a current across the filaments. The low-side filament is checked from a source current (20A typ.) out of pin RES, that produces a voltage drop at the sense resistor, which is connected via low-side filament to ground. An open filament is detected, when the voltage level at pin RES is above 1,6V. The high-side filament (or the high-side of a series topology) is checked by a current (15A typ.) into the LVS pin. An open high-side filament causes a higher source current (41A / 34A typ.) out of pin RES in order to exceed the 1,6V threshold. If the filament is not able to conduct the test current, the control circuit is disabled. The IC is enabled as soon as a sufficient current is detected across the filament or the supply voltage drops below the UVLO threshold (10,5V) e.g. by turn-off and turn-on of mains switch.
VCC 14,0V 10,5V START-UP HYSTERESIS IC ACTIVE SOFTSTART
UVLO IVCC 80A VRES 3,2V 1,6V 80A
t
<150A 5mA + QGate
t
<3,2V
t
IRES 20A ILVS >15A >15A < +/- 2,5mA 20A
t
t
Figure 2
Progress of levels during a typical start-up.
When the previous conditions are fulfilled, and Vcc has reached the start-up threshold (14V), there is finally a check of the Bus voltage. If the level is less than 15% of rated Bus voltage, the IC is waiting in power down mode until the voltage increases. If the level is above 109% of rated Bus voltage there is no Gate drive, but an active IC. The supply voltage Vcc will fall below the UVLO threshold and a new start-up attempt is initiated. As soon as start-up conditions are fulfilled the IC starts driving the inverter with the start-up frequency of 125kHz. Now the complete control including timers and the PFC control can be set in action. There are current limitation thresholds for PFC preconverter and ballast inverter equipped with spike filters. The PFC current limitation interrupts the on-time of the PFC MOSFET if the voltage drop at shunt resistor exceeds 1V and restarts after next input from ZCD. The inverter current limitation operates with a first threshold of 0,8V which increases the operating frequency during ignition mode if exceeded. A second threshold is provided at 1,6V that stops the whole control circuit and latches this event as a fault.
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Functional Description
VCC 16,0V 14,0V 10,5V LS FILAMENT OPEN UVLO HS FILAMENT CLOSED IVCC 80A VRES 5,0V 3,2V 1,6V 1,3V IRES 20A ILVS >15A POWER DOWN SIGNAL >15A >15A < +/- 2,5mA t
H <3,2V
LAMP REMOVAL VRES> 1,3V IC ACTIVE SOFTSTART LS + HS OPEN
START-UP HYSTERESIS 80A <170A <150A
t
5mA + QGate
t
t
20A 17A 34A 17A 20A
t
t
Figure 3
Start-up with LS filament broken and subsequent lamp removal.
VCC 16,0V 14,0V 10,5V HS FILAMENT OPEN UVLO LS FILAMENT CLOSED IVCC 80A VRES 5,0V 3,2V 1,6V 1,3V IRES 20A ILVS >15A POWER DOWN SIGNAL >15A < +/- 2,5mA t
H <3,2V
LAMP REMOVAL VRES> 1,3V IC ACTIVE SOFTSTART LS + HS OPEN
START-UP HYSTERESIS 80A <170A <150A
t
5mA + QGate
t
1,3V
t
41A 34A 34A 17A 20A
t
t
Figure 4
Start-up with HS filament broken and subsequent lamp removal.
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Functional Description 3.2 PFC Preconverter
PFC is starting with a fixed frequent operation (ca. 25kHz), beginning with an on-time of 1s and an off-time of 40s. The on-time is enlarged every 400s to a maximum on-time of 23s. The control switches over into critical conduction mode (CritCM) operation as soon as a sufficient ZCD signal is available. There is an overvoltage threshold at 109% of rated Bus voltage that stops PFC Gate drive as long as the Bus voltage has reached a level of 105% of rated Bus voltage again. The compensation of the voltage control loop is completely integrated. The internal reference level of the Bus voltage sense (PFCVS) is 2,5V with high accuracy. The PFC control operates in CritCM in the range of 23s > on-time > 2,3s. For lower loads the control operates in discontinuous conduction mode (DCM) with an on-time down to 0,5s and an increasing off-time. With this control method the PFC preconverter covers a stable operation from 100% of load to 0,1% .
R34 D5 C1 R1 90 ... 270 VAC PE C2 R3 R18R19 C11 R20 D9 C12 R21R22R23 C13 R2 R11 R12 Q1 C10 R13 R14 ICB1FL03G
RFRUN RFPH PFCZCD
L101 D1...4
L1
LVS
R15 R16
PFCGD PFCVS PFCCS GND VCC
HSGD HSVCC HSGND
LSGD LSCS RTPH RES
Figure 5
Circuit Diagram of the PFC preconverter section.
Overvoltage, undervoltage and open loop detection at pin PFCVS are sensed by analog comparators. The BUS voltage loop control is provided by a 8bit sigma-delta A/D-Converter with a sampling rate of 400s and a resolution of 4mV/bit. So a range of +/- 0,5V from the reference level of 2,50V is covered. The digital error signal has to pass a digital notch filter in order to suppress the AC voltage ripple of twice of the mains frequency. A subsequent error amplifier with PI characteristic cares for stable operation of the PFC preconverter. The zero current detection is sensed by a separate pin PFCZCD. The information of finished current flow during demagnetization is required in CritCM and in DCM as well. The input is equipped with a special filtering including a blanking of typically 500ns and is combined with a large hysteresis between the thresholds of typically 0,5V and 1,5V. In case of bad coupling between primary inductor winding and secondary ZCD-winding an additional filtering by a capacitor at ZCD pin might be necessary in order to avoid mistriggering by long lasting oscillations during switching slopes of the PFC MOSFET.
PFCVS
AUX
-ADC SRate 400s Res 4mV/bit
PFCGD
Notch Filter PI Loop Control Pulse width Generator Gate Driver
Undervoltage 73% +/- 2,5%
Overcurrent Protection 1,0V +/-5% ZCD 1,50V / 0,5V Start-up Clock 600kHz Reference 2,50V +/-1,5%
PFCCS
PFCZCD
Overvoltage 109% +/-2,0% Open Loop Detection 15% +/- 20%
Figure 6
Structure of the mixed digital and analog control of PFC preconverter.
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Functional Description
Discontinuous Conduction Mode <> Critical Conduction Mode 100 1000
10
100
1
10
0,1 0 32 64 96 128 160 192 224
1 256
Digital Control Steps
Figure 7
Relative output power and operating frequency of PFC control at VIN = VOUT /2 versus control step.
Discontinuous Conduction Mode <> Critical Conduction Mode 100 1000
10
100
1
10
0 0 32 64 96 128 160 192 224
1 256
Digital Control Steps
Figure 8
On-time and operating frequency of PFC control at VIN = VOUT /2 versus control step.
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Operating Frequency (kHz) at VIN = VOUT/2 identification markings filled
On-Time (s) identification markings unfilled
Operating Frequency (kHz) at VIN = VOUT/2 identification markings filled
Relative Power % identification markings unfilled
ICB1FL03G
Functional Description 3.3 Typical operating levels during start-up
Within 10ms after start-up the inverter shifts operating frequency from 125kHz to the preheating frequency set by resistor at pin RFPH. Preheating time can be selected by programming resistor at RFPH pin in steps of 17ms from 0ms to 2000ms. After preheating the operating frequency of the inverter is shifted downwards in 40ms typically to the run frequency. During this frequency shifting the voltage and current in the resonant circuit will rise when operating close to the resonant frequency with increasing voltage across the lamp. As soon as the lower current sense level (0,8V) is reached, the frequency shift downwards is stopped and increased by a couple of frequency steps in order to limit the current and the ignition voltage also. The procedure of shifting the operating frequency up and down in order to stay within the max ignition level is limited to a time frame of 235ms. If there is no ignition within this time the control is disabled and the status is latched as a fault mode.
Typical variation of operating frequency during start-up
125kHz
f,V
65kHz 50kHz 40kHz Lamp Voltage Frequency
10ms
0-2000ms
40-235ms
250ms
t
Normal Operation
Softstart
Preheating
Ignition
Pre-Run
Softstart proceeds in 15 steps a 650s according fPH = (120kHz - f PH)/ 15steps. Ignition proceeds in 127 steps a 324s according fIGN = (fPH - fRUN)/ 127steps.
Figure 9
Typical variation of operating frequency and lamp voltage during start-up.
1000 900 800 700
Lamp Voltage
Ignition
600 500 400 300 200 100 0 10000
Without Load Run With Load After Ignition Operating Frequency Preheating
100000
Figure 10
Typical lamp voltage versus operating frequency due to load change of the resonant circuit.
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Functional Description 3.4 Detection of End-of-Life and Rectifier Effect
After ignition the lamp voltage breaks down to its run voltage level (typically 50Vpeak to 300Vpeak). Reaching the run frequency there follows a time period of 250ms called Pre-Run Mode, in which some of the monitoring features (EOL1, EOL2, Cap.Load1) are still disabled. In the subsequent Run Mode the End-of-life (EOL) monitoring is enabled. The event EOL1 is detected by measuring the positive and negative peak level of the lamp voltage by a current fed into the LVS pin (R41, R42, R43 in Fig. 11). If the sensed current exceeds 215A for longer than 610s the status end-of-life (EOL1) or the exceeding of the maximum output power is detected. In Fig. 12 the different levels of the sensed lamp voltage are illustrated.
R34
AUX PFCZCD
R41 R35
LVS HSGD
R42 R43
Q2
L2 C17 C15
R26
ICB1FL03G
HSVCC HSGND
PFCGD PFCVS PFCCS GND VCC
C10
LSGD LSCS RTPH
C14 R27
Q3 C18
C24
RFRUN
RFPH
RES
D6
C16 R36
D7 D8 R24 R25
R61 R21R22R23 C13 R30 C19 D61 SMD-Z
D9
Figure 11
Circuit diagram of the lamp inverter section.
+ Shut down level + Ignition level VLAMP-IGN + EOL Threshold IVL+PEAKI/IV L-PEAKI 0 VLAMP-RUN - EOL Threshold
t
- Ignition level - Shut down level
Figure 12
Sensed lamp voltage levels.
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Functional Description
2,5 2,4 2,3 2,2
Ratio of high er Amplitude / smaller Amplitude
2,1 2 1,9 1,8 1,7 1,6 1,5 1,4 1,3 1,2 1,1 1 0 50 100 150 200 250
I LVS = Lamp Voltage / Sense Resistor [uA]
of smaller Amplitude
Figure 13
Maximum ratio of amplitudes versus sense current.
Furthermore the rectification effect (EOL2) is detected when the ratio of the higher amplitude divided by the smaller amplitude of the lamp voltage is bigger than illustrated in Fig. 13. for longer than 500ms. The ratio is evaluated each cycle of the lamp voltage. The limit of the ratio increases dependend on the peak current of the smaller amplitude of the lamp voltage from 1,15 at ILVS= 200A nonlinear to 1,4 at ILVS= 50A. If the EOL2 conditions are detected, the control is disabled and the status is latched as a failure mode. Measuring the duration of incorrect operating conditions is done by a check every 4ms. If the fault condition is existing, a counter counts up, if the fault condition is not existing, the counter counts down. So we get an integration of the fault events that allows a very effective monitoring of strange operating conditions. The detection of EOL1 and EOL2 requires an AC current input at the sense pin LVS for proper operation. A DC current at pin LVS will lead to a defined reaction only, if the level exeeds 175A (typically) for longer than 610s which results in a shut down and change over into the latched failure mode.
3.5
Detection of capacitive mode operating conditions
If there happens a situation like an open resonant circuit (e.g. a sudden break of the tube) the voltage across the resonant capacitor and current through the shunt of the low-side inverter MOSFET rise quickly. This event is detected by inverter current limitation (1,6V) and results in shut down of the control. This status is latched as a failure mode. In another kind of failure the operation of the inverter may leave the zero voltage switching (ZVS) and move into capacitive mode operation or into operation below resonance. There are two different levels for capacitive mode detection implemented in the IC. A first criteria detects low deviations from ZVS (CapLoad1) and changes operation into fault mode, if this operation lasts longer than 500ms. For CapLoad1 the same counter is used as for the end-of-life evaluation.
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Functional Description
A second threshold detects severe deviations such as rectangular shapes of voltage during operation below resonance (CapLoad2). Then the inverter is turned off as soon as these conditions last longer than 610s and the IC changes over into fault mode. The evaluation of the failure condition is done by an up and down counter which samples the status every 40s. CapLoad1 is sensed in the moment when low-side Gate drive is turned on. If the voltage level at pin RES is above the VREScap threshold (typ. 0,24V) related to the level VRESLLV, conditions of CapLoad1 are assumed. CapLoad2 is sensed in the moment when the high-side Gate drive is turned on. If the voltage level at pin RES is below the VREScap threshold related to the level VRESLLV, conditions of CapLoad2 are assumed. As the reference level VRESLLV is a floating level, it is updated every on-time of the low-side MOSFET. D61 limits voltage transients at pin RES that can occur during removal of the lamp in run mode.
VDSLS
IDLS
t
V RES VRESCAP VRESLLV
tCAPM1 tCAPM2
t
Gate HS t Gate LS Deadtime
Figure 14 Levels and points in time for detection of CapLoad1 and CapLoad2.
t
3.6
Interruption of Operation and Restart after Lamp Removal
In the event of a failing operation the fault latch is set after the specified reaction time (e.g. 500ms at EOL2). Then the Gate drives are shut down immediately, the control functions are disabled and the current consumption is reduced to a level of 150A (typically). Vcc is clamped by internal zener diode to max 17,5V at 2mA. So the internal zener diode is only designed to limit Vcc when fed from the start-up current, but not from the charge pump supply! There is a current limitation at the internal zener diode function (max 5mA at Vcc= 17,5V) in order to avoid conflicts with the clamping level of the external zener diode. The capacitor at pin RES is discharged and charged during 32 cycles in order to generate a delay of several 10ms. The delay is implemented for avoiding malfunctions in detecting the lamp removal due to voltage transients that can occur after shut down. The reset of the fault latch happens after exceeding the 1,6V threshold at pin RES and enabling the IC after lamp removal and subsequent decreasing voltage level at pin RES below the 1,3V threshold.
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Functional Description
The status failure mode is kept as long until a lamp removal is detected (interruption of current across filaments and detection of the return of the current) or the supply voltage drops below UVLO. After a break down of the supply voltage below the undervoltage lockout (UVLO) threshold the IC resets any failure latch and will try to restart as soon as Vcc exceeds the start-up threshold. An undervoltage (75%) of the bus voltage will not be latched as a fault condition. If the undervoltage lasts longer than 80s the Gate drives are switched off and the IC tries to restart after a Vcc hysteresis has been passed.
VCC 16,0V 14,0V 10,5V IC FAULT LATCH ACTIVE SET E.G. BY EOL IVCC 5mA + QGate VRES 5,0V 3,2V 1,6V 1,3V 0,375V IRES 41A 20A ILVS <2,5mA 32 CYCLES (>50ms typically) >15A POWER DOWN SIGNAL FAULT LATCH SIGNAL TRANSIENT AT LVS PIN
H
LAMP REMOVAL LS + HS OPEN V
RES>1,3V
IC ACTIVE SOFTSTART
t
<170A <150A 5mA + QGate
t
1,6V 1,3V
<3,2V
t
20A 34A 17A 20A
t
>15A < +/- 2,5mA t
H
>15A
t
SET SIGNAL RESET SIGNAL
t
Figure 15
Interruption of operation by a fault condition and subsequent lamp removal.
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State Diagram
4
State Diagram
Mains Switch turned on; 0 < Vcc < 10,5V; IS< 80A; IRES= 0A 10,5 < Vcc < 14,0V; IS< 150A; IRES= 20A Vcc > 14,0V & VRES< 1,6V=> Start 125kHz > f > F_PH; 10,5 < Vcc < 16,0V; f= F_PH 10,5 < Vcc < 16,0V; IRES= 20A; f= F_RUN 10,5 < Vcc < 16,0V; f= F_RUN 10,5 < Vcc < 16,0V; F_PH > f > F_RUN Earliest Stop by EOL
62ms UVLO
35ms Monitoring
10ms Softstart
0ms ...2000ms Preheating
40ms ...235ms Ignition
250ms Pre - Run
500ms Run
BUS Overvoltage >109% BUS Undervoltage <75% BUS Open Loop Overcurrent PFC Overcurrent PFC Capacitive Load 2 Capacitive Load 2 Cap.Load1; EOL1,2 <15% 1,0V 1,0V
active
active
(80s)
active
active
active active active
active active active active
(605s) (300ns)
active active active , & 0,8V
active active active
active act,Restar act,Restart t active active active active active
Overcurrent Inverter 1,6V
Fault Mode: disabled by Lamp Removal or UVLO; 10,5 < Vcc< 16,0V; IS< 150A; IRES= 20A
Figure 16
State Diagram
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Protection Functions
5
Protection Functions
Fault-Type Min. Duration of Effect Detection active during Ignition Mode 40 - 235ms Pre-Run Mode 250ms Run Mode
X X X X X Power down, latched Fault Mode Power down, latched Fault Mode Power down, latched Fault Mode Power down, latched Fault Mode Power down, latched Fault Mode Gate drivers off, restart after VCC hysteresis 5s 80s 1s 610s 235ms 1ms 1ms 260ns 250ns 400ns 1s 1s X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Turn-off PFC MOSFET until Bus Voltage < 105% Gate drivers off, restart after VCC hysteresis Power down Power down, latched Fault Mode Power down, latched Fault Mode Prevents power up Prevents power up Turn-off PFC MOSFET immediately Increases the Operating Frequency Power Down, Latched Fault Mode Prevents power up Power Down, Reset of Latched Fault Mode
Description of Fault
Consequence
+/- Peak Level of Lamp Voltage above threshold Ratio of +/- amplitudes of lamp voltage > 1.15 or < 0.85 No zero voltage switching Voltage at Pin RES > 3.0V Bus voltage > 109% of rated level in active operation Bus voltage > 109% of rated level 10s after power up Bus voltage > 109% of rated level in active operation Bus voltage < 75% of rated level Bus voltage < 15% of rated level Capacitive Load, Operation below resonance Run frequency can not be achieved Voltage at Pin RES > 1.6V before power up Current into Pin LVS < 12A Voltage at Pin PFCCS > 1.0V Voltage at Pin LSCS > 0.8V Voltage at Pin LSCS > 1.6V Supply voltage at Pin VCC < 14.0V before power up Supply voltage at Pin VCC < 10.5V after power up
EOL1 EOL2 Cap.Load 1 Open Filament Overvoltage Overvoltage PFC Overvoltage Undervoltage Open Loop Detection Cap.Load 2 No Ignition LS open Filament HS open Filament PFC Overcurrent Inverter Current Limit Inverter Overcurrent Below startup threshold Below UVLO threshold
610s 500ms 500ms 500ms 500ms
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Electrical Characteristics
6
Note:
Electrical Characteristics
All voltages without the high side signals are measured with respect to ground (pin 4). The high side voltages are measured with respect to pin17/20. The voltage levels are valid if other ratings are not violated.
6.1
Note:
Absolute Maximum Ratings
Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of the integrated circuit. For the same reason make sure, that any capacitor that will be connected to pin 3 (VCC) and pin 18 (HSVCC) is discharged before assembling the application circuit. Symbol Limit Values min. max. Unit Remarks
Parameter
LSCS Voltage LSCS Current LSGD Voltage VCC Voltage VCC Zener Clamp Current PFCGD Voltage PFCCS Voltage PFCCS Current PFCZCD Voltage PFCZCD Current PFCVS Voltage RFRUN Voltage RFPH Voltage RTPH Voltage RES Voltage LVS Current1 LVS Current2 HSGND Voltage HSGND, Voltage Transient HSVCC Voltage HSGD Voltage PFCGD Peak Source Current PFCGD Peak Sink Current LSGD Peak Source Current LSGD Peak Sink Current HSGD Peak Source Current HSGD Peak Sink Current Junction Temperature
VLSCS ILSCS VLSGD VVCC IVCCzener VPFCGD VPFCCS IPFCCS VPFCZCD IPFCZCD VPFCVS VRFRUN VRFPH VRTPH VRES ILVS_1 ILVS_2 VHSGND dVHSGND/dt VHSVCC VHSGD IPFCGDsomax IPFCGDsimax ILSGDsomax ILSGDsimax IHSGDsomax IHSGDsimax Tj
-5 -3 -0.3 -0.3 -5 -0.3 -5 -3 -3 -5 -0.3 -0.3 -0.3 -0.3 -0.3 -1 -3 -900 -40 -0.3 -0.3 -- -- -- -- -- -- -25
6 3 Vcc+0.3 18 5 Vcc+0.3 6 3 6 5 5.3 5.3 5.3 5.3 5.3 1 3 900 40 18 VHSVCC+ 0.3 150 700 75 400 75 400 150
V mA V V mA V V mA V mA V V V V V mA mA V V/ns V V mA mA mA mA mA mA C referring to HSGND internally clamped to 11V referring to HSGND < 100ns < 100ns < 100ns < 100ns < 100ns < 100ns IC in Power Down Mode IC in Active Mode referring to GND internally clamped to 11V see VCC Zener Clamp IC in Power Down Mode internally clamped to 11V
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Electrical Characteristics
Storage Temperature Max possible Power Dissipation Thermal Resistance (Both Chips) Junction-Ambient Thermal Resistance (HS Chips) Junction-Ambient Thermal Resistance (LS Chips) Junction-Ambient Soldering Temperature ESD Capability
1)
TS Ptot RthJA RthJAHS RthJALS
-55 -- -- -- --
150 2 60 120 120 260
C W K/W K/W K/W C kV PG-DSO-18-2, Tamb = 25C PG-DSO-18-2 PG-DSO-18-2 PG-DSO-18-2 wave sold. acc.JESD22A111 Human body model1)
VESD
--
2
According to EIA/JESD22-A114-B (discharging an 100pF capacitor through an 1.5k series resistor).
6.2
Operating Range
Symbol Limit Values min. max. Unit Remarks
Parameter
HSVCC Supply Voltage HSGND Supply Voltage VCC Supply Voltage LSCS Voltage Range PFCVS Voltage Range PFCCS Voltage Range PFCZCD Current Range LVS Voltage Range LVS Current Range LVS Current Range Junction Temperature Adjustable Preheating Frequency Range set by RFPH Adjustable Run Frequency Range set by RFRUN Adjustable Preheating Time Range set by RTPH Set Resistor for Run Frequency Set Resistor for Preheating Frequency (RFRUN parallel RFPH)
VHSVCC VHSGND VVCC VLSCS VPFCVS VPFCCS IPFCZCD VLVS ILVS ILVS Tj FRFPH FRFRUN tRTPH RFRUN RFRUN II RFPH
VHSVCCoff -900 VVCCoff -4 0 -4 -4 -0.3
2)
17.0 900 17.5 5 4 5 4
1)
V V V V V V mA V A mA C kHz kHz ms k k
referring to HSGND referring to GND
IC in Power Down Mode IC in Power Down Mode IC in Active Mode
300 2.5 125 150 100 1980 25
-2.5 -25 FRFRUN 20 0 5 3.3 0
Set Resistor for Preheating Time RTPH
1) 2)
20
k
Limited by maximum of current range at LVS Limited by minimum of voltage range at LVS
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Electrical Characteristics 6.3
6.3.1 Note:
Characteristics
Power Supply Section The electrical characteristics involve the spread of values given within the specified supply voltage and junction temperature range TJ from - 25 C to 125 C. Typical values represent the median values, which are related to 25C. If not otherwise stated, a supply voltage of VCC = 15 V and VHSVCC = 15V is assumed and the IC operates in active mode. Furthermore all voltages are referring to GND if not otherwise mentioned. Symbol min. Limit Values typ. max. Unit Test Condition
Parameter
High Side Leakage Current VCC Quiescent Current VCC Quiescent Current VCC Supply Current with Inactive Gates VCC Supply Current in Latched Fault Mode LS VCC Turn-On Threshold LS VCC Turn-Off Threshold LSVCC Turn-On/Off Hysteresis VCC Zener Clamp Voltage VCC Zener Clamp Current HSVCC Quiescent Current HSVCC Supply Current with Inactive Gate
IHSGNDleak IVCCqu1 IVCCqu2 IVCCsup1 IVCClatch VVCCon VVCCoff VVCChys VVCCclmp IVCCzener IHSVCCqu1) IHSVCCsup1
1)
0.01 80 110 5 -- 13.6 10.0 3.2 15.7 2.5 -- -- 9.6 7.9 1.4 110 14.1 10.5 3.6 16.3 -- 170 0.65 10.1 8.4 1.7
2 120 150 7 170 14.6 11.0 4.0 16.9 5 250 1.2 10.7 9.1 2.0
A A A mA A V V V V mA A mA V V V
VHSGND = 800V VGND = 0V VVCC = VVCCoff - 0.5V VVCC = VVCCon - 0.5V VPFCVS > 2.725V VRES = 5V
IVCC = 2mA VRES = 5V VVCC = 17.5V VRES = 5V VHSVCC = VHSVCCon -0.5V
HSVCC Turn-On Threshold VHSVCCon1) HSVCC Turn-Off Threshold VHSVCCoff1) HSVCC Turn-On/Off Hysteresis VHSVCChys1)
1)
With reference to High Side Ground HSGND
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Electrical Characteristics
6.3.2 6.3.2.1 PFC Section PFC Current Sense (PFCCS) Symbol min. Limit Values typ. max. Unit Test Condition
Parameter
Turn-Off Threshold Duration of Overcurrent for turn-off Spike Blanking PFCCS Bias Current
6.3.2.2
VPFCCSoff tPFCCSoff tblanking IPFCCSbias
0.95 200 140 -0.5
1.0 250 200
1.05 320 260 0.5
V ns ns A VPFCCS = 1.5V
PFC Zero Current Detector (PFCZCD) Symbol min. Limit Values typ. max. Unit Test Condition
Parameter
Zero Crossing Upper Threshold Zero Crossing Lower Threshold Zero Crossing Hysteresis Clamping of Positive Voltages Clamping of Negative Voltages PFCZCD Bias Current PFCZCD Ringing Suppression Time
6.3.2.3
VPFCZCDup VPFCZCDlow VPFCZCDhys VPFCZCDpclp VPFCZCDnclp IPFCZCDbias tringsup
1.4 0.4 5.0 -3.5 -0.5 350
1.5 0.5 1.0 6.3 -2.9 500
1.6 0.6 7.2 -2.0 0.5 650
V V V V V A ns IPFCZCD = 4mA IPFCZCD = 4mA VPFCZCD = 1.7V
PFC Bus Voltage Sense (PFCVS) Symbol min. Limit Values typ. max. Unit Test Condition
Parameter
Trimmed Reference Voltage Overvoltage Upper Detection Limit Overvoltage Lower Detection Limit Overvoltage Hysteresis Undervoltage Detection Limit Undervoltage Shut Down Bias Current (ESD-Stress<1KV) Bias Current (ESD-Stress>1KV)
VPFCVSref VPFCVSup VPFCVSlow VPFCVShys VPFCVSuv VPFCVSsd IPFCVSbias IPFCVSbias
2.47 2.675 2.57 70 1.79 0.30 -1 -2.5
2.5 2.725 2.625 100 1.83 0.375
2.53 2.78 2.67 130 1.87 0.45 1 2.5
V V V mV V V A A VPFCVS = 2.5V VPFCVS = 2.5V
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Electrical Characteristics
6.3.2.4 PFC PWM Generation Symbol min. Limit Values typ. max. Unit Test Condition
Parameter
Initial On-Time Max. On-Time Repetition Time when missing Zero Crossing Off-time when missing ZCD Signal
6.3.2.5 PFC Gate Drive (PFCGD)
tPFCon-initial tPFCon-max tPFCrep tPFCoff
2.0 19 38 35
3.0 23.5 50 42
3.8 28 62 49
s s s s
VPFCZCD = 0V 0.45V < VPFCVS < 2.45V VPFCZCD = 0V VPFCZCD = 0V
Parameter
Symbol min.
Limit Values typ. max.
Unit
Test Condition
PFCGD Low Voltage
VPFCGDlow
0.4 0.4 -0.1
0.7 0.75 0.3 11 --
0.9 1.1 0.6 11.8 --
V V V V V
IPFCGD = 5mA IPFCGD = 20mA IPFCGD = -20mA IPFCGD = -20mA IPFCGD = -1mA VVCC = VVCCoff + 0.3V IPFCGD = -5mA VVCC = VVCCoff + 0.3V IPFCGD = 20mA VVCC = 5V Rload = 4 + CLoad = 3.3nF1) Rload = 4 + CLoad = 3.3nF1) Rload = 4 + CLoad = 3.3nF Rload = 4 + CLoad = 3.3nF
PFCGD High Voltage
VPFCGDhigh
10.2 9.0
8.5
--
--
V
PFCGD Voltage Active Shut Down PFCGD Peak Source Current PFCGD Peak Sink Current PFCGD Rise Time 2V < VLSGD < 8V PFCGD Fall Time 8V > VLSGD > 2V
1)
VPFCGDsd IPFCGDsource IPFCGDsink tPFCGDrise tPFCGDfall
0.4 -- -- 110 20
0.75 100 -500 220 45
1.1 -- -- 400 70
V mA mA ns ns
The parameter is not subject to production test - verified by design/characterization
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Electrical Characteristics
6.3.3 6.3.3.1 Inverter Section Inverter Control (RFRUN, RFPH, RTPH) Symbol min. Limit Values typ. max. Unit Test Condition
Parameter
Fixed Start-Up Frequency Duration of Soft Start, shift F from Start-Up to Preheating Frequency Preheating Frequency Run Frequency Preheating Time Preheating Time Current Source Preheating Time Min. Duration of Ignition, shift F from Preheating to Run Frequency Max. Duration of Ignition, shift F from Preheating to Run Frequency Duration of Pre-Run, time period after operating frequency has reached Run Frequency first time after ignition Minimum Duration of fault condition by EOL2, Cap.Load 1, Open filament and Overvoltage for entering latched Fault Mode Minimum Duration of fault condition by EOL1, Cap.Load 2 for entering latched Fault Mode
1)
Fstartup tsoftstart FRFPH1 FRFRUN1 tRTPH1 tRTPH2 IRTPH tIGNITION tNOIGNITION tPRERUN
112 9.0 97.0 49.0 720 50 132 34 210 210
125 11.0 100 50.0 900 90 140 40 235 250
138 13.5 103.0 51.0 1080 130 148 48 290 290
kHz ms kHz kHz ms ms A ms ms ms
1)
RRFPH = 10k RRFRUN = 10k RRFRUN = 10k RRTPH = 8.06k RRTPH = 8061)
1)
1)
tCAPLOAD1
420
500
580
ms
1)
tCAPLOAD2
520
610
770
s
The parameter is not subject to production test - verified by design/characterization
Inverter Low Side Current Sense (LSCS) Symbol min. Limit Values typ. max. Unit Test Condition
6.3.3.2
Parameter
Current Limit Threshold during Ignition Mode Duration of Current above Threshold for enabling Frequency Increase Overcurrent Shut Down Threshold Duration of Overcurrent for entering Latched Fault Mode Bias Current LSCS Inverter Dead Time between LS off and HS on
VLSCSlimit tLSCSlimit VLSCSovc tLSCSovc ILSCSbias tdeadtime
0.76 200 1.55 320 -0.5 1.50
0.80 250 1.60 400
0.84 320 1.65 480 0.5
V ns V ns A s VLSCS = 1.5V
1.75
2.0
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Electrical Characteristics
6.3.3.3 Restart after Lamp Removal (RES) Symbol min. Limit Values typ. max. Unit Test Condition
Parameter
Low-side Open Filament Threshold Capacitive Load Detection Threshold Discharge Resistor during Latched Fault Mode I1 Current Source I2 Current Source I3 Current Source I4 Current Source C1 Comparator Threshold C2 Comparator Threshold C3 Comparator Threshold
6.3.3.4
VRESofil VREScap RRESdisch IRES1 IRES2 IRES3 IRES4 VRESC1 VRESC2 VRESC3
3.1 0.18 37 -54.3 -46 -27.0 -22.6 1.55 1.25 0.32
3.2 0.24 56 -41 -34 -20 -17 1.6 1.3 0.375
3.3 0.30 75 -30.0 -24.2 -15.1 -12.3 1.65 1.35 0.46
V V k A A A A V V V VRES=1V; LVS=5A VRES=2V; LVS=5A VRES=1V; LVS=50A VRES=2V; LVS=50A
Lamp Voltage Sense (LVS) Symbol min. Limit Values typ. max. Unit Test Condition
Parameter
Source Current before Start Up Threshold for enabling Lamp Monitoring Sink Current Threshold for Lamp Detection Positive EOL Current Threshold Negative EOL Current Threshold EOL Current Threshold Maximum Ratio between positive and negative Current Amplitude1) Minimum Ratio between positive and negative Current Amplitude1) Positive Clamping Voltage
ILVSsource VLVSenable ILVSsink ILVSpEOLAC ILVSnEOLAC ILVSEOLDC ROLVSmax
-8 1.5 9 185 -250 +/-145 1.1
-5 2.3 15 215 -215 +/-175 1.2
-2 3.0 26 250 -185 +/-210 1.3
A V A A A A
11 < VVCC < 13V VLVS = 0V 11 < VVCC < 13V VLVS > VVCC T > 0C, AC input T > 0C, AC input T > 0C, DC input ILVSsourpeak=150A ILVSsinkpeak= increasing ILVSsinkpeak=150A ILVSsourcepeak= increasing
ROLVSmin
0.75
0.85
0.95
ILVSclmp
-
VVCC + 1V
-
V
ILVS = 300A
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Electrical Characteristics
1)
Referring to the following equations:
RO
LVS
I (n + 1) LVS sin kpeak = -------------------------------------------------------I (n) LVSsourcepeak
I LVSsource ( n + 2 ) RO LVS = -------------------------------------------------------I (n + 1) LVS sin kp eak
6.3.3.5
Inverter Low Side Gate Drive (LSGD) Symbol min. Limit Values typ. max. Unit Test Condition
Parameter
LSGD Low Voltage
VLSGDlow
0.4 0.5 -0.3
0.7 0.8 0.1 10.8 --
1.0 1.2 0.4 11.6 --
V V V V V
ILSGD = 5mA ILSGD = 20mA ILSGD = -20mA IPFCGD = -20mA IPFCGD = -1mA VVCC = VVCCoff + 0.3V IPFCGD = -5mA VVCC = VVCCoff + 0.3V IHSGD = 20mA VHSVCC = 5V Rload = 10 + CLoad = 1nF1) Rload = 10 + CLoad = 1nF1) Rload = 10 + CLoad = 1nF Rload = 10 + CLoad = 1nF
LSGD High Voltage
VLSGDhigh
10.0 9.0
8.5
--
--
V
LSGD Voltage Active Shut Down LSGD Peak Source Current LSGD Peak Sink Current LSGD Rise Time 2V < VLSGD < 8V LSGD Fall Time 8V > VLSGD > 2V
1)
VLSGDsd ILSGDsource ILSGDsink tLSGDrise tLSGDfall
0.5 -- -- 110 20
0.8 50 -300 220 35
1.2 -- -- 400 60
V mA mA ns ns
The parameter is not subject to production test - verified by design/characterization
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Electrical Characteristics
6.3.3.6 Inverter High Side Gate Drive (HSGD) Symbol min. Limit Values typ. max. Unit Test Condition
Parameter
HSGD Low Voltage
VHSGDlow
0.02 0.5 -0.4
0.05 1.1 -0.2 10.5 --
0.1 2.5 -0.05 11.0 --
V V V V V
IHSGD = 5mA IHSGD = 100mA IHSGD = -20mA IHSGD = -20mA IHSGD = -1mA VHSVCC = VHSVCCoff + 0.3V IHSGD = 20mA VHSVCC = 5V Rload = 10 + CLoad = 1nF1) Rload = 10 + CLoad = 1nF1) Rload = 10 + CLoad = 1nF Rload = 10 + CLoad = 1nF
HSGD High Voltage
VHSGDhigh
9.5 7.8
HSGD Voltage Active Shut Down HSGD Peak Source Current HSGD Peak Sink Current HSGD Rise Time 2V < VHSGD < 8V HSGD Fall Time 8V > VHSGD > 2V
1)
VHSGDsd IHSGDsource IHSGDsink tHSGDrise tHSGDfall
0.05 -- -- 140 20
0.22 50 -300 220 35
0.50 -- -- 300 70
V mA mA ns ns
The parameter is not subject to production test - verified by design/characterization
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Application Examples
7
7.1
Application Examples
Operating Behaviour of a Ballast for a single Fluorescent Lamp
After turning on the mains switch the peak value of the rectified AC input voltage is available at C02 and smoothing capacitor C10 (Fig. 17). Via R11 and R12 the supply voltage increases at bypass capacitors C12 and C13. At a level of 10,5V a source current out of pin RES is sensing the existence of the low-side filament of the fluorescent lamp. Fed from the BUS voltage a current is detected at pin LVS via R41, R42, R43, when the high-side filament is connected. The current fed into pin LVS is used to charge C12 via internal clamping diode. The IC changes into active mode when Vcc level achieves the turn-on threshold of 14V and both filaments are detected. The active IC is sensing the BUS voltage level via R14, R15. Gate drives are disabled when open loop or overvoltage are detected. If BUS voltage level is within the allowed range, the low-side Gate drive is starting with the first pulse of the 125kHz softstart frequency. Only few cycles are required to charge the bootstrap capacitor C14 via D6, R30 and Q3. Without R30 there is a risk of overcurrent shut down by exceeding the 1,6V threshold at pin LSCS. The power supply is generated by a charge pump C16, D7 and D8. In normal operation C16 is charged and discharged via C17 from the current forced by the resonance inductor L2 during the deadtime of the inverter producing a zero voltage switching (ZVS) operation. Run frequency, preheating frequency and preheating time are set by resistors R21, R22 and R23.
R41 C5 L10 C1 D1...4 C4 R1 R2 90 ... 270 VAC PE C3 C2
GND VCC
L1 D5
R34 R13 R14 ICB1FL03G
PFCZCD
R35 Q2
HSGD HSVCC HSGND PFCGD PFCVS
R42 R43 L21 C21 K2 C17 C15 L2 C20 C16 C18 K4 K3 K1
LVS
R26
Q1
R15 R16
R11 C10 R3 R12 R18 R19 C11 R20 D9 C12
PFCCS RFRUN RFPH
LSGD LSCS RTPH RES
C14 R27
Q3
D6 R61
D7
R21R22R23 C13 C61 SMD
R30
R24R25
D8 K6 L22 C19 C22 K5 R36
D61 SMD-Z
Figure 17
Application circuit of a Ballast for a single Fluorescent Lamp with voltage mode Preheating.
During run mode the lamp voltage is sensed via R41, R42, R43 in order to detect an abnormal increasing of lamp voltage or an rectifier effect that can occur at end-of-life conditions of the lamp. At the pin RES there is also detected a non-ZVS operation, classified into Capmode1 and Capmode2. This will be done by the capacitive divider C18, C19, that transfers the divided AC-part of the inverter output voltage to pin RES. Dependent on the shape of the signal two different time windows can be started at abnormal conditions in order to protect the ballast. Zener diode D61 limits voltage transients at pin RES that can occur during removal of the lamp. Voltage mode preheating is done by two separate windings on the resonant inductor L2. The bandpass filters L21, C21 and L22, C22 are designed to pass preheating current at preheating frequency only and to block any current during run mode. Ignition is provided by shifting the operating frequency towards the resonant frequency of L2 and C20. The voltage level during ignition is limited by the current sensed at Shunt resistors R24, R25 with a level of 0,8V at pin LSCS. Overcurrents that exceed a voltage level of 1,6V for longer than 400ns will disable the IC at any time and change into fault mode. The PFC preconverter with L1, Q1 and D5 is starting with a fixed frequent operation and change over to a critical conduction mode (CritCM) as soon as the level at pin PFCZCD is sufficient to trigger the operation. During light load the operation mode changes into discontinuous conduction mode (DCM). Compensation of the voltage
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Application Examples
control loop is completely integrated with a digital filter and error amplifier. PFC overcurrent is sensed by R18, R19, Bus overvoltage and undervoltage at pin PFCVS. A bypass diode D11 between the DC side of the mains rectifier and BUS capacitor is recommended in order to avoid an overload of the PFC MOSFET Q1.
7.2
Design Equations of a Ballast Application
Subsequent the design equations are listed: Start-up resistors R11, R12:
V INMIN 200V= ------------------------- = ---------------- = 1, 33M I 150A VCCqu2
R
11
+R
12
Selected value: R11= 470k; R12= 470k Current limitation resistor R13 of PFC zero current detector (PFCZCD). The additional factor 2 is used in order to keep away from limit value.
V N 2 BUS SEC 410V 13 2 = ----------------------------------------------------------- = --------------------------------- = 20, 8k I N 1 4mA 128 1 PFCZCD PRIM
R
13
Selected value: R13= 33k. PFC Voltage sense resistor R20:
V REF 2, 50V ------------------------------------------ = ------------------------------ = 10k 100 I 100 2, 5A PFCBIAS
R
20
Selected value: R20= 10k. PFC Voltage sense resistors R14, R15:
V -V BUS REF 410V - ( 2, 5V ) = -------------------------------------- R = ------------------------------------- 10k = 1630k 20 V 2, 5V REF
R
14
+R
15
Selected values: R14= 820k; R15= 820k Low pass capacitor C11: Selected corner frequency fC1= 10kHz.
1 (R + R + R ) 20 14 15 1 ( 10k + 820k + 820k ) = --------------------------------------------------------------------------- = -------------------------------------------------------------------------------------- = 1, 60nF 2f R (R + R ) 2 10kHz 10k ( 820k + 820k ) C1 20 14 15
C
11
Selected value C3= 2,2nF PFC Shunt resistors R18, R19: Selected values: R18= 2,2Ohm; R19= 2,2Ohm Set resistor R21 for run frequency, at a projected run frequency of 45kHz:
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Application Examples
V V 2 R R PFCCSOFF INACMIN 18 19 1V 0, 95 180V 2 -------------------------- = ---------------------------------------------------------------------------------------------- = ----------------------------------------------------- = 1, 1 4P 4 55W R +R OUTPFC 18 19
R
21
=R
FRUN
8 8 5 10 Hz 5 10 Hz = -------------------------------- = -------------------------------- = 11, 1k f 45kHz RUN
Selected value: R21= 11,0k Set resistor R22 for preheating frequency, at a projected preheating frequency of 105kHz:
R FRUN 11, 0k = -------------------------------------------- = ------------------------------------------------ = 8, 4k f R 105kHz 11, 0k - 1 --------------------------------------PH FRUN ----------------------------------- - 1 8 8 5 10 Hz 5 10 Hz
R
22
=R
FPH
Selected value: R22= 8,2k Set resistor R23 for preheating time, at a projected preheating time of 900ms:
T [ ms ] PH 900ms = ------------------------------------- = ------------------------------------- = 8, 93k ( 112ms ) ( k ) ( 112ms ) ( k )
R
23
=R
TPH
Selected value: R23= 8,2k Gate drive resistors R16, R26, R27 are recommended to be equal or higher than 10Ohm. Shunt resistors R24, R25: The selected lamp type 54W-T5 requires an ignition voltage of VIGN= 800V peak. In our application example the resonant inductor is evaluated to L2= 1,46mH and the resonant capacitor C20= 4,7nF. With this inputs we can calculate the ignition frequency fIGN :
V 2 BUS 1 ----------------------V IGN --------------------------------------- = 2 4 L C 2 20
f
IGN
=
410V 2 1 ------------------- 800V ------------------------------------------------------------ = 69759Hz 2 4 1, 46mH 4, 7nF
The second solution of this equation (with the minus sign) leads to a result of 50163Hz, which is on the capacitive side of the resonant rise. This value is no solution, because the operating frequency approaches from the higher frequency level. In the next step we can calculate the current through the resonant capacitor C20 when reaching a voltage level of 800V peak.
I C20 =V IGN 2f IGN C 20 = 800V 2 69759Hz 4, 7nF = 1, 65A
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Application Examples
Finally the resistors R24, R25 can be calculated from IC20 and the current limitation threshold during ignition mode.
R R V 24 25 LSCSLIMIT 0, 8V -------------------------- = -------------------------------------- = ---------------- = 0, 485 R +R I 1, 65A 24 25 C20
Selected values are R24= 0,82Ohm; R25= 0,82Ohm. Lamp voltage sense resistors R41, R42, R43: The selected lamp type 54W-T5 has a typical run voltage of 167V peak. We decide to set the EOL-thresholds at a level of 1,5 times the run voltage level (= 250,5V peak).
V LEOL = -------------------------- = 250, 5V = 1165k ------------------I 215A LVSEOL
R
41
+R
42
+R
43
Selected values: R41= 390k; R42= 390k; R43= 390k (R41+R42+R43=1170k). Current source resistors R34, R35 for detection of high-side filament:
V 200V INMIN = -------------------------------------------- - ( R + R + R ) = ------------- - ( 1170k ) = 6522k 41 42 43 26A I LVSSINKMAX
R
34
+R
35
Selected values: R34= 2,2M; R35= 2,2M; Current limitation resistor R30 for floating bootstrap capacitor C14: A factor of 2 is provided in order to keep current level significant below LSCS turn-off threshold.
2V R R CCON24 25 2 14V 0, 82 0, 82 --------------------------------- -------------------------- = ----------------- ----------------------------- = 7, 18 V R +R 1, 6V 0, 82 + 0, 82 LSCSOVC 24 25
R
30
Selected value: R30= 10Ohm. Low-side filament sense resistor R36: For a single lamp ballast
V RESC1MIN 1, 55V ------------------------------------ = ------------------- = 57, 4k I 27, 0A RES3MIN
R
36
Selected value: R36= 56k Low pass filter capacitor C19: Capacitor C19 provides a low pass filter together with resistor R36 in order to suppress AC voltage drop at the low-side filament. When we estimate an AC voltage of 10V peak-to-peak at low-side filament during run mode at fRUN= 40kHz, we need a suppression of at least a factor FLP= 100 (-40dB).
2
C
19
=
LP ------------------------- = 2 100 - 1 56k - -------------------------2f R 40kHz RUN 36
F
-1
2
= 7, 1nF
Selected value for better ripple suppression: C19= 22nF.
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Application Examples
Detection of capacitive mode operation via C18: The DC level at pin RES is set by R36 and the source current IRES3. The preferred AC level is in the range between VACRES= 1,5V to 2,0V at a VBUS= 410V.
C =C V ACRES 2V ----------------------------- = 22nF ------------- = 107pF V 410V BUS
18
19
Selected value: C18= 82pF. Bandpass filters L21/C21 and L22/C22 can be used in order to conduct filament currents preferred at preheating frequency and to suppress these currents during run mode. Inductor L1 of the boost converter: The inductivity of the boost inductor typically is designed to operate within a specified voltage range above a minimum frequency in order to get an easier RFI suppression. It is well known, that in critical conduction mode (CritCM) there is a minimum operating frequency at low input voltages and another minimum at maximum input voltage. In state-of-the-art CritCM PFC controllers we use the lowest value out of these two criterias: At minimum AC input voltage:
L 2 (V 2) (V - (V 2)) INACMIN BUS INACMIN = ----------------------------------------------------------------------------------------------------------------------------------------------A 4F P V MIN OUTPFC BUS 2 ( 180V 2 ) ( 410V - ( 180V 2 ) ) 0, 95 = ------------------------------------------------------------------------------------------------------------ = 3, 89mH 4 25kHz 60 W 410V
L
A
At maximum AC input voltage
L 2 (V 2) (V - (V 2)) INACMAX BUS INACMAX = ---------------------------------------------------------------------------------------------------------------------------------------------------B 4F P V MIN OUTPFC BUS 2 = ( 270V 2 ) ( 410V - ( 270V 2 ) ) 0, 95 = 1, 58mH -----------------------------------------------------------------------------------------------------------4 25kHz 60 W 410V
L
B
With the new control principle for the PFC preconverter we have a third criteria that covers the maximum on-time tPFCOM-MAX= 23,5s:
2 (V 2) T INACMIN ONMAX = --------------------------------------------------------------------------------------------C 4P OUTPFC 2 = ( 180 2 ) 23, 5s 0, 95 = 6, 03mH ------------------------------------------------------------------4 60 W
L
L
C
With the assumed conditions the lowest value out of LA, LB, LC is 1,58mH. Selected value: L1= 1,58mH.
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Application Examples
Bill of material for the application circuit of Fig. 17 and the design equations standing ahead. This design was used as an evaluation board.
Table 1
F1 IC1 Q1 Q2 Q3 D1...D4 D5 D6 D7 D8 D9 D61 L0 L1 L2 L21 L22 C01 C02 C03 C10 C11 C12 C13 C14 C15 C16
Bill of Material for a FL-Ballast of a 54W-T5 Lamp
Fuse 1A fast ICB1FL03G SPP03N60C3 (600V/1,4) SPP03N60C3 (600V/1,4) SPP03N60C3 (600V/1,4) B250C1000 MUR160 MUR160 UF4003 UF4003 BZX79C16 BZX79C4V7 R15 2x68mH/0,65A 1,58mH; EFD25/13/9 Np/Ns= 128/13 1,46mH; EFD25/13/9 Np/Ns= 153/4 100H; 100H; 220nF/X2/275V AC 220nF/X2/275V AC 3,3nF/Y1/400V AC 10F/450V DC 2,2nF/63V 470nF/63V 470nF/63V 100nF/63V 150nF/630V 1nF/1kV R16 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R30 R41 R42 R43 R34 R35 R36 820k 22 2,2 2,2 10k 11,0k (45,5kHz) 8,2k (106,4kHz) 8,2k (918ms) 0,82 0,82 22 22 10 390k 390k 390k 2,2M 2,2M 56k R11 R12 R13 R14 470k 470k 33k 820k C17 C18 C19 C20 C21 C22 150nF/630V 82pF/2KV 22nF/63V 4,7nF/1600V DC 22nF/400V 22nF/400V
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Application Examples 7.3 Other Ballast Topologies
How to use ICB1FL03G in alternative topologies is demonstrated in the subsequent figures. In Fig. 18 we see an application for a single lamp with current mode preheating. Compared with Fig. 17 the difference is the connection of the resonant capacitor in series with the filaments. In respect of operating behaviour the current mode preheating cannot be designed with same variation of operating parameters: the preheating current is typically lower and lamp voltage during preheating higher than in topologies with voltage mode preheating. Figure 19 shows an application circuit of a ballast for a multi fluorescent lamp design in serial with voltage mode preheating
R41 C5 L10 C1 D1...4 C4 R1 R2 90 ... 270 VAC PE C3 C2
GND VCC
R42 R43
L1 D5
R34 R13 R14 ICB1FL03G
PFCZCD
R35 Q2
HSGD HSVCC HSGND PFCGD PFCVS
K2 C17 C15 L2
K1
LVS
R26
Q1
R15 R16
R11 C10 R3 R12 R18 R19 C11 R20 D9 C12
PFCCS RFRUN RFPH
LSGD LSCS RTPH RES
C14 R27
Q3 C16 C18 K6
C24
D6 R61
K5 R36
D7
R21R22R23 C13 C61 SMD
R30
R24R25
D8
D61 C19 SMD-Z
Figure 18
Application Circuit of a Ballast for a single Fluorescent Lamp with Current Mode Preheating.
R41 C5 L10 C1 D1...4 C4 R1 R2 90 ... 270 VAC PE C3 C2
GND VCC
L1 D5
R34 R13 R14 ICB1FL03G
PFCZCD
R35 Q2
HSGD HSVCC HSGND PFCGD PFCVS
R42 R43 L21 C21 K2 C17 C15 C25 L2 C20 C16 C18 C23 K4 K3 C24 K1
LVS
R26
Q1
R15 R16
R11 C10 R3 R12 R18 R19 C11 R20 D9 C12
PFCCS RFRUN RFPH
LSGD LSCS RTPH RES
C14 R27
Q3
D6 R61
D7
L23
R21R22R23 C13 C61 SMD
R30
R24R25
D8 K6 L22 C19 C22 K5 R36
D61 SMD-Z
Figure 19
Application Circuit of a Ballast for a Multilamp Design in Serial with Voltage Mode Preheating
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Package Outlines
8
Package Outlines
2.65 MAX.
2.45 -0.2
0.2 -0.1
+0.09
PG-DSO-18-2 (Plastic Dual Small Outline)
0.35 x 45
8 MAX.
7.6 -0.2 1)
1.27 0.35 +0.15 2) 20 0.2 20x 11 0.1
0.4
+0.8
10.3 0.3
1
12.8 -0.2 1)
10
Index Marking
1) 2)
Does not include plastic or metal protrusions of 0.15 max per side Does not include dambar protrusion of 0.05 max per side
Figure 20
Package dimensions and mechanical data (Dimensions in mm).
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0.23
ICB1FL03G
Package Outlines
Preliminary Datasheet Version 1.02
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http://www.infineon.com
Published by Infineon Technologies AG

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