View ISLA214P501103_5053301.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

14-Bit, 500MSPS ADC
ISLA214P50
The ISLA214P50 is a 14-bit, 500MSPS analog-to-digital converter designed with Intersil's proprietary FemtoChargeTM technology on a standard CMOS process. The ISLA214P50 is part of a pin-compatible portfolio of 12 to 16-bit A/Ds with maximum sample rates ranging from 130MSPS to 500MSPS. The device utilizes two time-interleaved 250MSPS unit ADCs to achieve the ultimate sample rate of 500MSPS. A single 500MHz conversion clock is presented to the converter, and all interleave clocking is managed internally. The proprietary Intersil Interleave Engine (I2E) performs automatic correction of offset, gain, and sample time mismatches between the unit ADCs to optimize performance. A serial peripheral interface (SPI) port allows for extensive configurability of the A/D. The SPI also controls the interleave correction circuitry, allowing the system to issue offline and continuous calibration commands as well as configure many dynamic parameters. Digital output data is presented in selectable LVDS or CMOS formats. The ISLA214P50 is available in a 72 Ld QFN package with an exposed paddle. Operating from a 1.8V supply, performance is specified over the full industrial temperature range (-40C to +85C).
Features
* * * * Automatic Fine Interleave Correction Calibration Single Supply 1.8V Operation Clock Duty Cycle Stabilizer 75fs Clock Jitter
* 700MHz Bandwidth * Programmable Built-in Test Patterns * Multi-ADC Support - SPI Programmable Fine Gain and Offset Control - Support for Multiple ADC Synchronization - Optimized Output Timing * Nap and Sleep Modes - 200s Sleep Wake-up Time * Data Output Clock * DDR LVDS-Compatible or LVCMOS Outputs * User-accessible Digital Temperature Monitor
Applications
* * * * * Radar Array Processing Software Defined Radios Broadband Communications High-Performance Data Acquisition Communications Test Equipment
Key Specifications
* SNR @ 500MSPS = 72.7dBFS fIN = 30MHz = 70.6dBFS fIN = 363MHz * SFDR @ 500MSPS = 84dBc fIN = 30MHz = 76dBc fIN = 363MHz * Total Power Consumption = 835mW @ 500MSPS
CLKDIVRSTN
CLKDIVRSTP
CLKDIV
Pin-Compatible Family
OVDD
AVDD
MODEL
CLKP CLKN CLOCK MANAGEMENT CLKOUTP CLKOUTN
RESOLUTION 16 16 16 14 14 14 14 12 12 12 12
SPEED (MSPS) 250 200 130 500 250 200 130 500 250 200 130
ISLA216P25 ISLA216P20
SHA
14-BIT 250 MSPS ADC
D[13:0]P D[13:0]N ORP I2E DIGITAL ERROR CORRECTION ORN
ISLA216P13 ISLA214P50 ISLA214P25 ISLA214P20 ISLA214P13 ISLA212P50
VREF VINP VINN Gain, Offset and Skew Adjustments
SHA
14-BIT 250 MSPS ADC
VREF VCM + - SPI CONTROL
ISLA212P25 ISLA212P20
RLVDS OVSS
NAPSLP
RESETN
AVSS
CSB SCLK SDIO SDO
ISLA212P13
March 15, 2011 FN7571.1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2011. All Rights Reserved Intersil (and design) and FemtoCharge are trademarks owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners.
ISLA214P50 Pin Configuration - LVDS MODE
ISLA214P50 (72 LD QFN) TOP VIEW
OVDD AVDD AVDD AVDD OVSS OVSS SDIO SCLK ORN SDO D0N D1N D2N 55 54 D3P 53 D3N 52 D4P 51 D4N 50 D5P 49 D5N 48 CLKOUTP 47 CLKOUTN 46 RLVDS 45 OVSS 44 D6P 43 D6N 42 D7P 41 D7N 40 D8P
Thermal Pad Not Drawn to Scale, Consult Mechanical Drawing for Physical Dimensions
ORP
D0P
D1P
72 DNC DNC NAPSLP VCM AVSS AVDD AVSS VINN VINN 1 2 3 4 5 6 7 8 9
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
VINP 10 VINP 11 AVSS 12 AVDD 13 AVSS 14 CLKDIV 15 IPTAT 16 DNC 17 RESETN 18 19 AVDD 20 AVDD 21 AVDD 22 CLKP 23 24 CLKDIVRSTP CLKN 25 CLKDIVRSTN 26 OVSS 27 OVDD 28 D13N 29 D13P 30 D12N 31 D12P 32 OVDD 33 D11N 34 D11P 35 D10N 36 D10P Connect Thermal Pad to AVSS
D2P
CSB
39 D8N 38 D9P 37 D9N
Pin Descriptions - 72 Ld QFN, LVDS Mode
PIN NUMBER 1, 2, 17 6, 13, 19, 20, 21, 70, 71, 72 5, 7, 12, 14 27, 32, 62 26, 45, 61, 65 3 4 8, 9 LVDS PIN NAME DNC AVDD AVSS OVDD OVSS NAPSLP VCM VINN Do Not Connect 1.8V Analog Supply Analog Ground 1.8V Output Supply Output Ground Tri-Level Power Control (Nap, Sleep modes) Common Mode Output Analog Input Negative LVDS PIN FUNCTION
2
FN7571.1 March 15, 2011
ISLA214P50 Pin Descriptions - 72 Ld QFN, LVDS Mode
PIN NUMBER 10, 11 15 16 18 22, 23 24, 25 28, 29 30, 31 33, 34 35, 36 37, 38 39, 40 41, 42 43, 44 46 47, 48 49, 50 51, 52 53, 54 55, 56 57, 58 59, 60 63, 64 66 67 68 69 Exposed Paddle LVDS PIN NAME VINP CLKDIV IPTAT RESETN CLKP, CLKN CLKDIVRSTP, CLKDIVRSTN D13N, D13P D12N, D12P D11N, D11P D10N, D10P D9N, D9P D8N, D8P D7N, D7P D6N, D6P RLVDS CLKOUTN, CLKOUTP D5N, D5P D4N, D4P D3N, D3P D2N, D2P D1N, D1P D0N, D0P ORN, ORP SDO CSB SCLK SDIO AVSS Analog Input Positive Tri-Level Clock Divider Control Temperature Monitor (Output current proportional to absolute temperature) Power On Reset (Active Low) Clock Input True, Complement Synchronous Clock Divider Reset True, Complement LVDS Bit 13 (MSB) Output Complement, True LVDS Bit 12 Output Complement, True LVDS Bit 11 Output Complement, True LVDS Bit 10 Output Complement, True LVDS Bit 9 Output Complement, True LVDS Bit 8 Output Complement, True LVDS Bit 7 Output Complement, True LVDS Bit 6 Output Complement, True LVDS Bias Resistor (connect to OVSS with 1%10kW) LVDS Clock Output Complement, True LVDS Bit 5 Output Complement, True LVDS Bit 4 Output Complement, True LVDS Bit 3 Output Complement, True LVDS Bit 2 Output Complement, True LVDS Bit 1 Output Complement, True LVDS Bit 0 (LSB) Output Complement, True LVDS Over Range Complement, True SPI Serial Data Output SPI Chip Select (active low) SPI Clock SPI Serial Data Input/Output Analog Ground
(Continued)
LVDS PIN FUNCTION
3
FN7571.1 March 15, 2011
ISLA214P50 Pin Configuration - CMOS MODE
ISLA214P50 (72 LD QFN) TOP VIEW
OVDD AVDD AVDD AVDD OVSS OVSS SDIO SCLK DNC DNC DNC DNC 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 Connect Thermal Pad to AVSS
Thermal Pad Not Drawn to Scale, Consult Mechanical Drawing for Physical Dimensions
SDO
CSB
OR
D0
D1
72 DNC DNC NAPSLP VCM AVSS AVDD AVSS VINN VINN 1 2 3 4 5 6 7 8 9
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
D2
D3 DNC D4 DNC D5 DNC CLKOUT DNC RLVDS OVSS D6 DNC D7 DNC D8 DNC D9 DNC
VINP 10 VINP 11 AVSS 12 AVDD 13 AVSS 14 CLKDIV 15 IPTAT 16 DNC 17 RESETN 18 19 AVDD 20 AVDD 21 AVDD 22 23 CLKN CLKP 24 CLKDIVRSTP 25 CLKDIVRSTN 26 OVSS 27 OVDD 28 DNC 29 D13 30 DNC 31 D12 32 OVDD 33 DNC 34 D11 35 DNC 36 D10
38 37
Pin Descriptions - 72 Ld QFN, CMOS Mode
PIN NUMBER 1, 2, 17, 28, 30, 33, 35, 37, 39, 41, 43, 47, 49, 51, 53, 55, 57, 59, 63 6, 13, 19, 20, 21, 70, 71, 72 5, 7, 12, 14 27, 32, 62 26, 45, 61, 65 3 4 CMOS PIN NAME DNC AVDD AVSS OVDD OVSS NAPSLP VCM Do Not Connect 1.8V Analog Supply Analog Ground 1.8V Output Supply Output Ground Tri-Level Power Control (Nap, Sleep modes) Common Mode Output CMOS PIN FUNCTION
4
FN7571.1 March 15, 2011
ISLA214P50 Pin Descriptions - 72 Ld QFN, CMOS Mode
PIN NUMBER 8, 9 10, 11 15 16 18 22, 23 24, 25 29 31 34 36 38 40 42 44 46 48 50 52 54 56 58 60 64 66 67 68 69 Exposed Paddle CMOS PIN NAME VINN VINP CLKDIV IPTAT RESETN CLKP, CLKN CLKDIVRSTP, CLKDIVRSTN D13 D12 D11 D10 D9 D8 D7 D6 RLVDS CLKOUT D5 D4 D3 D2 D1 D0 OR SDO CSB SCLK SDIO AVSS Analog Input Negative Analog Input Positive Tri-Level Clock Divider Control Temperature Monitor (Output current proportional to absolute temperature) Power On Reset (Active Low) Clock Input True, Complement Synchronous Clock Divider Reset True, Complement CMOS Bit 13 (MSB) Output CMOS Bit 12 Output CMOS Bit 11 Output CMOS Bit 10 Output CMOS Bit 9 Output CMOS Bit 8 Output CMOS Bit 7 Output CMOS Bit 6 Output LVDS Bias Resistor (connect to OVSS with 1%10kW) CMOS Clock Output CMOS Bit 5 Output CMOS Bit 4 Output CMOS Bit 3 Output CMOS Bit 2 Output CMOS Bit 1 Output CMOS Bit 0 (LSB) Output CMOS Over Range SPI Serial Data Output SPI Chip Select (active low) SPI Clock SPI Serial Data Input/Output Analog Ground
(Continued)
CMOS PIN FUNCTION
5
FN7571.1 March 15, 2011
ISLA214P50 Ordering Information
PART NUMBER (Notes 1, 2) ISLA214P50IRZ ISLA214P50IR72EV1Z NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate--e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. For Moisture Sensitivity Level (MSL), please see device information page for ISLA214P50. For more information on MSL please see techbrief TB363. PART MARKING ISLA214P50 IRZ Evaluation Board TEMP. RANGE (C) -40 to +85 PACKAGE (Pb-free) 72 Ld QFN PKG. DWG. # L72.10x10E
6
FN7571.1 March 15, 2011
ISLA214P50 Table of Contents
Key Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin-Compatible Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin Descriptions - 72 Ld QFN, LVDS Mode . . . . . . . . . . . . . 2 Pin Descriptions - 72 Ld QFN, CMOS Mode . . . . . . . . . . . . 4 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Digital Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 I2E Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Switching Specifications. . . . . . . . . . . . . . . . . . . . . . . . 13 Typical Performance Curves. . . . . . . . . . . . . . . . . . . . . . . 14 Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Power-On Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 User Initiated Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Temperature Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . 19 Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Nap/Sleep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 I2E Requirements and Restrictions. . . . . . . . . . . . . . . . . 21 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Active Run State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Power Meter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 FS/4 Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Nyquist Zones . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Configurability and Communication . . . . . . . . . . . . . . .22 Clock Divider Synchronous Reset . . . . . . . . . . . . . . . . . . . 22 Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . 25 SPI Physical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 25 SPI Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Device Configuration/Control . . . . . . . . . . . . . . . . . . . .26 Address 0x60-0x64: I2E initialization . . . . . . . . . . . . . 28 Global Device Configuration/Control . . . . . . . . . . . . . .28 SPI Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Equivalent Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 A/D Evaluation Platform . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Split Ground and Power Planes . . . . . . . . . . . . . . . . . . 35 Clock Input Considerations . . . . . . . . . . . . . . . . . . . . . .35 Exposed Paddle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Bypass and Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 LVDS Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 LVCMOS Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Unused Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . 37
7
FN7571.1 March 15, 2011
ISLA214P50
Absolute Maximum Ratings
AVDD to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.4V to 2.1V OVDD to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.4V to 2.1V AVSS to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V Analog Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V Clock Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V Logic Input to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V Logic Inputs to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V Latchup (Tested per JESD-78C;Class 2,Level A . . . . . . . . . . . . . . . . 100mA
Thermal Information
Thermal Resistance (Typical) JA (C/W) JC (C/W) 72 Ld QFN (Notes 3, 4) . . . . . . . . . . . . . . . . 23 0.9 Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 3. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 4. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V, TA = -40C to +85C (typical specifications at +25C), AIN = -1dBFS, fSAMPLE = 500MSPS. Boldface limits apply over the operating temperature range, -40C to +85C.
ISLA214P50 PARAMETER SYMBOL CONDITIONS MIN (Note 5) TYP MAX (Note 5) UNITS
Electrical Specifications
DC SPECIFICATIONS (Note 6) Analog Input
Full-Scale Analog Input Range Input Resistance Input Capacitance Full Scale Range Temp. Drift Input Offset Voltage Common-Mode Output Voltage Common-Mode Input Current (per pin) Clock Inputs Inputs Common Mode Voltage CLKP, CLKN Input Swing 0.9 1.8 V V VFS RIN CIN AVTC VOS VCM ICM Differential Differential Differential Full Temp -5.0 1.95 2.0 300 9 160 -1.3 0.94 2.6 5.0 2.15 VP-P pF ppm/C mV V A/MSPS
Power Requirements
1.8V Analog Supply Voltage 1.8V Digital Supply Voltage 1.8V Analog Supply Current 1.8V Digital Supply Current (Note 6) Power Supply Rejection Ratio AVDD OVDD IAVDD IOVDD PSRR 3mA LVDS, (I2E powered down, Fs/4 Filter powered down) 30MHz, 45mVP-P signal on AVDD 1.7 1.7 1.8 1.8 374 90 60 1.9 1.9 391 104 V V mA mA dB
8
FN7571.1 March 15, 2011
ISLA214P50
All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V, TA = -40C to +85C (typical specifications at +25C), AIN = -1dBFS, fSAMPLE = 500MSPS. Boldface limits apply over the operating temperature range, -40C to +85C. (Continued)
ISLA214P50 PARAMETER SYMBOL CONDITIONS MIN (Note 5) TYP MAX (Note 5) UNITS
Electrical Specifications
Total Power Dissipation
Normal Mode PD 2mA LVDS, (I2E powered down, Fs/4 Filter powered down) 3mA LVDS, (I2E powered down, Fs/4 Filter powered down) 3mA LVDS, (I2E on, Fs/4 Filter off) 3mA LVDS, (I2E on, Fs/4 Filter on) Nap Mode Sleep Mode Nap/Sleep Mode Wakeup Time PD PD CSB at logic high Sample Clock Running 809 835 867 900 89 7 200 958 104 19 891 mW mW mW mW mW mW s
AC SPECIFICATIONS
Differential Nonlinearity Integral Nonlinearity Minimum Conversion Rate (Note 7) Maximum Conversion Rate Signal-to-Noise Ratio (Note 8) DNL INL fS MIN fS MAX SNR fIN = 30MHz fIN = 105MHz fIN = 190MHz fIN = 363MHz fIN = 461MHz fIN = 605MHz Signal-to-Noise and Distortion (Note 8) SINAD fIN = 30MHz fIN = 105MHz fIN = 190MHz fIN = 363MHz fIN = 461MHz fIN = 605MHz Effective Number of Bits (Note 8) ENOB fIN = 30MHz fIN = 105MHz fIN = 190MHz fIN = 363MHz fIN = 461MHz fIN = 605MHz 11.09 68.5 69.0 500 72.7 72.6 71.9 70.6 70.0 68.3 72.2 71.7 70.7 69.3 64.7 60.7 11.70 11.62 11.44 11.22 10.45 9.79 fIN = 105MHz No Missing Codes fin = 105MHz -0.99 0.5 2.5 80 1.4 LSB LSB MSPS MSPS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS Bits Bits Bits Bits Bits Bits
9
FN7571.1 March 15, 2011
ISLA214P50
All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V, TA = -40C to +85C (typical specifications at +25C), AIN = -1dBFS, fSAMPLE = 500MSPS. Boldface limits apply over the operating temperature range, -40C to +85C. (Continued)
ISLA214P50 PARAMETER Spurious-Free Dynamic Range (Note 8) SYMBOL SFDR fIN = 30MHz fIN = 105MHz fIN = 190MHz fIN = 363MHz fIN = 461MHz fIN = 605MHz Spurious-Free Dynamic Range Excluding H2,H3 (Note 8) SFDRX23 fIN = 30MHz fIN = 105MHz fIN = 190MHz fIN = 363MHz fIN = 461MHz fIN = 605MHz Intermodulation Distortion IMD fIN = 70MHz fIN = 170MHz Word Error Rate Full Power Bandwidth NOTES: 5. Compliance to datasheet limits is assured by one of the following methods: production test, characterization and/or design. 6. Digital Supply Current is dependent upon the capacitive loading of the digital outputs. IOVDD specifications apply for 10pF load on each digital output. 7. The DLL Range setting must be changed for low speed operation. 8. Minimum specification guaranteed when calibrated at +85C. WER FPBW 72 CONDITIONS MIN (Note 5) TYP 84 82 78 76 66 61 88 89 88 83 84 77 88 96 10-12 700 MHz MAX (Note 5) UNITS dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBFS dBFS
Electrical Specifications
Digital Specifications
Boldface limits apply over the operating temperature range, -40C to +85C.
SYMBOL IIH IIL IIH IIL IIH IIL IIH IIL VIH VIL CDI VICM VID 825 250 4 1575 450 CONDITIONS VIN = 1.8V VIN = 0V VIN = 1.8V VIN = 0V VIN = 1.8V VIN = 0V 16 -34 1.17 .63 -600 40 MIN (Note 5) 0 -25 TYP 1 -12 4 -415 58 5 25 -25 MAX (Note 5) 10 -8 12 -300 75 10 34 -16 UNITS A A A A A A A A V V pF mV mV
PARAMETER
INPUTS (Note 9)
Input Current High (RESETN) Input Current Low (RESETN) Input Current High (SDIO) Input Current Low (SDIO) Input Current High (CSB) Input Current Low (CSB) Input Current High (CLKDIV) Input Current Low (CLKDIV) Input Voltage High (SDIO, RESETN) Input Voltage Low (SDIO, RESETN) Input Capacitance
LVDS INPUTS (CLKRSTP,CLKRSTN)
Input Common Mode Range Input Differential Swing (peak to peak, single-ended)
10
FN7571.1 March 15, 2011
ISLA214P50
Digital Specifications
Boldface limits apply over the operating temperature range, -40C to +85C. (Continued)
SYMBOL RIpd RIpu VT VOS tR tF VOH VOL tR tF IOH = -500A IOL = 1mA 3mA Mode 3mA Mode 1120 CONDITIONS MIN (Note 5) TYP 100 100 612 1150 240 240 OVDD - 0.3 OVDD - 0.1 0.1 1.8 1.4 0.3 1200 MAX (Note 5) UNITS k k mVP-P mV ps ps V V ns ns
PARAMETER CLKDIVRSTP Input Pull-down Resistance CLKDIVRSTN Input Pull-up Resistance
LVDS OUTPUTS
Differential Output Voltage (Note 10) Output Offset Voltage Output Rise Time Output Fall Time
CMOS OUTPUTS
Voltage Output High Voltage Output Low Output Rise Time Output Fall Time NOTES: 9. The Tri-Level Inputs internal switching thresholds are approximately. 0.43V and 1.34V. It is advised to float the inputs, tie to ground or AVDD depending on desired function. 10. The voltage is expressed in peak-to-peak differential swing. The peak-to-peak singled-ended swing is 1/2 of the differential swing.
I2E Specifications
Boldface limits apply over the operating temperature range, -40C to +85C.
SYMBOL CONDITIONS No I2E Calibration performed Active Run state enabled I2Epost_t tTE Calibration settling time for Active Run state Allow one I2E iteration of Offset, Gain and Phase correction fIN = 10MHz to 240MHz, Active Run State enabled, in Track Mode fIN = 10MHz to 240MHz, Active Run State enabled and previously settled, in Hold Mode fIN = 260MHz to 490MHz, Active Run State enabled, in Track Mode fIN = 260MHz to 490MHz, Active Run State enabled and previously settled, in Hold Mode -75 -99 -80 MIN (Note 5) TYP -65 -70 1000 100 MAX (Note 5) UNITS dBFS dBFS ms s dBc dBc
PARAMETER Offset Mismatch-induced Spurious Power I2E Settling Times Minimum Duration of Valid Analog Input Largest Interleave Spur
-99 -75
dBc dBc
Total Interleave Spurious Power
Active Run State enabled, in Track Mode, fIN is a broadband signal in the 1st Nyquist zone Active Run State enabled, in Track Mode, fIN is a broadband signal in the 2nd Nyquist zone
-85
dBc
-75
dBc
Sample Time Mismatch Between Unit ADCs Gain Mismatch Between Unit ADCs Offset Mismatch Between Unit ADCs
Active Run State enabled, in Track Mode
25 0.01 1
fs %FS mV
11
FN7571.1 March 15, 2011
ISLA214P50 Timing Diagrams
INP
INN tA CLKN CLKP tCPD CLKOUTN CLKOUTP tDC tPD DATA N-L D[13:0]P DATA N-L+1 DATA N LATENCY = L CYCLES
D[13:0]N
FIGURE 1A. LVDS
INP
INN tA
CLK tCPD LATENCY = L CYCLES
CLKOUT tDC tPD DATA N-L D[13:0] DATA N-L+1 DATA N
FIGURE 1B. CMOS FIGURE 1. TIMING DIAGRAMS
12
FN7571.1 March 15, 2011
ISLA214P50
Switching Specifications
PARAMETER
Boldface limits apply over the operating temperature range, -40C to +85C.
CONDITION SYMBOL MIN (Note 5) TYP MAX (Note 5) UNITS
ADC OUTPUT
Aperture Delay RMS Aperture Jitter Input Clock to Output Clock Propagation Delay AVDD, OVDD = 1.7V to 1.9V, TA = -40C to +85C AVDD, OVDD = 1.8V, TA = +25C Relative Input Clock to Output Clock Propagation Delay (Note 13) Input Clock to Data Propagation Delay Output Clock to Data Propagation Delay, LVDS Mode Output Clock to Data Propagation Delay, CMOS Mode Synchronous Clock Divider Reset Setup Time (with respect to the positive edge of CLKP) Synchronous Clock Divider Reset Hold Time (with respect to the positive edge of CLKP) Synchronous Clock Divider Reset Recovery Time Latency (Pipeline Delay) Overvoltage Recovery DLL recovery time after Synchronous Reset Rising/Falling Edge Rising/Falling Edge AVDD, OVDD = 1.7V to 1.9V, TA = -40C to +85C tA jA tCPD tCPD dtCPD tPD tDC tDC tRSTS 1.65 1.9 -450 1.65 -0.1 -0.1 0.4 2.4 0.16 0.2 0.06 114 75 2.4 2.3 3 2.75 450 3.5 0.5 0.65 ps fs ns ns ps ns ns ns ns
tRSTH tRSTRT L tOVR
t CLK
0.02 52 20 2
0.35
ns s cycles cycles
SPI INTERFACE (Notes 11, 12)
SCLK Period Write Operation Read Operation CSB to SCLK Setup Time CSB after SCLK Hold Time Data Valid to SCLK Setup Time Data Valid after SCLK Hold Time Data Valid after SCLK Time NOTES: 11. SPI Interface timing is directly proportional to the ADC sample period (tS). Values above reflect multiples of a 4ns sample period, and must be scaled proportionally for lower sample rates. ADC sample clock must be running for SPI communication. 12. The SPI may operate asynchronously with respect to the ADC sample clock. 13. The relative propagation delay is the difference in propagation time between any two devices that are matched in temperature and voltage, and is specified over the full operating temperature and voltage range. Read or Write Write Write Read or Write Read 32 32 56 10 12 8 10 cycles cycles cycles cycles cycles cycles cycles
tCLK tS tH tDS tDH tDVR
13
FN7571.1 March 15, 2011
ISLA214P50 Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA = +25C, AIN = -1dBFS, fIN = 105MHz, fSAMPLE = 500MSPS.
95 SNR (dBFS) AND SFDR (dBc) 90 SFDR (EXCLUDING H2,H3) 85 80 75 70 65 60 55 0 100 200 300 400 500 600 SNR SFDR HD2 AND HD3 MAGNITUDE (dBc) -55 -60 -65 -70 -75 -80 HD3 -85 -90 -95 0 100 200 300 400 INPUT FREQUENCY (MHz) 500 600 HD2
INPUT FREQUENCY (MHz)
FIGURE 2. SNR AND SFDR vs fIN
FIGURE 3. HD2 AND HD3 vs fIN
100 90 80 SNR AND SFDR SNR AND SFDR 70 60 50 40 30 20 10 -60 -50 -40 -30 -20 -10 0 SNR (dBFS) SFDR (dBc) SNR (dBc) SFDR (dBFS)
-30 -40 HD2 (dBc) -50 -60 HD3 (dBc) -70 -80 -90 -100 -110 -120 -60 HD3 (dBFS) -50 -40 -30 -20 -10 0 HD2 (dBFS)
INPUT AMPLITUDE (dBFS)
INPUT AMPLITUDE (dBFS)
FIGURE 4. SNR AND SFDR vs AIN
FIGURE 5. HD2 AND HD3 vs AIN
90 SNR (dBFS) AND SFDR (dBc)
-75 -80 H3 -85
85
SFDR
80
dBc
-90 -95 H2
75 SNR 70 250 300 350 400 SAMPLE RATE (MSPS) 450 500
-100 -105 250
300
350 400 SAMPLE RATE (MSPS)
450
500
FIGURE 6. SNR AND SFDR vs f SAMPLE
FIGURE 7. HD2 AND HD3 vs fSAMPLE
14
FN7571.1 March 15, 2011
ISLA214P50 Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA = +25C, AIN = -1dBFS, fIN = 105MHz, fSAMPLE = 500MSPS. (Continued)
900 1.00 0.75 850 TOTAL POWER (mW) 0.50 DNL (LSBs) 0.25 0 -0.25 -0.50 700 -0.75 650 250 300 350 400 SAMPLE RATE (MSPS) 450 500 -1.00 0 2000 4000 6000 8000 10000 12000 14000 16000 CODE
800
750
FIGURE 8. POWER vs fSAMPLE IN 3mA LVDS MODE
FIGURE 9. DIFFERENTIAL NONLINEARITY
4 SNR (dBFS) AND SFDR (dBc) 0 2000 4000 6000 8000 10000 12000 14000 16000 CODE 3 2 INL (LSBs) 1 0 -1 -2 -3 -4
90 85 80 75 70 65 60 0.75
0.80
0.85
0.90
0.95 1.00 VCM (V)
1.05
1.10
1.15
FIGURE 10. INTEGRAL NONLINEARITY
FIGURE 11. SNR AND SFDR vs VCM
70000 60000 NUMBER OF HITS 50000 40000 30000 20000 10000 0 0 4 9157 64 1117 CODE 6846 1145 77 8 0 39405 32263 57701 AMPLITUDE (dBFS) 52213
0 -20 -40 -60 -80 -100 -120 0 AIN = -1 dBFS SNR = 72.7 dBFS SFDR = 81 dBc SINAD = 71.81 dBFS
8174 8175 8176 8177 8178 8179 8180 8181 8182 8183 8184 8185 8186 8187
50
100 150 FREQUENCY (MHz)
200
250
FIGURE 12. NOISE HISTOGRAM
FIGURE 13. SINGLE-TONE SPECTRUM @ 105MHz
15
FN7571.1 March 15, 2011
ISLA214P50 Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA = +25C, AIN = -1dBFS, fIN = 105MHz, fSAMPLE = 500MSPS. (Continued)
0 AIN = -1 dBFS SNR = 72.2 dBFS -20 SFDR = 79 dBc SINAD = 70.8 dBFS -40 -60 -80 -100 -120 0 50 100 150 FREQUENCY (MHz) 200 250 0 AIN = -1.0 dBFS -20 AMPLITUDE (dBFS) -40 -60 -80 -100 -120 SNR = 70.6 dBFS SFDR = 75 dBc SINAD = 69.4 dBFS
AMPLITUDE (dBFS)
0
50
100 150 FREQUENCY (MHz)
200
250
FIGURE 14. SINGLE-TONE SPECTRUM @ 190MHz
FIGURE 15. SINGLE-TONE SPECTRUM @ 363MHz
0 -20 AMPLITUDE (dBFS) -40 IMD2 IMD3 2ND HARMONICS 3RD HARMONICS AMPLITUDE (dBFS)
0 -20 -40 IMD2 IMD3 2ND HARMONICS 3RD HARMONICS
-60 -80 IMD3 = -88 dBFS -100 -120
-60 -80 -100 -120 0 50 100 150 200 250 FREQUENCY (MHz)
IMD3 = -96 dBFS
0
50
100
150
200
250
FREQUENCY (MHz)
FIGURE 16. TWO-TONE SPECTRUM (F1 = 70MHz, F2 = 71MHz -7dBFS)
FIGURE 17. TWO-TONE SPECTRUM (F1 = 170MHz, F2 = 171MHz -7dBFS)
SNR (dBFS), SFDR (dBc) AND FIS (dBc)
SNR (dBFS), SFDR (dBc) AND FIS (dBc)
100 95 90 85 80 SFDR 75 70 65 SNR FIS (INTERLEAVING SPUR) FIS IS APPROX. 96dB BELOW FULL SCALE AT CAL FREQUENCY
100 95 90 85 80 75 70 SNR 65 60 250 300 350 400 FREQUENCY (MHz) 450 500 SFDR FIS IS APPROX. 97dB BELOW FULL SCALE AT CAL FREQUENCY
FIS (INTERLEAVING SPUR)
30
50
70
90
110 130 150 170 190 210 230 250 FREQUENCY (MHz)
FIGURE 18. INPUT FREQUENCY SWEEP WITH I2E FROZEN, I2E PREVIOUSLY CALIBRATED AT 105MHZ
FIGURE 19. INPUT FREQUENCY SWEEP WITH I2E FROZEN, I2E PREVIOUSLY CALIBRATED AT 363MHZ
16
FN7571.1 March 15, 2011
ISLA214P50 Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA = +25C, AIN = -1dBFS, fIN = 105MHz, fSAMPLE = 500MSPS. (Continued)
SFDR IS DETERMINED BY FIS (INTERLEAVING SPUR) SNR (dBFS) AND SFDR (dBc) 80 SFDR (= FIS) 75 SNR (dBFS), SFDR (dBc) AND FIS (dBc) 85 100 95 90 FIS 85 SFDR 80 75 70 65 1.70 SNR
70
SNR
65
60 -40
-20
0
20
40
60
80
1.75
1.80
1.85
1.90
TEMPERATURE (C)
SUPPLY VOLTAGE (AVDD)
FIGURE 20. TEMPERATURE SWEEP WITH I2E FROZEN, I2E PREVIOUSLY CALIBRATED AT +25C, F IN = 105MHZ
FIGURE 21. ANALOG SUPPLY VOLTAGE SWEEP WITH I2E FROZEN, I2E PREVIOUSLY CALIBRATED AT 1.8V, FIN = 105MHZ
Theory of Operation
Functional Description
The ISLA214P50 is based upon a 14-bit, 250MSPS A/D converter core that utilizes a pipelined successive approximation architecture (Figure 22). The input voltage is captured by a Sample-Hold Amplifier (SHA) and converted to a unit of charge. Proprietary charge-domain techniques are used to successively compare the input to a series of reference charges. Decisions made during the successive approximation operations determine the digital code for each input value. Digital error correction is also applied, resulting in a total latency of 20 clock cycles. This is evident to the user as a latency between the start of a conversion and the data being available on the digital outputs. The device contains two core A/D converters with carefully matched transfer characteristics. The cores are clocked on alternate clock edges, resulting in a doubling of the sample rate. Time-interleaved A/D systems can exhibit non-ideal artifacts in the frequency domain if the individual core A/D characteristics are not well matched. Gain, offset and timing skew mismatches are of primary concern. The Intersil Interleave Engine (I2E) performs automatic interleave calibration for the offset, gain, and sample time skew mismatch between the core A/Ds. The I2E circuitry also adjusts in real-time for temperature and voltage variations. Residual gain and sample time skew mismatch result in fundamental image spurs at fNYQUIST fIN. Offset mismatches create spurs at DC and multiples of fNYQUIST.
analog and digital supply voltages are above a threshold. The following conditions must be adhered to for the power-on calibration to execute successfully: * A frequency-stable conversion clock must be applied to the CLKP/CLKN pins * DNC pins must not be connected * SDO has an internal pull-up and should not be driven externally * RESETN is pulled low by the ADC internally during POR. External driving of RESETN is optional. * SPI communications must not be attempted A user-initiated reset can subsequently be invoked in the event that the above conditions cannot be met at power-up. After the power supply has stabilized the internal POR releases RESETN and an internal pull-up pulls it high, which starts the calibration sequence. If a subsequent user-initiated reset is desired, the RESETN pin should be connected to an open-drain driver with an off-state/high impedance state leakage of less than 0.5mA to assure exit from the reset state so calibration can start. The calibration sequence is initiated on the rising edge of RESETN, as shown in Figure 23. Calibration status can be determined by reading the cal_status bit (LSB) at 0xB6. This bit is `0' during calibration and goes to a logic `1' when calibration is complete. The data outputs output 0xCCCC during calibration; this can also be used to determine calibration status. While RESETN is low, the output clock (CLKOUTP/CLKOUTN) is set low. Normal operation of the output clock resumes at the next input clock edge (CLKP/CLKN) after RESETN is de-asserted. At 250MSPS the nominal calibration time is 200ms, while the maximum calibration time is 550ms.
Power-On Calibration
As mentioned previously, the cores perform a self-calibration at start-up. An internal power-on-reset (POR) circuit detects the supply voltage ramps and initiates the calibration when the
17
FN7571.1 March 15, 2011
ISLA214P50
CLOCK GENERATION
INP SHA INN 2.5-BIT FLASH
2.5-BIT FLASH
6- STAGE 1.5-BIT/ STAGE
3- STAGE 1- BIT/ STAGE
3-BIT FLASH
1.25V
+ -
DIGITAL ERROR CORRECTION
LVDS/ LVCMOS OUTPUTS
FIGURE 22. A/D CORE BLOCK DIAGRAM
CLKN CLKP CALIBRATION TIME RESETN CAL_STATUS BIT CALIBRATION BEGINS
changes may necessitate recalibration, depending on system performance requirements. Best performance will be achieved by recalibrating the A/D under the environmental conditions at which it will operate. A supply voltage variation of less than 100mV will generally result in an SNR change of less than 0.5dBFS and SFDR change of less than 3dBc.
CALIBRATION COMPLETE CLKOUTP
FIGURE 23. CALIBRATION TIMING
In situations where the sample rate is not constant, best results will be obtained if the device is calibrated at the highest sample rate. Reducing the sample rate by less than 80MSPS will typically result in an SNR change of less than 0.5dBFS and an SFDR change of less than 3dBc. Figures 24 through 26 show the effect of temperature on SNR and SFDR performance with power on calibration performed at -40C, +25C, and +85C. Each plot shows the variation of SNR/SFDR across temperature after a single power on calibration at -40C, +25C and +85C. Best performance is typically achieved by a user-initiated power on calibration at the operating conditions, as stated earlier. Applications working across the full temperature range can use the on-chip calibration feature to maximize performance when large temperature variations are expected.
User Initiated Reset
Recalibration of the A/D can be initiated at any time by driving the RESETN pin low for a minimum of one clock cycle. An open-drain driver with a drive strength in its high impedance state of less than 0.5mA is recommended, as RESETN has an internal high impedance pull-up to OVDD. As is the case during power-on reset, RESETN and DNC pins must be in the proper state for the calibration to successfully execute. The performance of the ISLA214P50 changes with variations in temperature, supply voltage or sample rate. The extent of these
18
FN7571.1 March 15, 2011
ISLA214P50 Temperature Calibration
90 SFDR (dBc) SFDR (dBc) 85 SNR AND SFDR SNR AND SFDR SNR (dBFS) 85 90
80
80
75
75
SNR (dBFS)
70 -40
-35
-30 TEMPERATURE (C)
-25
-20
70
5
10
15
20
25
30
35
40
45
TEMPERATURE (C)
FIGURE 24. TYPICAL SNR, SFDR PERFORMANCE vs TEMPERATURE,DEVICE CALIBRATED AT -40C, 500MSPS OPERATION, fIN = 105MHz
FIGURE 25. TYPICAL SNR, SFDR PERFORMANCE vs TEMPERATURE, DEVICE CALIBRATED AT +25C, 500MSPS OPERATION, fIN = 105MHz
85
SNR AND SFDR
80
SFDR (dBc)
Best performance is obtained when the analog inputs are driven differentially. The common-mode output voltage, VCM, should be used to properly bias the inputs as shown in Figures 28 through 30. An RF transformer will give the best noise and distortion performance for wideband and/or high intermediate frequency (IF) inputs. Two different transformer input schemes are shown in Figures 28 and 29.
ADT1-1WT ADT1-1WT
75
1000pF
SNR (dBFS) 70 65
A/D
VCM
70
75 TEMPERATURE (C)
80
85
0.1F
FIGURE 26. TYPICAL SNR, SFDR PERFORMANCE vs TEMPERATURE, DEVICE CALIBRATED AT +85C, 500MSPS OPERATION, fIN = 105MHz
Analog Input
A single fully differential input (VINP/VINN) connects to the sample and hold amplifier (SHA) of each unit A/D. The ideal full-scale input voltage is 2.0V, centered at the VCM voltage of 0.94V as shown in Figure 27.
1.8 VINP 1.4 1.0 0.6 0.2 1.0V VCM 0.94V VINN
FIGURE 28. TRANSFORMER INPUT FOR GENERAL PURPOSE APPLICATIONS
ADTL1-12 TX-2-5-1
1000pF
A/D
VCM
1000pF
FIGURE 29. TRANSMISSION-LINE TRANSFORMER INPUT FOR HIGH IF APPLICATIONS
This dual transformer scheme is used to improve common-mode rejection, which keeps the common-mode level of the input matched to VCM. The value of the shunt resistor should be determined based on the desired load impedance. The differential input resistance of the ISLA214P50 is 300. The SHA design uses a switched capacitor input stage (see Figure 43 on page 34), which creates current spikes when the sampling capacitance is reconnected to the input voltage. This causes a disturbance at the input which must settle before the
FIGURE 27. ANALOG INPUT RANGE
19
FN7571.1 March 15, 2011
ISLA214P50
next sampling point. Lower source impedance will result in faster settling and improved performance. Therefore a 1:1 transformer and low shunt resistance are recommended for optimal performance.
TABLE 1. CLKDIV PIN SETTINGS CLKDIV PIN AVSS Float AVDD DIVIDE RATIO 2 1 Not Allowed
Jitter
A/D
In a sampled data system, clock jitter directly impacts the achievable SNR performance. The theoretical relationship between clock jitter (tJ) and SNR is shown in Equation 1 and is illustrated in Figure 32.
1 SNR = 20 log 10 ------------------ 2f t
IN J 100 95 90 85 SNR (dB) 80 75 70 65 60 55 50 1M 10M 100M INPUT FREQUENCY (Hz) 1G tj = 100ps tj = 10ps 10 BITS tj = 1ps 12 BITS tj = 0.1ps 14 BITS
(EQ. 1)
FIGURE 30. DIFFERENTIAL AMPLIFIER INPUT
A differential amplifier, as shown in the simplified block diagram in Figure 30, can be used in applications that require DC-coupling. In this configuration, the amplifier will typically dominate the achievable SNR and distortion performance. Intersil's new ISL552xx differential amplifier family can also be used in certain AC applications with minimal performance degradation. Contact the factory for more information.
Clock Input
The clock input circuit is a differential pair (see Figure 44). Driving these inputs with a high level (up to 1.8VP-P on each input) sine or square wave will provide the lowest jitter performance. A transformer with 4:1 impedance ratio will provide increased drive levels. The clock input is functional with AC-coupled LVDS, LVPECL, and CML drive levels. To maintain the lowest possible aperture jitter, it is recommended to have high slew rate at the zero crossing of the differential clock input signal. The recommended drive circuit is shown in Figure 31. A duty range of 40% to 60% is acceptable. The clock can be driven single-ended, but this will reduce the edge rate and may impact SNR performance. The clock inputs are internally self-biased to AVDD/2 to facilitate AC coupling.
TC4-19G2+ 1000pF CLKP
FIGURE 32. SNR vs CLOCK JITTER
This relationship shows the SNR that would be achieved if clock jitter were the only non-ideal factor. In reality, achievable SNR is limited by internal factors such as linearity, aperture jitter and thermal noise. Internal aperture jitter is the uncertainty in the sampling instant shown in Figure1A. The internal aperture jitter combines with the input clock jitter in a root-sum-square fashion, since they are not statistically correlated, and this determines the total jitter in the system. The total jitter, combined with other noise sources, then determines the achievable SNR.
Voltage Reference
A temperature compensated internal voltage reference provides the reference charges used in the successive approximation operations. The full-scale range of each A/D is proportional to the reference voltage. The nominal value of the voltage reference is 1.25V.
0.01F
200
1000pF 1000pF
CLKN
Digital Outputs
Output data is available as a parallel bus in LVDS-compatible(default) or CMOS modes. In either case, the data is presented in double data rate (DDR) format. Figures 1A and 1B show the timing relationships for LVDS and CMOS modes, respectively. Additionally, the drive current for LVDS mode can be set to a nominal 3mA(default) or a power-saving 2mA. The lower current setting can be used in designs where the receiver is in close physical proximity to the A/D. The applicability of this setting is dependent upon the PCB layout, therefore the user should
FIGURE 31. RECOMMENDED CLOCK DRIVE
A selectable 2x frequency divider is provided in series with the clock input. The divider can be used in the 2x mode with a sample clock equal to twice the desired sample rate. This allows the use of the Phase Slip feature, which enables synchronization of multiple ADCs. The Phase Slip feature can be used as an alternative to using the CLKDIVRST pins to synchronize ADCs in a multiple ADC system.
20
FN7571.1 March 15, 2011
ISLA214P50
experiment to determine if performance degradation is observed. The output mode can be controlled through the SPI port, by writing to address 0x73, see "Serial Peripheral Interface" on page 25. An external resistor creates the bias for the LVDS drivers. A 10k, 1% resistor must be connected from the RLVDS pin to OVSS.
BINARY 13 12 11
****
1
0
****
Power Dissipation
The power dissipated by the ISLA214P50 is primarily dependent on the sample rate and the output modes: LVDS vs CMOS and DDR vs SDR. There is a static bias in the analog supply, while the remaining power dissipation is linearly related to the sample rate. The output supply dissipation changes to a lesser degree in LVDS mode, but is more strongly related to the clock frequency in CMOS mode.
GRAY CODE
13
12
11
****
1
0
FIGURE 33. BINARY TO GRAY CODE CONVERSION
Converting back to offset binary from Gray code must be done recursively, using the result of each bit for the next lower bit as shown in Figure 34.
GRAY CODE 13 12 11
****
1
0
Nap/Sleep
Portions of the device may be shut down to save power during times when operation of the A/D is not required. Two power saving modes are available: Nap, and Sleep. Nap mode reduces power dissipation to less than 104mW while Sleep mode reduces power dissipation to less than 19mW. All digital outputs (Data, CLKOUT and OR) are placed in a high impedance state during Nap or Sleep. The input clock should remain running and at a fixed frequency during Nap or Sleep, and CSB should be high. Recovery time from Nap mode will increase if the clock is stopped, since the internal DLL can take up to 52s to regain lock at 500MSPS. By default after the device is powered on, the operational state is controlled by the NAPSLP pin as shown in Table 2.
TABLE 2. NAPSLP PIN SETTINGS NAPSLP PIN AVSS Float AVDD MODE Normal Sleep Nap
BINARY 13 12 11
****
****
****
1
0
Mapping of the input voltage to the various data formats is shown in Table 3.
TABLE 3. INPUT VOLTAGE TO OUTPUT CODE MAPPING INPUT VOLTAGE -Full Scale -Full Scale + 1LSB Mid-Scale +Full Scale - 1LSB +Full Scale OFFSET BINARY 00 0000 0000 0000 00 0000 0000 0001 10 0000 0000 0000 11 1111 1111 1110 11 1111 1111 1111 TWO'S COMPLEMENT 10 0000 0000 0000 10 0000 0000 0001 00 0000 0000 0000 01 1111 1111 1110 01 1111 1111 1111 GRAY CODE 00 0000 0000 0000 00 0000 0000 0001 11 0000 0000 0000 10 0000 0000 0001 10 0000 0000 0000
The power-down mode can also be controlled through the SPI port, which overrides the NAPSLP pin setting. Details on this are contained in "Serial Peripheral Interface" on page 25.
Data Format
Output data can be presented in three formats: two's complement (default), Gray code and offset binary. The data format can also be controlled through the SPI port, by writing to address 0x73. Details on this are contained in "Serial Peripheral Interface" on page 25. Offset binary coding maps the most negative input voltage to code 0x000 (all zeros) and the most positive input to 0xFFF (all ones). Two's complement coding simply complements the MSB of the offset binary representation. When calculating Gray code the MSB is unchanged. The remaining bits are computed as the XOR of the current bit position and the next most significant bit. Figure 33 shows this operation. 21
FN7571.1 March 15, 2011
ISLA214P50 I2E Requirements and Restrictions
Overview
I2E is a blind and background capable algorithm, designed to transparently eliminate interleaving artifacts. This circuitry eliminates interleave artifacts due to offset, gain, and sample time mismatches between unit A/Ds, and across supply voltage and temperature variations in real-time. Differences in the offset, gain, and sample times of time-interleaved A/Ds create artifacts in the digital outputs. Each of these artifacts creates a unique signature that may be detectable in the captured samples. The I2E algorithm optimizes performance by detecting error signatures and adjusting each unit A/D using minimal additional power. I2E calibration is off by default at power-up. The I2E algorithm can be put in Active Run state via SPI. When the I2E algorithm is in Active Run state, it detects and corrects for offset, gain, and sample time mismatches in real time (see Track Mode description under "Active Run State" on page 22). However, certain analog input characteristics can obscure the estimation of these mismatches. The I2E algorithm is capable of detecting these obscuring analog input characteristics, and as long as they are present I2E will stop updating the correction in real time. Effectively, this freezes the current correction circuitry to the last known-good state (see Hold Mode description under "Active Run State" on page 22). Once the analog input signal stops obscuring the interleaved artifacts, the I2E algorithm will automatically start correcting for mismatch in real time again. been met, the specifications of the device will continue to be met while I2E remains in Track Mode, even in the presence of temperature and supply voltage changes. 2. Hold Mode refers to the state of the I2E algorithm when the analog input signal does not meet the requirements specified above. If the algorithm detects that the signal no longer meets the criteria, it automatically enters Hold Mode. In Hold Mode, the I2E circuitry freezes the adjustment values based on the most recent set of valid input conditions. However, in Hold Mode, the I2E circuitry will not correct for new changes in interleave artifacts induced by supply voltage and temperature changes. The I2E circuitry will remain in Hold Mode until such time as the analog input signal meets the requirements for Track Mode.
Power Meter
The power meter calculates the average power of the analog input, and determines if it's within range to allow operation in Track Mode. Both AC RMS and total RMS power are calculated, and there are separate SPI programmable thresholds and hysteresis values for each.
FS/4 Filter
A digital filter removes the signal energy in a 100kHz band around fS/4 before the I2E circuitry uses these samples for estimating offset, gain, and sample time mismatches (data samples produced by the A/D are unaffected by this filtering). This allows the I2E algorithm to continue in Active Run state while in the presence of a large amount of input energy near the fS/4 frequency. This filter can be powered down if it's known that the signal characteristics won't violate the restrictions. Powering down the FS/4 filter will reduce power consumption by approximately 30mW.
Active Run State
During the Active Run state the I2E algorithm actively suppresses artifacts due to interleaving based on statistics in the digitized data. I2E has two modes of operation in this state (described in the following), dynamically chosen in real-time by the algorithm based on the statistics of the analog input signal. 1. Track Mode refers to the default state of the algorithm, when all artifacts due to interleaving are actively being eliminated. To be in Track Mode the analog input signal to the device must adhere to the following requirements: * Possess total power greater than -20dBFS, integrated from 1MHz to Nyquist but excluding signal energy in a 100kHz band centered at fS/4 The criteria above assumes 500MSPS operation; the frequency bands should be scaled proportionally for lower sample rates. Note that the effect of excluding energy in the 100kHz band around of fS/4 exists in every Nyquist zone. This band generalizes to the form (N*fS/4 - 50kHz) to (N*fS/4 + 50kHz), where N is any odd integer. An input signal that violates these criteria briefly (approximately 10s), before and after which it meets this criteria, will not impact system performance. The algorithm must be in Track Mode for approximately one second (defined as I2Epost_t on "I2E Specifications" on page 11) after power-up before the specifications apply. Once this requirement has
Nyquist Zones
The I2E circuitry allows the use of any one Nyquist zone without configuration, but requires the use of only one Nyquist zone. Inputs that switch dynamically between Nyquist zones will cause poor performance for the I2E circuitry. For example, I2E will function properly for a particular application that has fS = 500MSPS and uses the 1st Nyquist zone (0MHz to 250MHz). I2E will also function properly for an application that uses fS = 500MSPS and the 2nd Nyquist zone (250MHz to 500MHz). I2E will not function properly for an application that uses fS = 500MSPS, and input frequency bands from 150MHz to 210MHz and 250MHz to 290MHz simultaneously. There is no need to configure the I2E algorithm to use a particular Nyquist zone, but no dynamic switching between Nyquist zones is permitted while I2E is running.
Configurability and Communication
I2E can respond to status queries, be turned on and turned off, and generally configured via SPI programmable registers. Configuring of I2E is generally unnecessary unless the application cannot meet the requirements of Track Mode on or after power up. Parameters that can be adjusted and read back include FS/4 filter threshold and status, Power Meter threshold and status, and initial values for the offset, gain, and sample time values to use when I2E starts.
22
FN7571.1 March 15, 2011
ISLA214P50 Clock Divider Synchronous Reset
An output clock (CLKOUTP, CLKOUTN) is provided to facilitate latching of the sampled data. This clock is at half the frequency of the sample clock, and the absolute phase of the output clocks for multiple A/Ds is indeterminate. This feature allows the phase
Sample Clock Input
of multiple A/Ds to be synchronized (refer to Figure 35), which greatly simplifies data capture in systems employing multiple A/Ds. The reset signal must be well-timed with respect to the sample clock (see "Switching Specifications" Table on page 13).
s1 Analog Input s2 tRSTH CLKDIVRSTP (Note 15) tRSTS tRSTRT ADC1 Output Data
(Note 14)
L+td
s0
s1
s2
s3
ADC1 CLKOUTP ADC2 Output Data s0 s1 s2 s3
ADC2 CLKOUTP (phase 1) (Note 16) ADC2 CLKOUTP (phase 2) (Note 16)
NOTES: 14. Delay equals fixed pipeline latency (L cycles) plus fixed analog propagation delay td 15. CLKDIVRSTP setup and hold times are with respect to input sample clock rising edge. CLKDIVRSTN is not shown, but must be driven, and is the compliment of CLKDIVRSTP 16. Either Output Clock Phase (phase 1 or phase 2 ) equally likely prior to synchronization. FIGURE 35. SYNCHRONOUS RESET OPERATION
CSB
SCLK
SDIO
R/W
W1
W0
A12
A11
A10
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
FIGURE 36. MSB-FIRST ADDRESSING
23
FN7571.1 March 15, 2011
ISLA214P50
CSB
SCLK
SDIO
A0
A1
A2
A11
A12
W0
W1
R/W
D0
D1
D2
D3
D4
D5
D6
D7
FIGURE 37. LSB-FIRST ADDRESSING
tDSW CSB tS tDHW tHI tLO t CLK tH
SCLK
SDIO R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0
SPI WRITE
FIGURE 38. SPI WRITE
tDSW CSB tS tDHW
tHI tLO
tCLK tDVR
tH
SCLK
WRITING A READ COMMAND SDIO R/W SDO W1 W0 A12 A11 A10 A9 A2 A1 A0
READING DATA ( 3 WIRE MODE ) D7 D6 D3 D2 D1 D0
( 4 WIRE MODE) D7 D3 D2 D1 D0
FIGURE 39. SPI READ
CSB STALLING CSB
SCLK
SDIO
INSTRUCTION/ADDRESS
DATA WORD 1
DATA WORD 2
FIGURE 40. 2-BYTE TRANSFER
24
FN7571.1 March 15, 2011
ISLA214P50
CSB LAST LEGAL CSB STALLING
SCLK
SDIO
INSTRUCTION/ADDRESS
DATA WORD 1
DATA WORD N
FIGURE 41. N-BYTE TRANSFER
Serial Peripheral Interface
A serial peripheral interface (SPI) bus is used to facilitate configuration of the device and to optimize performance. The SPI bus consists of chip select (CSB), serial clock (SCLK) serial data output (SDO), and serial data input/output (SDIO). The maximum SCLK rate is equal to the A/D sample rate (fSAMPLE) divided by 32 for both write operations and read operations. At fSAMPLE = 500MHz, maximum SCLK is 15.63MHz for writing and read operations. There is no minimum SCLK rate. The following sections describe various registers that are used to configure the SPI or adjust performance or functional parameters. Many registers in the available address space (0x00 to 0xFF) are not defined in this document. Additionally, within a defined register there may be certain bits or bit combinations that are reserved. Undefined registers and undefined values within defined registers are reserved and should not be selected. Setting any reserved register or value may produce indeterminate results.
In the default mode, the MSB is R/W, which determines if the data is to be read (active high) or written. The next two bits, W1 and W0, determine the number of data bytes to be read or written (see Table 4). The lower 13 bits contain the first address for the data transfer. This relationship is illustrated in Figure 38, and timing values are given in "Switching Specifications Boldface limits apply over the operating temperature range, -40C to +85C." on page 13. After the instruction/address bytes have been read, the appropriate number of data bytes are written to or read from the A/D (based on the R/W bit status). The data transfer will continue as long as CSB remains low and SCLK is active. Stalling of the CSB pin is allowed at any byte boundary (instruction/address or data) if the number of bytes being transferred is three or less. For transfers of four bytes or more, CSB is allowed to stall in the middle of the instruction/address bytes or before the first data byte. If CSB transitions to a high state after that point the state machine will reset and terminate the data transfer.
TABLE 4. BYTE TRANSFER SELECTION [W1:W0] 00 01 10 11 BYTES TRANSFERRED 1 2 3 4 or more
SPI Physical Interface
The serial clock pin (SCLK) provides synchronization for the data transfer. By default, all data is presented on the serial data input/output (SDIO) pin in three-wire mode. The state of the SDIO pin is set automatically in the communication protocol (described in the following). A dedicated serial data output pin (SDO) can be activated by setting 0x00[7] high to allow operation in four-wire mode. The SPI port operates in a half duplex master/slave configuration, with the ISLA214P50 functioning as a slave. Multiple slave devices can interface to a single master in threewire mode only, since the SDO output of an unaddressed device is asserted in four wire mode. The chip-select bar (CSB) pin determines when a slave device is being addressed. Multiple slave devices can be written to concurrently, but only one slave device can be read from at a given time (again, only in three-wire mode). If multiple slave devices are selected for reading at the same time, the results will be indeterminate. The communication protocol begins with an instruction/address phase. The first rising SCLK edge following a high to low transition on CSB determines the beginning of the two-byte instruction/address command; SCLK must be static low before the CSB transition. Data can be presented in MSB-first order or LSB-first order. The default is MSB-first, but this can be changed by setting 0x00[6] high. Figures 36 and 37 show the appropriate bit ordering for the MSB-first and LSB-first modes, respectively. In MSB-first mode, the address is incremented for multi-byte transfers, while in LSB-first mode it's decremented. 25
Figures 40 and 41 illustrate the timing relationships for 2-byte and N-byte transfers, respectively. The operation for a 3-byte transfer can be inferred from these diagrams.
SPI Configuration
ADDRESS 0X00: CHIP_PORT_CONFIG
Bit ordering and SPI reset are controlled by this register. Bit order can be selected as MSB to LSB (MSB first) or LSB to MSB (LSB first) to accommodate various micro controllers. Bit 7 SDO Active Bit 6 LSB First Setting this bit high configures the SPI to interpret serial data as arriving in LSB to MSB order. Bit 5 Soft Reset Setting this bit high resets all SPI registers to default values. Bit 4 Reserved This bit should always be set high.
FN7571.1 March 15, 2011
ISLA214P50
Bits 3:0 These bits should always mirror bits 4:7 to avoid ambiguity in bit ordering.
ADDRESS 0X02: BURST_END
If a series of sequential registers are to be set, burst mode can improve throughput by eliminating redundant addressing. Setting the burst_end address determines the end of the transfer; during a write operation, the user must be cautious to transmit the correct number of bytes based on the starting and ending addresses. Bits 7:0 Burst End Address This register value determines the ending address of the burst data.
The default value of each register will be the result of the self-calibration after initial power-up. If a register is to be incremented or decremented, the user should first read the register value then write the incremented or decremented value back to the same register.
TABLE 6. COARSE GAIN ADJUSTMENT 0x22[3:0] core 0 0x26[3:0] core 1 Bit3 Bit2 Bit1 Bit0 NOMINAL COARSE GAIN ADJUST (%) +2.8 +1.4 -2.8 -1.4
Device Information
ADDRESS 0X08: CHIP_ID ADDRESS 0X09: CHIP_VERSION
The generic die identifier and a revision number, respectively, can be read from these two registers.
TABLE 7. MEDIUM AND FINE GAIN ADJUSTMENTS PARAMETER Steps -Full Scale (0x00) Mid-Scale (0x80) +Full Scale (0xFF) Nominal Step Size 0x23[7:0] MEDIUM GAIN 256 -2% 0.00% +2% 0.016% 0x24[7:0] FINE GAIN 256 -0.20% 0.00% +0.2% 0.0016%
Device Configuration/Control
A common SPI map, which can accommodate single-channel or multi-channel devices, is used for all Intersil A/D products.
ADDRESS 0X20: OFFSET_COARSE_ADC0 ADDRESS 0X21: OFFSET_FINE_ADC0
The input offset of the A/D core can be adjusted in fine and coarse steps. Both adjustments are made via an 8-bit word as detailed in Table 5. The data format is twos complement. The default value of each register will be the result of the selfcalibration after initial power-up. If a register is to be incremented or decremented, the user should first read the register value then write the incremented or decremented value back to the same register.
TABLE 5. OFFSET ADJUSTMENTS PARAMETER Steps -Full Scale (0x00) Mid-Scale (0x80) +Full Scale (0xFF) Nominal Step Size 0x20[7:0] COARSE OFFSET 255 -133LSB (-47mV) 0.0LSB (0.0mV) +133LSB (+47mV) 1.04LSB (0.37mV) 0x21[7:0] FINE OFFSET 255 -5LSB (-1.75mV) 0.0LSB +5LSB (+1.75mV) 0.04LSB (0.014mV)
ADDRESS 0X25: MODES
Two distinct reduced power modes can be selected. By default, the tri-level NAPSLP pin can select normal operation, nap or sleep modes (refer to"Nap/Sleep" on page 21). This functionality can be overridden and controlled through the SPI. This is an indexed function when controlled from the SPI, but a global function when driven from the pin. This register is not changed by a Soft Reset.
TABLE 8. POWER-DOWN CONTROL VALUE 000 001 010 100 0x25[2:0] POWER DOWN MODE Pin Control Normal Operation Nap Mode Sleep Mode
ADDRESS 0X26: OFFSET_COARSE_ADC1 ADDRESS 0X22: GAIN_COARSE__ADC0 ADDRESS 0X23: GAIN_MEDIUM_ADC0 ADDRESS 0X24: GAIN_FINE_ADC0
Gain of the A/D core can be adjusted in coarse, medium and fine steps. Coarse gain is a 4-bit adjustment while medium and fine are 8-bit. Multiple Coarse Gain Bits can be set for a total adjustment range of 4.2%. (`0011' -4.2% and `1100' +4.2%) It is recommended to use one of the coarse gain settings (-4.2%, -2.8%, -1.4%, 0, 1.4%, 2.8%, 4.2%) and fine-tune the gain using the registers at 23h and 24h.
ADDRESS 0X27: OFFSET_FINE_ADC1
The input offset of A/D core#1 can be adjusted in fine and coarse steps in the same way that offset for core#0 can be adjusted. Both adjustments are made via an 8-bit word as detailed in Table 5. The data format is twos complement. The default value of each register will be the result of the self-calibration after initial power-up. If a register is to be incremented or decremented, the user should first read the register value then write the incremented or decremented value back to the same register.
26
FN7571.1 March 15, 2011
ISLA214P50
ADDRESS 0X28: GAIN_COARSE__ADC1 ADDRESS 0X29: GAIN_MEDIUM_ADC1 ADDRESS 0X2A: GAIN_FINE_ADC1
Gain of A/D core #1 can be adjusted in coarse, medium and fine steps in the same way that core #0 can be adjusted. Coarse gain is a 4-bit adjustment while medium and fine are 8-bit. Multiple Coarse Gain Bits can be set for a total adjustment range of 4.2. turned on. This bit would typically be used if optimal analog adjustment values for offset, gain, and sample time skew have been preloaded in order to have the I2E algorithm converge more quickly. The system gain of the pair of interleaved core A/Ds can be set by programming the medium and fine gain of the reference A/D before turning I2E on. In this case, I2E will adjust the non-reference A/D's gain to match the reference A/D's gain. Bit 7: Reserved, always set to 0
ADDRESS 0X30: I2E STATUS
The I2E general status register. Bits 0 and 1 indicate if the I2E circuitry is in Active Run or Hold state. The state of the I2E circuitry is dependent on the analog input signal itself. If the input signal obscures the interleave mismatched artifacts such that I2E cannot estimate the mismatch, the algorithm will dynamically enter the Hold state. For example, a DC mid-scale input to the A/D does not contain sufficient information to estimate the gain and sample time skew mismatches, and thus the I2E algorithm will enter the Hold state. In the Hold state, the analog adjustments for interleave correction will be frozen and mismatch estimate calculations will cease until such time as the analog input achieves sufficient quality to allow the I2E algorithm to make mismatch estimates again. Bit 0: 0 = I2E has not detected a low power condition. 1 = I2E has detected a low power condition, and the analog adjustments for interleave correction are frozen. Bit 1: 0 = I2E has not detected a low AC power condition. 1 = I2E has detected a low AC power condition, and I2E will continue to correct with best known information but will not update its interleave correction adjustments until the input signal achieves sufficient AC RMS power. Bit 2: When first started, the I2E algorithm can take a significant amount of time to settle (~1s), dependent on the characteristics of the analog input signal. 0 = I2E is still settling, 1 = I2E has completed settling.
ADDRESS 0X4A: I2E POWER DOWN
This register provides the capability to completely power down the I2E algorithm and the Notch filter. This would typically be done to conserve power. BIT 0: Power down the I2E Algorithm BIT 1: Power down the Notch Filter
ADDRESS 0X50-0X55: I2E FREEZE THRESHOLDS
This group of registers provides programming access to configure I2E's dynamic freeze control. As with any interleave mismatch correction algorithm making estimates of the interleave mismatch errors using the digitized application input signal, there are certain characteristics of the input signal that can obscure the mismatch estimates. For example, a DC input to the A/D contains no information about the sample time skew mismatch between the core A/Ds, and thus should not be used by the I2E algorithm to update its sample time skew estimate. Under such circumstances, I2E enters Hold state. In the Hold state, the analog adjustments will be frozen and mismatch estimate calculations will cease until such time as the analog input achieves sufficient quality to allow the I2E algorithm to make mismatch estimates again. These registers allow the programming of the thresholds of the meters used to determine the quality of the input signal. This can be used by the application to optimize I2E's behavior based on knowledge of the input signal. For example, if a specific application had an input signal that was typically 30dB down from full scale, and was primarily concerned about analog performance of the A/D at this input power, lowering the RMS power threshold would allow I2E to continue tracking with this input power level, thus allowing it to track over voltage and temperature changes. 0x50 (LSBs), 0x51 (MSBs) RMS Power Threshold This 16-bit quantity is the RMS power threshold at which I2E will enter Hold state. The RMS power of the analog input is calculated continuously by I2E on incoming data. Only the upper 12 bits of the ADC sample outputs are used in the averaging process for comparison to the power threshold registers. A 12-bit number squared produces a 24-bit result (for A/D resolutions under 12-bits, the A/D samples are MSB-aligned to 12-bit data). A dynamic number of these 24-bit results are averaged to compare with this threshold approximately every 1s to decide whether or not to freeze I2E. The 24-bit threshold is constructed with bits 23 through 20 (MSBs) assigned to 0, bits 19 through 4 assigned to this 16-bit quantity, and bits 3 through 0 (LSBs) assigned to 0. As an example, if the application wanted to set this threshold to trigger near the RMS analog input of a -20dBFS sinusoidal input, the calculation to determine this register's value would be:
ADDRESS 0X31: I2E CONTROL
The I2E general control register. This register can be written while I2E is running to control various parameters. Bit 0: 0 = turn I2E off, 1= turn I2E on Bit 1: 0 = no action, 1 = freeze I2E, leaving all settings in the current state. Subsequently writing a 0 to this bit will allow I2E to continue from the state it was left in. Bit 2-4: Disable any of the interleave adjustments of offset, gain, or sample time skew Bit 5: 0 = bypass notch filter, 1 = use notch filter on incoming data before estimating interleave mismatch terms
ADDRESS 0X32: I2E STATIC CONTROL
The I2E general static control register. This register must be written prior to turning I2E on for the settings to take effect. Bit 1-4: Reserved, always set to 0 Bit 5: 0 = normal operation, 1 = skip coarse adjustment of the offset, gain, and sample time skew analog controls when I2E is first 27
FN7571.1 March 15, 2011
ISLA214P50
2 RMS codes = ------ x 10 2
2 - 20 -------- 20
0x55 AC RMS Power Hysteresis
x2
12
( 290 )codes (EQ. 2)
hex ( ( ( 290 ) ) ) = 0x14884 TruncateMSBandLSBhexdigit = 0x1488 (EQ. 3)
Therefore, programming 0x1488 into these two registers will cause I2E to freeze when the signal being digitized has less RMS power than a -20dBFS sinusoid. The default value of this register is 0x1000, causing I2E to freeze when the input amplitude is less than -21.2 dBFS. The freezing of I2E by the RMS power meter threshold affects the gain and sample time skew interleave mismatch estimates, but not the offset mismatch estimate. 0x52 RMS Power Hysteresis In order to prevent I2E from constantly oscillating between the Hold and Track state, there is hysteresis in the comparison described above. After I2E enters a frozen state, the RMS input power must achieve threshold value + hysteresis to again enter the Track state. The hysteresis quantity is a 24-bit value, constructed with bits 23 through 12 (MSBs) being assigned to 0, bits 11 through 4 assigned to this register's value, and bits 3 through 0 (LSBs) assigned to 0.
In order to prevent I2E from constantly oscillating between the Hold and Track state, there is hysteresis in the comparison described above. After I2E enters a frozen state, the AC RMS input power must achieve threshold value + hysteresis to again enter the Track state. The hysteresis quantity is a 24-bit value, constructed with bits 23 through 12 (MSBs) being assigned to 0, bits 11 through 4 assigned to this register's value, and bits 3 through 0 (LSBs) assigned to 0.
Address 0x60-0x64: I2E initialization
These registers provide access to the initialization values for each of offset, gain, and sample time skew that I2E programs into the target core A/D before adjusting to minimize interleave mismatch. They can be used by the system to, for example, reduce the convergence time of the I2E algorithm by programming in the optimal values before turning I2E on. In this case, I2E only needs to adjust for temperature and voltage-induced changes since the optimal values were recorded.
Global Device Configuration/Control
ADDRESS 0X70: SKEW_DIFF
The value in the skew_diff register adjusts the timing skew between the two A/D cores. The nominal range and resolution of this adjustment are given in Table 9. The default value of this register after power-up is 80h.
TABLE 9. DIFFERENTIAL SKEW ADJUSTMENT PARAMETER Steps -Full Scale (0x00) Mid-Scale (0x80) +Full Scale (0xFF) Nominal Step Size 0x70[7:0] DIFFERENTIAL SKEW 256 -6.5ps 0.0ps +6.5ps 51fs
0X53(LSBS), 0X54(MSBS) AC RMS POWER THRESHOLD
Similar to RMS power threshold, there must be sufficient AC RMS power (or dV/dt) of the input signal to measure sample time skew mismatch for an arbitrary input. This is clear from observing the effect when a high voltage (and therefore large RMS value) DC input is applied to the A/D input. Without sufficient dV/dt in the input signal, no information about the sample time skew between the core A/Ds can be determined from the digitized samples. The AC RMS Power Meter is implemented as a high-passed (via DSP) RMS power meter. The required algorithm is documented as follows. 1. Write the MSBs of the 16-bit quantity to SPI Address 0x54 2. Write the LSBs of the 16-bit quantity to SPI Address 0x53 Only the upper 12 bits of the ADC sample outputs are used in the averaging process for comparison to the power threshold registers. A 12-bit number squared produces a 24-bit result (for A/D resolutions under 12-bits, the A/D samples are MSB-aligned to 12-bit data). A dynamic number of these 24-bit results are averaged to compare with this threshold approximately every 1s to decide whether or not to freeze I2E. The 24-bit threshold is constructed with bits 23 through 20 (MSBs) assigned to 0, bits 19 through 4 assigned to this 16-bit quantity, and bits 3 through 0 (LSBs) assigned to 0. The calculation methodology to set this register is identical to the description in the RMS power threshold description. The freezing of I2E when the AC RMS power meter threshold is not met affects the sample time skew interleave mismatch estimate, but not the offset or gain mismatch estimates.
ADDRESS 0X71: PHASE_SLIP
The output data clock is generated by dividing down the A/D input sample clock. Some systems with multiple A/Ds can more easily latch the data from each A/D by controlling the phase of the output data clock. This control is accomplished through the use of the phase_slip SPI feature, which allows the rising edge of the output data clock to be advanced by one input clock period, as shown in the Figure 42. Execution of a phase_slip command is accomplished by first writing a '0' to bit 0 at address 0x71, followed by writing a '1' to bit 0 at address 0x71.
28
FN7571.1 March 15, 2011
ISLA214P50
ADC Input Clock (500MHz)
2ns 4ns
ADDRESS 0X74: OUTPUT_MODE_B
Bit 6 DLL Range This bit sets the DLL operating range to fast (default) or slow. Internal clock signals are generated by a delay-locked loop (DLL), which has a finite operating range. Table 13 shows the allowable sample rate ranges for the slow and fast settings. Note that Bit 4 at 0x74 is reserved and must not change value. A user writing to Bit 6 should first read 0x74 to determine proper value to write back to Bit 4 when writing to 0x74.
TABLE 13. DLL RANGES DLL RANGE FIGURE 42. PHASE SLIP Slow Fast MIN 80 160 MAX 200 500 UNIT MSPS MSPS
Output Data Clock (250MHz) No clock_slip Output Data Clock (250MHz) 1 clock_slip Output Data Clock (250MHz) 2 clock_slip
2n s
ADDRESS 0X72: CLOCK_DIVIDE
The ISLA214P50 has a selectable clock divider that can be set to divide by two or one (no division). By default, the tri-level CLKDIV pin selects the divisor This functionality can be overridden and controlled through the SPI, as shown in Table 10. This register is not changed by a Soft Reset.
TABLE 10. CLOCK DIVIDER SELECTION VALUE 000 001 010 other 0x72[2:0] CLOCK DIVIDER Pin Control Divide by 1 Divide by 2 Not Allowed
ADDRESS 0XB6: CALIBRATION STATUS
The LSB at address 0xB6 can be read to determine calibration status. The bit is `0' during calibration and goes to a logic `1' when calibration is complete.This register is unique in that it can be read after POR at calibration, unlike the other registers on chip, which can't be read until calibration is complete.
DEVICE TEST
The ISLA214P50 can produce preset or user defined patterns on the digital outputs to facilitate in-situ testing. A user can pick from preset built-in patterns by writing to the output test mode field [7:4] at C0h or user defined patterns by writing to the user test mode field [2:0] at C0h. The user defined patterns should be loaded at address space C1 through D0, see the "SPI Memory Map" on page 31 for more detail. The predefined patterns are shown in Table 14. The test mode is enabled asynchronously to the sample clock, therefore several sample clock cycles may elapse before the data is present on the output bus.
ADDRESS 0X73: OUTPUT_MODE_A
The output_mode_A register controls the physical output format of the data, as well as the logical coding. The ISLA214P50 can present output data in two physical formats: LVDS (default) or LVCMOS. Additionally, the drive strength in LVDS mode can be set high (default, 3mA or low (2mA). Data can be coded in three possible formats: two's complement (default), Gray code or offset binary. See Table 12. This register is not changed by a Soft Reset.
TABLE 11. OUTPUT MODE CONTROL VALUE 000 001 100 0x73[7:5] OUTPUT MODE LVDS 3mA (Default) LVDS 2mA LVCMOS
ADDRESS 0XC0: TEST_IO
Bits 7:4 Output Test Mode These bits set the test mode according to table below. Other values are reserved.User test patterns loaded at 0xC1 through 0xD0 are also available by writing `1000' to [7:4] at 0xC0 and a pattern depth value to [2:0] at 0xC0. See the memory map. Bits 2:0 User Test Mode The three LSBs in this register determine the test pattern in combination with registers 0xC1 through 0xD0. Refer to the SPI Memory Map on page 31.
TABLE 12. OUTPUT FORMAT CONTROL VALUE 000 010 100 0x73[2:0] OUTPUT FORMAT Two's Complement (Default) Gray Code Offset Binary
29
FN7571.1 March 15, 2011
ISLA214P50
TABLE 14. OUTPUT TEST MODES VALUE 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 0xC0[7:4] OUTPUT TEST MODE Off Midscale Positive Full-Scale Negative Full-Scale Reserved Reserved Reserved Reserved User Pattern Reserved Ramp user_patt1 N/A N/A user_patt2 N/A N/A 0x8000 0xFFFF 0x0000 N/A N/A N/A N/A N/A N/A N/A N/A N/A WORD 1 WORD 2
ADDRESS 0XCF: USER_PATT8_LSB ADDRESS 0XD0: USER_PATT8_MSB These registers define the lower and upper eight bits, respectively, of the user-defined pattern 8 Digital Temperature Sensor
ADDRESS 0X4B: TEMP_COUNTER_HIGH Bits [2:0] of this register hold the 3 MSB's of the 11-bit temperature code. Bit [7] of this register indicates a valid temperature_counter read was performed. A logic `1' indicates a valid read. ADDRESS 0X4C: TEMP_COUNTER_LOW Bits [7:0] of this register hold the lower 8 LSBs of the 11-bit temperature code. ADDRESS 0X4D: TEMP_COUNTER_CONTROL Bit [7] Measurement mode select bit, set to `1' for recommended PTAT mode. `0' (default) is IPTAT mode and is less accurate and not recommended. Bit [6] Temperature counter enable bit. Set to `1' to enable. Bit [5] Temperature counter power down bit. Set to `1' to power down temperature counter. Bit [4] Temperature counter reset bit. Set to `1' to reset count. Bit [3:1] Three bit frequency divider field. Sets temperature counter update rate. Update rate is proportional to ADC sample clock rate and divide ratio. A `101' updates the temp counter every ~ 66s (for 250Msps). Faster updates rates result in lower precision. Bit [0] Select sampler bit. Set to `0'. This set of registers provides digital access to an PTAT or IPTAT-based temperature sensor, allowing the system to estimate the temperature of the die, allowing easy access to information that can be used to decide when to recalibrate the A/D as needed. The nominal transfer function of the temperature counter is Codes (in decimal) = 0.56*T(C) + 618. This corresponds to approximately a 65 LSB increase from -40C to +85C. The accuracy of the sensor is approximately 20% for both slope and starting code offset. A typical temperature measurement can occur as follows: 1. Write '0xCA' to address 0x4D - enable temp counter, divide ='101' 2. Wait >= 132uS (at 250Msps) - longer wait time ensures the sensor completes one valid cycle. 3. Write `0x20' to address 0x4D - power-down, disable temp counter - recommended between measurements. This ensures that the output does not change between MSB and LSB reads. 4. Read address 0x4B (MSBs) 5. Read address 0x4C (LSBs) 6. Record temp code value 7. Write `0x20' to address 0x4D - power-down, disable temp counter Contact the factory for more information if needed.
ADDRESS 0XC1: USER_PATT1_LSB ADDRESS 0XC2: USER_PATT1_MSB
These registers define the lower and upper eight bits, respectively, of the user-defined pattern 1.
ADDRESS 0XC3: USER_PATT2_LSB ADDRESS 0XC4: USER_PATT2_MSB
These registers define the lower and upper eight bits, respectively, of the user-defined pattern 2
ADDRESS 0XC5: USER_PATT3_LSB ADDRESS 0XC6: USER_PATT3_MSB
These registers define the lower and upper eight bits, respectively, of the user-defined pattern 3
ADDRESS 0XC7: USER_PATT4_LSB ADDRESS 0XC8: USER_PATT4_MSB
These registers define the lower and upper eight bits, respectively, of the user-defined pattern 4.
ADDRESS 0XC9: USER_PATT5_LSB ADDRESS 0XCA: USER_PATT5_MSB
These registers define the lower and upper eight bits, respectively, of the user-defined pattern 5.
ADDRESS 0XCB: USER_PATT6_LSB ADDRESS 0XCC: USER_PATT6_MSB
These registers define the lower and upper eight bits, respectively, of the user-defined pattern 6
ADDRESS 0XCD: USER_PATT7_LSB ADDRESS 0XCE: USER_PATT7_MSB
These registers define the lower and upper eight bits, respectively, of the user-defined pattern 7.
30
FN7571.1 March 15, 2011
ISLA214P50
SPI Memory Map
Addr. (Hex) DUT Info SPI Config/Control 00 01 02 03-07 08 09 0A-0F 10-1F 20 21 22 23 24 25 Device Config/Control Parameter Name port_config Reserved burst_end Reserved chip_id chip_version Reserved Reserved offset_coarse_adc0 offset_fine_adc0 gain_coarse_adc0 gain_medium_adc0 gain_fine_adc0 modes_adc0 Reserved Reserved Medium Gain Fine Gain Power Down Mode ADC0 [2:0] 000 = Pin Control 001 = Normal Operation 010 = Nap 100 = Sleep Other codes = Reserved Coarse Offset Fine Offset Reserved Medium Gain Fine Gain Reserved Power Down Mode ADC1 [2:0] 000 = Pin Control 001 = Normal Operation 010 = Nap 100 = Sleep Other codes = Reserved Reserved Reserved I2E Settled Disable Skew Low AC RMS Power Freeze Low RMS Power Run Read only Coarse Gain Bit 7 (MSB) SDO Active Bit 6 LSB First Bit 5 Soft Reset Reserved Burst end address [7:0] Reserved Chip ID # Chip Version # Reserved Reserved Coarse Offset Fine Offset Coarse Gain cal. value cal. value cal. value cal. value cal. value 00h NOT reset by Soft Reset Read only Read only 00h Bit 4 Bit 3 Bit 2 Mirror (bit5) Bit 1 Mirror (bit6) Bit 0 (LSB) Mirror (bit7) Def. Value (Hex) 00h
26 27 28 29 2A 2B
offset_coarse_adc1 offset_fine_adc1 gain_coarse_adc1 gain_medium_adc1 gain_fine_adc1 modes_adc1
cal. value cal. value cal. value cal. value cal. value 00h NOT reset by Soft Reset
2C-2F 30
Reserved I2E_status
31
I2E_control
Enable Notch Filter Reserved must be set to 0 Skip coarse adj.
Disable Offset
Disable Gain
20h
I2E Control and Status
32
I2E_static_control
Reserved, must be set to 0
Should be set to 1
01h
33-49 4A
Reserved I2E_power_down
Reserved Notch Filter Power Down Temp Counter [7:0] Enable PD Reset Reserved RMS Power Threshold, LSBs [7:0] 00h Divider [2:0] Select I2E Power Down 03h
4B 4C 4D 4E-4F 50
temp_counter_high temp_counter_low temp_counter_control Reserved I2E_rms_power_threshold_lsb
Temp Counter [10:8]
Read only Read only 00h
31
FN7571.1 March 15, 2011
ISLA214P50
SPI Memory Map (Continued)
Addr. (Hex) 51 52 53 I2E Control and Status 54 55 56-5F 60 61 62 63 64 65-6F 70 71 72 Parameter Name I2E_rms_power_threshold_ms b I2E_rms_hysteresis I2E_ac_rms_power_threshold _lsb I2E_ac_rms_power_threshold _msb I2E_ac_rms_hysteresis Reserved coarse_offset_init fine_offset_init medium_gain_init fine_gain_init sample_time_skew_init Reserved skew_diff phase_slip clock_divide Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Def. Value (Hex) 10h FFh 50h 00h 10h 80h 80h 80h 80h 80h 80h Next Clock Edge Clock Divide [2:0] 000 = Pin Control 001 = divide by 1 010 = divide by 2 Other codes = Reserved Output Mode [7:5] 000 =LVDS 3mA (Default) 001 = LVDS 2mA 100 = LVCMOS Other codes = Reserved DLL Range 0 = Fast 1 = Slow (Default = '0') Reserved Output Format [2:0] 000 = Two's Complement (Default) 010 = Gray Code 100 = Offset Binary Other codes = Reserved 00h 00h NOT reset by Soft Reset RMS Power Threshold, MSBs [15:8] RMS Power Hysteresis AC Power Threshold, LSBs, [7:0] AC Power Threshold, MSBs, [15:8] AC RMS Power Hysteresis Reserved Coarse Offset Initialization value Fine Offset Initialization value Medium Gain Initialization value Fine Gain Initialization value Sample Time Skew Initialization value Reserved Differential Skew Reserved
73
output_mode_A
00h NOT reset by Soft Reset
DeviceConfig/Control
74
output_mode_B
00h NOT reset by Soft Reset
75-BF A4 A5 A6 A7 A8 A9 AA AB AC-B5 B6 B7-BF
Reserved dll_ctrl_upper_adc0 dll_ctrl_lower_adc0 dll_status_upper_adc0 dll_status_lower_adc0 dll_ctrl_upper_adc1 dll_ctrl_lower_adc1 dll_status_upper_adc1 dll_status_lower_adc1 Reserved Cal_Status Reserved
Reserved Consult Factory Consult Factory Consult Factory Consult Factory Consult Factory Consult Factory Consult Factory Consult Factory Reserved Reserved Reserved Calibration Done Read only cal. value cal. value Read only Read only cal. value cal. value Read only Read only
32
FN7571.1 March 15, 2011
ISLA214P50
SPI Memory Map (Continued)
Addr. (Hex) C0 Parameter Name test_io Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Def. Value (Hex) 00h Output Test Mode (DDR) [7:4] 0 = Off (Note 14) 1 = Midscale Short 2 = +FS Short 3 = -FS Short 4 = Checker Board output - 0xAAAA, 0x5555 DDR 5 = Reserved 6 = Reserved 7 = 0xFFFF,0x0000 all on pattern, DDR Word Toggle 8 = User Pattern (1 to 8 deep,DDR, MSB justified) 9 = Reserved 10 = Ramp 11-15 = Reserved Device Test C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1-FD FE FF user_patt1_lsb user_patt1_msb user_patt2_lsb user_patt2_msb user_patt3_lsb user_patt3_msb user_patt4_lsb user_patt4_msb user_patt5_lsb user_patt5_msb user_patt6_lsb user_patt6_msb user_patt7_lsb user_patt7_msb user_patt8_lsb user_patt8_msb Reserved VRAM_latch_enable Reserved B7 B15 B7 B15 B7 B15 B7 B15 B7 B15 B7 B15 B7 B15 B7 B15 B6 B14 B6 B14 B6 B14 B6 B14 B6 B14 B6 B14 B6 B14 B6 B14 B5 B13 B5 B13 B5 B13 B5 B13 B5 B13 B5 B13 B5 B13 B5 B13 B4 B12 B4 B12 B4 B12 B4 B12 B4 B12 B4 B12 B4 B12 B4 B12 Reserved Reserved LE Active high 00h B3 B11 B3 B11 B3 B11 B3 B11 B3 B11 B3 B11 B3 B11 B3 B11 User Test Mode(DDR) [2:0] 0 = cycle pattern 1 through 2 1 = cycle pattern 1 through 4 2 = cycle pattern 1 through 6 3 = cycle pattern 1 through 8 4-7 =NA
B2 B10 B2 B10 B2 B10 B2 B10 B2 B10 B2 B10 B2 B10 B2 B10
B1 B9 B1 B9 B1 B9 B1 B9 B1 B9 B1 B9 B1 B9 B1 B9
B0 B8 B0 B8 B0 B8 B0 B8 B0 B8 B0 B8 B0 B8 B0 B8
00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h
NOTE: 14. During Calibration xCCCC (MSB justified) is presented at the output data bus, toggling on the LSB (and higher) data bits occurs at completion of calibration. This behavior can be used as an option to monitoring Over range to determine calibration state.
33
FN7571.1 March 15, 2011
ISLA214P50 Equivalent Circuits
AVDD
AVDD
TO CLOCKPHASE GENERATION AVDD 11kO 18kO
CLKP
AVDD INP E2 CSAMP 9pF CSAMP 9pF TO CHARGE PIPELINE E3
300
AVDD INN
E1
TO CHARGE PIPELINE E3
AVDD 11kO
18kO
E1
E2
CLKN
FIGURE 43. ANALOG INPUTS
AVDD AVDD AVDD
(20k PULL-UP ON RESETN ONLY)
FIGURE 44. CLOCK INPUTS
OVDD
75kO
AVDD
75kO 280O
TO SENSE LOGIC
INPUT
OVDD OVDD 20k TO 280 LOGIC
INPUT
75kO
75kO
FIGURE 45. TRI-LEVEL DIGITAL INPUTS
FIGURE 46. DIGITAL INPUTS
OVDD 2mA OR 3mA OVDD DATA DATA D[13:0]P OVDD
OVDD OVDD
D[13:0]N
DATA
D[13:0]
DATA
DATA
2mA OR 3mA
FIGURE 47. LVDS OUTPUTS
FIGURE 48. CMOS OUTPUTS
34
FN7571.1 March 15, 2011
ISLA214P50 Equivalent Circuits (Continued)
AVDD
VCM 0.94V + -
FIGURE 49. VCM_OUT OUTPUT
A/D Evaluation Platform
Intersil offers an A/D Evaluation platform which can be used to evaluate any of Intersil's high speed A/D products. The platform consists of a FPGA based data capture motherboard and a family of A/D daughtercards. This USB based platform allows a user to quickly evaluate the A/D's performance at a user's specific application frequency requirements. More information is available at http://www.intersil.com/converters/adc_eval_platform/
LVDS Outputs
Output traces and connections must be designed for 50 (100 differential) characteristic impedance. Keep traces direct and minimize bends where possible. Avoid crossing ground and power-plane breaks with signal traces.
LVCMOS Outputs
Output traces and connections must be designed for 50 characteristic impedance.
Layout Considerations
Split Ground and Power Planes
Data converters operating at high sampling frequencies require extra care in PC board layout. Many complex board designs benefit from isolating the analog and digital sections. Analog supply and ground planes should be laid out under signal and clock inputs. Locate the digital planes under outputs and logic pins. Grounds should be joined under the chip.
Unused Inputs
Standard logic inputs (RESETN, CSB, SCLK, SDIO, SDO) which will not be operated do not require connection to ensure optimal A/D performance. These inputs can be left floating if they are not used. Tri-level inputs (NAPSLP) accept a floating input as a valid state, and therefore should be biased according to the desired functionality.
Definitions
Analog Input Bandwidth is the analog input frequency at which the spectral output power at the fundamental frequency (as determined by FFT analysis) is reduced by 3dB from its full-scale low-frequency value. This is also referred to as Full Power Bandwidth. Aperture Delay or Sampling Delay is the time required after the rise of the clock input for the sampling switch to open, at which time the signal is held for conversion. Aperture Jitter is the RMS variation in aperture delay for a set of samples. Clock Duty Cycle is the ratio of the time the clock wave is at logic high to the total time of one clock period. Differential Non-Linearity (DNL) is the deviation of any code width from an ideal 1 LSB step. Effective Number of Bits (ENOB) is an alternate method of specifying Signal to Noise-and-Distortion Ratio (SINAD). In dB, it is calculated as: ENOB = (SINAD - 1.76)/6.02 Gain Error is the ratio of the difference between the voltages that cause the lowest and highest code transitions to the full-scale voltage less 2 LSB. It is typically expressed in percent. I2E The Intersil Interleave Engine. This highly configurable circuitry performs estimates of offset, gain, and sample time
Clock Input Considerations
Use matched transmission lines to the transformer inputs for the analog input and clock signals. Locate transformers and terminations as close to the chip as possible.
Exposed Paddle
The exposed paddle must be electrically connected to analog ground (AVSS) and should be connected to a large copper plane using numerous vias for optimal thermal performance.
Bypass and Filtering
Bulk capacitors should have low equivalent series resistance. Tantalum is a good choice. For best performance, keep ceramic bypass capacitors very close to device pins. Longer traces will increase inductance, resulting in diminished dynamic performance and accuracy. Make sure that connections to ground are direct and low impedance. Avoid forming ground loops.
35
FN7571.1 March 15, 2011
ISLA214P50
skew mismatches between the core converters, and updates analog adjustments for each to minimize interleave spurs. Integral Non-Linearity (INL) is the maximum deviation of the A/D's transfer function from a best fit line determined by a least squares curve fit of that transfer function, measured in units of LSBs. Least Significant Bit (LSB) is the bit that has the smallest value or weight in a digital word. Its value in terms of input voltage is VFS/(2N-1) where N is the resolution in bits. Missing Codes are output codes that are skipped and will never appear at the A/D output. These codes cannot be reached with any input value. Most Significant Bit (MSB) is the bit that has the largest value or weight. Pipeline Delay is the number of clock cycles between the initiation of a conversion and the appearance at the output pins of the data. Power Supply Rejection Ratio (PSRR) is the ratio of the observed magnitude of a spur in the A/D FFT, caused by an AC signal superimposed on the power supply voltage. Signal to Noise-and-Distortion (SINAD) is the ratio of the RMS signal amplitude to the RMS sum of all other spectral components below one half the clock frequency, including harmonics but excluding DC. Signal-to-Noise Ratio (without Harmonics) is the ratio of the RMS signal amplitude to the RMS sum of all other spectral components below one-half the sampling frequency, excluding harmonics and DC. SNR and SINAD are either given in units of dB when the power of the fundamental is used as the reference, or dBFS (dB to full scale) when the converter's full-scale input power is used as the reference. Spurious-Free-Dynamic Range (SFDR) is the ratio of the RMS signal amplitude to the RMS value of the largest spurious spectral component. The largest spurious spectral component may or may not be a harmonic.
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev.
DATE 3/14/11 REVISION FN7571.1 CHANGE Removed coming soon part ISLA214P50IR1Z from ordering information (not being offered). Page 1 Features changed "75fS" to "75fs". Updated ordering Eval board name from "ISLA214P50EVAL" to "ISLA214P50IR72EV1Z" matching Intrepid. Updated Temperature Calibration Curves (see ISLA214P50_CHG History.docx for detailed changes) Added paragraph to "Clock Input" on page 20. Removed 100% Matte Tin Plate w/Anneal-e3 lead finish note from ordering information due to both parts having NiPdAu plate--e4 termination finish. Added Note reference to meet new standard in MIN and MAX to I2E Specifications Table on page 11. FN7571.0 Initial Release
3/1/11 2/28/11 2/8/11
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISLA214P50 To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff FITs are available from our website at: http://rel.intersil.com/reports/sear
For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com
36
FN7571.1 March 15, 2011
ISLA214P50
Package Outline Drawing
L72.10x10E
72 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 0, 11/09
10.00 9.75 72 1 6 PIN 1 INDEX AREA 9.75 3.000 REF. 6.000 REF. 10.00 A B EXPOSED PAD AREA 72 1 6 PIN #1 INDEX AREA Z X Y (3.00 ) (6.00) DETAIL "X" DETAIL "Z"
8.500 REF. (4X)
0.100 M C A B (4X) 0.15 4.150 REF. TOP VIEW 7.150 REF. BOTTOM VIEW 11 ALL AROUND 9.75 0.10 0.100 M C A B
C0.400X45 (4X) 10.00 0.10 (0.350) SIDE VIEW (7.15) (4.15 REF)
25 .1 (0 LL A A O R D N )
R0.200 0.450
C0.190X45
1 72
0.500 0.100 R0.115 TYP.
(4X 9.70) (4X 8.50)
( 72X 0 .23)
R0.200 MAX. ALL AROUND ( 72X 0 .70) 0.100 C 0.650 0.050 0.85 0.050
TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. 2. 3. 4. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to ANSI Y14.5m-1994. Unless otherwise specified, tolerance : Decimal 0.10 Angular 2.50 Dimension applies to the metallized terminal and is measured between 0.015mm and 0.30mm from the terminal tip. 5. 6. Tiebar shown (if present) is a non-functional feature. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 indentifier may be either a mold or mark feature. 7. Package outline compliant to JESD-M0220. 0.190~0.245 0.23 0.050 0.080 C 0.50
SEATING PLANE C
0.025 0.020 0.100 M C A B 0.050 M C DETAIL "Y"
37
FN7571.1 March 15, 2011
(1.500)
U

▲Up To Search▲

Price & Availability of ISLA214P501103

	To Download ISLA214P501103 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .