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| FDD8424H Dual N & P-Channel PowerTrench(R) MOSFET March 2007 FDD8424H Dual N & P-Channel PowerTrench(R) MOSFET N-Channel: 40V, 20A, 24m P-Channel: -40V, -20A, 54m Features Q1: N-Channel Max rDS(on) = 24m at VGS = 10V, ID = 9.0A Max rDS(on) = 30m at VGS = 4.5V, ID = 7.0A Q2: P-Channel Max rDS(on) = 54m at VGS = -10V, ID = -6.5A Max rDS(on) = 70m at VGS = -4.5V, ID = -5.6A Fast switching speed RoHS Compliant Inverter H-Bridge tm General Description These dual N and P-Channel enhancement mode Power MOSFETs are produced using Fairchild Semiconductor's advanced PowerTrench- process that has been especially tailored to minimize on-state resistance and yet maintain superior switching performance. Application D1 D2 D1/D2 www..com G1 G2 S2 G1 S1 S1 Dual DPAK 4L N-Channel G2 S2 P-Channel MOSFET Maximum Ratings TC = 25C unless otherwise noted Symbol VDS VGS Parameter Drain to Source Voltage Gate to Source Voltage Drain Current ID - Continuous (Package Limited) - Continuous (Silicon Limited) - Continuous - Pulsed Power Dissipation for Single Operation PD EAS TJ, TSTG Single Pulse Avalanche Energy Operating and Storage Junction Temperature Range TC = 25C (Note 1) TA = 25C (Note 1a) TA = 25C (Note 1b) (Note 3) 29 TC = 25C TA = 25C Q1 40 20 20 26 9.0 55 30 3.1 1.3 33 mJ C -55 to +150 Q2 -40 20 -20 -20 -6.5 -40 35 W A Units V V Thermal Characteristics RJC RJC Thermal Resistance, Junction to Case, Single Operation for Q1 Thermal Resistance, Junction to Case, Single Operation for Q2 (Note 1) (Note 1) 4.1 3.5 C/W Package Marking and Ordering Information Device Marking FDD8424H Device FDD8424H Package TO-252-4L 1 Reel Size 13" Tape Width 12mm Quantity 2500 units (c)2007 Fairchild Semiconductor Corporation FDD8424H Rev.C www.fairchildsemi.com FDD8424H Dual N & P-Channel PowerTrench(R) MOSFET Electrical Characteristics TJ = 25C unless otherwise noted Symbol Parameter Test Conditions Type Min Typ Max Units Off Characteristics BVDSS BVDSS TJ IDSS IGSS Drain to Source Breakdown Voltage Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current Gate to Source Leakage Current ID = 250A, VGS = 0V ID = -250A, VGS = 0V ID = 250A, referenced to 25C ID = -250A, referenced to 25C VDS = 32V, VGS = 0V VDS = -32V, VGS = 0V VGS = 20V, VDS = 0V Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q2 40 -40 34 -32 1 -1 100 100 V mV/C A nA nA On Characteristics VGS(th) VGS(th) TJ Gate to Source Threshold Voltage Gate to Source Threshold Voltage Temperature Coefficient VGS = VDS, ID = 250A VGS = VDS, ID = -250A ID = 250A, referenced to 25C ID = -250A, referenced to 25C VGS = 10V, ID = 9.0A VGS = 4.5V, ID = 7.0A VGS = 10V, ID = 9.0A, TJ = 125C VGS = -10V, ID = -6.5A VGS = -4.5V, ID = -5.6A VGS = -10V, ID = -6.5A, TJ = 125C VDS = 5V, ID = 9.0A VDS = -5V, ID = -6.5A Q1 Q2 Q1 Q2 Q1 1 -1 1.7 -1.6 -5.3 4.8 19 23 29 42 58 62 29 13 24 30 37 54 70 80 3 -3 V mV/C rDS(on) Static Drain to Source On Resistance m Q2 Q1 Q2 gFS Forward Transconductance S Dynamic Characteristics www..com Ciss Coss Crss Rg Input Capacitance Output Capacitance Reverse Transfer Capacitance Gate Resistance Q1 VDS = 20V, VGS = 0V, f = 1MHZ Q2 VDS = -20V, VGS = 0V, f = 1MHZ Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q2 750 1000 115 140 75 75 1.1 3.3 1000 1330 155 185 115 115 pF pF pF f = 1MHz Switching Characteristics td(on) tr td(off) tf Qg(TOT) Qgs Qgd Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge Gate to Source Charge Gate to Drain "Miller" Charge Q2 VGS = -10V, VDD = -20V, ID = -6.5A Q1 VDD = 20V, ID = 9.0A, VGS = 10V, RGEN = 6 Q2 VDD = -20V, ID = -6.5A, VGS = -10V, RGEN = 6 Q1 VGS = 10V, VDD = 20V, ID = 9.0A Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q2 7 7 13 3 17 20 6 3 14 17 2.3 3.0 3.2 3.6 14 14 24 10 31 36 12 10 20 24 ns ns ns ns nC nC nC (c)2007 Fairchild Semiconductor Corporation FDD8424H Rev.C 2 www.fairchildsemi.com FDD8424H Dual N & P-Channel PowerTrench(R) MOSFET Electrical Characteristics TJ = 25C unless otherwise noted Symbol Parameter Test Conditions Type Min Typ Max Units Drain-Source Diode Characteristics VSD trr Qrr Notes: 1. RJA is determined with the device mounted on a 1in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RJC is guaranteed by design while RCA is determined by the user's board design. Source to Drain Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge VGS = 0V, IS = 9.0A VGS = 0V, IS = -6.5A Q1 IF = 9.0A, di/dt = 100A/s Q2 IF = -6.5A, di/dt = 100A/s (Note 2) (Note 2) Q1 Q2 Q1 Q2 Q1 Q2 0.87 0.88 25 29 19 29 1.2 -1.2 38 44 29 44 V ns nC Q1 a. 40C/W when mounted on a 1 in2 pad of 2 oz copper b. 96C/W when mounted on a minimum pad of 2 oz copper Scale 1 : 1 on letter size paper Q2 a. 40C/W when mounted on a 1 in2 pad of 2 oz copper b. 96C/W when mounted on a minimum pad of 2 oz copper www..com Scale 1 : 1 on letter size paper 2. Pulse Test: Pulse Width < 300s, Duty cycle < 2.0%. 3. Starting TJ = 25C, N-ch: L = 0.3mH, IAS = 14A, VDD = 40V, VGS = 10V; P-ch: L = 0.3mH, IAS = -15A, VDD = -40V, VGS = -10V. (c)2007 Fairchild Semiconductor Corporation FDD8424H Rev.C 3 www.fairchildsemi.com FDD8424H Dual N & P-Channel PowerTrench(R) MOSFET Typical Characteristics (Q1 N-Channel)TJ = 25C unless otherwise noted 60 VGS = 4.0V NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 3.0 VGS = 3.0V 50 ID, DRAIN CURRENT (A) VGS = 10V PULSE DURATION = 80s DUTY CYCLE = 0.5%MAX VGS = 4.5V VGS = 3.5V 2.5 2.0 1.5 1.0 VGS = 3.5V PULSE DURATION = 80s DUTY CYCLE = 0.5%MAX VGS = 4.0V VGS = 4.5V 40 30 20 10 0 0 VGS = 3.0V VGS = 10V 0.5 0 10 20 30 40 50 60 ID, DRAIN CURRENT(A) 1 2 3 4 VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 1. On- Region Characteristics Figure 2. Normalized On-Resistance vs Drain Current and Gate Voltage 50 SOURCE ON-RESISTANCE (m) 1.8 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 1.6 1.4 1.2 1.0 0.8 0.6 -75 ID = 9A VGS = 10V ID = 9A PULSE DURATION = 80s DUTY CYCLE = 0.5%MAX 40 TJ = 125oC rDS(on), DRAIN TO 30 TJ = 25oC www..com 20 -50 -25 0 25 50 75 100 125 150 o 10 2 4 6 8 10 VGS, GATE TO SOURCE VOLTAGE (V) TJ, JUNCTION TEMPERATURE ( C) Figure 3. Normalized On -Resistance vs Junction Temperature 60 IS, REVERSE DRAIN CURRENT (A) Figure 4. On-Resistance vs Gate to Source Voltage 60 50 ID, DRAIN CURRENT (A) PULSE DURATION = 80s DUTY CYCLE = 0.5%MAX VGS = 0V 10 TJ = 150oC 40 30 20 VDS = 5V 1 0.1 TJ = 25oC TJ = 150oC TJ = 25oC TJ = -55oC 10 0 1.5 0.01 TJ = -55oC 2.0 2.5 3.0 3.5 4.0 4.5 0.001 0.0 0.3 0.6 0.9 1.2 1.5 VGS, GATE TO SOURCE VOLTAGE (V) VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 5. Transfer Characteristics Figure 6. Source to Drain Diode Forward Voltage vs Source Current (c)2007 Fairchild Semiconductor Corporation FDD8424H Rev.C 4 www.fairchildsemi.com FDD8424H Dual N & P-Channel PowerTrench(R) MOSFET Typical Characteristics (Q1 N-Channel)TJ = 25C unless otherwise noted 10 VGS, GATE TO SOURCE VOLTAGE(V) ID = 9A 2000 8 6 VDD = 15V VDD = 20V CAPACITANCE (pF) 1000 Ciss 4 VDD = 25V Coss 100 f = 1MHz VGS = 0V 2 0 0 4 8 Qg, GATE CHARGE(nC) Crss 12 16 30 0.1 1 10 40 VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 7. Gate Charge Characteristics Figure 8. Capacitance vs Drain to Source Voltage 30 ID, DRAIN CURRENT (A) 30 IAS, AVALANCHE CURRENT(A) 25 20 Limited by Package 10 TJ = 25oC VGS = 10V 15 10 VGS = 4.5V TJ = 125oC www..com 5 RJC = 4.1 C/W o 1 0.001 0.01 0.1 1 10 100 0 25 50 75 100 o 125 150 tAV, TIME IN AVALANCHE(ms) TC, CASE TEMPERATURE ( C) Figure 9. Unclamped Inductive Switching Capability 100 P(PK), PEAK TRANSIENT POWER (W) Figure 10. Maximum Continuous Drain Current vs Case Temperature 10000 10us VGS = 10V FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I = I25 150 - T C ----------------------125 ID, DRAIN CURRENT (A) 10 THIS AREA IS LIMITED BY rDS(on) 100us 1000 1 SINGLE PULSE TJ = MAX RATED RJC = 4.1 C/W TC = 25oC o 1ms 10ms DC 100 SINGLE PULSE RJC = 4.1 C/W o TC = 25oC 0.1 1 10 VDS, DRAIN to SOURCE VOLTAGE (V) 80 10 -5 10 10 -4 10 -3 10 -2 10 -1 10 0 10 1 t, PULSE WIDTH (s) Figure 11. Forward Bias Safe Operating Area Figure 12. Single Pulse Maximum Power Dissipation (c)2007 Fairchild Semiconductor Corporation FDD8424H Rev.C 5 www.fairchildsemi.com FDD8424H Dual N & P-Channel PowerTrench(R) MOSFET Typical Characteristics (Q1 N-Channel)TJ = 25C unless otherwise noted 2 1 NORMALIZED THERMAL IMPEDANCE, ZJC DUTY CYCLE-DESCENDING ORDER 0.1 D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC 0.01 0.005 -5 10 SINGLE PULSE RJC = 4.1oC/W 10 -4 10 -3 10 -2 10 -1 10 0 10 1 t, RECTANGULAR PULSE DURATION (s) Figure 13. Transient Thermal Response Curve www..com (c)2007 Fairchild Semiconductor Corporation FDD8424H Rev.C 6 www.fairchildsemi.com FDD8424H Dual N & P-Channel PowerTrench(R) MOSFET www..com (c)2007 Fairchild Semiconductor Corporation FDD8424H Rev.C 7 www.fairchildsemi.com FDD8424H Dual N & P-Channel PowerTrench(R) MOSFET Typical Characteristics (Q2 P-Channel)TJ = 25C unless otherwise noted 40 -ID, DRAIN CURRENT (A) VGS = -10V NORMALIZED DRAIN TO SOURCE ON-RESISTANCE PULSE DURATION = 80s DUTY CYCLE = 0.5%MAX VGS = -4.5V VGS = -4V 3.0 VGS = -3V 30 2.5 VGS = -3.5V PULSE DURATION = 80s DUTY CYCLE = 0.5%MAX VGS = -4V 2.0 1.5 1.0 0.5 0 10 20 VGS = -4.5V VGS = -10V VGS = -3.5V 10 VGS = -3V 0 0 1 2 3 4 -VDS, DRAIN TO SOURCE VOLTAGE (V) 20 -ID, DRAIN CURRENT(A) 30 40 Figure 14. On- Region Characteristics 1.6 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE Figure 15. Normalized on-Resistance vs Drain Current and Gate Voltage 160 SOURCE ON-RESISTANCE (m) PULSE DURATION = 80s DUTY CYCLE = 0.5%MAX ID = -6.5A VGS = -10V 1.4 1.2 1.0 0.8 0.6 -75 rDS(on), DRAIN TO 120 ID = -6.5A TJ = 125oC 80 40 TJ = 25oC www..com -50 -25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (oC) 0 2 4 6 8 10 -VGS, GATE TO SOURCE VOLTAGE (V) Figure 16. Normalized On-Resistance vs Junction Temperature Figure 17. On-Resistance vs Gate to Source Voltage 40 -IS, REVERSE DRAIN CURRENT (A) PULSE DURATION = 80s DUTY CYCLE = 0.5%MAX -ID, DRAIN CURRENT (A) 40 10 VGS = 0V 30 VDS = -5V 1 TJ = 25oC TJ = 150oC TJ = -55oC 20 TJ = 25oC 0.1 10 TJ = 150oC TJ = -55oC 0.01 0 1 2 3 4 -VGS, GATE TO SOURCE VOLTAGE (V) 5 0.001 0.0 0.3 0.6 0.9 1.2 1.5 -VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 18. Transfer Characteristics Figure 19. Source to Drain Diode Forward Voltage vs Source Current (c)2007 Fairchild Semiconductor Corporation FDD8424H Rev.C 8 www.fairchildsemi.com FDD8424H Dual N & P-Channel PowerTrench(R) MOSFET Typical Characteristics (Q2 P-Channel)TJ = 25C unless otherwise noted 10 -VGS, GATE TO SOURCE VOLTAGE(V) 2000 Ciss ID = -6.5A VDD = -15V CAPACITANCE (pF) 8 6 4 2 0 0 1000 VDD = -20V VDD = -25V Coss 100 f = 1MHz VGS = 0V Crss 4 8 12 16 20 30 0.1 1 10 40 Qg, GATE CHARGE(nC) -VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 20. Gate Charge Characteristics Figure 21. Capacitance vs Drain to Source Voltage 25 -ID, DRAIN CURRENT (A) 30 -IAS, AVALANCHE CURRENT(A) 20 VGS = -10V 10 TJ = 125oC TJ = 25oC 15 10 VGS = -4.5V www..com 5 RJC = 3.5 C/W o 1 0.001 0.01 0.1 1 10 100 0 25 50 75 100 o 125 150 tAV, TIME IN AVALANCHE(ms) TC, CASE TEMPERATURE ( C) Figure 22. Unclamped Inductive Switching Capability 100 10us -ID, DRAIN CURRENT (A) Figure 23. Maximum Continuous Drain Current vs Case Temperature 10000 P(PK), PEAK TRANSIENT POWER (W) VGS = -10V FOR TEMPERATURES ABOVE 25oC DERATE PEAK 10 THIS AREA IS LIMITED BY rds(on) 100us 1000 CURRENT AS FOLLOWS: I = I25 150 - T C ----------------------125 1 1ms SINGLE PULSE TJ = MAX RATED RJC = 3.5oC/W TC = 25oC 100 SINGLE PULSE TC = 25oC 10ms DC 80 0.1 1 10 -VDS, DRAIN to SOURCE VOLTAGE (V) 10 -5 10 RJC = 3.5 C/W o 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 2 10 3 t, PULSE WIDTH (s) Figure 24. Forward Bias Safe Operating Area Figure 25. Single Pulse Maximum Power Dissipation (c)2007 Fairchild Semiconductor Corporation FDD8424H Rev.C 9 www.fairchildsemi.com FDD8424H Dual N & P-Channel PowerTrench(R) MOSFET Typical Characteristics (Q2 P-Channel)TJ = 25C unless otherwise noted 2 1 NORMALIZED THERMAL IMPEDANCE, ZJC DUTY CYCLE-DESCENDING ORDER 0.1 D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC 0.01 0.005 -5 10 SINGLE PULSE RJC = 3.5 C/W o 10 -4 10 -3 10 -2 10 -1 10 0 10 1 t, RECTANGULAR PULSE DURATION (s) Figure 26. Transient Thermal Response Curve www..com (c)2007 Fairchild Semiconductor Corporation FDD8424H Rev.C 10 www.fairchildsemi.com FDD8424H Dual N & P-Channel PowerTrench(R) MOSFET www..com (c)2007 Fairchild Semiconductor Corporation FDD8424H Rev.C 11 www.fairchildsemi.com FDD8424H Dual N & P-Channel PowerTrench(R) MOSFET tm TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx(R) Across the board. Around the world.TM ActiveArrayTM BottomlessTM Build it NowTM CoolFETTM CROSSVOLTTM CTLTM Current Transfer LogicTM DOMETM E2CMOSTM EcoSPARK(R) EnSignaTM FACT Quiet SeriesTM FACT(R) FAST(R) FASTrTM FPSTM FRFET(R) GlobalOptoisolatorTM GTOTM HiSeCTM i-LoTM ImpliedDisconnectTM IntelliMAXTM ISOPLANARTM MICROCOUPLERTM MicroPakTM MICROWIRETM MSXTM MSXProTM OCXTM OCXProTM OPTOLOGIC(R) OPTOPLANAR(R) PACMANTM POPTM Power220(R) Power247(R) PowerEdgeTM PowerSaverTM PowerTrench(R) Programmable Active DroopTM QFET(R) QSTM QT OptoelectronicsTM Quiet SeriesTM RapidConfigureTM RapidConnectTM ScalarPumpTM SMART STARTTM SPM(R) STEALTHTM SuperFETTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TCMTM The Power Franchise(R) TM TinyBoostTM TinyBuckTM tm TinyLogic(R) TINYOPTOTM TinyPowerTM TinyWireTM TruTranslationTM SerDesTM UHC(R) UniFETTM VCXTM WireTM www..com DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD'S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. PRODUCT STATUS DEFINITIONS Definition of Terms 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor.The datasheet is printed for reference information only. Preliminary First Production No Identification Needed Full Production Obsolete Not In Production Rev. I24 (c)2007 Fairchild Semiconductor Corporation FDD8424H Rev.C www.fairchildsemi.com |
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