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S3C9454B/F9454B
8-BIT CMOS MICROCONTROLLER USER'S MANUAL Revision 1
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Important Notice
The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. Samsung assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein. Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes. This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others. Samsung makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation any consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by the customer's technical experts. Samsung products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, for other applications intended to support or sustain life, or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur. Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application, the Buyer shall indemnify and hold Samsung and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, expenses, and reasonable attorney fees arising out of, either directly or indirectly, any claim of personal injury or death that may be associated with such unintended or unauthorized use, even if such claim alleges that Samsung was negligent regarding the design or manufacture of said product.
S3C9454B/F9454B 8-Bit CMOS Microcontroller User's Manual, Revision 1 Publication Number: 21-S3-C9454B/F9454B-200409 (c) 2004 Samsung Electronics All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of Samsung Electronics. Samsung Electronics' microcontroller business has been awarded full ISO-14001 certification (BVQ1 Certificate No. FM9300). All semiconductor products are designed and manufactured in accordance with the highest quality standards and objectives. Samsung Electronics Co., Ltd. San #24 Nongseo-Ri, Giheung-Eup Yongin-City, Gyeonggi-Do, Korea C.P.O. Box #37, Suwon 440-900 TEL: (0331) 209-1907 FAX: (0331) 209-1899 Home-Page URL: Http://www.samsungsemi.com/ Printed in the Republic of Korea
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Preface
The S3C9454B/F9454B Microcontroller User's Manual is designed for application designers and programmers who are using the S3C9454B/F9454B microcontroller for application development. It is organized in two parts: Part I Programming Model Part II Hardware Descriptions
Part I contains software-related information to familiarize you with the microcontroller's architecture, programming model, instruction set, and interrupt structure. It has six sections: Chapter 1 Chapter 2 Chapter 3 Product Overview Address Spaces Addressing Modes Chapter 4 Chapter 5 Chapter 6 Control Registers Interrupt Structure SAM88RCRI Instruction Set
Chapter 1, "Product Overview," is a high-level introduction to the S3C9454B/F9454B with a general product description, and detailed information about individual pin characteristics and pin circuit types. Chapter 2, "Address Spaces," explains the S3C9454B/F9454B program and data memory, internal register file, and mapped control registers, and explains how to address them. Chapter 2 also describes working register addressing, as well as system and user-defined stack operations. Chapter 3, "Addressing Modes," contains detailed descriptions of the six addressing modes that are supported by the CPU. Chapter 4, "Control Registers," contains overview tables for all mapped system and peripheral control register values, as well as detailed one-page descriptions in standard format. You can use these easy-to-read, alphabetically organized, register descriptions as a quick-reference source when writing programs. Chapter 5, "Interrupt Structure," describes the S3C9454B/F9454B interrupt structure in detail and further prepares you for additional information presented in the individual hardware module descriptions in Part II. Chapter 6, "SAM88RCRI Instruction Set," describes the features and conventions of the instruction set used for all S3C9-series microcontrollers. Several summary tables are presented for orientation and reference. Detailed descriptions of each instruction are presented in a standard format. Each instruction description includes one or more practical examples of how to use the instruction when writing an application program. A basic familiarity with the information in Part I will help you to understand the hardware module descriptions in Part II. If you are not yet familiar with the SAM88RCRI product family and are reading this manual for the first time, we recommend that you first read chapter 1-3 carefully. Then, briefly look over the detailed information in chapters 4, 5, and 6. Later, you can reference the information in Part I as necessary. Part II contains detailed information about the peripheral components of the S3C9454B/F9454B microcontrollers. Also included in Part II are electrical, mechanical, MTP, and development tools data. It has 10 chapters: Chapter 7 Chapter 8 Chapter 9 Chapter 10 Chapter 11 Clock Circuit RESET and Power-Down I/O Ports Basic Timer and Timer 0 8-bit PWM Chapter 12 Chapter 13 Chapter 14 Chapter 15 Chapter 16 A/D Converter Electrical Data Mechanical Data S3F945B MTP Development Tools
Two order forms are included at the back of this manual to facilitate customer order S3C9454B/F9454B microcontrollers: the Mask ROM Order Form, and the Mask Option Selection Form. You can photocopy these forms, fill them out, and then forward them to your local Samsung Sales Representative.
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Table of Contents
Part I -- Programming Model
Chapter 1 Product Overview
SAM88RCRI Product Family......................................................................................................................... 1-1 S3C9454B/F9454B Microcontroller............................................................................................................... 1-1 MTP............................................................................................................................................................... 1-1 Features ........................................................................................................................................................ 1-2 Block Diagram............................................................................................................................................... 1-3 Pin Assignments ........................................................................................................................................... 1-4 Pin Descriptions ............................................................................................................................................ 1-6 Pin Circuits .................................................................................................................................................... 1-7
Chapter 2
Address Spaces
Overview ....................................................................................................................................................... 2-1 Program Memory (ROM) .............................................................................................................................. 2-2 Register Architecture..................................................................................................................................... 2-5 Common Working Register Area (C0H-CFH).............................................................................................. 2-7 System Stack ................................................................................................................................................ 2-8
Chapter 3
Addressing Modes
Overview ....................................................................................................................................................... 3-1 Register Addressing Mode (R) ............................................................................................................. 3-2 Indirect Register Addressing Mode (IR) ............................................................................................... 3-3 Indexed Addressing Mode (X).............................................................................................................. 3-7 Direct Address Mode (DA) ................................................................................................................... 3-10 Relative Address Mode (RA) ................................................................................................................ 3-12 Immediate Mode (IM) ........................................................................................................................... 3-12
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Table of Contents (Continued)
Chapter 4 Control Registers
Overview........................................................................................................................................................4-1
Chapter 5
Interrupt Structure
Overview........................................................................................................................................................5-1 Interrupt Processing Control Points ......................................................................................................5-1 Enable/Disable Interrupt Instructions (EI, DI) .......................................................................................5-2 Interrupt Pending Function Types.........................................................................................................5-2 Interrupt Priority ....................................................................................................................................5-2 Interrupt Source Service Sequence......................................................................................................5-3 Interrupt Service Routines ....................................................................................................................5-3 Generating Interrupt Vector Addresses ................................................................................................5-3 S3C9454B/F9454B Interrupt Structure.................................................................................................5-4
Chapter 6
SAM88RCRI Instruction Set
Overview........................................................................................................................................................6-1 Register Addressing .............................................................................................................................6-1 Addressing Modes ................................................................................................................................6-1 Flags Register (FLAGS) .......................................................................................................................6-4 Flag Descriptions ..................................................................................................................................6-4 Instruction Set Notation ........................................................................................................................6-5 Condition Codes ...................................................................................................................................6-9 Instruction Descriptions ........................................................................................................................6-10
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Table of Contents (Continued)
Part II -- Hardware Descriptions
Chapter 7 Clock Circuit
Overview ....................................................................................................................................................... 7-1 Main Oscillator Logic ............................................................................................................................ 7-1 Clock Status During Power-Down Modes ............................................................................................ 7-2 System Clock Control Register (CLKCON) .......................................................................................... 7-2
Chapter 8
RESET and Power-Down
System Reset................................................................................................................................................ 8-1 Overview............................................................................................................................................... 8-1 Power-Down Modes...................................................................................................................................... 8-3 Stop Mode ............................................................................................................................................ 8-3 Idle Mode.............................................................................................................................................. 8-3 Hardware Reset Values ................................................................................................................................ 8-4
Chapter 9
I/O Ports
Overview ....................................................................................................................................................... 9-1 Port Data Registers .............................................................................................................................. 9-2 Port 0 .................................................................................................................................................... 9-3 Port 1 .................................................................................................................................................... 9-7 Port 2 .................................................................................................................................................... 9-9
Chapter 10
Basic Timer and Timers
Module Overview .......................................................................................................................................... 10-1 Basic Timer (BT) ........................................................................................................................................... 10-2 Basic Timer Control Register (BTCON) ............................................................................................... 10-2 Basic Timer Function Description ........................................................................................................ 10-3 Timer 0 .......................................................................................................................................................... 10-7 Timer 0 Control Registers (T0CON)..................................................................................................... 10-7 Timer 0 Function Description ............................................................................................................... 10-8
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Table of Contents (Continued)
Chapter 11 8-Bit PWM
Overview........................................................................................................................................................11-1 Function Description......................................................................................................................................11-1 PWM.....................................................................................................................................................11-1 PWM Control Register (PWMCON) .....................................................................................................11-5
Chapter 12
A/D Converter
Overview........................................................................................................................................................12-1 Using A/D Pins for Standard Digital Input.............................................................................................12-2 A/D Converter Control Register (ADCON)............................................................................................12-2 Internal Reference Voltage Levels........................................................................................................12-3 Conversion Timing................................................................................................................................12-4 Internal A/D Conversion Procedure ......................................................................................................12-5
Chapter 13
Electrical Data
Overview........................................................................................................................................................13-1
Chapter 14
Mechanical Data
Overview........................................................................................................................................................14-1
Chapter 15
S3F9454B MTP
Overview ...................................................................................................................................................................... 15-1 Operating Mode Characteristics ..................................................................................................................... 15-3
Chapter 16
Development Tools
Overview........................................................................................................................................................16-1 SHINE...................................................................................................................................................16-1 SAMA Assembler..................................................................................................................................16-1 SASM86................................................................................................................................................16-1 HEX2ROM ............................................................................................................................................16-1 Target Boards .......................................................................................................................................16-2 Mtps ......................................................................................................................................................16-2 TB9454B Target Board.........................................................................................................................16-3
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List of Figures
Figure Number 1-1 1-2 1-3 1-5 1-6 1-7 1-8 1-9 1-10 1-11 2-1 2-2 2-3 2-4 2-5 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 4-1 5-1 5-2 5-3 6-1 Title Page Number
Block Diagram ......................................................................................................................... 1-3 Pin Assignment Diagram (20-Pin DIP/SOP/SSOP Package) ................................................. 1-4 Pin Assignment Diagram (16-Pin DIP/SOP/SSOP Package) ................................................. 1-5 Pin Circuit Type A.................................................................................................................... 1-7 Pin Circuit Type B.................................................................................................................... 1-7 Pin Circuit Type C.................................................................................................................... 1-7 Pin Circuit Type D.................................................................................................................... 1-7 Pin Circuit Type E.................................................................................................................... 1-8 Pin Circuit Type E-1................................................................................................................. 1-8 Pin Circuit Type E-2................................................................................................................. 1-9 Program Memory Address Space ........................................................................................... 2-2 Smart Option ........................................................................................................................... 2-3 Internal Register File Organization .......................................................................................... 2-6 16-Bit Register Pairs ............................................................................................................... 2-7 Stack Operations..................................................................................................................... 2-8 Register Addressing ...........................................................................................................................3-2 Working Register Addressing ...........................................................................................................3-2 Indirect Register Addressing to Register File..................................................................................3-3 Indirect Register Addressing to Program Memory .........................................................................3-4 Indirect Working Register Addressing to Register File..................................................................3-5 Indirect Working Register Addressing to Program or Data Memory ...........................................3-6 Indexed Addressing to Register File ................................................................................................3-7 Indexed Addressing to Program or Data Memory with Short Offset............................................3-8 Indexed Addressing to Program or Data Memory with Long Offset ............................................3-9 Direct Addressing for Load Instructions...........................................................................................3-10 Direct Addressing for Call and Jump Instructions ..........................................................................3-11 Relative Addressing............................................................................................................................3-12 Immediate Addressing .......................................................................................................................3-12 Register Description Format..............................................................................................................4-4 S3F9-Series Interrupt Type ..................................................................................................... 5-1 Interrupt Function Diagram...................................................................................................... 5-2 S3C9454B/F9454B Interrupt Structure ................................................................................... 5-4 System Flags Register (FLAGS) ............................................................................................. 6-4
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List of Figures (Continued)
Figure Number 7-1 7-2 7-3 7-4 8-1 8-2 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 10-1 10-2 10-3 10-4 10-5 10-6 10-7 11-1 11-2 11-3 11-4 12-1 12-2 12-3 12-4 12-5 Title Page Number
Main Oscillator Circuit (RC Oscillator with Internal Capacitor) ...............................................7-1 Main Oscillator Circuit (Crystal/Ceramic Oscillator)................................................................7-1 System Clock Control Register (CLKCON) .............................................................................7-2 System Clock Circuit Diagram .................................................................................................7-3 Reset Block Diagram ...............................................................................................................8-2 Timing for S3C9454B/F9454B After RESET ...........................................................................8-2 Port Data Register Format.......................................................................................................9-2 Port 0 Circuit Diagram .............................................................................................................9-3 Port 0 Control Register (P0CONH, High Byte) ........................................................................9-4 Port 0 Control Register (P0CONL, Low Byte).........................................................................9-5 Port 0 Interrupt Pending Registers (P0PND) ...........................................................................9-6 Port 1 Circuit Diagram .............................................................................................................9-7 Port 1 Control Register (P1CON) ............................................................................................9-8 Port 2 Circuit Diagram .............................................................................................................9-9 Port 2 Control Register (P2CONH, High Byte) ........................................................................9-10 Port 2 Control Register (P2CONL, Low Byte)..........................................................................9-11 Basic Timer Control Register (BTCON) ..................................................................................10-2 Oscillation Stabilization Time on RESET.................................................................................10-4 Oscillation Stabilization Time on STOP Mode Release...........................................................10-5 Timer 0 Control Registers (T0CON)........................................................................................10-7 Simplified Timer 0 Function Diagram (Interval Timer Mode)...................................................10-8 Timer 0 Timing Diagram ..........................................................................................................10-9 Basic Timer and Timer 0 Block Diagram.................................................................................10-10 8-Bit PWM Basic Waveform ....................................................................................................11-3 8-Bit Extended PWM Waveform .............................................................................................11-4 PWM Control Register (PWMCON) ........................................................................................11-5 PWM Functional Block Diagram..............................................................................................11-6 A/D Converter Control Register (ADCON) ..............................................................................12-2 A/D Converter Circuit Diagram ................................................................................................12-3 A/D Converter Data Register (ADDATAH/L) ...........................................................................12-3 A/D Converter Timing Diagram ...............................................................................................12-4 Recommended A/D Converter Circuit for Highest Absolute Accuracy....................................12-5
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List of Figures (Concluded)
Figure Number 13-1 13-2 13-3 13-4 13-5 14-1 14-2 14-3 14-4 14-5 14-6 15-1 15-2 16-1 16-2 16-3 16-4 16-5 Title Page Number
Input Timing Measurement Points .......................................................................................... 13-4 Operating Voltage Range........................................................................................................ 13-6 Schmitt Trigger Input Characteristics Diagram ....................................................................... 13-6 Stop Mode Release Timing When Initiated by a RESET ........................................................ 13-7 LVR Reset Timing ................................................................................................................... 13-9 20-DIP-300A Package Dimensions......................................................................................... 14-1 20-SOP-375 Package Dimensions ......................................................................................... 14-2 20-SSOP-225 Package Dimensions ....................................................................................... 14-3 16-DIP-300A Package Dimensions......................................................................................... 14-4 16-SOP-BD300-SG Package Dimensions .............................................................................. 14-5 16-SSOP-BD44 Package Dimensions .................................................................................... 14-6 Pin Assignment Diagram (20-Pin Package)............................................................................ 15-1 Pin Assignment Diagram (16-Pin Package)............................................................................ 15-2 SMDS2+ or SK-1000 Product Configuration ........................................................................... 16-2 TB9454B Target Board Configuration ..................................................................................... 16-3 DIP Switch for Smart Option ................................................................................................... 16-5 20-Pin Connector for TB9454B ............................................................................................... 16-6 S3C9454B/F9454B Probe Adapter for 20-DIP Package......................................................... 16-6
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List of Tables
Table Number 1-1 2-1 4-1 6-1 6-2 6-3 6-4 6-5 6-6 8-1 9-1 9-2 11-1 11-2 13-1 13-2 13-3 13-4 13-5 13-6 13-7 13-8 15-1 15-2 15-3 16-1 16-2 16-3 Title Page Number
S3C9454B/F9454B Pin Descriptions ...................................................................................... 1-6 Register Type Summary.......................................................................................................... 2-5 System and Peripheral control Registers ........................................................................................4-2 Instruction Group Summary ..............................................................................................................6-2 Flag Notation Conventions ................................................................................................................6-5 Instruction Set Symbols .....................................................................................................................6-5 Instruction Notation Conventions......................................................................................................6-6 Opcode Quick Reference ..................................................................................................................6-7 Condition Codes..................................................................................................................................6-9 Register Values After a Reset ................................................................................................. 8-4 S3C9454B/F9454B Port Configuration Overview ................................................................... 9-1 Port Data Register Summary .................................................................................................. 9-2 PWM Control and Data Registers ........................................................................................... 11-2 PWM output "stretch" Values for Extension Data Register (PWMDATA.1-.0) ....................... 11-3 Absolute Maximum Ratings .................................................................................................... 13-2 DC Electrical Characteristics................................................................................................... 13-3 AC Electrical Characteristics ................................................................................................... 13-4 Oscillator Characteristics......................................................................................................... 13-5 Oscillation Stabilization Time .................................................................................................. 13-5 Data Retention Supply Voltage in Stop Mode ......................................................................... 13-7 A/D Converter Electrical Characteristics ................................................................................. 13-8 LVR Circuit Characteristics ..................................................................................................... 13-9 Descriptions of Pins Used to Read/Write the Flash ROM....................................................... 15-3 Comparison of S3F9454B and S3C9454B Features .............................................................. 15-3 Operating Mode Selection Criteria .......................................................................................... 15-3 Power Selection Settings for TB9454B ................................................................................... 16-4 The SMDS2+ Tool Selection Setting....................................................................................... 16-4 Using Single Header Pins as the Input Path for External Trigger Sources ............................. 16-5
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List of Programming Tips
Description Chapter 2: Address Spaces Page Number
Smart Option Setting..................................................................................................................................... 2-4 Addressing the Common Working Register Area......................................................................................... 2-7 Standard Stack Operations Using PUSH and POP...............................................................................................2-9 Chapter 8: RESET and Power-Down
Sample S3C9454B/F9454B Initialization Routine ..................................................................................................8-6 Chapter 10: Basic Timer and Timer 0
Configuring the Basic Timer......................................................................................................................................10-6 Configuring Timer 0 (Interval Mode) ........................................................................................................................10-11 Chapter 11: 8-Bit PWM
Programming the PWM Module to Sample Specifications ...................................................................................11-7 Chapter 12: A/D Converter
Configuring A/D Converter ........................................................................................................................................12-6
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List of Register Descriptions
Register Identifier ADCON BTCON CLKCON FLAGS P0CONH P0CONL P0PND P1CON P2CONH P2CONL PWMCON STOPCON SYM T0CON Full Register Name Page Number
A/D Converter Control Register.................................................................................. 4-5 Basic Timer Control Register ..................................................................................... 4-6 Clock Control Register ............................................................................................... 4-7 System Flags Register ............................................................................................... 4-8 Port 0 Control Register (High Byte) ............................................................................ 4-9 Port 0 Control Register (Low Byte)............................................................................. 4-10 Port 0 Interrupt Pending Register............................................................................... 4-11 Port 1 Control Register............................................................................................... 4-12 Port 2 Control Register (High Byte) ............................................................................ 4-13 Port 2 Control Register (Low Byte)............................................................................. 4-14 PWM Control Register ............................................................................................... 4-15 STOP Mode Control Register..................................................................................... 4-16 System Mode Register ............................................................................................... 4-16 TIMER 0 Control Register .......................................................................................... 4-17
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List of Instruction Descriptions
Instruction Mnemonic ADC ADD AND CALL CCF CLR COM CP DEC DI EI IDLE INC IRET JP JR LD LD LDC/LDE LDC/LDE LDCD/LDED LDCI/LDEI Full Instruction Name Page Number
Add with Carry............................................................................................................ 6-11 Add ............................................................................................................................. 6-12 Logical AND ............................................................................................................... 6-13 Call Procedure............................................................................................................ 6-14 Complement Carry Flag ............................................................................................. 6-15 Clear........................................................................................................................... 6-16 Complement............................................................................................................... 6-17 Compare..................................................................................................................... 6-18 Decrement.................................................................................................................. 6-19 Disable Interrupts ....................................................................................................... 6-20 Enable Interrupts ........................................................................................................ 6-21 Idle Operation............................................................................................................. 6-22 Increment ................................................................................................................... 6-23 Interrupt Return .......................................................................................................... 6-24 Jump........................................................................................................................... 6-25 Jump Relative............................................................................................................. 6-26 Load ........................................................................................................................... 6-27 Load ........................................................................................................................... 6-28 Load Memory ............................................................................................................. 6-29 Load Memory ............................................................................................................. 6-30 Load Memory and Decrement.................................................................................... 6-31 Load Memory and Increment ..................................................................................... 6-32
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List of Instruction Descriptions (Continued)
Instruction Mnemonic NOP OR POP PUSH RCF RET RL RLC RR RRC SBC SCF SRA STOP SUB TCM TM XOR Full Instruction Name Page Number
No Operation ..............................................................................................................6-33 Logical OR ..................................................................................................................6-34 Pop From Stack..........................................................................................................6-35 Push To Stack ............................................................................................................6-36 Reset Carry Flag.........................................................................................................6-37 Return .........................................................................................................................6-38 Rotate Left ..................................................................................................................6-39 Rotate Left Through Carry..........................................................................................6-40 Rotate Right................................................................................................................6-41 Rotate Right Through Carry........................................................................................6-42 Subtract With Carry ....................................................................................................6-43 Set Carry Flag.............................................................................................................6-44 Shift Right Arithmetic ..................................................................................................6-45 Stop Operation............................................................................................................6-46 Subtract ......................................................................................................................6-47 Test Complement Under Mask...................................................................................6-48 Test Under Mask ........................................................................................................6-49 Logical Exclusive OR..................................................................................................6-50
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PRODUCT OVERVIEW
1
PRODUCT OVERVIEW
SAM88RCRI PRODUCT FAMILY
Samsung's SAM88RCRI family of 8-bit single-chip CMOS microcontrollers offer a fast and efficient CPU, a wide range of integrated peripherals, and various mask-programmable ROM sizes. A address/data bus architecture and a large number of bit-configurable I/O ports provide a flexible programming environment for applications with varied memory and I/O requirements. Timer/counters with selectable operating modes are included to support real-time operations.
S3C9454B/F9454B MICROCONTROLLER
The S3C9454B/F9454B single-chip 8-bit microcontroller is designed for useful A/D converter application field. The S3C9454B/F9454B uses powerful SAM88RCRI CPU and S3C9454B/F9454B architecture. The internal register file is logically expanded to increase the on-chip register space. The S3C9454B/F9454B has 4K bytes of on-chip program ROM and 208 bytes of RAM. The S3C9454B/F9454B is a versatile general-purpose microcontroller that is ideal for use in a wide range of electronics applications requiring simple timer/counter, PWM. In addition, the S3C9454B/F9454's advanced CMOS technology provides for low power consumption and wide operating voltage range. Using the SAM88RCRI design approach, the following peripherals were integrated with the SAM88RCRI core: -- Three configurable I/O ports (18 pins) -- Four interrupt sources with one vector and one interrupt level -- One 8-bit timer/counter with time interval mode -- Analog to digital converter with nine input channels(MAX) and 10-bit resolution -- One 8-bit PWM output The S3C9454B/F9454B microcontroller is ideal for use in a wide range of electronic applications requiring simple timer/counter, PWM, ADC. S3C9454B/F9454B is available in a 20/16-pin DIP and a 20/16-pin SOP and a 20/16pin SSOP package.
MTP
The S3F9454B is an MTP (Multi Time Programmable) version of the S3C9454B microcontroller. The S3F9454B has on-chip 4-Kbyte multi-time programmable flash ROM instead of masked ROM. The S3F9454B is fully compatible with the S3C9454B, in function, in D.C. electrical characteristics and in pin configuration.
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PRODUCT OVERVIEW
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S3C9454B/F9454B
FEATURES
CPU * * SAM88RCRI CPU core The SAM88RCRI core is low-end version of the current SAM87 core. Timer/Counters * * One 8-bit basic timer for watchdog function One 8-bit timer/counter with time interval modes
A/D Converter Memory * * 4-Kbyte internal program memory 208-byte general purpose register area Oscillation Frequency Instruction Set * * 41 instructions The SAM88RCRI core provides all the SAM87 core instruction except the word-oriented instruction, multiplication, division, and some one-byte instruction. * * * 1 MHz to 10 MHz external crystal oscillator Maximum 10 MHz CPU clock Internal RC: 3.2 MHz (typ.), 0.5 MHz (typ.) in VDD = 5 V * * Nine analog input pins (MAX) 10-bit conversion resolution
Operating Temperature Range Instruction Execution Time * 400 ns at 10 MHz fOSC (minimum) Operating Voltage Range Interrupts * * 4 interrupt sources with one vector One interrupt level Smart Option General I/O * * Three I/O ports (Max 18 pins) Bit programmable ports Package Types * S3C9454B/F9454B: - - - - - - 20-SSOP-225 20-DIP-300A 20-SOP-375 16-SOP-BD300-SG 16-DIP-300A 16-SSOP-BD44 * * 2.0 V to 5.5 V (LVR disable) LVR to 5.5V (LVR enable) * - 25C to + 85C
8-bit High-speed PWM * * 8-bit PWM 1-ch (Max: 156 kHz) 6-bit base + 2-bit extension
Built-in Reset Circuit * Low voltage detector for safe Reset
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PRODUCT OVERVIEW
BLOCK DIAGRAM
XIN XOUT
OSC Port 0 Port I/O and Interrupt Control Basic Timer
P0.0/ADC0/INT0 P0.1/ADC1/INT1 P0.2/ADC2 P0.7/ADC7
...
P1.0 P1.1 P1.2
Timer 0 88RCRI SAMRI CPU ADC
Port 1
ADC0-ADC8
P0.6/PWM
PWM
4 KB ROM
208 Byte Register File
Port 2
P2.0/T0 P2.1 P2.6
...
NOTE:
P1.2 is used as input only
Figure 1-1. Block Diagram
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PRODUCT OVERVIEW
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S3C9454B/F9454B
PIN ASSIGNMENTS
VSS XIN/P1.0 XOUT/P1.1 nRESET/P1.2 P2.0/T0 P2.1 P2.2 P2.3 P2.4 P2.5
1 2 3 4 5 6 7 8 9 10
20 19 18 17
VDD P0.0/ADC0/INT0 P0.1/ADC1/INT1 P0.2/ADC2 P0.3/ADC3 P0.4/ADC4 P0.5/ADC5 P0.6/ADC6/PWM P0.7/ADC7 P2.6/ADC8/CLO
S3C9454B/F9454B
(20-DIP-300A/ 20-SOP-375/ 20-SSOP-225)
16 15 14 13 12 11
Figure 1-2. Pin Assignment Diagram (20-Pin DIP/SOP/SSOP Package)
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PRODUCT OVERVIEW
VSS XIN/P1.0 XOUT/P1.1 nRESET/P1.2 P2.0/T0 P2.1 P2.2 P2.3
1 2 3 4 5 6 7 8 (16-DIP-300A/ 16-SOP-BD300-SG/ 16-SSOP-BD44)
16 15
VDD P0.0/ADC0/INT0 P0.1/ADC1/INT1 P0.2/ADC2 P0.3/ADC3 P0.4/ADC4 P0.5/ADC5 P0.6/ADC6/PWM
S3C9454B/F9454B
14 13 12 11 10 9
Figure 1-3. Pin Assignment Diagram (16-Pin DIP/SOP/SSOP Package)
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PRODUCT OVERVIEW
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S3C9454B/F9454B
PIN DESCRIPTIONS
Table 1-1. S3C9454B/F9454B Pin Descriptions Pin Name P0.0-P0.7 Input/ Output I/O Pin Description Bit-programmable I/O port for Schmitt trigger input or push-pull output. Pull-up resistors are assignable by software. Port0 pins can also be used as A/D converter input, PWM output or external interrupt input. Bit-programmable I/O port for Schmitt trigger input or push-pull, open-drain output. Pull-up resistors or pull-down resistors are assignable by software. Schmitt trigger input port Bit-programmable I/O port for Schmitt trigger input or pushpull, open-drain output. Pull-up resistors are assignable by software. Crystal/Ceramic, or RC oscillator signal for system clock. Internal LVR or external RESET Voltage input pin and ground System clock output port External interrupt input port 8-Bit high speed PWM output Timer0 match output A/D converter input E-1 E-1 E-1 E-1 E-1 E B Pin Type E-1 Share Pins ADC0-ADC7 INT0/INT1 PWM XIN, XOUT
P1.0-P1.1
I/O
E-2
P1.2 P2.0-P2.6
I I/O
B E E-1
RESET - ADC8/CLO T0 P1.0-P1.1 P1.2 - P2.6 P0.0, P0.1 P0.6 P2.0 P0.0-P0.7 P2.6
XIN, XOUT nRESET VDD, VSS CLO INT0-INT1 PWM T0 ADC0-ADC8
- I - O I O O I
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PRODUCT OVERVIEW
PIN CIRCUITS
VDD
P-channel IN N-channel
IN
Figure 1-5. Pin Circuit Type A
Figure 1-6. Pin Circuit Type B
VDD
VDD
Data Out Output DIsable
Pull-up Enable Data Output Disable
Circuit Type C
I/O
Digital Input
Figure 1-7. Pin Circuit Type C
Figure 1-8. Pin Circuit Type D
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PRODUCT OVERVIEW
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S3C9454B/F9454B
VDD Open-drain Enable P2CONH P2CONL Alternative Output P2.x VDD Pull-up enable
P-CH M U X Data I/O N-CH
Output Disable (Input Mode) Digital Input
Analog Input Enable ADC
Figure 1-9. Pin Circuit Type E
VDD
P0CONH Alternative Output P0.x
VDD
Pull-up enable
P-CH M U X Data I/O N-CH
Output Disable (Input Mode) Digital Input
Interrupt Input Analog Input Enable ADC
Figure 1-10. Pin Circuit Type E-1
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PRODUCT OVERVIEW
VDD Open-drain Enable VDD Pull-up enable
P1.x I/O Output Disable (Input Mode) Pull-down enable
Digital Input XIN XOUT
Figure 1-11. Pin Circuit Type E-2
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PRODUCT OVERVIEW
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NOTES
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ADDRESS SPACES
2
OVERVIEW
ADDRESS SPACES
The S3C9454B/F9454B microcontroller has two kinds of address space: -- Internal program memory (ROM) -- Internal register file A 12-bit address bus supports program memory operations. A separate 8-bit register bus carries addresses and data between the CPU and the internal register file. The S3C9454B/F9454B have 4-Kbytes of mask-programmable on-chip program memory: which is configured as the Internal ROM mode, all of the 4-Kbyte internal program memory is used. The S3C9454B/F9454B microcontroller has 208 general-purpose registers in its internal register file. Twenty-six bytes in the register file are mapped for system and peripheral control functions.
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ADDRESS SPACES
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S3C9454B/F9454B
PROGRAM MEMORY (ROM)
Normal Operating Mode The S3C9454B/F9454B have 4-Kbytes (locations 0H-0FFFH) of internal mask-programmable program memory. The first 2-bytes of the ROM (0000H-0001H) are interrupt vector address. Unused locations (0002H-00FFH except 3CH, 3DH, 3EH, 3FH) can be used as normal program memory. 3CH, 3DH, 3EH, 3FH is used smart option ROM cell. The program Reset address in the ROM is 0100H.
(Decimal) 4.095
(HEX) 1000H
4-Kbyte Program Memory Area
256 Program Start 64 60 2 1 0 Interrupt Vector Smart option ROM cell
0100H 0040H 003CH 0002H 0001H 0000H
Figure 2-1. Program Memory Address Space
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ADDRESS SPACES
Smart Option Smart option is the ROM option for starting condition of the chip. The ROM addresses used by smart option are from 003CH to 003FH. The S3C9454B/F9454B only use 003EH, 003FH. Not used ROM address 003CH, 003DH should be initialized to be initialized to 00H. The default value of ROM is FFH (LVR enable, internal RC oscillator).
ROM Address: 003CH MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Must be initialized to 00H. ROM Address: 003DH MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Must be initialized to 00H.
ROM Address: 003EH MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
LVR enable/disable bit: 0 = Disable 1 = Enable LVR level selection bits: 11001 = 2.3 V 10010 = 3.0 V 01100 = 3.9 V
Not used
ROM Address: 003FH MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Not used.
NOTES: 1. When you use external oscillator, P1.0, P1.1 must be set to output port to prevent current consumption. 2. The value of unused bits of 3EH, 3FH is don't care. 3. When LVR is enabled, LVR level must be set to appropriate value, not default value.
Oscillator selection bits: 00 = External crystal/ ceramic oscillator 01 = External RC 10 = Internal RC (0.5 MHz in VDD = 5 V) 11 = Internal RC (3.2 MHz in VDD = 5 V)
Figure 2-2. Smart Option
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S3C9454B/F9454B
F PROGRAMMING TIP -- Smart Option Setting
; << Interrupt Vector Address >> ORG Vector ; 0000H 00H, INT_9454 ; S3C9454B/F9454B has only one interrupt vector
<< Smart Option Setting >> ORG DB DB DB DB 003CH 00H 00H 0E7H 03H ; ; ; ; 003CH, must be initialized to 0. 003DH, must be initialized to 0. 003EH, enable LVR (2.3 V) 003FH, Internal RC (3.2 MHz in VDD = 5 V)
;
<< Reset >> ORG RESET: 0100H DI
* * *
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ADDRESS SPACES
REGISTER ARCHITECTURE
The upper 64-bytes of the S3C9454B/F9454B's internal register file are addressed as working registers, system control registers and peripheral control registers. The lower 192-bytes of internal register file(00H-BFH) is called the general purpose register space. 234 registers in this space can be accessed; 208 are available for generalpurpose use. For many SAM88RCRI microcontrollers, the addressable area of the internal register file is further expanded by additional register pages at the general purpose register space (00H-BFH: page0). This register file expansion is not implemented in the S3C9454B/F9454B, however. The specific register types and the area (in bytes) that they occupy in the internal register file are summarized in Table 2-1. Table 2-1. Register Type Summary Register Type CPU and system control registers Peripheral, I/O, and clock control and data registers General-purpose registers (including the 16-bit common working register area) Total Addressable Bytes Number of Bytes 11 15 208 234
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FFH Peripheral Control Registers 64 Bytes of Common Area E0H DFH D0H CFH C0H BFH
System Control Registers Working Registers
192 Bytes ~
General Purpose Register File and Stack Area
00H
Figure 2-3. Internal Register File Organization
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ADDRESS SPACES
COMMON WORKING REGISTER AREA (C0H-CFH)
The SAM88RCRI register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time. This16-byte address range is called common area. That is, locations in this area can be used as working registers by operations that address any location on any page in the register file. Typically, these working registers serve as temporary buffers for data operations between different pages. However, because the S3C9454B/F9454B uses only page 0, you can use the common area for any internal data operation. The Register (R) addressing mode can be used to access this area Registers are addressed either as a single 8-bit register or as a paired 16-bit register. In 16-bit register pairs, the address of the first 8-bit register is always an even number and the address of the next register is an odd number. The most significant byte of the 16-bit data is always stored in the even-numbered register; the least significant byte is always stored in the next (+ 1) odd-numbered register.
MSB Rn
LSB Rn+1
n = Even address
Figure 2-4. 16-Bit Register Pairs
F PROGRAMMING TIP -- Addressing the Common Working Register Area
As the following examples show, you should access working registers in the common area, locations C0H-CFH, using working register addressing mode only. Examples: 1. LD 0C2H,40H ; Invalid addressing mode! ; R2 (C2H) the value in location 40H ; Invalid addressing mode! ; R3 (C3H) R3 + 45H
Use working register addressing instead: LD 2. ADD R2,40H 0C3H,#45H
Use working register addressing instead: ADD R3,#45H
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SYSTEM STACK
S3C9-series microcontrollers use the system stack for subroutine calls and returns and to store data. The PUSH and POP instructions are used to control system stack operations. The S3C9454B/F9454B architecture supports stack operations in the internal register file. Stack Operations Return addresses for procedure calls and interrupts and data are stored on the stack. The contents of the PC are saved to stack by a CALL instruction and restored by the RET instruction. When an interrupt occurs, the contents of the PC and the FLAGS register are pushed to the stack. The IRET instruction then pops these values back to their original locations. The stack address is always decremented before a push operation and incremented after a pop operation. The stack pointer (SP) always points to the stack frame stored on the top of the stack, as shown in Figure 2-5.
High Address
PCL PCL Top of stack PCH PCH Top of stack Flags Stack contents after an interrupt
Stack contents after a call instruction
Low Address
Figure 2-5. Stack Operations Stack Pointer (SP) Register location D9H contains the 8-bit stack pointer (SP) that is used for system stack operations. After a reset, the SP value is undetermined. Because only internal memory space is implemented in the S3C9454B/F9454B, the SP must be initialized to an 8bit value in the range 00H-0C0H. NOTE In case a Stack Pointer is initialized to 00H, it is decreased to FFH when stack operation starts. This means that a Stack Pointer access invalid stack area. We recommend that a stack pointer is initialized to C0H to set upper address of stack to BFH.
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ADDRESS SPACES
F PROGRAMMING TIP -- Standard Stack Operations Using PUSH and POP
The following example shows you how to perform stack operations in the internal register file using PUSH and POP instructions: LD
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SP,#0C0H
; SP C0H (Normally, the SP is set to C0H by the ; initialization routine)
PUSH PUSH PUSH PUSH
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SYM R15 20H R3
; ; ; ;
Stack address 0BFH Stack address 0BEH Stack address 0BDH Stack address 0BCH

SYM R15 20H R3
POP POP POP POP
R3 20H R15 SYM
; ; ; ;
R3 Stack address 0BCH 20H Stack address 0BDH R15 Stack address 0BEH SYM Stack address 0BFH
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NOTES
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ADDRESSING MODES
3
OVERVIEW
-- Register (R)
ADDRESSING MODES
Instructions that are stored in program memory are fetched for execution using the program counter. Instructions indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to determine the location of the data operand. The operands specified in SAM88RCRI instructions may be condition codes, immediate data, or a location in the register file, program memory, or data memory. The SAM88RCRI instruction set supports six explicit addressing modes. Not all of these addressing modes are available for each instruction. The addressing modes and their symbols are as follows:
-- Indirect Register (IR) -- Indexed (X) -- Direct Address (DA) -- Relative Address (RA) -- Immediate (IM)
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ADDRESSING MODES
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REGISTER ADDRESSING MODE (R) In Register addressing mode, the operand is the content of a specified register (see Figure 3-1). Working register addressing differs from Register addressing because it uses an 16-byte working register space in the register file and an 4-bit register within that space (see Figure 3-2).
Program Memory 8-Bit Register File Address One-Operand Instruction (Example)
Register File
dst OPCODE
Point to one register in register file Value used in Instruction Execution
OPERAND
Sample Instruction: DEC CNTR ; Where CNTR is the label of an 8-bit register address
Figure 3-1. Register Addressing
Register File MSB point to RP0 to RP1 RP0 or RP1
Program Memory 4-Bit Working Register Two-Operand Instruction (Example) 3 LSBs Point to the working register (1 of 8) OPERAND
dst
src
Selected RP points to start of working register block
OPCODE
Sample Instruction: ADD R1, R2 ; Where R1 and R2 are registers in the currently selected working register area.
Figure 3-2. Working Register Addressing
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ADDRESSING MODES
INDIRECT REGISTER ADDRESSING MODE (IR) In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the operand. Depending on the instruction used, the actual address may point to a register in the register file, to program memory (ROM), or to an external memory space (see Figures 3-3 through 3-6). You can use any 8-bit register to indirectly address another register. Any 16-bit register pair can be used to indirectly address another memory location.
Program Memory 8-Bit Register File Address
Register File
dst OPCODE
One-Operand Instruction (Example)
Point to one register in register file Address of operand used by instruction
ADDRESS
Value used in instruction execution
OPERAND
Sample Instruction: RL @SHIFT ; Where SHIFT is the label of an 8-bit register ddress
Figure 3-3. Indirect Register Addressing to Register File
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INDIRECT REGISTER ADDRESSING MODE (Continued)
Register File
Program Memory Example Instruction References Program Memory REGISTER PAIR Point to register pair 16-bit address points to program memory
dst OPCODE
Program Memory Value used in instruction
OPERAND
Sample Instructions: CALL JP @RR2 @RR2
Figure 3-4. Indirect Register Addressing to Program Memory
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ADDRESSING MODES
INDIRECT REGISTER ADDRESSING MODE (Continued)
Register File CFH
Program Memory 4-Bit Working Register Address 4 LSBs Point to the working register (1 of 16)
. . . . OPERAND C0H
dst
src
OPCODE
Sample Instruction: OR R6, @R2
Value used in instruction
OPERAND
Figure 3-5. Indirect Working Register Addressing to Register File
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INDIRECT REGISTER ADDRESSING MODE (Concluded)
Register File CFH
Program Memory 4-Bit Working Register Address dst src OPCODE Next 3 Bits Point to working register pair (1 of 8) LSB Selects
. . . .
Register Pair C0H 16-Bit address points to program memory or data memory
Example instruction references either program memory or data memory
Program Memory or Data Memory
Value used in instruction
OPERAND
Sample Instructions: LCD LDE LDE R5,@RR6 R3,@RR14 @RR4, R8 ; Program memory access ; External data memory access ; External data memory access
Figure 3-6. Indirect Working Register Addressing to Program or Data Memory
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ADDRESSING MODES
INDEXED ADDRESSING MODE (X) Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see Figure 3-7). You can use Indexed addressing mode to access locations in the internal register file or in external memory. In short offset Indexed addressing mode, the 8-bit displacement is treated as a signed integer in the range - 128 to + 127. This applies to external memory accesses only (see Figure 3-8). For register file addressing, an 8-bit base address provided by the instruction is added to an 8-bit offset contained in a working register. For external memory accesses, the base address is stored in the working register pair designated in the instruction. The 8-bit or 16-bit offset given in the instruction is then added to the base address (see Figure 3-9). The only instruction that supports Indexed addressing mode for the internal register file is the Load instruction (LD). The LDC and LDE instructions support Indexed addressing mode for internal program memory, external program memory, and for external data memory, when implemented.
Register File
~
Value used in instruction OPERAND
~
+
Program Memory X (OFFSET) dst src OPCODE 4 LSBs Point to one of the working register (1 of 16)
~
INDEX
~
Two-Operand Instruction Example
Sample Instruction: LD R0, #BASE[R1] ; Where BASE is an 8-bit immediate value
Figure 3-7. Indexed Addressing to Register File
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INDEXED ADDRESSING MODE (Continued)
Program Memory 4-Bit Working Register Address XS (OFFSET) dst src OPCODE NEXT 3 Bits Point to working register pair (1 of 8)
Register File
Register Pair 16-Bit address added to offset
LSB Selects
+
8-Bit 16-Bit Program Memory or Data memory Value used in instruction
16-Bit
OPERAND
Sample Instructions: LDC LDE R4, #04H[RR2] R4,#04H[RR2] ; The values in the program address (RR2 + #04H) are loaded into register R4. ; Identical operation to LDC example, except that external program memory is accessed.
Figure 3-8. Indexed Addressing to Program or Data Memory with Short Offset
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ADDRESSING MODES
INDEXED ADDRESSING MODE (Concluded)
Program Memory XLH (OFFSET) 4-Bit Working Register Address XLL (OFFSET) dst src OPCODE NEXT 3 Bits Point to working register pair (1 of 8) LSB Selects + 16-Bit 16-Bit
Register File
Register Pair 16-Bit address added to offset
Program Memory or Datamemory
16-Bit Sample Instructions: LDC LDE R4, #1000H[RR2] R4, #1000H[RR2]
OPERAND
Value used in instruction
; The values in the program address (RR2 + #1000H) are loaded into register R4. ; Identical operation to LDC example, except that external program memory is accessed.
Figure 3-9. Indexed Addressing to Program or Data Memory with Long Offset
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DIRECT ADDRESS MODE (DA) In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call (CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed. The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for Load operations to program memory (LDC) or to external data memory (LDE), if implemented.
Program or Data Memory
Program Memory
Memory Address Used
Upper Address Byte Lower Address Byte dst/src "0" or "1" OPCODE
LSB Selects Program Memory or Data Memory: "0" = Program Memory "1" = Data Memory
Sample Instructions: LDC LDE R5,1234H ; R5,1234H ; The values in the program address (1234H)are loaded into register R5. Identical operation to LDC example, except that external program memory is accessed.
Figure 3-10. Direct Addressing for Load Instructions
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ADDRESSING MODES
DIRECT ADDRESS MODE (Continued)
Program Memory
Next OPCODE Program Memory Address Used Lower Address Byte Upper Address Byte OPCODE
Sample Instructions: JP CALL C,JOB1 DISPLAY ; ; Where JOB1 is a 16-bit immediate address Where DISPLAY is a 16-bit immediate address
Figure 3-11. Direct Addressing for Call and Jump Instructions
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RELATIVE ADDRESS MODE (RA) In Relative Address (RA) mode, a two's-complement signed displacement between - 128 and + 127 is specified in the instruction. The displacement value is then added to the current PC value. The result is the address of the next instruction to be executed. Before this addition occurs, the PC contains the address of the instruction immediately following the current instruction. The instructions that support RA addressing is JR.
Program Memory
Next OPCODE Program Memory Address Used
Current Instruction
Displacement OPCODE
Current PC Value Signed Displacement Value
+
Sample Instructions: JR ULT,$ + OFFSET ; Where OFFSET is a value in the range + 127 to - 128
Figure 3-12. Relative Addressing
IMMEDIATE MODE (IM) In Immediate (IM) addressing mode, the operand value used in the instruction is the value supplied in the operand field itself. Immediate addressing mode is useful for loading constant values into registers.
Program Memory OPERAND OPCODE
(The Operand value is in the instruction) Sample Instruction: LD R0,#0AAH
Figure 3-13. Immediate Addressing
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CONTROL REGISTERS
4
OVERVIEW
CONTROL REGISTERS
In this section, detailed descriptions of the S3C9454B/F9454B control registers are presented in an easy-to-read format. These descriptions will help familiarize you with the mapped locations in the register file. You can also use them as a quick-reference source when writing application programs. System and peripheral registers are summarized in Table 4-1. Figure 4-1 illustrates the important features of the standard register description format. Control register descriptions are arranged in alphabetical order according to register mnemonic. More information about control registers is presented in the context of the various peripheral hardware descriptions in Part II of this manual.
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Table 4-1. System and Peripheral Control Registers Register name Timer 0 counter register Timer 0 data register Timer 0 control register Clock control register System flags register Stack pointer register MDS special register Basic timer control register Basic timer counter Test mode control register System mode register Mnemonic T0CNT T0DATA T0CON CLKCON FLAGS SP MDSREG BTCON BTCNT FTSTCON SYM Address & Location Address D0H D1H D2H D4H D5H D9H DBH DCH DDH DEH DFH R/W R R/W R/W R/W R/W R/W R/W R/W R W R/W 7 0 1 0 0 x x 0 0 0 - - 6 0 1 0 - x x 0 0 0 - - RESET value (Bit) 5 0 1 - - x x 0 0 0 0 - 4 0 1 - 0 x x 0 0 0 0 - 3 0 1 0 0 - x 0 0 0 0 - 2 0 1 - - - x 0 0 0 0 0 1 0 1 0 - - x 0 0 0 0 0 0 0 1 0 - - x 0 0 0 0 0
Location D3H is not mapped
Locations D6H-D8H are not mapped Location DAH is not mapped
NOTES: 1. - : Not mapped or not used, x: Undefined 2. The factory test mode register, FTSTCON, is for factory use only. Its value should always be '00H' during the normal operation.
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CONTROL REGISTERS
Table 4-1. System and Peripheral Control Registers (Continued) Register Name Port 0 data register Port 1 data register Port 2 data register Port 0 control register (High byte) Port 0 control register Port 0 interrupt pending register Port 1 control register Port 2 control register (High byte) Port 2 control register (Low byte) PWM data register PWM control register STOP .control register A/D control register A/D converter data register ( High ) A/D converter data register ( Low ) Mnemonic P0 P1 P2 P0CONH P0CONL P0PND P1CON P2CONH P2CONL PWMDATA PWMCON STOPCON ADCON ADDATAH ADDATAL Address Hex E0H E1H E2H E6H E7H E8H E9H EAH EBH F2H F3H F4H F7H F8H F9H R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W 7 0 - - 0 0 - 0 - 0 0 0 0 0 x 0 Bit Values After RESET 6 0 - 0 0 0 - 0 0 0 0 0 0 0 x 0 5 0 - 0 0 0 - - 0 0 0 - 0 0 x 0 4 0 - 0 0 0 - - 0 0 0 0 0 0 x 0 3 0 - 0 0 0 0 0 0 0 0 0 0 0 x 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 x 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x
Locations E3H-E5H are not mapped
Locations ECH-F1H are not mapped
Locations F5H-F6H are not mapped
Locations FAH-FFH are not mapped
NOTE: - : Not mapped or not used, x: Undefined
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Bit number(s) that is/are appended to the register name for bit addressing Name of individual Register bit or related bits Register name ID
Register address (hexadecimal)
FLAGS - System Flags Register
Bit Identifier RESET Value Read/Write
.7 .7 x R/W .6 x R/W .5 x R/W .4 x R/W .3 x R/W
D5H .2 x R/W .1 0 R/W .0 0 R/W
Carry Flag (C) 0 1 Operation dose not generate a carry or borrow condition Operation generates carry-out or borrow into high-order bit7
.6
Zero Flag 0 1 Operation result is a non-zero value Operation result is zero
.5
Sign Flag 0 1 Operation generates positive number (MSB = "0") Operation generates negative number (MSB = "1")
R = Read-only W = Write-only R/W = Read/write ' - ' = Not used
Description of the effect of specific bit settings
RESET value notation: '-' = Not used 'x' = Undetermind value '0' = Logic zero '1' = Logic one
Bit number: MSB = Bit 7 LSB = Bit 0
Figure 4-1. Register Description Format
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CONTROL REGISTERS
ADCON -- A/D Converter Control Register
Bit Identifier RESET Value Read/Write .7-.4 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W .0 0
F7H
R/W
A/D Converter Input Pin Selection Bits 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ADC0 (P0.0) ADC1 (P0.1) ADC2 (P0.2) ADC3 (P0.3) ADC4 (P0.4) ADC5 (P0.5) ADC6 (P0.6) ADC7 (P0.7) ADC8 (P2.6) Connected with GND internally Connected with GND internally Connected with GND internally Connected with GND internally Connected with GND internally Connected with GND internally Connected with GND internally
.3
End-of-Conversion Status Bit 0 1 A/D conversion is in progress A/D conversion complete
.2-.1
Clock Source Selection Bit (note) 0 0 1 1 0 1 0 1 fOSC/16 (fOSC 10 MHz) fOSC/8 (fOSC 10 MHz) fOSC/4 (fOSC 10 MHz) fOSC/1 (fOSC 4 MHz)
.0
Conversion Start Bit 0 1 No meaning A/D conversion start
NOTE: Maximum ADC clock input = 4 MHz.
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BTCON -- Basic Timer Control Register
Bit Identifier RESET Value Read/Write .7-.4 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W
DCH
.0 0 R/W
Watchdog Timer Function Enable Bit 1 0 1 0 Disable watchdog timer function Enable watchdog timer function Others
.3-.2
Basic Timer Input Clock Selection Code 0 0 1 1 0 1 0 1 fOSC/4096 fOSC/1024 fOSC/128 Invalid setting
.1
Basic Timer 8-Bit Counter Clear Bit 0 1 No effect Clear the basic timer counter value
.0
Basic Timer Divider Clear Bit 0 1 No effect Clear both dividers
NOTE: When you write a "1" to BTCON.0 (or BTCON.1), the basic timer counter (or basic timer divider) is cleared. The bit is then cleared automatically to "0".
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CONTROL REGISTERS
CLKCON -- Clock Control Register
Bit Identifier RESET Value Read/Write .7 .7 0 R/W .6 - - .5 - - .4 0 R/W .3 0 R/W .2 - - .1 - - - -
D4H
.0
Oscillator IRQ Wake-up Function Enable Bit 0 1 Enable IRQ for main system oscillator wake-up function Disable IRQ for main system oscillator wake-up function
.6-.5 .4-.3
Not used for S3C9454B/F9454B Divided by Selection Bits for CPU Clock frequency 0 0 1 1 0 1 0 1 Divide by 16 (fOSC/16) Divide by 8 (fOSC/8) Divide by 2 (fOSC/2) Non-divided clock (fOSC)
.2-.0
Not used for S3C9454B/F9454B
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FLAGS -- System Flags Register
Bit Identifier RESET Value Read/Write .7 .7 x R/W .6 x R/W .5 x R/W .4 x R/W .3 - - .2 - - .1 - - - -
D5H
.0
Carry Flag (C) 0 1 Operation does not generate a carry or borrow condition Operation generates a carry-out or borrow into high-order bit 7
.6
Zero Flag (Z) 0 1 Operation result is a non-zero value Operation result is zero
.5
Sign Flag (S) 0 1 Operation generates a positive number (MSB = "0") Operation generates a negative number (MSB = "1")
.4
Overflow Flag (V) 0 1 Operation result is + 127 or - 128 Operation result is > + 127 or < - 128
.3-.0
Not used for S3C9454B/F9454B
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CONTROL REGISTERS
P0CONH -- Port 0 Control Register (High Byte)
Bit Identifier RESET Value Read/Write .7-.6 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W .0 0
E6H
R/W
Port 0, P0.7/INT7 Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input; pull-up enable Schmitt trigger input Push-pull output A/D converter input (ADC7); Schmitt trigger input off
.5-.4
Port 0, P0.6/ADC6/PWM Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input; pull-up enable Alternative function (PWM output) Push-pull output A/D converter input (ADC6); Schmitt trigger input off
.3-.2
Port 0, P0.5/ADC5 Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input; pull-up enable Schmitt trigger input Push-pull output A/D converter input (ADC5); Schmitt trigger input off
.1-.0
Port 0, P0.4/ADC4 Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input; pull-up enable Schmitt trigger input Push-pull output A/D converter input (ADC4); Schmitt trigger input off
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P0CONL -- Port 0 Control Register (Low Byte)
Bit Identifier RESET Value Read/Write .7-.6 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W .0 0
E7H
R/W
Port 0, P0.3/INT3 Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input Schmitt trigger input; pull-up enable Push-pull output A/D converter input (ADC3); Schmitt trigger input off
.5-.4
Port 0, P0.2/ADC2 Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input Schmitt trigger input; pull-up enable Push-pull output A/D converter input (ADC2); Schmitt trigger input off
.3-.2
Port 0, P0.1/ADC1/INT1 Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input/falling edge interrupt input Schmitt trigger input; pull-up enable/falling edge interrupt input Push-pull output A/D converter input (ADC1); Schmitt trigger input off
.1-.0
Port 0, P0.0/ADC0/INT0 Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input/falling edge interrupt input Schmitt trigger input; pull-up enable/falling edge interrupt input Push-pull output A/D converter input (ADC0); Schmitt trigger input off
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CONTROL REGISTERS
P0PND -- Port 0 Interrupt Pending Register
Bit Identifier RESET Value Read/Write .7-.4 .3 .7 - - .6 - - .5 - - .4 - - .3 0 R/W .2 0 R/W .1 0 R/W .0 0
E8H
R/W
Not used for the S3C9454B/F9454B Port 0.1/ADC1/INT1 Interrupt Enable Bit 0 1 INT1 falling edge interrupt disable INT1 falling edge interrupt enable
.2
Port 0.1/ADC1/INT1 Interrupt Pending Bit 0 0 1 1 No interrupt pending (when read) Pending bit clear (when write) Interrupt is pending (when read) No effect (when write)
.1
Port 0.0/ADC0/INT0 Interrupt Enable Bit 0 1 INT0 falling edge interrupt disable INT0 falling edge interrupt enable
.0
Port 0.0/ADC0/INT0 Interrupt Pending Bit 0 0 1 1 No interrupt pending (when read) Pending bit clear (when write) Interrupt pending (when read) No effect (when write)
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P1CON -- Port 1 Control Register
Bit Identifier RESET Value Read/Write .7 .7 0 R/W .6 0 R/W .5 - - .4 - - .3 0 R/W .2 0 R/W .1 0 R/W .0 0
E9H
R/W
Part 1.1 N-channel open-drain Enable Bit 0 1 Configure P1.1 as a push-pull output Configure P1.1 as a n-channel open-drain output
.6
Port 1.0 N-channel open-drain Enable Bit 0 1 Configure P1.0 as a push-pull output Configure P1.0 as a n-channel open-drain output
.5-.4 .3-.2
Not used for S3C9454B/F9454B Port 1, P1.1 Interrupt Pending Bits 0 0 1 1 0 1 0 1 Schmitt trigger input; Schmitt trigger input; pull-up enable Output Schmitt trigger input; pull-down enable
.1-.0
Port 1, P1.0 Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input; Schmitt trigger input; pull-up enable Output Schmitt trigger input; pull-down enable
NOTE: When you use external oscillator, P1.0, P1.1 must be set to output port to prevent current consumption.
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CONTROL REGISTERS
P2CONH -- Port 2 Control Register (High Byte)
Bit Identifier RESET Value Read/Write .7 .6-.4 .7 - - .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W 0
EAH
.0 R/W
Not used for the S3C9454B/F9454B Port 2, P2.6/ADC8/CLO Configuration Bits 0 0 0 1 1 1 1 0 0 1 0 0 1 1 0 1 x 0 1 0 1 Schmitt trigger input; pull-up enable Schmitt trigger input ADC input Push-pull output Open-drain output; pull-up enable Open-drain output Alternative function; CLO output
.3-.2
Port 2, 2.5 Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input; pull-up enable Schmitt trigger input Push-pull output Open-drain output
.1-.0
Port 2, 2.4 Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input; pull-up enable Schmitt trigger input Push-pull output Open-drain output
NOTE: When noise problem is important issue, you had better not use CLO output.
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P2CONL -- Port 2 Control Register (Low Byte)
Bit Identifier RESET Value Read/Write .7-.6 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W
EBH
.0 0 R/W
Part 2, P2.3 Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input; pull-up enable Schmitt trigger input Push-pull output Open-drain output
.5-.4
Port 2, P2.2 Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input; pull-up enable Schmitt trigger input Push-pull output Open-drain output
.3-.2
Port 2, P2.1 Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input; pull-up enable Schmitt trigger input Push-pull output Open-drain output
.1-.0
Port 2, P2.0 Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input; pull-up enable Schmitt trigger input Push-pull output T0 match output
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CONTROL REGISTERS
PWMCON -- PWM Control Register
Bit Identifier RESET Value Read/Write .7-.6 .7 0 R/W .6 0 R/W .5 - - .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W .0 0
E3H
R/W
PWM Input Clock Selection Bits 0 0 1 1 0 1 0 1 fOSC/64 fOSC/8 fOSC/2 fOSC/1
.5 .4
Not used for S3C9454B/F9454B PWMDATA Reload Interval Selection Bit 0 1 Reload from 8-bit up counter overflow Reload from 6-bit up counter overflow
.3
PWM Counter Clear Bit 0 1 No effect Clear the PWM counter (when write)
.2
PWM Counter Enable Bit 0 1 Stop counter Start (Resume countering)
.1
PWM Overflow Interrupt Enable Bit (8-Bit Overflow) 0 1 Disable interrupt Enable interrupt
.0
PWM Overflow Interrupt Pending Bit 0 0 1 1 No interrupt pending (when read) Clear pending bit (when write) Interrupt is pending (when read) No effect (when write)
NOTE: PWMCON.3 is not auto-cleared. You must pay attention when clear pending bit. (refer to page 11-8).
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STOPCON -- STOP Mode Control Register
Bit Identifier RESET Value Read/Write .7-.0 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W .0 0
E4H
R/W
Watchdog Timer Function Enable Bit 10100101 Other value Enable STOP instruction Disable STOP instruction
NOTE: When STOPCON register is not #0A5H value, if you use STOP instruction, PC is changed to reset address.
SYM -- System Mode Register
Bit Identifier RESET Value Read/Write .7-.3 .3 .7 - - .6 - - .5 - - .4 - - .3 0 R/W .2 0 R/W .1 0 R/W 0
DFH
.0 R/W
Not used for S3C9454B/F9454B Global Interrupt Enable Bit 0 1 Disable all interrupts Enable all interrupt
.2-.0
Page Select Bits 0 0 0 0 0 0 1 1 0 1 0 1 Page 0 Page 1 (Not used for S3C9454B/F9454B) Page 2 (Not used for S3C9454B/F9454B) Page 3 (Not used for S3C9454B/F9454B)
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CONTROL REGISTERS
T0CON -- TIMER 0 Control Register
Bit Identifier RESET Value Read/Write .7-.6 .7 0 R/W .6 0 R/W .5 - - .4 - - .3 0 R/W .2 - - .1 0 R/W .0 0
F4H
R/W
Timer 0 Input Clock Selection Bits 0 0 1 1 0 1 0 1 fOSC/4096 fOSC/256 fOSC/8 fOSC/1
.5-.4 .3
Not used for the S3C9454B/F9454B Timer 0 Counter Clear Bit 0 1 No effect Clear the timer 0 counter (when write)
.2 .1
Not used for the S3C9454B/F9454B Timer 0 Interrupt Enable Bit 0 1 Disable interrupt Enable interrupt
.0
Timer 0 Interrupt Pending Bit (Capture or match interrupt) 0 0 1 1 No interrupt pending (when read) Clear pending bit (when write) Interrupt is pending (when read) No effect (when write)
NOTES: 1. T0CON.3 is not auto-cleared. You must pay attention when clear pending bit. (refer to page 10-12) 2. To use T0 match output, you set T0CON.3 to "1". (refer to page 10-7)
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NOTES
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INTERRUPT STRUCTURE
5
OVERVIEW
INTERRUPT STRUCTURE
The SAM88RCRI interrupt structure has two basic components: a vector, and sources. The number of interrupt sources can be serviced through an interrupt vector which is assigned in ROM address 0000H.
VECTOR
SOURCES S1
0000H 0001H
S2 S3 Sn
NOTES: 1. The SAM88RCRI interrupt has only one vector address (0000H-0001H). 2. The numbern of Sn value is expandable.
Figure 5-1. S3F9-Series Interrupt Type
INTERRUPT PROCESSING CONTROL POINTS Interrupt processing can be controlled in two ways: either globally, or by specific interrupt level and source. The system-level control points in the interrupt structure are therefore: -- Global interrupt enable and disable (by EI and DI instructions) -- Interrupt source enable and disable settings in the corresponding peripheral control register(s)
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ENABLE/DISABLE INTERRUPT INSTRUCTIONS (EI, DI) The system mode register, SYM (DFH), is used to enable and disable interrupt processing. SYM.3 is the enable and disable bit for global interrupt processing respectively, by modifying SYM.3. An Enable Interrupt (EI) instruction must be included in the initialization routine that follows a reset operation in order to enable interrupt processing. Although you can manipulate SYM.3 directly to enable and disable interrupts during normal operation, we recommend that you use the EI and DI instructions for this purpose. INTERRUPT PENDING FUNCTION TYPES When the interrupt service routine has executed, the application program's service routine must clear the appropriate pending bit before the return from interrupt subroutine (IRET) occurs. INTERRUPT PRIORITY Because there is not a interrupt priority register in SAM88RCRI, the order of service is determined by a sequence of source which is executed in interrupt service routine.
"EI" Instruction Execution RESET Source Interrupts Source Interrupt Enable
S R
Q
Interrupt Pending Register Interrpt priority is determind by software polling method
Vector Interrupt Cycle
Global Interrupt Control (EI, DI instruction)
Figure 5-2. Interrupt Function Diagram
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INTERRUPT STRUCTURE
INTERRUPT SOURCE SERVICE SEQUENCE The interrupt request polling and servicing sequence is as follows: 1. A source generates an interrupt request by setting the interrupt request pending bit to "1". 2. The CPU generates an interrupt acknowledge signal. 3. The service routine starts and the source's pending flag is cleared to "0" by software. 4. Interrupt priority must be determined by software polling method.
INTERRUPT SERVICE ROUTINES Before an interrupt request can be serviced, the following conditions must be met: -- Interrupt processing must be enabled (EI, SYM.3 = "1") -- Interrupt must be enabled at the interrupt's source (peripheral control register) If all of the above conditions are met, the interrupt request is acknowledged at the end of the instruction cycle. The CPU then initiates an interrupt machine cycle that completes the following processing sequence: 1. Reset (clear to "0") the global interrupt enable bit in the SYM register (DI, SYM.3 = "0") to disable all subsequent interrupts. 2. Save the program counter and status flags to stack. 3. Branch to the interrupt vector to fetch the service routine's address. 4. Pass control to the interrupt service routine. When the interrupt service routine is completed, an Interrupt Return instruction (IRET) occurs. The IRET restores the PC and status flags and sets SYM.3 to "1" (EI), allowing the CPU to process the next interrupt request. GENERATING INTERRUPT VECTOR ADDRESSES The interrupt vector area in the ROM contains the address of the interrupt service routine. Vectored interrupt processing follows this sequence: 1. Push the program counter's low-byte value to stack. 2. Push the program counter's high-byte value to stack. 3. Push the FLAGS register values to stack. 4. Fetch the service routine's high-byte address from the vector address 0000H. 5. Fetch the service routine's low-byte address from the vector address 0001H. 6. Branch to the service routine specified by the 16-bit vector address.
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S3C9454B/F9454B INTERRUPT STRUCTURE The S3C9454B/F9454B microcontroller has four peripheral interrupt sources: -- PWM overflow -- Timer 0 match -- P0.0 external interrupt -- P0.1 external interrupt
Vector
Pending Bits T0CON.0
Enable/Disable
Source Timer 0 Match
T0CON.1 PWM Overflow PWMCON.1 P0.0 External Interrupt P0PND.1 P0.1 External Interrupt P0PND.3
PWMCON.0 0000H 0001H P0PND.0 SYM.2 (EI, DI)
P0PND.2
Figure 5-3. S3C9454B/F9454B Interrupt Structure
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SAM88RCRI INSTRUCTION SET
6
OVERVIEW
SAM88RCRI INSTRUCTION SET
The SAM88RCRI instruction set is designed to support the large register file. It includes a full complement of 8-bit arithmetic and logic operations. There are 41 instructions. No special I/O instructions are necessary because I/O control and data registers are mapped directly into the register file. Flexible instructions for bit addressing, rotate, and shift operations complete the powerful data manipulation capabilities of the SAM88RCRI instruction set. REGISTER ADDRESSING To access an individual register, an 8-bit address in the range 0-255 or the 4-bit address of a working register is specified. Paired registers can be used to construct 13-bit program memory or data memory addresses. For detailed information about register addressing, please refer to Chapter 2, "Address Spaces". ADDRESSING MODES There are six addressing modes: Register (R), Indirect Register (IR), Indexed (X), Direct (DA), Relative (RA), and Immediate (IM). For detailed descriptions of these addressing modes, please refer to Chapter 3, "Addressing Modes".
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Table 6-1. Instruction Group Summary Mnemonic Operands Instruction
Load Instructions CLR LD LDC LDE LDCD LDED LDCI LDEI POP PUSH dst dst,src dst,src dst,src dst,src dst,src dst,src dst,src dst src Clear Load Load program memory Load external data memory Load program memory and decrement Load external data memory and decrement Load program memory and increment Load external data memory and increment Pop from stack Push to stack
Arithmetic Instructions ADC ADD CP DEC INC SBC SUB dst,src dst,src dst,src dst dst dst,src dst,src Add with carry Add Compare Decrement Increment Subtract with carry Subtract
Logic Instructions AND COM OR XOR dst,src dst dst,src dst,src Logical AND Complement Logical OR Logical exclusive OR
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Table 6-1. Instruction Group Summary (Continued) Mnemonic Operands Instruction
Program Control Instructions CALL IRET JP JP JR RET cc,dst dst cc,dst dst Call procedure Interrupt return Jump on condition code Jump unconditional Jump relative on condition code Return
Bit Manipulation Instructions TCM TM dst,src dst,src Test complement under mask Test under mask
Rotate and Shift Instructions RL RLC RR RRC SRA dst dst dst dst dst Rotate left Rotate left through carry Rotate right Rotate right through carry Shift right arithmetic
CPU Control Instructions CCF DI EI IDLE NOP RCF SCF STOP Complement carry flag Disable interrupts Enable interrupts Enter Idle mode No operation Reset carry flag Set carry flag Enter stop mode
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FLAGS REGISTER (FLAGS) The flags register FLAGS contains eight bits that describe the current status of CPU operations. Four of these bits, FLAGS.4-FLAGS.7, can be tested and used with conditional jump instructions; FLAGS register can be set or reset by instructions as long as its outcome does not affect the flags, such as, Load instruction. Logical and Arithmetic instructions such as, AND, OR, XOR, ADD, and SUB can affect the Flags register. For example, the AND instruction updates the Zero, Sign and Overflow flags based on the outcome of the AND instruction. If the AND instruction uses the Flags register as the destination, then simultaneously, two write will occur to the Flags register producing an unpredictable result.
System Flags Register (FLAGS) D5H, R/W MSB Carry flag (C) Not mapped Zero flag (Z) .7 .6 .5 .4 .3 .2 .1 .0 LSB
Sign flag (S)
Overflow flag (V)
Figure 6-1. System Flags Register (FLAGS) FLAG DESCRIPTIONS 030303Overflow Flag (FLAGS.4, V) The V flag is set to "1" when the result of a two's-complement operation is greater than + 127 or less than - 128. It is also cleared to "0" following logic operations. Sign Flag (FLAGS.5, S) Following arithmetic, logic, rotate, or shift operations, the sign bit identifies the state of the MSB of the result. A logic zero indicates a positive number and a logic one indicates a negative number. Zero Flag (FLAGS.6, Z) For arithmetic and logic operations, the Z flag is set to "1" if the result of the operation is zero. For operations that test register bits, and for shift and rotate operations, the Z flag is set to "1" if the result is logic zero. Carry Flag (FLAGS.7, C) The C flag is set to "1" if the result from an arithmetic operation generates a carry-out from or a borrow to the bit 7 position (MSB). After rotate and shift operations, it contains the last value shifted out of the specified register. Program instructions can set, clear, or complement the carry flag.
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INSTRUCTION SET NOTATION Table 6-2. Flag Notation Conventions Flag C Z S V 0 1 * - x Carry flag Zero flag Sign flag Overflow flag Cleared to logic zero Set to logic one Set or cleared according to operation Value is unaffected Value is undefined Description
Table 6-3. Instruction Set Symbols Symbol dst src @ PC FLAGS # H D B opc Source operand Indirect register address prefix Program counter Flags register (D5H) Immediate operand or register address prefix Hexadecimal number suffix Decimal number suffix Binary number suffix Opcode Description Destination operand
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Table 6-4. Instruction Notation Conventions Notation cc r rr R RR Condition code Working register only Working register pair Register or working register Register pair or working register pair Description Actual Operand Range See list of condition codes in Table 6-6. Rn (n = 0-15) RRp (p = 0, 2, 4, ..., 14) reg or Rn (reg = 0-255, n = 0-15) reg or RRp (reg = 0-254, even number only, where p = 0, 2, ..., 14) @Rn (n = 0-15)
Ir IR Irr IRR
Indirect working register only
Indirect register or indirect working register @Rn or @reg (reg = 0-255, n = 0-15) Indirect working register pair only Indirect register pair or indirect working register pair Indexed addressing mode Indexed (short offset) addressing mode @RRp (p = 0, 2, ..., 14) @RRp or @reg (reg = 0-254, even only, where p = 0, 2, ..., 14) #reg[Rn] (reg = 0-255, n = 0-15) #addr[RRp] (addr = range - 128 to + 127, where p = 0, 2, ..., 14) #addr [RRp] (addr = range 0-8191, where p = 0, 2, ..., 14) addr (addr = range 0-8191) addr (addr = number in the range + 127 to - 128 that is an offset relative to the address of the next instruction) #data (data = 0-255)
X XS
XL
Indexed (long offset) addressing mode
DA RA
Direct addressing mode Relative addressing mode
IM
Immediate addressing mode
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Table 6-5. Opcode Quick Reference OPCODE MAP LOWER NIBBLE (HEX) - U P P E R 0 1 2 3 4 5 N I B B L E 6 7 8 9 A B C H E X D E F CLR R1 RRC R1 SRA R1 RR R1 CLR IR1 RRC IR1 SRA IR1 RR IR1 LDCD r1,Irr2 RL R1 RL IR1 CP r1,r2 XOR r1,r2 CP r1,Ir2 XOR r1,Ir2 LDC r1,Irr2 LDC r2,Irr1 LDCI r1,Irr2 LD R2,R1 CALL IRR1 LD R2,IR1 LD IR2,R1 LD IR1,IM LD R1,IM CALL DA1 CP R2,R1 XOR R2,R1 CP IR2,R1 XOR IR2,R1 CP R1,IM XOR R1,IM POP R1 COM R1 PUSH R2 POP IR1 COM IR1 PUSH IR2 0 DEC R1 RLC R1 INC R1 JP IRR1 1 DEC IR1 RLC IR1 INC IR1 2 ADD r1,r2 ADC r1,r2 SUB r1,r2 SBC r1,r2 OR r1,r2 AND r1,r2 TCM r1,r2 TM r1,r2 3 ADD r1,Ir2 ADC r1,Ir2 SUB r1,Ir2 SBC r1,Ir2 OR r1,Ir2 AND r1,Ir2 TCM r1,Ir2 TM r1,Ir2 4 ADD R2,R1 ADC R2,R1 SUB R2,R1 SBC R2,R1 OR R2,R1 AND R2,R1 TCM R2,R1 TM R2,R1 5 ADD IR2,R1 ADC IR2,R1 SUB IR2,R1 SBC IR2,R1 OR IR2,R1 AND IR2,R1 TCM IR2,R1 TM IR2,R1 6 ADD R1,IM ADC R1,IM SUB R1,IM SBC R1,IM OR R1,IM AND R1,IM TCM R1,IM TM R1,IM LD r1, x, r2 LD r2, x, r1 LDC r1, Irr2, xL LDC r2, Irr2, xL LD r1, Ir2 LD Ir1, r2 LDC r1, Irr2, xs LDC r2, Irr1, xs 7
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Table 6-5. Opcode Quick Reference (Continued) OPCODE MAP LOWER NIBBLE (HEX) - U P 0 1 8 LD r1,R2 9 LD r2,R1 A B JR cc,RA C LD r1,IM D JP cc,DA E INC r1 F

P E R
2 3 4 5
N I B B L E
6 7 8 9 A B C
IDLE

STOP DI EI RET IRET RCF
H E X
D E F

SCF CCF
LD r1,R2
LD r2,R1
JR cc,RA
LD r1,IM
JP cc,DA
INC r1
NOP
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CONDITION CODES The opcode of a conditional jump always contains a 4-bit field called the condition code (cc). This specifies under which conditions it is to execute the jump. For example, a conditional jump with the condition code for "equal" after a compare operation only jumps if the two operands are equal. Condition codes are listed in Table 6-6. The carry (C), zero (Z), sign (S), and overflow (V) flags are used to control the operation of conditional jump instructions. Table 6-6. Condition Codes Binary 0000 1000 0111 (1) 1111 (1) 0110 (1) 1110 (1) 1101 0101 0100 1100 0110 (1) 1110 (1) 1001 0001 1010 0010 1111 (1) 0111 (1) 1011 0011 Mnemonic F T C NC Z NZ PL MI OV NOV EQ NE GE LT GT LE UGE ULT UGT ULE Description Always false Always true Carry No carry Zero Not zero Plus Minus Overflow No overflow Equal Not equal Greater than or equal Less than Greater than Less than or equal Unsigned greater than or equal Unsigned less than Unsigned greater than Unsigned less than or equal C=1 C=0 Z=1 Z=0 S=0 S=1 V=1 V=0 Z=1 Z=0 (S XOR V) = 0 (S XOR V) = 1 (Z OR (S XOR V)) = 0 (Z OR (S XOR V)) = 1 C=0 C=1 (C = 0 AND Z = 0) = 1 (C OR Z) = 1 Flags Set - -
NOTES: 1. It indicates condition codes that are related to two different mnemonics but which test the same flag. For example, Z and EQ are both true if the zero flag (Z) is set, but after an ADD instruction, Z would probably be used; after a CP instruction, however, EQ would probably be used. 2. For operations involving unsigned numbers, the special condition codes UGE, ULT, UGT, and ULE must be used.
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INSTRUCTION DESCRIPTIONS This section contains detailed information and programming examples for each instruction in the SAM87RI instruction set. Information is arranged in a consistent format for improved readability and for fast referencing. The following information is included in each instruction description: -- Instruction name (mnemonic) -- Full instruction name -- Source/destination format of the instruction operand -- Shorthand notation of the instruction's operation -- Textual description of the instruction's effect -- Specific flag settings affected by the instruction -- Detailed description of the instruction's format, execution time, and addressing mode(s) -- Programming example(s) explaining how to use the instruction
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SAM88RCRI INSTRUCTION SET
ADC -- Add with Carry
ADC Operation: dst,src dst dst + src + c The source operand, along with the setting of the carry flag, is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's-complement addition is performed. In multiple precision arithmetic, this instruction permits the carry from the addition of low-order operands to be carried into the addition of high-order operands. Flags: C: Z: S: V: Set if there is a carry from the most significant bit of the result; cleared otherwise. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurs, that is, if both operands are of the same sign and the result is of the opposite sign; cleared otherwise.
Format: Bytes opc dst | src 2 Cycles 4 6 opc src dst 3 6 6 opc dst src 3 6 Opcode (Hex) 12 13 14 15 16 Addr Mode dst src r r R R R r lr R IR IM
Examples:
Given: R1 = 10H, R2 = 03H, C flag = "1", register 01H = 20H, register 02H = 03H, and register 03H = 0AH: ADC ADC ADC ADC ADC R1,R2 R1,@R2 01H,02H 01H,@02H 01H,#11H R1 = 14H, R2 = 03H R1 = 1BH, R2 = 03H Register 01H = 24H, register 02H = 03H Register 01H = 2BH, register 02H = 03H Register 01H = 32H
In the first example, destination register R1 contains the value 10H, the carry flag is set to "1", and the source working register R2 contains the value 03H. The statement "ADC R1,R2" adds 03H and the carry flag value ("1") to the destination value 10H, leaving 14H in register R1.
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ADD -- Add
ADD Operation: dst,src dst dst + src The source operand is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's-complement addition is performed. Flags: C: Z: S: V: Set if there is a carry from the most significant bit of the result; cleared otherwise. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurred, that is, if both operands are of the same sign and the result is of the opposite sign; cleared otherwise.
Format: Bytes opc dst | src 2 Cycles 4 6 opc src dst 3 6 6 opc dst src 3 6 Opcode (Hex) 02 03 04 05 06 Addr Mode dst src r r R R R r lr R IR IM
Examples:
Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH: ADD ADD ADD ADD ADD R1,R2 R1,@R2 01H,02H 01H,@02H 01H,#25H R1 = 15H, R2 = 03H R1 = 1CH, R2 = 03H Register 01H = 24H, register 02H = 03H Register 01H = 2BH, register 02H = 03H Register 01H = 46H
In the first example, destination working register R1 contains 12H and the source working register R2 contains 03H. The statement "ADD R1,R2" adds 03H to 12H, leaving the value 15H in register R1.
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SAM88RCRI INSTRUCTION SET
AND -- Logical AND
AND Operation: dst,src dst dst AND src The source operand is logically ANDed with the destination operand. The result is stored in the destination. The AND operation results in a "1" bit being stored whenever the corresponding bits in the two operands are both logic ones; otherwise a "0" bit value is stored. The contents of the source are unaffected. Flags: C: Z: S: V: Format: Bytes opc dst | src 2 Cycles 4 6 opc src dst 3 6 6 opc dst src 3 6 Opcode (Hex) 52 53 54 55 56 Addr Mode dst src r r R R R r lr R IR IM Unaffected. Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Always cleared to "0".
Examples:
Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH: AND AND AND AND AND R1,R2 R1,@R2 01H,02H 01H,@02H 01H,#25H R1 = 02H, R2 = 03H R1 = 02H, R2 = 03H Register 01H = 01H, register 02H = 03H Register 01H = 00H, register 02H = 03H Register 01H = 21H
In the first example, destination working register R1 contains the value 12H and the source working register R2 contains 03H. The statement "AND R1,R2" logically ANDs the source operand 03H with the destination operand value 12H, leaving the value 02H in register R1.
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SAM88RCRI INSTRUCTION SET
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CALL -- Call Procedure
CALL Operation: dst SP @SP SP @SP PC SP - 1 PCL SP -1 PCH dst
The current contents of the program counter are pushed onto the top of the stack. The program counter value used is the address of the first instruction following the CALL instruction. The specified destination address is then loaded into the program counter and points to the first instruction of a procedure. At the end of the procedure the return instruction (RET) can be used to return to the original program flow. RET pops the top of the stack back into the program counter. Flags: Format: Bytes opc opc dst dst 3 2 Cycles 14 12 Opcode (Hex) F6 F4 Addr Mode dst DA IRR No flags are affected.
Examples:
Given: R0 = 15H, R1 = 21H, PC = 1A47H, and SP = 0B2H: CALL 1521H SP = 0B0H (Memory locations 00H = 1AH, 01H = 4AH, where 4AH is the address that follows the instruction.) SP = 0B0H (00H = 1AH, 01H = 49H)
CALL
@RR0
In the first example, if the program counter value is 1A47H and the stack pointer contains the value 0B2H, the statement "CALL 1521H" pushes the current PC value onto the top of the stack. The stack pointer now points to memory location 00H. The PC is then loaded with the value 1521H, the address of the first instruction in the program sequence to be executed. If the contents of the program counter and stack pointer are the same as in the first example, the statement "CALL @RR0" produces the same result except that the 49H is stored in stack location 01H (because the two-byte instruction format was used). The PC is then loaded with the value 1521H, the address of the first instruction in the program sequence to be executed.
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SAM88RCRI INSTRUCTION SET
CCF -- Complement Carry Flag
CCF Operation: C NOT C The carry flag (C) is complemented. If C = "1", the value of the carry flag is changed to logic zero; if C = "0", the value of the carry flag is changed to logic one. Flags: C: Complemented. No other flags are affected.
Format: Bytes opc 1 Cycles 4 Opcode (Hex) EF
Example:
Given: The carry flag = "0": CCF If the carry flag = "0", the CCF instruction complements it in the FLAGS register (0D5H), changing its value from logic zero to logic one.
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CLR -- Clear
CLR Operation: dst dst "0" The destination location is cleared to "0". Flags: Format: Bytes opc dst 2 Cycles 4 4 Opcode (Hex) B0 B1 Addr Mode dst R IR No flags are affected.
Examples:
Given: Register 00H = 4FH, register 01H = 02H, and register 02H = 5EH: CLR CLR 00H @01H Register 00H = 00H Register 01H = 02H, register 02H = 00H
In Register (R) addressing mode, the statement "CLR 00H" clears the destination register 00H value to 00H. In the second example, the statement "CLR @01H" uses Indirect Register (IR) addressing mode to clear the 02H register value to 00H.
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SAM88RCRI INSTRUCTION SET
COM -- Complement
COM Operation: dst dst NOT dst The contents of the destination location are complemented (one's complement); all "1s" are changed to "0s", and vice-versa. Flags: C: Z: S: V: Format: Bytes opc dst 2 Cycles 4 4 Opcode (Hex) 60 61 Addr Mode dst R IR Unaffected. Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Always reset to "0".
Examples:
Given: R1 = 07H and register 07H = 0F1H: COM COM R1 @R1 R1 = 0F8H R1 = 07H, register 07H = 0EH
In the first example, destination working register R1 contains the value 07H (00000111B). The statement "COM R1" complements all the bits in R1: all logic ones are changed to logic zeros, and vice-versa, leaving the value 0F8H (11111000B). In the second example, Indirect Register (IR) addressing mode is used to complement the value of destination register 07H (11110001B), leaving the new value 0EH (00001110B).
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CP -- Compare
CP Operation: dst,src dst - src The source operand is compared to (subtracted from) the destination operand, and the appropriate flags are set accordingly. The contents of both operands are unaffected by the comparison. Flags: C: Z: S: V: Set if a "borrow" occurred (src > dst); cleared otherwise. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurred, that is, if the operands were of opposite signs and the sign of the result is of the same as the sign of the source operand; cleared otherwise.
Format: Bytes opc dst | src 2 Cycles 4 6 opc src dst 3 6 6 opc dst src 3 6 Opcode (Hex) A2 A3 A4 A5 A6 Addr Mode dst src r r R R R r lr R IR IM
Examples:
1. Given: R1 = 02H and R2 = 03H: CP R1,R2 Set the C and S flags
Destination working register R1 contains the value 02H and source register R2 contains the value 03H. The statement "CP R1,R2" subtracts the R2 value (source/subtrahend) from the R1 value (destination/minuend). Because a "borrow" occurs and the difference is negative, C and S are "1". 2. Given: R1 = 05H and R2 = 0AH: CP JP INC LD R1,R2 UGE,SKIP R1 R3,R1
SKIP
In this example, destination working register R1 contains the value 05H which is less than the contents of the source working register R2 (0AH). The statement "CP R1,R2" generates C = "1" and the JP instruction does not jump to the SKIP location. After the statement "LD R3,R1" executes, the value 06H remains in working register R3.
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SAM88RCRI INSTRUCTION SET
DEC -- Decrement
DEC Operation: dst dst dst - 1 The contents of the destination operand are decremented by one. Flags: C: Z: S: V: Unaffected. Set if the result is "0"; cleared otherwise. Set if result is negative; cleared otherwise. Set if arithmetic overflow occurred, that is, dst value is - 128 (80H) and result value is + 127 (7FH); cleared otherwise.
Format: Bytes opc dst 2 Cycles 4 4 Opcode (Hex) 00 01 Addr Mode dst R IR
Examples:
Given: R1 = 03H and register 03H = 10H: DEC DEC R1 @R1 R1 = 02H Register 03H = 0FH
In the first example, if working register R1 contains the value 03H, the statement "DEC R1" decrements the hexadecimal value by one, leaving the value 02H. In the second example, the statement "DEC @R1" decrements the value 10H contained in the destination register 03H by one, leaving the value 0FH.
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DI -- Disable Interrupts
DI Operation: SYM (2) 0 Bit zero of the system mode register, SYM.2, is cleared to "0", globally disabling all interrupt processing. Interrupt requests will continue to set their respective interrupt pending bits, but the CPU will not service them while interrupt processing is disabled. Flags: Format: Bytes opc 1 Cycles 4 Opcode (Hex) 8F No flags are affected.
Example:
Given: SYM = 04H: DI If the value of the SYM register is 04H, the statement "DI" leaves the new value 00H in the register and clears SYM.2 to "0", disabling interrupt processing.
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SAM88RCRI INSTRUCTION SET
EI -- Enable Interrupts
EI Operation: SYM (2) 1 An EI instruction sets bit 2 of the system mode register, SYM.2 to "1". This allows interrupts to be serviced as they occur. If an interrupt's pending bit was set while interrupt processing was disabled (by executing a DI instruction), it will be serviced when you execute the EI instruction. Flags: Format: Bytes opc 1 Cycles 4 Opcode (Hex) 9F No flags are affected.
Example:
Given: SYM = 00H: EI If the SYM register contains the value 00H, that is, if interrupts are currently disabled, the statement "EI" sets the SYM register to 04H, enabling all interrupts. (SYM.2 is the enable bit for global interrupt processing.)
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IDLE -- Idle Operation
IDLE Operation: The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue. Idle mode can be released by an interrupt request (IRQ) or an external reset operation. Flags: Format: Bytes opc 1 Cycles 4 Opcode (Hex) 6F Addr Mode dst src - - No flags are affected.
Example:
The instruction IDLE NOP NOP NOP stops the CPU clock but not the system clock.
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SAM88RCRI INSTRUCTION SET
INC -- Increment
INC Operation: dst dst dst + 1 The contents of the destination operand are incremented by one. Flags: C: Z: S: V: Unaffected. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurred, that is dst value is + 127 (7FH) and result is - 128 (80H); cleared otherwise.
Format: Bytes dst | opc 1 Cycles 4 Opcode (Hex) rE r = 0 to F opc dst 2 4 4 20 21 R IR Addr Mode dst r
Examples:
Given: R0 = 1BH, register 00H = 0CH, and register 1BH = 0FH: INC INC INC R0 00H @R0 R0 = 1CH Register 00H = 0DH R0 = 1BH, register 01H = 10H
In the first example, if destination working register R0 contains the value 1BH, the statement "INC R0" leaves the value 1CH in that same register. The next example shows the effect an INC instruction has on register 00H, assuming that it contains the value 0CH. In the third example, INC is used in Indirect Register (IR) addressing mode to increment the value of register 1BH from 0FH to 10H.
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IRET -- Interrupt Return
IRET Operation: IRET FLAGS @SP SP SP + 1 PC @SP SP SP + 2 SYM(2) 1 This instruction is used at the end of an interrupt service routine. It restores the flag register and the program counter. It also re-enables global interrupts. Flags: Format: IRET (Normal) opc Bytes 1 Cycles 10 12 Opcode (Hex) BF All flags are restored to their original settings (that is, the settings before the interrupt occurred).
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SAM88RCRI INSTRUCTION SET
JP -- Jump
JP JP Operation: cc,dst dst (Conditional) (Unconditional)
If cc is true, PC dst The conditional JUMP instruction transfers program control to the destination address if the condition specified by the condition code (cc) is true; otherwise, the instruction following the JP instruction is executed. The unconditional JP simply replaces the contents of the PC with the contents of the specified register pair. Control then passes to the statement addressed by the PC.
Flags: Format: (1)
No flags are affected.
Bytes
(2)
Cycles 8
Opcode (Hex) ccD cc = 0 to F
Addr Mode dst DA
cc | opc
dst
3
opc
dst
2
8
30
IRR
NOTES: 1. The 3-byte format is used for a conditional jump and the 2-byte format for an unconditional jump. 2. In the first byte of the three-byte instruction format (conditional jump), the condition code and the op code are both four bits.
Examples:
Given: The carry flag (C) = "1", register 00 = 01H, and register 01 = 20H: JP JP C,LABEL_W @00H LABEL_W = 1000H, PC = 1000H PC = 0120H
The first example shows a conditional JP. Assuming that the carry flag is set to "1", the statement "JP C,LABEL_W" replaces the contents of the PC with the value 1000H and transfers control to that location. Had the carry flag not been set, control would then have passed to the statement immediately following the JP instruction. The second example shows an unconditional JP. The statement "JP @00" replaces the contents of the PC with the contents of the register pair 00H and 01H, leaving the value 0120H.
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JR -- Jump Relative
JR Operation: cc,dst If cc is true, PC PC + dst If the condition specified by the condition code (cc) is true, the relative address is added to the program counter and control passes to the statement whose address is now in the program counter; otherwise, the instruction following the JR instruction is executed (See list of condition codes). The range of the relative address is + 127, - 128, and the original value of the program counter is taken to be the address of the first instruction byte following the JR statement. Flags: Format: Bytes
(note)
No flags are affected.
Cycles 6
Opcode (Hex) ccB cc = 0 to F
Addr Mode dst RA
cc | opc
dst
2
NOTE: In the first byte of the two-byte instruction format, the condition code and the op code are each four bits.
Example:
Given: The carry flag = "1" and LABEL_X = 1FF7H: JR C,LABEL_X PC = 1FF7H
If the carry flag is set (that is, if the condition code is true), the statement "JR C,LABEL_X" will pass control to the statement whose address is now in the PC. Otherwise, the program instruction following the JR would be executed.
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SAM88RCRI INSTRUCTION SET
LD -- Load
LD Operation: dst,src dst src The contents of the source are loaded into the destination. The source's contents are unaffected. Flags: Format: Bytes dst | opc src 2 Cycles 4 4 Opcode (Hex) rC r8 Addr Mode dst src r r IM R No flags are affected.
src | opc
dst
2
4
r9 r = 0 to F
R
r
opc
dst | src
2
4 4
C7 D7
r Ir
lr r
opc
src
dst
3
6 6
E4 E5
R R
R IR
opc
dst
src
3
6 6
E6 D6
R IR
IM IM
opc
src
dst
3
6
F5
IR
R
opc
dst | src
x
3
6
87
r
x [r]
opc
src | dst
x
3
6
97
x [r]
r
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LD -- Load
LD Examples: (Continued) Given: R0 = 01H, R1 = 0AH, register 00H = 01H, register 01H = 20H, register 02H = 02H, LOOP = 30H, and register 3AH = 0FFH: LD LD LD LD LD LD LD LD LD LD LD LD R0,#10H R0,01H 01H,R0 R1,@R0 @R0,R1 00H,01H 02H,@00H 00H,#0AH @00H,#10H @00H,02H R0,#LOOP[R1] #LOOP[R0],R1 R0 = 10H R0 = 20H, register 01H = 20H Register 01H = 01H, R0 = 01H R1 = 20H, R0 = 01H R0 = 01H, R1 = 0AH, register 01H = 0AH Register 00H = 20H, register 01H = 20H Register 02H = 20H, register 00H = 01H Register 00H = 0AH Register 00H = 01H, register 01H = 10H Register 00H = 01H, register 01H = 02, register 02H = 02H R0 = 0FFH, R1 = 0AH Register 31H = 0AH, R0 = 01H, R1 = 0AH
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SAM88RCRI INSTRUCTION SET
LDC/LDE -- Load Memory
LDC/LDE Operation: dst,src dst src This instruction loads a byte from program or data memory into a working register or vice-versa. The source values are unaffected. LDC refers to program memory and LDE to data memory. The assembler makes "Irr" or "rr" values an even number for program memory and odd an odd number for data memory. Flags: Format: Bytes 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. opc opc opc opc opc opc opc opc opc opc
dst | src 2
No flags are affected.
Cycles
10
Opcode (Hex)
C3
Addr Mode dst src
r Irr
src | dst
2
10
D3
Irr
r
dst | src
XS XS XLL XLL DAL DAL DAL DAL XLH XLH DAH DAH DAH DAH
3
12
E7
r
XS [rr]
src | dst
3
12
F7
XS [rr]
r
dst | src
4
14
A7
r
XL [rr]
src | dst
4
14
B7
XL [rr]
r
dst | 0000
4
14
A7
r
DA
src | 0000
4
14
B7
DA
r
dst | 0001
4
14
A7
r
DA
src | 0001
4
14
B7
DA
r
NOTES: 1. The source (src) or working register pair [rr] for formats 5 and 6 cannot use register pair 0-1. 2. For formats 3 and 4, the destination address "XS [rr]" and the source address "XS [rr]" are each one byte. 3. For formats 5 and 6, the destination address "XL [rr]" and the source address "XL [rr]" are each two bytes. 4. The DA and r source values for formats 7 and 8 are used to address program memory; the second set of values, used in formats 9 and 10, are used to address data memory.
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LDC/LDE -- Load Memory
LDC/LDE Examples: (Continued) Given: R0 = 11H, R1 = 34H, R2 = 01H, R3 = 04H, R4 = 00H, R5 = 60H; Program memory locations 0061 = AAH, 0103H = 4FH, 0104H = 1A, 0105H = 6DH, and 1104H = 88H. External data memory locations 0061H = BBH, 0103H = 5FH, 0104H = 2AH, 0105H = 7DH, and 1104H = 98H: LDC LDE R0,@RR2 R0,@RR2 ; R0 contents of program memory location 0104H ; R0 = 1AH, R2 = 01H, R3 = 04H ; R0 contents of external data memory location 0104H ; R0 = 2AH, R2 = 01H, R3 = 04H ; 11H (contents of R0) is loaded into program memory ; location 0104H (RR2), ; working registers R0, R2, R3 no change ; 11H (contents of R0) is loaded into external data memory ; location 0104H (RR2), ; working registers R0, R2, R3 no change ; R0 contents of program memory location 0061H ; (01H + RR4), ; R0 = AAH, R2 = 00H, R3 = 60H ; R0 contents of external data memory location 0061H ; (01H + RR4), R0 = BBH, R4 = 00H, R5 = 60H ; 11H (contents of R0) is loaded into program memory location ; 0061H (01H + 0060H) ; 11H (contents of R0) is loaded into external data memory ; location 0061H (01H + 0060H)
LDC (note) @RR2,R0
LDE
@RR2,R0
LDC
R0,#01H[RR4]
LDE
R0,#01H[RR4]
LDC (note) #01H[RR4],R0 LDE LDC LDE LDC LDE #01H[RR4],R0
R0,#1000H[RR2] ; R0 contents of program memory location 1104H ; (1000H + 0104H), R0 = 88H, R2 = 01H, R3 = 04H R0,#1000H[RR2] ; R0 contents of external data memory location 1104H ; (1000H + 0104H), R0 = 98H, R2 = 01H, R3 = 04H R0,1104H R0,1104H ; R0 contents of program memory location 1104H, R0 = 88H ; R0 contents of external data memory location 1104H, ; R0 = 98H ; 11H (contents of R0) is loaded into program memory location ; 1105H, (1105H) 11H ; 11H (contents of R0) is loaded into external data memory ; location 1105H, (1105H) 11H
LDC (note) 1105H,R0 LDE 1105H,R0
NOTE: These instructions are not supported by masked ROM type devices.
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SAM88RCRI INSTRUCTION SET
LDCD/LDED -- Load Memory and Decrement
LDCD/LDED Operation: dst,src dst src rr rr - 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair. The contents of the source location are loaded into the destination location. The memory address is then decremented. The contents of the source are unaffected. LDCD references program memory and LDED references external data memory. The assembler makes "Irr" an even number for program memory and an odd number for data memory. Flags: Format: Bytes opc dst | src 2 Cycles 10 Opcode (Hex) E2 Addr Mode dst src r Irr No flags are affected.
Examples:
Given: R6 = 10H, R7 = 33H, R8 = 12H, program memory location 1033H = 0CDH, and external data memory location 1033H = 0DDH: LDCD R8,@RR6 ; 0CDH (contents of program memory location 1033H) is loaded ; into R8 and RR6 is decremented by one ; R8 = 0CDH, R6 = 10H, R7 = 32H (RR6 RR6 - 1) ; 0DDH (contents of data memory location 1033H) is loaded ; into R8 and RR6 is decremented by one (RR6 RR6 - 1) ; R8 = 0DDH, R6 = 10H, R7 = 32H
LDED
R8,@RR6
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LDCI/LDEI -- Load Memory and Increment
LDCI/LDEI Operation: dst,src dst src rr rr + 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair. The contents of the source location are loaded into the destination location. The memory address is then incremented automatically. The contents of the source are unaffected. LDCI refers to program memory and LDEI refers to external data memory. The assembler makes "Irr" even for program memory and odd for data memory. Flags: Format: Bytes opc dst | src 2 Cycles 10 Opcode (Hex) E3 Addr Mode dst src r Irr No flags are affected.
Examples:
Given: R6 = 10H, R7 = 33H, R8 = 12H, program memory locations 1033H = 0CDH and 1034H = 0C5H; external data memory locations 1033H = 0DDH and 1034H = 0D5H: LDCI R8,@RR6 ; 0CDH (contents of program memory location 1033H) is loaded ; into R8 and RR6 is incremented by one (RR6 RR6 + 1) ; R8 = 0CDH, R6 = 10H, R7 = 34H ; 0DDH (contents of data memory location 1033H) is loaded ; into R8 and RR6 is incremented by one (RR6 RR6 + 1) ; R8 = 0DDH, R6 = 10H, R7 = 34H
LDEI
R8,@RR6
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SAM88RCRI INSTRUCTION SET
NOP -- No Operation
NOP Operation: No action is performed when the CPU executes this instruction. Typically, one or more NOPs are executed in sequence in order to effect a timing delay of variable duration. No flags are affected.
Flags: Format:
Bytes opc 1
Cycles 4
Opcode (Hex) FF
Example:
When the instruction NOP is encountered in a program, no operation occurs. Instead, there is a delay in instruction execution time.
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OR -- Logical OR
OR Operation: dst,src dst dst OR src The source operand is logically ORed with the destination operand and the result is stored in the destination. The contents of the source are unaffected. The OR operation results in a "1" being stored whenever either of the corresponding bits in the two operands is a "1"; otherwise a "0" is stored. Flags: C: Z: S: V: Format: Bytes opc dst | src 2 Cycles 4 6 opc src dst 3 6 6 opc dst src 3 6 Opcode (Hex) 42 43 44 45 46 Addr Mode dst src r r R R R r lr R IR IM Unaffected. Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Always cleared to "0".
Examples:
Given: R0 = 15H, R1 = 2AH, R2 = 01H, register 00H = 08H, register 01H = 37H, and register 08H = 8AH: OR OR OR OR OR R0,R1 R0,@R2 00H,01H 01H,@00H 00H,#02H R0 = 3FH, R1 = 2AH R0 = 37H, R2 = 01H, register 01H = 37H Register 00H = 3FH, register 01H = 37H Register 00H = 08H, register 01H = 0BFH Register 00H = 0AH
In the first example, if working register R0 contains the value 15H and register R1 the value 2AH, the statement "OR R0,R1" logical-ORs the R0 and R1 register contents and stores the result (3FH) in destination register R0. The other examples show the use of the logical OR instruction with the various addressing modes and formats.
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SAM88RCRI INSTRUCTION SET
POP -- Pop From Stack
POP Operation: dst dst @SP SP SP + 1 The contents of the location addressed by the stack pointer are loaded into the destination. The stack pointer is then incremented by one. Flags: Format: Bytes opc dst 2 Cycles 8 8 Opcode (Hex) 50 51 Addr Mode dst R IR No flags affected.
Examples:
Given: Register 00H = 01H, register 01H = 1BH, SP (0D9H) = 0BBH, and stack register 0BBH = 55H: POP POP 00H @00H Register 00H = 55H, SP = 0BCH Register 00H = 01H, register 01H = 55H, SP = 0BCH
In the first example, general register 00H contains the value 01H. The statement "POP 00H" loads the contents of location 0BBH (55H) into destination register 00H and then increments the stack pointer by one. Register 00H then contains the value 55H and the SP points to location 0BCH.
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PUSH -- Push To Stack
PUSH Operation: src SP SP - 1 @SP src A PUSH instruction decrements the stack pointer value and loads the contents of the source (src) into the location addressed by the decremented stack pointer. The operation then adds the new value to the top of the stack. Flags: Format: Bytes opc src 2 Cycles 8 8 Opcode (Hex) 70 71 Addr Mode dst R IR No flags are affected.
Examples:
Given: Register 40H = 4FH, register 4FH = 0AAH, SP = 0C0H: PUSH PUSH 40H @40H Register 40H = 4FH, stack register 0BFH = 4FH, SP = 0BFH Register 40H = 4FH, register 4FH = 0AAH, stack register 0BFH = 0AAH, SP = 0BFH
In the first example, if the stack pointer contains the value 0C0H, and general register 40H the value 4FH, the statement "PUSH 40H" decrements the stack pointer from 0C0 to 0BFH. It then loads the contents of register 40H into location 0BFH. Register 0BFH then contains the value 4FH and SP points to location 0BFH.
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SAM88RCRI INSTRUCTION SET
RCF -- Reset Carry Flag
RCF Operation: RCF C0 The carry flag is cleared to logic zero, regardless of its previous value. Flags: C: Cleared to "0". No other flags are affected. Format: Bytes opc 1 Cycles 4 Opcode (Hex) CF
Example:
Given: C = "1" or "0": The instruction RCF clears the carry flag (C) to logic zero.
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RET -- Return
RET Operation: PC @SP SP SP + 2 The RET instruction is normally used to return to the previously executing procedure at the end of a procedure entered by a CALL instruction. The contents of the location addressed by the stack pointer are popped into the program counter. The next statement that is executed is the one that is addressed by the new program counter value. Flags: Format: Bytes opc 1 Cycles 8 10 Opcode (Hex) AF No flags are affected.
Example:
Given: SP = 0BCH, (SP) = 101AH, and PC = 1234: RET PC = 101AH, SP = 0BEH
The statement "RET" pops the contents of stack pointer location 0BCH (10H) into the high byte of the program counter. The stack pointer then pops the value in location 0BDH (1AH) into the PC's low byte and the instruction at location 101AH is executed. The stack pointer now points to memory location 0BEH.
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SAM88RCRI INSTRUCTION SET
RL -- Rotate Left
RL Operation: dst C dst (7) dst (0) dst (7) dst (n + 1) dst (n), n = 0-6 The contents of the destination operand are rotated left one bit position. The initial value of bit 7 is moved to the bit zero (LSB) position and also replaces the carry flag.
7 C
0
Flags:
C: Z: S: V:
Set if the bit rotated from the most significant bit position (bit 7) was "1". Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise.
Format: Bytes opc dst 2 Cycles 4 4 Opcode (Hex) 90 91 Addr Mode dst R IR
Examples:
Given: Register 00H = 0AAH, register 01H = 02H and register 02H = 17H: RL RL 00H @01H Register 00H = 55H, C = "1" Register 01H = 02H, register 02H = 2EH, C = "0"
In the first example, if general register 00H contains the value 0AAH (10101010B), the statement "RL 00H" rotates the 0AAH value left one bit position, leaving the new value 55H (01010101B) and setting the carry and overflow flags.
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RLC -- Rotate Left Through Carry
RLC Operation: dst dst (0) C C dst (7) dst (n + 1) dst (n), n = 0-6 The contents of the destination operand with the carry flag are rotated left one bit position. The initial value of bit 7 replaces the carry flag (C); the initial value of the carry flag replaces bit zero.
7 C
0
Flags:
C: Z: S: V:
Set if the bit rotated from the most significant bit position (bit 7) was "1". Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise.
Format: Bytes opc dst 2 Cycles 4 4 Opcode (Hex) 10 11 Addr Mode dst R IR
Examples:
Given: Register 00H = 0AAH, register 01H = 02H, and register 02H = 17H, C = "0": RLC RLC 00H @01H Register 00H = 54H, C = "1" Register 01H = 02H, register 02H = 2EH, C = "0"
In the first example, if general register 00H has the value 0AAH (10101010B), the statement "RLC 00H" rotates 0AAH one bit position to the left. The initial value of bit 7 sets the carry flag and the initial value of the C flag replaces bit zero of register 00H, leaving the value 55H (01010101B). The MSB of register 00H resets the carry flag to "1" and sets the overflow flag.
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SAM88RCRI INSTRUCTION SET
RR -- Rotate Right
RR Operation: dst C dst (0) dst (7) dst (0) dst (n) dst (n + 1), n = 0-6 The contents of the destination operand are rotated right one bit position. The initial value of bit zero (LSB) is moved to bit 7 (MSB) and also replaces the carry flag (C).
7 C
0
Flags:
C: Z: S: V:
Set if the bit rotated from the least significant bit position (bit zero) was "1". Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise.
Format: Bytes opc dst 2 Cycles 4 4 Opcode (Hex) E0 E1 Addr Mode dst R IR
Examples:
Given: Register 00H = 31H, register 01H = 02H, and register 02H = 17H: RR RR 00H @01H Register 00H = 98H, C = "1" Register 01H = 02H, register 02H = 8BH, C = "1"
In the first example, if general register 00H contains the value 31H (00110001B), the statement "RR 00H" rotates this value one bit position to the right. The initial value of bit zero is moved to bit 7, leaving the new value 98H (10011000B) in the destination register. The initial bit zero also resets the C flag to "1" and the sign flag and overflow flag are also set to "1".
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RRC -- Rotate Right Through Carry
RRC Operation: dst dst (7) C C dst (0) dst (n) dst (n + 1), n = 0-6 The contents of the destination operand and the carry flag are rotated right one bit position. The initial value of bit zero (LSB) replaces the carry flag; the initial value of the carry flag replaces bit 7 (MSB).
7 C
0
Flags:
C: Z: S: V:
Set if the bit rotated from the least significant bit position (bit zero) was "1". Set if the result is "0" cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise.
Format: Bytes opc dst 2 Cycles 4 4 Opcode (Hex) C0 C1 Addr Mode dst R IR
Examples:
Given: Register 00H = 55H, register 01H = 02H, register 02H = 17H, and C = "0": RRC RRC 00H @01H Register 00H = 2AH, C = "1" Register 01H = 02H, register 02H = 0BH, C = "1"
In the first example, if general register 00H contains the value 55H (01010101B), the statement "RRC 00H" rotates this value one bit position to the right. The initial value of bit zero ("1") replaces the carry flag and the initial value of the C flag ("1") replaces bit 7. This leaves the new value 2AH (00101010B) in destination register 00H. The sign flag and overflow flag are both cleared to "0".
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SAM88RCRI INSTRUCTION SET
SBC -- Subtract With Carry
SBC Operation: dst,src dst dst - src - c The source operand, along with the current value of the carry flag, is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. Subtraction is performed by adding the two's-complement of the source operand to the destination operand. In multiple precision arithmetic, this instruction permits the carry ("borrow") from the subtraction of the low-order operands to be subtracted from the subtraction of high-order operands. Flags: C: Z: S: V: Set if a borrow occurred (src > dst); cleared otherwise. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurred, that is, if the operands were of opposite sign and the sign of the result is the same as the sign of the source; cleared otherwise.
Format: Bytes opc dst | src 2 Cycles 4 6 opc src dst 3 6 6 opc dst src 3 6 Opcode (Hex) 32 33 34 35 36 Addr Mode dst src r r R R R r lr R IR IM
Examples:
Given: R1 = 10H, R2 = 03H, C = "1", register 01H = 20H, register 02H = 03H, and register 03H = 0AH: SBC SBC SBC SBC SBC R1,R2 R1,@R2 01H,02H 01H,@02H 01H,#8AH R1 = 0CH, R2 = 03H R1 = 05H, R2 = 03H, register 03H = 0AH Register 01H = 1CH, register 02H = 03H Register 01H = 15H,register 02H = 03H, register 03H = 0AH Register 01H = 95H; C, S, and V = "1"
In the first example, if working register R1 contains the value 10H and register R2 the value 03H, the statement "SBC R1,R2" subtracts the source value (03H) and the C flag value ("1") from the destination (10H) and then stores the result (0CH) in register R1.
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SCF -- Set Carry Flag
SCF Operation: C1 The carry flag (C) is set to logic one, regardless of its previous value. Flags: C: Set to "1". No other flags are affected. Format: Bytes opc 1 Cycles 4 Opcode (Hex) DF
Example:
The statement SCF sets the carry flag to logic one.
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SAM88RCRI INSTRUCTION SET
SRA -- Shift Right Arithmetic
SRA Operation: dst dst (7) dst (7) C dst (0) dst (n) dst (n + 1), n = 0-6 An arithmetic shift-right of one bit position is performed on the destination operand. Bit zero (the LSB) replaces the carry flag. The value of bit 7 (the sign bit) is unchanged and is shifted into bit position 6.
76 C
0
Flags:
C: Z: S: V:
Set if the bit shifted from the LSB position (bit zero) was "1". Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Always cleared to "0".
Format: Bytes opc dst 2 Cycles 4 4 Opcode (Hex) D0 D1 Addr Mode dst R IR
Examples:
Given: Register 00H = 9AH, register 02H = 03H, register 03H = 0BCH, and C = "1": SRA SRA 00H @02H Register 00H = 0CD, C = "0" Register 02H = 03H, register 03H = 0DEH, C = "0"
In the first example, if general register 00H contains the value 9AH (10011010B), the statement "SRA 00H" shifts the bit values in register 00H right one bit position. Bit zero ("0") clears the C flag and bit 7 ("1") is then shifted into the bit 6 position (bit 7 remains unchanged). This leaves the value 0CDH (11001101B) in destination register 00H.
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STOP -- Stop Operation
STOP Operation: The STOP instruction stops the both the CPU clock and system clock and causes the microcontroller to enter Stop mode. During Stop mode, the contents of on-chip CPU registers, peripheral registers, and I/O port control and data registers are retained. Stop mode can be released by an external reset operation or External interrupt input. For the reset operation, the RESET pin must be held to Low level until the required oscillation stabilization interval has elapsed. No flags are affected.
Flags: Format:
Bytes opc 1
Cycles 4
Opcode (Hex) 7F
Addr Mode dst src - -
Example:
The statement LD STOP NOP NOP NOP halts all microcontroller operations. When STOPCON register is not #0A5H value, if you use STOP instruction, PC is changed to reset address. STOPCON, #0A5H
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SAM88RCRI INSTRUCTION SET
SUB -- Subtract
SUB Operation: dst,src dst dst - src The source operand is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. Subtraction is performed by adding the two's complement of the source operand to the destination operand. Flags: C: Z: S: V: Set if a "borrow" occurred; cleared otherwise. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurred, that is, if the operands were of opposite signs and the sign of the result is of the same as the sign of the source operand; cleared otherwise.
Format: Bytes opc dst | src 2 Cycles 4 6 opc src dst 3 6 6 opc dst src 3 6 Opcode (Hex) 22 23 24 25 26 Addr Mode dst src r r R R R r lr R IR IM
Examples:
Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH: SUB SUB SUB SUB SUB SUB R1,R2 R1,@R2 01H,02H 01H,@02H 01H,#90H 01H,#65H R1 = 0FH, R2 = 03H R1 = 08H, R2 = 03H Register 01H = 1EH, register 02H = 03H Register 01H = 17H, register 02H = 03H Register 01H = 91H; C, S, and V = "1" Register 01H = 0BCH; C and S = "1", V = "0"
In the first example, if working register R1 contains the value 12H and if register R2 contains the value 03H, the statement "SUB R1,R2" subtracts the source value (03H) from the destination value (12H) and stores the result (0FH) in destination register R1.
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TCM -- Test Complement Under Mask
TCM Operation: dst,src (NOT dst) AND src This instruction tests selected bits in the destination operand for a logic one value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask). The TCM statement complements the destination operand, which is then ANDed with the source mask. The zero (Z) flag can then be checked to determine the result. The destination and source operands are unaffected. Flags: C: Z: S: V: Format: Bytes opc dst | src 2 Cycles 4 6 opc src dst 3 6 6 opc dst src 3 6 Opcode (Hex) 62 63 64 65 66 Addr Mode dst src r r R R R r lr R IR IM Unaffected. Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Always cleared to "0".
Examples:
Given: R0 = 0C7H, R1 = 02H, R2 = 12H, register 00H = 2BH, register 01H = 02H, and register 02H = 23H: TCM TCM TCM TCM TCM R0,R1 R0,@R1 00H,01H 00H,@01H 00H,#34 R0 = 0C7H, R1 = 02H, Z = "1" R0 = 0C7H, R1 = 02H, register 02H = 23H, Z = "0" Register 00H = 2BH, register 01H = 02H, Z = "1" Register 00H = 2BH, register 01H = 02H, register 02H = 23H, Z = "1" Register 00H = 2BH, Z = "0"
In the first example, if working register R0 contains the value 0C7H (11000111B) and register R1 the value 02H (00000010B), the statement "TCM R0,R1" tests bit one in the destination register for a "1" value. Because the mask value corresponds to the test bit, the Z flag is set to logic one and can be tested to determine the result of the TCM operation.
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SAM88RCRI INSTRUCTION SET
TM -- Test Under Mask
TM Operation: dst,src dst AND src This instruction tests selected bits in the destination operand for a logic zero value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask), which is ANDed with the destination operand. The zero (Z) flag can then be checked to determine the result. The destination and source operands are unaffected. Flags: C: Z: S: V: Format: Bytes opc dst | src 2 Cycles 4 6 opc src dst 3 6 6 opc dst src 3 6 Opcode (Hex) 72 73 74 75 76 Addr Mode dst src r r R R R r lr R IR IM Unaffected. Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Always reset to "0".
Examples:
Given: R0 = 0C7H, R1 = 02H, R2 = 18H, register 00H = 2BH, register 01H = 02H, and register 02H = 23H: TM TM TM TM TM R0,R1 R0,@R1 00H,01H 00H,@01H 00H,#54H R0 = 0C7H, R1 = 02H, Z = "0" R0 = 0C7H, R1 = 02H, register 02H = 23H, Z = "0" Register 00H = 2BH, register 01H = 02H, Z = "0" Register 00H = 2BH, register 01H = 02H, register 02H = 23H, Z = "0" Register 00H = 2BH, Z = "1"
In the first example, if working register R0 contains the value 0C7H (11000111B) and register R1 the value 02H (00000010B), the statement "TM R0,R1" tests bit one in the destination register for a "0" value. Because the mask value does not match the test bit, the Z flag is cleared to logic zero and can be tested to determine the result of the TM operation.
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XOR -- Logical Exclusive OR
XOR Operation: dst,src dst dst XOR src The source operand is logically exclusive-ORed with the destination operand and the result is stored in the destination. The exclusive-OR operation results in a "1" bit being stored whenever the corresponding bits in the operands are different; otherwise, a "0" bit is stored. Flags: C: Z: S: V: Format: Bytes opc dst | src 2 Cycles 4 6 opc src dst 3 6 6 opc dst src 3 6 Opcode (Hex) B2 B3 B4 B5 B6 Addr Mode dst src r r R R R r lr R IR IM Unaffected. Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Always reset to "0".
Examples:
Given: R0 = 0C7H, R1 = 02H, R2 = 18H, register 00H = 2BH, register 01H = 02H, and register 02H = 23H: XOR XOR XOR XOR XOR R0,R1 R0,@R1 00H,01H 00H,@01H 00H,#54H R0 = 0C5H, R1 = 02H R0 = 0E4H, R1 = 02H, register 02H = 23H Register 00H = 29H, register 01H = 02H Register 00H = 08H, register 01H = 02H, register 02H = 23H Register 00H = 7FH
In the first example, if working register R0 contains the value 0C7H and if register R1 contains the value 02H, the statement "XOR R0,R1" logically exclusive-ORs the R1 value with the R0 value and stores the result (0C5H) in the destination register R0.
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CLOCK CIRCUIT
7
OVERVIEW
CLOCK CIRCUIT
By smart option (3FH.1-.0 in ROM), user can select internal RC oscillator or external oscillator. In using internal oscillator, XIN (P1.0), XOUT (P1.1) can be used by normal I/O pins. An internal RC oscillator source provides a typical 3.2 MHz or 0.5 MHz (in VDD = 5 V) depending on smart option. An external RC oscillation source provides a typical 4 MHz clock for S3C9454B/F9454B. An internal capacitor supports the RC oscillator circuit. An external crystal or ceramic oscillation source provides a maximum 10 MHz clock. The XIN and XOUT pins connect the oscillation source to the on-chip clock circuit. Simplified external RC oscillator and crystal/ceramic oscillator circuits are shown in Figures 7-1 and 7-2. When you use external oscillator, P1.0, P1.1 must be set to output port to prevent current consumption
C1
XIN
R
S3C9454B/F9454B
S3C9454B/P9454B
XOUT
C2
XOUT
Figure 7-1. Main Oscillator Circuit (RC Oscillator with Internal Capacitor) MAIN OSCILLATOR LOGIC
Figure 7-2. Main Oscillator Circuit (Crystal/Ceramic Oscillator)
To increase processing speed and to reduce clock noise, non-divided logic is implemented for the main oscillator circuit. For this reason, very high resolution waveforms (square signal edges) must be generated in order for the CPU to efficiently process logic operations.
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CLOCK CIRCUIT
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CLOCK STATUS DURING POWER-DOWN MODES The two power-down modes, Stop mode and Idle mode, affect clock oscillation as follows: -- In Stop mode, the main oscillator "freezes", halting the CPU and peripherals. The contents of the register file and current system register values are retained. Stop mode is released, and the oscillator started, by a reset operation or by an external interrupt with RC-delay noise filter (for S3C9454B/F9454B, INT0-INT1). -- In Idle mode, the internal clock signal is gated off to the CPU, but not to interrupt control and the timer. The current CPU status is preserved, including stack pointer, program counter, and flags. Data in the register file is retained. Idle mode is released by a reset or by an interrupt (external or internally-generated). SYSTEM CLOCK CONTROL REGISTER (CLKCON) The system clock control register, CLKCON, is located in location D4H. It is read/write addressable and has the following functions: -- Oscillator IRQ wake-up function enable/disable (CLKCON.7) -- Oscillator frequency divide-by value: non-divided, 2, 8, or 16 (CLKCON.4 and CLKCON.3) The CLKCON register controls whether or not an external interrupt can be used to trigger a Stop mode release (This is called the "IRQ wake-up" function). The IRQ wake-up enable bit is CLKCON.7. After a reset, the external interrupt oscillator wake-up function is enabled, the main oscillator is activated, and the fOSC/16 (the slowest clock speed) is selected as the CPU clock. If necessary, you can then increase the CPU clock speed to fOSC, fOSC/2 or fOSC/8.
System Clock Control Register (CLKCON) D4H, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Oscillator IRQ wake-up enable bit: 0 = Enable IRQ for main system oscillator wake-up function in power mode. 1 = Disable IRQ for main system oscillator wake-up function in power down mode.
Not used for S3C9454B/F9454B Divide-by selection bits for CPU clock frequency: 00 = fosc/16 01 = fosc/8 10 = fosc/2 11 = fosc (non-divided)
Not used for S3C9454B/F9454B
Figure 7-3. System Clock Control Register (CLKCON)
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CLOCK CIRCUIT
Smart Option (3F.1-0 in ROM)
Stop Instruction CLKCON.4-.3
Internal RC Oscillator (3.2 MHz) Internal RC Oscillator (0.5 MHz) MUX External Crystal/ Ceramic Oscillator External RC Oscillator Oscillator Stop Selected OSC Oscillator Wake-up Noise Filter P2.6/CLO CLKCON.7 P2CONH.6-.4 1/2 1/8 1/16 M U X
CPU Clock
INT Pin NOTE: An external interrupt (with RC-delay noise filter) can be used to release stop mode and "wake-up" the main oscillator. In the S3C9454B/F9454B, the INT0-INT1 external interrupts are of this type.
Figure 7-4. System Clock Circuit Diagram
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NOTES
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RESET and POWER-DOWN
8
OVERVIEW
RESET and POWER-DOWN
SYSTEM RESET
By smart option (3EH.7 in ROM), user can select internal RESET (LVR) or external RESET. In using internal RESET (LVR), nRESET pin (P1.2) can be used by normal I/O pin. The S3C9454B/F9454B can be RESET in four ways: -- by external power-on-reset -- by the external nRESET input pin pulled low -- by the digital watchdog peripheral timing out -- by Low Voltage Reset (LVR) During a external power-on reset, the voltage at VDD is High level and the nRESET pin is forced to Low level. The nRESET signal is input through a Schmitt trigger circuit where it is then synchronized with the CPU clock. This brings the S3C9454B/F9454B into a known operating status. To ensure correct start-up, the user should take care that nRESET signal is not released before the VDD level is sufficient to allow MCU operation at the chosen frequency. The nRESET pin must be held to Low level for a minimum time interval after the power supply comes within tolerance in order to allow time for internal CPU clock oscillation to stabilize. The minimum required oscillation stabilization time for a reset is approximately 6.55 ms (@ 216/fOSC, fOSC = 10 MHz). When a reset occurs during normal operation (with both VDD and nRESET at High level), the signal at the nRESET pin is forced Low and the Reset operation starts. All system and peripheral control registers are then set to their default hardware Reset values (see Table 8-1). The MCU provides a watchdog timer function in order to ensure graceful recovery from software malfunction. If watchdog timer is not refreshed before an end-of-counter condition (overflow) is reached, the internal reset will be activated. The on-chip Low Voltage Reset, features static Reset when supply voltage is below a reference value (Typ. 2.3, 3.0, 3.9 V). Thanks to this feature, external reset circuit can be removed while keeping the application safety. As long as the supply voltage is below the reference value, there is a internal and static RESET. The MCU can start only when the supply voltage rises over the reference value.
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RESET and POWER-DOWN
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NOTE To program the duration of the oscillation stabilization interval, you must make the appropriate settings to the basic timer control register, BTCON, before entering Stop mode. Also, if you do not want to use the basic timer watchdog function (which causes a system reset if a basic timer counter overflow occurs), you can disable it by writing "1010B" to the upper nibble of BTCON. MCU Initialization Sequence The following sequence of events occurs during a Reset operation: -- All interrupts are disabled. -- The watchdog function (basic timer) is enabled. -- Ports 0-2 are set to input mode -- Peripheral control and data registers are disabled and reset to their initial values (see Table 8-1). -- The program counter is loaded with the ROM reset address, 0100H. -- When the programmed oscillation stabilization time interval has elapsed, the address stored in ROM location 0100H (and 0101H) is fetched and executed.
Smart Option (3EH.7)
nRESET MUX LVR nRESET Internal nRESET
Watchdog nRESET
Figure 8-1. Reset Block Diagram
Oscillation Stabilization Wait Time (6.55 ms/at 10 MHz) nRESET Input
Normal Mode or Power-Down Mode RESET Operation
Idle Mode
Operation Mode
Figure 8-2. Timing for S3C9454B/F9454B After RESET
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POWER-DOWN MODES
STOP MODE Stop mode is invoked by the instruction STOP (opcode 7FH). In Stop mode, the operation of the CPU and all peripherals is halted. That is, the on-chip main oscillator stops and the supply current is reduced to less than 5 A except that the LVR(Low Voltage Reset) is enable. All system functions are halted when the clock "freezes", but data stored in the internal register file is retained. Stop mode can be released in one of two ways: by a nRESET signal or by an external interrupt. Using RESET to Release Stop Mode Stop mode is released when the nRESET signal is released and returns to High level. All system and peripheral control registers are then Reset to their default values and the contents of all data registers are retained. A Reset operation automatically selects a slow clock (fOSC/16) because CLKCON.3 and CLKCON.4 are cleared to "00B". After the oscillation stabilization interval has elapsed, the CPU executes the system initialization routine by fetching the 16-bit address stored in ROM locations 0100H and 0101H. Using an External Interrupt to Release Stop Mode External interrupts with an RC-delay noise filter circuit can be used to release Stop mode (Clock-related external interrupts cannot be used). External interrupts INT0-INT1 in the S3C9454B/F9454B interrupt structure meet this criteria. Note that when Stop mode is released by an external interrupt, the current values in system and peripheral control registers are not changed. When you use an interrupt to release Stop mode, the CLKCON.3 and CLKCON.4 register values remain unchanged, and the currently selected clock value is used. If you use an external interrupt for Stop mode release, you can also program the duration of the oscillation stabilization interval. To do this, you must put the appropriate value to BTCON register before entering Stop mode. The external interrupt is serviced when the Stop mode release occurs. Following the IRET from the service routine, the instruction immediately following the one that initiated Stop mode is executed. IDLE MODE Idle mode is invoked by the instruction IDLE (opcode 6FH). In Idle mode, CPU operations are halted while select peripherals remain active. During Idle mode, the internal clock signal is gated off to the CPU, but not to interrupt logic and timer/counters. Port pins retain the mode (input or output) they had at the time Idle mode was entered. There are two ways to release Idle mode: 1. Execute a Reset. All system and peripheral control registers are Reset to their default values and the contents of all data registers are retained. The Reset automatically selects a slow clock (fOSC/16) because CLKCON.3 and CLKCON.4 are cleared to "00B". If interrupts are masked, a Reset is the only way to release Idle mode. 2. Activate any enabled interrupt, causing Idle mode to be released. When you use an interrupt to release Idle mode, the CLKCON.3 and CLKCON.4 register values remain unchanged, and the currently selected clock value is used. The interrupt is then serviced. Following the IRET from the service routine, the instruction immediately following the one that initiated Idle mode is executed. NOTES 1. Only external interrupts that are not clock-related can be used to release stop mode. To release Idle mode, however, any type of interrupt (that is, internal or external) can be used. 2. Before enter the STOP or IDLE mode, the ADC must be disabled. Otherwise, the STOP or IDLE current will be increased significantly.
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HARDWARE RESET VALUES
Table 8-1 lists the values for CPU and system registers, peripheral control registers, and peripheral data registers following a Reset operation in normal operating mode. -- A "1" or a "0" shows the Reset bit value as logic one or logic zero, respectively. -- An "x" means that the bit value is undefined following a reset. -- A dash ("-") means that the bit is either not used or not mapped.
Table 8-1. Register Values After a Reset Register Name Timer 0 counter register Timer 0 data register Timer 0 control register Clock control register System flags register Stack pointer register MDS special register Basic timer control register Basic timer counter Test mode control register System mode register
NOTE: - : Not mapped or not used, x: undefined
Mnemonic T0CNT T0DATA T0CON CLKCON FLAGS SP MDSREG BTCON BTCNT FTSTCON SYM
Address & Location Address D0H D1H D2H D4H D5H D9H DBH DCH DDH DEH DFH R/W R R/W R/W R/W R/W R/W R/W R/W R W R/W 7 0 1 0 0 x x 0 0 0 - -
RESET Value (Bit) 6 0 1 0 - x x 0 0 0 - - 5 0 1 - - x x 0 0 0 0 - 4 0 1 - 0 x x 0 0 0 0 - 3 0 1 0 0 - x 0 0 0 0 0 2 0 1 - - - x 0 0 0 0 0 1 0 1 0 - - x 0 0 0 0 0 0 0 1 0 - - x 0 0 0 0 0
Location D3H is not mapped
Locations D6H-D8H are not mapped Location DAH is not mapped
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Table 8-1. Register Values After a Reset (Continued) Register Name Mnemonic Address Hex Port 0 data register Port 1 data register Port 2 data register Port 0 control register (High byte) Port 0 control register Port 0 interrupt pending register Port 1 control register Port 2 control register (High byte) Port 2 control register (Low byte) PWM data register PWM control register STOP control register A/D control register A/D converter data register (High) A/D converter data register (Low) P0 P1 P2 P0CONH P0CON P0PND P1CON P2CONH P2CONL PWMDATA PWMCON STOPCON ADCON ADDATAH ADDATAL E0H E1H E2H E6H E7H E8H E9H EAH EBH F2H F3H F4H F7H F8H F9H R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W 7 0 - - 0 0 - 0 - 0 0 0 0 0 x 0 Bit Values After RESET 6 0 - 0 0 0 - 0 0 0 0 0 0 0 x 0 5 0 - 0 0 0 - - 0 0 0 - 0 0 x 0 4 0 - 0 0 0 - - 0 0 0 0 0 0 x 0 3 0 - 0 0 0 0 0 0 0 0 0 0 0 x 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 x 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x
Locations E3H-E5H are not mapped
Locations ECH-F1H are not mapped
Locations F5H-F6H are not mapped
Locations FAH-FFH are not mapped
NOTE: - : Not mapped or not used, x: undefined
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F PROGRAMMING TIP -- Sample S3C9454B/F9454B Initialization Routine
;--------------<< Interrupt Vector Address >> ORG VECTOR 0000H 00H,INT_9454 ; S3C9454B/F9454B has only one interrupt vector
;--------------<< Smart Option >> ORG DB DB DB DB 003CH 00H 00H 0E7H 03H ; 003CH, must be initialized to 0 ; 003DH, must be initialized to 0 ; 003EH, enable LVR (2.3 V) ; 003FH, internal RC (3.2 MHz in VDD = 5 V )
;--------------<< Initialize System and Peripherals >> RESET: ORG DI LD LD LD 0100H BTCON,#10100011B CLKCON,#00011000B SP,#0C0H ; ; ; ; disable interrupt Watch-dog disable Select non-divided CPU clock Stack pointer must be set
LD LD LD LD LD
P0CONH,#10101010B P0CONL,#10101010B P1CON,#00001010B P2CONH,#01001010B P2CONL,#10101010B
; ; P0.0-P0.7 push-pull output ; P1.0-P1.1 push-pull output ; ; P2.0-P2.6 push-pull output
;--------------<< Timer 0 settings >> LD LD T0DATA,#50H T0CON,#01001010B ; CPU = 3.2 MHz, interrupt interval = 6.4 msec ; fOSC/256, Timer 0 interrupt enable
;--------------<< Clear all data registers from 00h to 5FH >> LD RAM_CLR: CLR INC CP JP R0,#0 @R0 R0 R0,#0BFH ULE,RAM_CLR ; RAM clear ; ; ;
;--------------<< Initialize other registers >>
* * *
EI
; Enable interrupt
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F PROGRAMMING TIP -- Sample S3C9454B/F9454B Initialization Routine (Continued)
;--------------<< Main loop >> MAIN: NOP LD
* *
BTCON,#02H
; Start main loop ; Enable watchdog function ; Basic counter (BTCNT) clear
CALL
* * *
KEY_SCAN
;
CALL
* * *
LED_DISPLAY
;
CALL
* * *
JOB
;
JR
T,MAIN
;
;--------------<< Subroutines >> KEY_SCAN: NOP
* * *
;
RET LED_DISPLAY: NOP
* * *
;
RET JOB: NOP
* * *
;
RET
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F PROGRAMMING TIP -- Sample S3C9454B/F9454B Initialization Routine (Continued)
;--------------<< Interrupt Service Routines >> INT_9454: TM JR TM JP T0CON,#00000010B Z,NEXT_CHK1 T0CON,#00000001B NZ,INT_TIMER0 ; Interrupt enable bit and pending bit check ; Timer0 interrupt enable check ; ; If timer0 interrupt was occurred, ; T0CON.0 bit would be set.
NEXT_CHK1: TM JR TM JP NEXT_CHK2: TM JR TM JP NEXT_CHK3: TM JP TM JP IRET END_INT ; IRET P0PND,#00001000B Z,END_INT P0PND,#00000100B NZ,INT1_INT ; INT1 interrupt enable check ; ; ; ; Interrupt return P0PND,#00000010B Z,NEXT_CHK3 P0PND,#00000001B NZ,INT0_INT ; INT0 interrupt enable check ; ; ; PWMCOM,#00000010B Z,NEXT_CHK2 P0PND,#00000001B NZ,PWMOVF_INT ; PWM overflow interrupt enable check ; ; ;
;--------------< Timer0 interrupt service routine > INT_TIMER0:
* *
; T0CON,#11110110B ; Pending bit clear ; Interrupt return
AND IRET
;--------------< PWM overflow interrupt service routine > PWMOVF_INT:
* *
AND IRET
PWMCON,#11110110B
; Pending bit clear ; Interrupt return
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F PROGRAMMING TIP -- Sample S3C9454B/F9454B Initialization Routine (Continued)
;--------------< External interrupt0 service routine > INT0_INT:
* *
AND IRET
P0PND,#11111110B
; INT0 Pending bit clear ; Interrupt return
;--------------< External interrupt1 service routine > INT1_INT:
* *
AND IRET
* *
P0PND,#11111011B
; INT1 Pending bit clear ; Interrupt return
END
;
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NOTES
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I/O PORTS
9
OVERVIEW
Port 0
I/O PORTS
The S3C9454B/F9454B has three I/O ports: with 18 pins total. You access these ports directly by writing or reading port data register addresses. All ports can be configured as LED drive. (High current output: typical 10 mA) Table 9-1. S3C9454B/F9454B Port Configuration Overview Function Description Bit-programmable I/O port for schmitt trigger input or push-pull output. Pull-up resistors are assignable by software. Port 0 pins can also be used as alternative function. (ADC input, external interrupt input). Bit-programmable I/O port for schmitt trigger input or push-pull, open-drain output. Pull-up or pull-down resistors are assignable by software. Port 1 pins can also oscillator input/output or reset input by smart option. P1.2 is input only. Bit-programmable I/O port for schmitt trigger input or push-pull, open-drain output. Pull-up resistor are assignable by software. Port 2 can also be used as alternative function (ADC input, CLO, T0 clock output) Programmability Bit
1
Bit
2
Bit
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PORT DATA REGISTERS Table 9-2 gives you an overview of the port data register names, locations, and addressing characteristics. Data registers for ports 0-2 have the structure shown in Figure 9-1. Table 9-2. Port Data Register Summary Register Name Port 0 data register Port 1 data register Port 2 data register Mnemonic P0 P1 P2 Hex E0H E1H E2H R/W R/W R/W R/W
NOTE: A reset operation clears the P0-P2 data register to "00H".
I/O Port n Data Register (n = 0-2) MSB .7 .6 .5 .4 .3 .2 .1 Pn.1 .0 Pn.0 LSB
Pn.7
Pn.6
Pn.5
Pn.4
Pn.3
Pn.2
Figure 9-1. Port Data Register Format
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I/O PORTS
PORT 0 Port 0 is a bit-programmable, general-purpose, I/O ports. You can select normal input or push-pull output mode. In addition, you can configure a pull-up resistor to individual pins using control register settings. It is designed for high-current functions such as LED direct drive. Part 0 pins can also be used as alternative functions (ADC input, external interrupt input and PWM output). Two control resisters are used to control Port 0: P0CONH (E6H) and P0CONL (E7H). You access port 0 directly by writing or reading the corresponding port data register, P0 (E0H).
VDD
Pull-up Enable P0CONH VDD
Pull-up register (50 k typical)
PWM P0 Data Output DIsable (input mode) Input Data
M U X
In/Out
MUX
D1 D0 Circuit type A
External Interrupt Input To ADC
Noise Filter
NOTE: I/O pins have protection diodes through VDD and VSS.
Mode Output Input
Input Data D0 D1
Figure 9-2. Port 0 Circuit Diagram
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Port 0 Control Register (High Byte) E6H, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
[.7-.6] Port, P0.7/ADC7 Configuration Bits 0 0 = Schmitt trigger input; pull-up enable 0 1 = Schmitt trigger input 1 0 = Push-pull output 1 1 = A/D converter input (ADC7); schmitt trigger input off [.5-.4] Port 0, P0.6/ADC6/PWM Configuration Bits 0 0 = Schmitt trigger input; pull-up enable 0 1 = Alternative function (PWM output) 1 0 = Push-pull output 1 1 = A/D converter input (ADC6); schmitt trigger input off [.3-.2] Port 0, P0.5/ADC5 Configuration Bits 0 0 = Schmitt trigger input; pull-up enable 0 1 = Schmitt trigger input 1 0 = Push-pull output 1 1 = A/D converter input (ADC5); schmitt trigger input off [.1-.0] Port 0, P0.4/ADC4 Configuration Bits 0 0 = Schmitt trigger input; pull-up enable 0 1 = Schmitt trigger input 1 0 = Push-pull output 1 1 = A/D converter input (ADC4); schmitt trigger input off
Figure 9-3. Port 0 Control Register (P0CONH, High Byte)
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Port 0 Control Register (Low Byte) E7H, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
[.7-.6] Port 0, P0.3/ADC3 Configuration Bits 0 0 = Schmitt trigger input 0 1 = Schmitt trigger input; pull-up enable 1 0 = Push-pull output 1 1 = A/D converter input (ADC3); Schmitt trigger input off [.5-.4] Port 0, P0.2/ADC2 Configuration Bits 0 0 = Schmitt trigger input 0 1 = Schmitt trigger input; pull-up enable 1 0 = Push-pull output 1 1 = A/D converter input (ADC2); Schmitt trigger input off [.3-.2] Port 0, P0.1/ADC1/INT1 Configuration Bits 0 0 = Schmitt trigger input/falling edge interrupt input 0 1 = Schmitt trigger input; pull-up enable/falling edge interrupt input 1 0 = Push-pull output 1 1 = A/D converter input (ADC1); Schmitt trigger input off [.1-.0] Port 0, P0.0/ADC0/INT0 Configuration Bits 0 0 = Schmitt trigger input/falling edge interrupt input 0 1 = Schmitt trigger input; pull-up enable/falling edge interrupt input 1 0 = Push-pull output 1 1 = A/D converter input (ADC0); Schmitt trigger input off
Figure 9-4. Port 0 Control Register (P0CONL, Low Byte)
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Port 0 Interrupt Pending Register E8H, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
[.7-.4] Not used for S3C9454B/F9454B [.3] Port 0.1/ADC1/INT1, Interrupt Enable Bit 0 = INT1 falling edge interrupt disable 1 = INT1 falling edge interrupt enable [.2] Port 0.1/ADC1/INT1, Interrupt Pending Bit 0 = No interrupt pending (when read) 0 = Pending bit clear (when write) 1 = Interrupt is pending (when read) 1 = No effect (when write) [.1] Port 0.0/ADC0/INT0, Interrupt Enable Bit 0 = INT0 falling edge interrupt disable 1 = INT0 falling edge interrupt enable [.0] Port 0.0/ADC0/INT0, Interrupt Pending Bit 0 = No interrupt pending (when read) 0 = Pending bit clear (when write) 1 = Interrupt is pending (when read) 1 = No effect (when write)
Figure 9-5. Port 0 Interrupt Pending Registers (P0PND)
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PORT 1 Port 1, is a 3-bit I/O port with individually configurable pins. It can be used for general I/O port (Schmitt trigger input mode, push-pull output mode or n-channel open-drain output mode). In addition, you can configure a pull-up and pull-down resistor to individual pin using control register settings. It is designed for high-current functions such as LED direct drive. P1.0, P1.1 are used for oscillator input/output by smart option. Also, P1.2 is used for RESET pin by smart option. One control register is used to control port 1: P1CON (E9H). You address port 1 bits directly by writing or reading the port 1 data register, P1 (E1H). When you use external oscillator, P1.0, P1.1 must be set to output port to prevent current consumption.
VDD Pull-Up Register (50 k typical) Pull-up Enable Open-Drain VDD Smart option P1 Data Output DIsable (input mode) Input Data MUX D1 D0 Circuit type A XIN, XOUT or RESET In/Out
MUX
Pull-Down Enable Pull-Down Register (50 k typical)
Mode NOTE: I/O pins have protection diodes through VDD and VSS. Output Input
Input Data D0 D1
Figure 9-6. Port 1 Circuit Diagram
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Port 1 Control Register E9H, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
[.7] Port 1.1 N-Channel Open-Drain Enable Bit 0 = Configure P1.1 as a push-pull output 1 = Configure P1.1 as a n-channel open-drain output [.6] Port 1.0 N-Channel Open-Drain Enable Bit 0 = Configure P1.0 as a push-pull output 1 = Configure P1.0 as a N-channel open-drain output [.5-.4] Not used for S3C9454B/F9454B [.3-.2] Port 1, P1.1 Configuration Bits 0 0 = Schmitt trigger input; 0 1 = Schmitt trigger input; pull-up enable 1 0 = Push-pull output 1 1 = Schmitt trigger input; pull-down enable [.1-.0] Port 1, P1.0 Configuration Bits 0 0 = Schmitt trigger input; 0 1 = Schmitt trigger input; pull-up enable 1 0 = Push-pull output 1 1 = Schmitt trigger input; pull-down enable NOTE: When you use external oscillator, P1.0, P1.1 must be set to output port to prevent current consumption.
Figure 9-7. Port 1 Control Register (P1CON)
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PORT 2 Port 2 is a 7-bit I/O port with individually configurable pins. It can be used for general I/O port (schmitt trigger input mode, push-pull output mode or N-channel open-drain output mode). You can also use some pins of port 2 ADC input, CLO output and T0 clock output. In addition, you can configure a pull-up resistor to individual pins using control register settings. It is designed for high-current functions such as LED direct drive. You address port 2 bits directly by writing or reading the port 2 data register, P2 (E2H). The port 2 control register, P2CONH and P2CONL is located at addresses EAH, EBH respectively.
VDD
Pull-up Enable Open-Drain P2CONH/L VDD
Pull-up register (50 k typical)
CLO, T0 P0 Data Output DIsable (input mode) Input Data
M U X
In/Out
MUX
D1 D0 Circuit Type A
to ADC
NOTE:
I/O pins have protection diodes through VDD and VSS.
Mode Output Input
Input Data D0 D1
Figure 9-8. Port 2 Circuit Diagram
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Port 2 Control Register (High Byte) EAH, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
[.7] Not sued for S3C9454B/F9454B [.6-.4] Port 2, P2.6/ADC8/CLO Configuration Bits 0 0 0 = Schmitt trigger input; pull-up enable 0 0 1 = Schmitt trigger input 0 1 x = ADC input 1 0 0 = Push-pull output 1 0 1 = Open-drain output; pull-up enable 1 1 0 = Open-drain output 1 1 1 = Alternative function; CLO output [.3-.2] Port 2, P2.5 Configuration Bits 0 0 = Schmitt trigger input; pull-up enable 0 1 = Schmitt trigger input 1 0 = Push-pull output 1 1 = Open-drain output [.1-.0] Port 2, P2.4 Configuration Bits 0 0 = Schmitt trigger input; pull-up enable 0 1 = Schmitt trigger input 1 0 = Push-pull output 1 1 = Open-drain output NOTE: When noise problem is important issue, you had better not use CLO output
Figure 9-9. Port 2 Control Register (P2CONH, High Byte)
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Port 2 Control Register (Low Byte) EBH, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
[.7-.6] Port 2, P2.3 Configuration Bits 0 0 = Schmitt trigger input; pull-up enable 0 1 = Schmitt trigger input 1 0 = Push-pull output 1 1 = Open-drain output [.5-.4] Port 2, P2.2 Configuration Bits 0 0 = Schmitt trigger input; pull-up enable 0 1 = Schmitt trigger input 1 0 = Push-pull output 1 1 = Open-drain output [.3-.2] Port 2, P2.1 Configuration Bits 0 0 = Schmitt trigger input; pull-up enable 0 1 = Schmitt trigger input 1 0 = Push-pull output 1 1 = Open-drain output [.1-.0] Port 2, P2.0 Configuration Bits 0 0 = Schmitt trigger input; pull-up enable 0 1 = Schmitt trigger input 1 0 = Push-pull output 1 1 = T0 match output
Figure 9-10. Port 2 Control Register (P2CONL, Low Byte)
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NOTES
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BASIC TIMER and TIMER 0
10
Basic Timer (BT)
BASIC TIMER and TIMER 0
MODULE OVERVIEW
The S3C9454B/F9454B has two default timers: an 8-bit basic timer, one 8-bit general-purpose timer/counter, called timer 0.
You can use the basic timer (BT) in two different ways: -- As a watchdog timer to provide an automatic Reset mechanism in the event of a system malfunction. -- To signal the end of the required oscillation stabilization interval after a Reset or a Stop mode release. The functional components of the basic timer block are: -- Clock frequency divider (fOSC divided by 4096, 1024, or 128) with multiplexer -- 8-bit basic timer counter, BTCNT (DDH, read-only) -- Basic timer control register, BTCON (DCH, read/write) Timer 0 Timer 0 has the following functional components: -- Clock frequency divider (fOSC divided by 4096, 256, 8, or fOSC) with multiplexer -- 8-bit counter (T0CNT), 8-bit comparator, and 8-bit data register (T0DATA) -- Timer 0 control register (T0CON)
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BASIC TIMER (BT)
BASIC TIMER CONTROL REGISTER (BTCON) The basic timer control register, BTCON, is used to select the input clock frequency, to clear the basic timer counter and frequency dividers, and to enable or disable the watchdog timer function. A Reset clears BTCON to "00H". This enables the watchdog function and selects a basic timer clock frequency of fOSC/4096. To disable the watchdog function, you must write the signature code "1010B" to the basic timer register control bits BTCON.7-BTCON.4. The 8-bit basic timer counter, BTCNT, can be cleared during normal operation by writing a "1" to BTCON.1. To clear the frequency dividers for both the basic timer input clock and the timer 0 clock, you write a "1" to BTCON.0.
Basic Timer Control Register (BTCON) DCH, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Watchdog timer enable bits: 1010B = Disable watchdog function Other value = Enable watchdog function
Divider clear bit for basic timer and timer 0: 0 = No effect 1 = Clear both dividers Basic timer counter clear bits: 0 = No effect 1 = Clear basic timer counter
Basic timer input clock selection bits: 00 = fosc/4096 01 = fosc/1024 10 = fosc/128 11 = Invalid selection NOTE: When you write a 1 to BTCON.0 (or BTCON.1), the basic timer divider (or basic timer counter) is cleared. The bit is then cleared automatically to 0.
Figure 10-1. Basic Timer Control Register (BTCON)
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BASIC TIMER and TIMER 0
BASIC TIMER FUNCTION DESCRIPTION Watchdog Timer Function You can program the basic timer overflow signal (BTOVF) to generate a Reset by setting BTCON.7-BTCON.4 to any value other than "1010B" (The "1010B" value disables the watchdog function). A Reset clears BTCON to "00H", automatically enabling the watchdog timer function. A Reset also selects the oscillator clock divided by 4096 as the BT clock. A Reset whenever a basic timer counter overflow occurs. During normal operation, the application program must prevent the overflow, and the accompanying reset operation, from occurring. To do this, the BTCNT value must be cleared (by writing a "1" to BTCON.1) at regular intervals. If a system malfunction occurs due to circuit noise or some other error condition, the BT counter clear operation will not be executed and a basic timer overflow will occur, initiating a Reset. In other words, during normal operation, the basic timer overflow loop (a bit 7 overflow of the 8-bit basic timer counter, BTCNT) is always broken by a BTCNT clear instruction. If a malfunction does occur, a Reset is triggered automatically. Oscillation Stabilization Interval Timer Function You can also use the basic timer to program a specific oscillation stabilization interval following a Reset or when Stop mode has been released by an external interrupt. In Stop mode, whenever a Reset or an external interrupt occurs, the oscillator starts. The BTCNT value then starts increasing at the rate of fOSC/4096 (for Reset), or at the rate of the preset clock source (for an external interrupt). When BTCNT.4 is set, a signal is generated to indicate that the stabilization interval has elapsed and to gate the clock signal off to the CPU so that it can resume normal operation. In summary, the following events occur when Stop mode is released: 1. During Stop mode, a external power-on Reset or an external interrupt occurs to trigger the Stop mode release and oscillation starts. 2. If a external power-on Reset occurred, the basic timer counter will increase at the rate of fOSC/4096. If an external interrupt is used to release Stop mode, the BTCNT value increases at the rate of the preset clock source. 3. Clock oscillation stabilization interval begins and continues until bit 4 of the basic timer counter is set. 4. When a BTCNT.4 is set, normal CPU operation resumes. Figure 10-2 and 10-3 shows the oscillation stabilization time on RESET and STOP mode release
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BASIC TIMER and TIMER 0
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S3C9454B/F9454B
Oscillation Stabilization Time
Normal Operating mode
0.8 VDD VDD Reset Release Voltage RESET trst Internal Reset Release
~ RC
0.8 VDD
Oscillator (XOUT) Oscillator Stabilization Time
BTCNT clock BTCNT value 10000B 00000B tWAIT = (4096x16)/fOSC
Basic timer increment and CPU operations are IDLE mode
NOTE: Duration of the oscillator stabilization wait time, t WAIT, when it is released by a Power-on-reset is 4096 x 16/fOSC. tRST ~ RC (R and C are value of external power on Reset)
Figure 10-2. Oscillation Stabilization Time on RESET
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BASIC TIMER and TIMER 0
Normal Operating Mode VDD STOP Instruction Execution External Interrupt RESET STOP Release Signal
STOP Mode
Oscillation Stabilization Time
Normal Operating Mode
STOP Mode Release Signal
Oscillator (XOUT)
BTCNT clock
10000B BTCNT Value 00000B tWAIT Basic Timer Increment NOTE: Duration of the oscillator stabilzation wait time, t WAIT, it is released by an interrupt is determined by the setting in basic timer control register, BTCON.
BTCON.3 0 0 1 1
BTCON.2 0 1 0 1
tWAIT
(4096 x 16)/fosc (1024 x 16)/fosc (128 x 16)/fosc Invalid setting
tWAIT (When fOSC is 10 MHz)
6.55 ms 1.64 ms 0.2 ms
Figure 10-3. Oscillation Stabilization Time on STOP Mode Release
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S3C9454B/F9454B
F PROGRAMMING TIP -- Configuring the Basic Timer
This example shows how to configure the basic timer to sample specification. ORG VECTOR 0000H 00H,INT_9454 ; S3C9454B/F9454B has only one interrupt vector
;--------------<< Smart Option >> ORG DB DB DB DB 003CH 00H 00H 0E7H 03H ; ; ; ; 003CH, must be initialized to 0 003DH, must be initialized to 0 003EH, enable LVR (2.3 V) 003FH, internal RC (3.2 MHz in VDD = 5 V)
;--------------<< Initialize System and Peripherals >> ORG RESET: DI LD LD
* *
0100H CLKCON,#00011000B SP,#0C0H ; Disable interrupt ; Select non-divided CPU clock ; Stack pointer must be set
LD
BTCON,#02H
; Enable watchdog function ; Basic timer clock: fOSC/4096 ; Basic counter (BTCNT) clear
* * *
EI ;--------------<< Main loop >> MAIN:
*
; Enable interrupt
LD
* * *
BTCON,#02H
; Enable watchdog function ; Basic counter (BTCNT) clear
JR
T,MAIN
;
;--------------<< Interrupt Service Routines >> INT_9454:
* * *
IRET
* *
; Interrupt enable bit and pending bit check ; ; Pending bit clear ;
END
;
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BASIC TIMER and TIMER 0
TIMER 0
TIMER 0 CONTROL REGISTERS (T0CON) The timer 0 control register, T0CON, is used to select the timer 0 operating mode (interval timer) and input clock frequency, to clear the timer 0 counter, and to enable the T0 match interrupt. It also contains a pending bit for T0 match interrupts. A Reset clears T0CON to "00H". This sets timer 0 to normal interval timer mode, selects an input clock frequency of fOSC /4096, and disables the T0 match interrupts. The T0 counter can be cleared at any time during normal operation by writing a "1" to T0CON.3.
Timer 0 Control Register D3H, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Timer 0 input clock selection bits: 00 = fosc/4096 01 = fosc/256 10 = fosc/8 11 = fosc
Timer 0 interrupt pending bit: 0 = No T0 interrupt pending (when read) 0 = Clear T0 pending bit (when write) 1 = Interrupt is pending (when read) 1 = No effect (when write) Timer 0 interrupt enable bit: 0 = Disable T0 interrupt 1 = Enable T0 interrupt Not used for S3C9454B/F9454B
Not used for S3C9454B/F9454B
Timer 0 counter clear bit: 0 = No effect 1 = Clear the Timer 0 counter (when write)
NOTE: To use T0 match output(P2.0), T0CON.3 must be set to "1". In this case, there can be same delay in the timer operation In case time interval is very important, make T0CON.3 "0".
Figure 10-4. Timer 0 Control Registers (T0CON)
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BASIC TIMER and TIMER 0
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S3C9454B/F9454B
TIMER 0 FUNCTION DESCRIPTION Interval Timer Mode In interval timer mode, a match signal is generated when the counter value is identical to the value written to the Timer 0 reference data register, T0DATA. The match signal generates a Timer 0 match interrupt (T0INT, vector 00H) and then clears the counter. If, for example, you write the value "10H" to T0DATA, the counter will increment until it reaches "10H". At this point, the Timer 0 interrupt request is generated, the counter value is reset and counting resumes.
CLK
Counter (T0CNT)
T0CON.3 R (clear) Timer 0 counter clear
Match Comparator PND IRQ0 (T0INT)
Data Register (T0DATA)
T0CON.1 Interrupt Enable/Disable
NOTE:
T0CON.3 is not auto-cleared, you must pay attention when clear pending bit (refer to P10-12)
Figure 10-5. Simplified Timer 0 Function Diagram (Interval Timer Mode)
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BASIC TIMER and TIMER 0
Compare Value (T0DATA) Up Counter Value (T0CNT) 00H
Match Match Match Match Match Match Match
Clear Clear Count start T0CON.3 1 T0DATA Value change Counter Clear (T0CON.3) Interrupt Request (T0CON.0) T0 Match Output (P2.0)
Clear
Figure 10-6. Timer 0 Timing Diagram
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BASIC TIMER and TIMER 0
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S3C9454B/F9454B
Bit 1 RESET or STOP Bits 3, 2 MUX 1/4096 XIN DIV R 1/1024 1/128 MUX 8-Bit Up Counter (BTCNT, Read-Only) OVF RESET Data Bus Clear Basic Timer Control Register (Write '1010xxxxB' to disable.)
When BTCNT.4 is set after releasing from RESET or STOP mode, CPU clock starts.
Bit 0 Bits 7, 6 Data Bus
R XIN DIV
1/4096 1/256 1/8 1 Match 8-Bit Comparator Bit 0 P2.0 P2CONL.1-.0 T0DATA Buffer IRQ0 MUX T0CNT (D0H) (Read-Only) Clear Bit 3
Bit 1
Bit 3 Match Signal T0DATA (D1H) (Read/Write) Basic Timer Control Register Data Bus Timer 0 Control Register
NOTE:
During a power-on Reset operation, the CPU is idle during the required oscillation stabilization interval (until bit 4 the basic timer counter is set).
Figure 10-7. Basic Timer and Timer 0 Block Diagram
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BASIC TIMER and TIMER 0
F PROGRAMMING TIP1 - Configuring Timer 0 (Interval Mode)
The following sample program sets Timer 0 to interval timer mode. ORG VECTOR ORG DB DB DB DB ORG RESET: DI LD LD LD LD LD LD LD LD 0000H 00H,INT_9454 003CH 00H 00H 0E7H 03H 0100H BTCON,#10100011B CLKCON,#00011000B SP,#0C0H P0CONH,#10101010B P0CONL,#10101010B P1CON,#00001010B P2CONH,#01001010B P2CONL,#10101010B ; ; ; ; ; ; ; ; ; Disable interrupt Watchdog disable Select non-divided CPU clock Set stack pointer P0.0-0.7 push-pull output P1.0-P1.1 push-pull output P2.0-P2.6 push-pull output ; S3C9454B/F9454B has only one interrupt vector ; ; ; ; 003CH, must be initialized to 0 003DH, must be initialized to 0 003EH, enable LVR (2.3 V) 003FH, internal RC (3.2 MHz in VDD = 5 V)
;--------------<< Timer 0 settings >> LD LD
* * *
T0DATA,#50H T0CON,#01001010B
; CPU = 3.2 MHz, interrupt interval = 4 msec ; fOSC/256, Timer 0 interrupt enable
EI ;--------------<< Main loop >> MAIN: NOP
* * *
; Enable interrupt
; Start main loop
CALL
* * *
LED_DISPLAY
; Sub-block module
CALL
* * *
JOB
; Sub-block module
JR
T,MAIN
;
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BASIC TIMER and TIMER 0
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S3C9454B/F9454B
F PROGRAMMING TIP1 - Configuring Timer 0 (Interval Mode) (Continued)
LED_DISPLAY: NOP
* * *
RET JOB: NOP
* * *
; ; ; ; ; ; ; ; ; ;
RET ;--------------<< Interrupt Service Routines >> INT_9454: TM JR TM JP NEXT_CHK1:
* * *
T0CON,#00000010B Z,NEXT_CHK1 T0CON,#00000001B NZ,INT_TIMER0
; Interrupt enable check ; ; If timer 0 interrupt was occurred, ; T0CON.0 bit would be set. ; Interrupt enable bit and pending bit check ; ; ; ; Timer 0 interrupt service routine
IRET INT_TIMER0:
* * *
AND IRET
* *
T0CON,#11110110B
; ;
Pending bit clear
END
;
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8-BIT PWM
11
OVERVIEW
8-BIT PWM (PULSE WIDTH MODULATION)
This microcontroller has the 8-bit PWM circuit. The operation of all PWM circuit is controlled by a single control register, PWMCON. The PWM counter is a 8-bit incrementing counter. It is used by the 8-bit PWM circuits. To start the counter and enable the PWM circuits, you set PWMCON.2 to "1". If the counter is stopped, it retains its current count value; when re-started, it resumes counting from the retained count value. When there is a need to clear the counter you set PWMCON.3 to "1". You can select a clock for the PWM counter by set PWMCON.6-.7. Clocks which you can select are fOSC/64, fOSC/8, fOSC/2, fOSC/1.
FUNCTION DESCRIPTION
PWM The 8-bit PWM circuits have the following components: -- 6-bit comparator and extension cycle circuit -- 6-bit reference data register (PWMDATA.7-.2) -- 2-bit extension data register (PWMDATA.1-.0) -- PWM output pins (P0.6/PWM) PWM Counter To determine the PWM module's base operating frequency, the upper 6-bits of counter is compared to the PWM data (PWMDATA.7-.2). In order to achieve higher resolutions, the lower 2-bits of the counter can be used to modulate the "stretch" cycle. To control the "stretching" of the PWM output duty cycle at specific intervals, the lower 2-bits of counter value is compared with the PWMDATA.1-.0.
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8-BIT PWM
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PWM Data and Extension Registers PWM (duty) data registers, located in F2H, determine the output value generated by each 8-bit PWM circuit. To program the required PWM output, you load the appropriate initialization values into the 6-bit reference data register (PWMDATA.7-.2) and the 2-bit extension data register (PWMDATA.1-.0). To start the PWM counter, or to resume counting, you set PWMCON.2 to "1". A reset operation disables all PWM output. The current counter value is retained when the counter stops. When the counter starts, counting resumes at the retained value. PWM Clock Rate The timing characteristics of PWM output is based on the fOSC clock frequency. The PWM counter clock value is determined by the setting of PWMCON.6-.7. Table 11-1. PWM Control and Data Registers Register Name PWM data registers PWM control registers Mnemonic PWMDATA.7-.2 PWMDATA.1-.0 PWMCON Address F2H.7-.2 F2H.1-.0 F3H Function 6-bit PWM basic cycle frame value 2-bit extension ("stretch") value PWM counter stop/start (resume), and PWM counter clock settings
PWM Function Description The PWM output signal toggles to Low level whenever the lower 6-bit of counter matches the reference data register (PWMDATA.7-.2). If the value in the PWMDATA.7-.2 register is not zero, an overflow of the lower 6-bits of counter causes the PWM output to toggle to High level. In this way, the reference value written to the reference data register determines the module's base duty cycle. The value in the upper 2-bits of counter is compared with the extension settings in the 2-bit extension data register (PWMDATA.1-.0). This lower 2-bits of counter value, together with extension logic and the PWM module's extension data register , is then used to "stretch" the duty cycle of the PWM output. The "stretch" value is one extra clock period at specific intervals, or cycles (see Table 11-2). If, for example, the value in the extension data register is '01B', the 2nd cycle will be one pulse longer than the other 3 cycles. If the base duty cycle is 50 %, the duty of the 2nd cycle will therefore be "stretched" to approximately 51% duty. For example, if you write 10B to the extension data register, all odd-numbered pulses will be one cycle longer. If you write 11H to the extension data register, all pulses will be stretched by one cycle except the 4th pulse. PWM output goes to an output buffer and then to the corresponding PWM output pin. In this way, you can obtain high output resolution at high frequencies.
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8-BIT PWM
Table 11-2. PWM output "stretch" Values for Extension Data Register (PWMDATA.1-.0) PWMDATA Bit (Bit1-Bit0) 00 01 10 11 "Stretched" Cycle Number - 2 1, 3 1, 2, 3
PWM Clock:
0H 4 MHz 000000xxB
40H
80H
PWM Data Register Values: (PWMDATA)
000001xxB
250 ns
250 ns
100000xxB
8 ms
8 ms
111111xxB 250 ns
Figure 11-1. 8-Bit PWM Basic Waveform
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8-BIT PWM
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S3C9454B/F9454B
0H PWM Clock: 4 MHz
40H
000010xxB PWMDATA : 0000 1001B Basic Extended waveform waveform 1st
500 ns
2nd 3th
4th
1st
2nd 3th
4th
0H 4 MHz
40H
750 ns
Figure 11-2. 8-Bit Extended PWM Waveform
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8-BIT PWM
PWM CONTROL REGISTER (PWMCON) The control register for the PWM module, PWMCON, is located at register address F3H. PWMCON is used the 8bit PWM modules. Bit settings in the PWMCON register control the following functions: -- PWM counter clock selection -- PWM data reload interval selection -- PWM counter clear -- PWM counter stop/start (or resume) operation -- PWM counter overflow (8-bit counter overflow) interrupt control A reset clears all PWMCON bits to logic zero, disabling the entire PWM module.
PWM Control Register (PWMCON) F3H, Reset: 00H MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
PWM input clock selection bits: 00 = fOSC/64 01 = fOSC/8 10 = fOSC/2 11 = fOSC/1 Not used for S3C9454B/F9454B PWMDATA reload interval selection bit: 0 : reload from 8-bit up counter overflow 1: reload from 6-bit up counter overflow
PWM OVF interrupt pending bit: 0 = No interrupt pending 0 = Clear pending condition (when write) 1 = Interrupt pending PWM OVF interrupt enable bit: 0 = Disable interrupt 1 = Enable interrupt PWM counter enable bit: 0 = Stop counter 1 = Start (resume countering) PWM counter clear bit: 0 = No effect 1 = Clear the PWM counter
Figure 11-3. PWM Control Register (PWMCON)
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8-BIT PWM
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S3C9454B/F9454B
fOSC/8 fOSC fOSC/64 fOSC/2
PWMCON.6-.7 From 8-bit up counter (7:6) 2-bit Counter From 8-bit up counter (5:0) 6-bit Counter
MUX
PWMCON.2 "1" When REG > Count 6-bit Comparator P0.6/PWM "1" When REG = Count
Extension Control Logic
6-bit Data Buffer
Extension Data Buffer 6-bit Data Register (F2H) F2H bit7-2
F2H bit1-0
PWM Extension Data Register PWMCON.3 (clear) 8 or 6-bit up counter overflow
DATA BUS (7:0)
Figure 11-4. PWM Functional Block Diagram
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8-BIT PWM
F PROGRAMMING TIP -- Programming the PWM Module to Sample Specifications
;--------------<< Interrupt Vector Address >> ORG 0000H VECTOR 00H,INT_9454 ; S3C9454/F9454 has only one interrupt vector
;--------------<< Smart Option >> ORG 003CH DB DB DB DB 00H 00H 0E7H 03H ; ; ; ; 003CH, must be initialized to 0. 003DH, must be initialized to 0. 003EH, enable LVR (2.3 V) 003FH, internal RC (3.2 MHz in VDD = 5 V)
;--------------<< Initialize System and Peripherals >> RESET: ORG DI LD
* *
0100H BTCON,#10100011B ; disable interrupt ; Watchdog disable
LD LD LD
* *
P0CONH,#10011010B PWMCON,#00000110B PWMDATA,#80H
; Configure P0.6 PWM output ; fOSC/64, counter/interrupt enable ;
EI ;--------------<< Main loop >> MAIN:
* * * *
; Enable interrupt
JR
t,MAIN
; ; ; ; ; ;
;--------------<< Interrupt Service Routines >> INT_9454:
*
TM JR TM JP NEXT_CHK1:
* * *
PWMCON,#00000010B Z,NEXT_CHK1 PWMCON,#00000001B NZ,INT_PWM
; ; ; ; ;
Interrupt enable bit and pending bit check Interrupt enable check Interrupt pending bit check PWMCON's pending bit set --> PWM interrupt
IRET
;
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F PROGRAMMING TIP -- Programming the PWM Module to Sample Specifications (Continued)
INT_PWM:
* * *
; PWM interrupt service routine
AND IRET
* *
PWMCON,#11110110B
; pending bit clear ;
END
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A/D CONVERTER
12
OVERVIEW
-- D/A converter logic
A/D CONVERTER
The 10-bit A/D converter (ADC) module uses successive approximation logic to convert analog levels entering at one of the nine input channels to equivalent 10-bit digital values. The analog input level must lie between the VDD and VSS values. The A/D converter has the following components: -- Analog comparator with successive approximation logic -- ADC control register (ADCON) -- Nine multiplexed analog data input pins (ADC0-ADC8) -- 10-bit A/D conversion data output register (ADDATAH/L): To initiate an analog-to-digital conversion procedure, you write the channel selection data in the A/D converter control register ADCON to select one of the nine analog input pins (ADCn, n = 0-8) and set the conversion start or enable bit, ADCON.0. The read-write ADCON register is located at address F7H. During a normal conversion, ADC logic initially sets the successive approximation register to 200H (the approximate half-way point of an 10-bit register). This register is then updated automatically during each conversion step. The successive approximation block performs 10-bit conversions for one input channel at a time. You can dynamically select different channels by manipulating the channel selection bit value (ADCON.7-4) in the ADCON register. To start the A/D conversion, you should set a the enable bit, ADCON.0. When a conversion is completed, ACON.3, the end-of-conversion (EOC) bit is automatically set to 1 and the result is dumped into the ADDATA register where it can be read. The A/D converter then enters an idle state. Remember to read the contents of ADDATA before another conversion starts. Otherwise, the previous result will be overwritten by the next conversion result. NOTE Because the ADC does not use sample-and-hold circuitry, it is important that any fluctuations in the analog level at the ADC0-ADC8 input pins during a conversion procedure be kept to an absolute minimum. Any change in the input level, perhaps due to circuit noise, will invalidate the result.
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A/D CONVERTER
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S3C9454B/F9454B
USING A/D PINS FOR STANDARD DIGITAL INPUT The ADC module's input pins are alternatively used as digital input in port 0 and P2.6. A/D CONVERTER CONTROL REGISTER (ADCON) The A/D converter control register, ADCON, is located at address F7H. ADCON has four functions: -- Bits 7-4 select an analog input pin (ADC0-ADC8). -- Bit 3 indicates the status of the A/D conversion. -- Bits 2-1 select a conversion speed. -- Bit 0 starts the A/D conversion. Only one analog input channel can be selected at a time. You can dynamically select any one of the ten analog input pins (ADC0-ADC8) by manipulating the 4-bit value for ADCON.7-ADCON.4.
A/D Converter Control Register (ADCON) F7H, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
A/D Conversion input pin selection bits 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 ... 1111 ADC0 (P0.0) ADC1 (P0.1) ADC2 (P0.2) ADC3 (P0.3) ADC4 (P0.4) ADC5 (P0.5) ADC6 (P0.6) ADC7 (P0.7) ADC8 (P2.6) Connected with GND internally ... Connected with GND internally Conversion start bit: 0 = No effect 1 = A/D conversion start
Conversion speed selection bits: (note) 00 = fOSC/16 (fOSC < 10 MHz) 01 = fOSC/8 (fOSC < 10 MHz) 10 = fOSC/4 (fOSC < 10 MHz) 11 = fOSC/1 (fOSC < 4 MHz)
End-of-conversion (ECO) status bit: 0 = A/D conversion is in progress 1 = A/D conversion complete
NOTE:
Maximum ADC clock input = 4 MHz
Figure 12-1. A/D Converter Control Register (ADCON)
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A/D CONVERTER
INTERNAL REFERENCE VOLTAGE LEVELS In the ADC function block, the analog input voltage level is compared to the reference voltage. The analog input level must remain within the range VSS to VDD. Different reference voltage levels are generated internally along the resistor tree during the analog conversion process for each conversion step. The reference voltage level for the first bit conversion is always 1/2 VDD.
A/D Converter Control Register ADCON (F7H) ADCON.7-.4 ADCON.0 (ADEN) Control Circuit M U L T I P L E X E R Clock Selector ADCON.2-.1
+
ADCON.3 (EOC Flag)
ADC0/P0.0 ADC1/P0.1 ADC2/P0.2
-
Successive Approximation Circuit
Analog Comparator
ADC7/P0.7 ADC8/P2.6
VDD D/A Converter VSS
Conversion Result ADDATAH (F8H) ADDATAL (F9H)
To data bus
Figure 12-2. A/D Converter Circuit Diagram
ADDATAH
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
ADDATAL
MSB
-
-
-
-
-
-
.1
.0
LSB
Figure 12-3. A/D Converter Data Register (ADDATAH/L)
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A/D CONVERTER
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ADC0N.0 Conversion Start ECO ADDATA
1 50 ADC clock
9 Privious Value
8
7
6
5
4
3
2
1
0 Valid data
ADDATAH (8-bit) + ADDATAL (2-bit) Set-up time 10 clock 40 clock
Figure 12-4. A/D Converter Timing Diagram
CONVERSION TIMING The A/D conversion process requires 4 steps (4 clock edges) to convert each bit and 10 clocks to step-up A/D conversion. Therefore, total of 50 clocks are required to complete an 10-bit conversion: With an 10 MHz CPU clock frequency, one clock cycle is 400 ns (4/fosc). If each bit conversion requires 4 clocks, the conversion rate is calculated as follows: 4 clocks/bit x 10-bits + step-up time (10 clock) = 50 clocks 50 clock x 400 ns = 20 s at 10 MHz, 1 clock time = 4/fOSC (assuming ADCON.2-.1 = 10)
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A/D CONVERTER
INTERNAL A/D CONVERSION PROCEDURE 1. Analog input must remain between the voltage range of VSS and VDD. 2. Configure the analog input pins to input mode by making the appropriate settings in P0CONH, P0CONL and P2CONH registers. 3. Before the conversion operation starts, you must first select one of the nine input pins (ADC0-ADC8) by writing the appropriate value to the ADCON register. 4. When conversion has been completed, (50 clocks have elapsed), the EOC flag is set to "1", so that a check can be made to verify that the conversion was successful. 5. The converted digital value is loaded to the output register, ADDATAH (8-bit) and ADDATAL (2-bit), then the ADC module enters an idle state. 6. The digital conversion result can now be read from the ADDATAH and ADDATAL register.
VDD XIN Analog Input Pin 101 ADC0-ADC8 XOUT
S3C9454B/ F9454B
VSS
Figure 12-5. Recommended A/D Converter Circuit for Highest Absolute Accuracy
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A/D CONVERTER
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F PROGRAMMING TIP - Configuring A/D Converter
ORG 0000H VECTOR 00H,INT_9454 ORG 003CH DB DB DB DB ORG DI LD
* * *
; S3C9454/F9454 has only one interrupt vector ; ; ; ; 003CH, must be initialized to 0 003DH, must be initialized to 0 003EH, enable LVR (2.3 V) 003FH, internal RC (3.2 MHz in VDD = 5 V)
00H 00H 0E7H 03H 0100H BTCON,#10100011B
RESET:
; disable interrupt ; Watchdog disable
LD LD LD EI
P0CONH,#11111111B P0CONL,#11111111B P2CONH,#00100000B
; ; ; ;
Configure P0.4-P0.7 AD input Configure P0.0-P0.3 AD input Configure P2.6 AD input Enable interrupt
;--------------<< Main loop >> MAIN:
* * *
CALL
* * *
AD_CONV
; Subroutine for AD conversion
JR AD_CONV: LD
t,MAIN ADCON,#00000001B
; ; Select analog input channel P0.0 ; select conversion speed fOSC/16 ; set conversion start bit
NOP NOP NOP
; If you select conversion speed to fOSC/16 ; at least three nop must be included
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A/D CONVERTER
F PROGRAMMING TIP - Configuring A/D Converter (Continued)
CONV_LOOP: TM JR LD LD LD ADCON,#00001000B Z,CONV_LOOP R0,ADDATAH R1,ADDATAL ADCON,#00010011B ; ; ; ; Check EOC flag If EOC flag=0, jump to CONV_LOOP until EOC flag=1 High 8 bits of conversion result are stored to ADDATAH register
; Low 2 bits of conversion result are stored ; to ADDATAL register ; Select analog input channel P0.1 ; Select conversion speed fOSC/8 ; Set conversion start bit
CONV_LOOP2:TM JR LD LD
* * *
ADCON,#00001000B Z,CONV_LOOP2 R2,ADDATAH R3,ADDATAL
; Check EOC flag
RET INT_9454:
* * *
IRET
* *
; ; Interrupt enable bit and pending bit check ; ; Pending bit clear ;
END
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NOTES
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ELECTRICAL DATA
13
OVERVIEW
ELECTRICAL DATA
In this section, the following S3C9454B/F9454B electrical characteristics are presented in tables and graphs: -- Absolute maximum ratings -- D.C. electrical characteristics -- A.C. electrical characteristics -- Input timing measurement points -- Oscillator characteristics -- Oscillation stabilization time -- Operating voltage range -- Schmitt trigger input characteristics -- Data retention supply voltage in stop mode -- Stop mode release timing when initiated by a RESET -- A/D converter electrical characteristics -- LVR circuit characteristics -- LVR reset timing
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ELECTRICAL DATA
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Table 13-1. Absolute Maximum Ratings (TA = 25 C) Parameter Supply voltage Input voltage Output voltage Output current high Symbol VDD VI VO IOH IOL TA TSTG All ports All output ports One I/O pin active All I/O pins active Output current low One I/O pin active All I/O pins active Operating temperature Storage temperature - - Conditions - Rating - 0.3 to + 6.5 - 0.3 to VDD + 0.3 - 0.3 to VDD + 0.3 - 25 - 80 + 30 + 150 - 25 to + 85 - 65 to + 150 C C mA Unit V V V mA
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ELECTRICAL DATA
Table 13-2. DC Electrical Characteristics (TA = - 25 C to + 85 C, VDD = 2.0 V to 5.5 V) Parameter Input high voltage Input low voltage Output high voltage Output low voltage Input high leakage current Input low leakage current Output high leakage current Output low leakage current Pull-up resistors Pull-down resistors Supply current Symbol VIH1 VIH2 VIL1 VIL2 VOH VOL ILIH1 ILIH2 ILIL1 ILIL2 ILOH ILOL RP RP IDD1
RESET
Conditions Ports 0, 1, 2 and XIN and XOUT Ports 0, 1, 2 and
RESET
Min 0.8 VDD VDD- 0.1
Typ -
Max VDD
Unit V
VDD= 2.0 to 5.5 V
VDD= 2.0 to 5.5 V
-
-
0.2 VDD 0.1
V
XIN and XOUT IOH = - 10 mA ports 0, 1, 2 IOL = 25 mA port 0, 1, and 2 All input except ILIH2 XIN, XOUT All input except ILIL2 XIN, XOUT All output pins All output pins VIN = 0 V, TA=25C Ports 0, 1, 2 VIN = 0 V, TA=25C Ports 1 Run mode 10 MHz CPU clock 3 MHz CPU clock Idle mode 10 MHz CPU clock 3 MHz CPU clock Stop mode TA = 25C VDD= 4.5 to 5.5 V VDD= 4.5 to 5.5 V VIN = VDD VIN = VDD VIN = 0 V VIN = 0 V VOUT = VDD VOUT = 0 V VDD = 5 V VDD = 5 V VDD = 4.5 to 5.5 V VDD = 2.0 V VDD = 4.5 to 5.5 V VDD = 2.0 V VDD = 4.5 to 5.5 V (LVR disable) VDD = 4.5 to 5.5 V (LVR enable) VDD = 2.6 V (LVR enable) - - - - 25 25
-
VDD-1.5 - -
VDD- 0.4 0.4 -
- 2.0 1 20
V V uA
-
-
-1 -20
uA
- - 50 50 5 2 2 0.5 0.1 100 30
2 -2 100 100 10 5 4 1.5 5 200 60
uA uA k
mA
IDD2
IDD3
uA
NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads and ADC module.
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ELECTRICAL DATA
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S3C9454B/F9454B
Table 13-3. AC Electrical Characteristics (TA = - 25 C to + 85 C, VDD = 2.0 V to 5.5 V) Parameter Interrupt input low width RESET input low width Symbol tINTL tRSL Conditions INT0, INT1 VDD = 5 V 10 % Input VDD = 5 V 10 % Min - - Typ 200 1 Max - - Unit ns us
tINTL
tINTH
XIN
0.8 VDD 0.2 VDD
Figure 13-1. Input Timing Measurement Points
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ELECTRICAL DATA
Table 13-4. Oscillator Characteristics (TA = - 25 C to + 85 C) Oscillator Main crystal or ceramic Clock Circuit
C1 XIN
Test Condition VDD = 4.5 to 5.5 V
Min 1
Typ -
Max 10
Unit MHz
C2
XOUT
VDD = 2.7 to 4.5 V VDD = 2.0 to 2.7 V External clock (Main System)
XIN
1 1 1
- - -
6 3 10
MHz MHz MHz
VDD = 4.5 to 5.5 V
XOUT
VDD = 2.7 to 4.5 V VDD = 2.0 to 2.7 V External RC oscillator Internal RC oscillator - - VDD = 5 V VDD = 5 V Tolerance:20% at TA =25C
1 1 - -
- - 4 3.2 0.5
6 3 -
MHz MHz MHz
Table 13-5. Oscillation Stabilization Time (TA = - 25 C to + 85 C, VDD = 2.0 V to 5.5 V) Oscillator Main crystal Main ceramic External clock (main system) Oscillator stabilization Wait time fOSC > 1.0 MHz Oscillation stabilization occurs when VDD is equal to the minimum oscillator voltage range. XIN input high and low width (tXH, tXL) tWAIT when released by a reset (1) tWAIT when released by an interrupt (2) Test Condition Min - - 25 - -
16
Typ - - - 2 /fOSC -
Max 20 10 500 - -
Unit ms ms ns ms ms
NOTES: 1. fOSC is the oscillator frequency. 2. The duration of the oscillator stabilization wait time, tWAIT, when it is released by an interrupt is determined by the settings in the basic timer control register, BTCON.
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S3C9454B/F9454B
CPU Clock 10 MHz 6 MHz 4 MHz 3 MHz 2 MHz 1 MHz 1 2 2.7 3 4 4.5 5 5.5 6 7
Supply Voltage (V)
Figure 13-2. Operating Voltage Range
VOUT VDD A = 0.2 VDD B = 0.4 VDD C = 0.6 VDD D = 0.8 VDD VSS A B C D
VIN
0.3 VDD
0.7 VDD
Figure 13-3. Schmitt Trigger Input Characteristics Diagram
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ELECTRICAL DATA
Table 13-6. Data Retention Supply Voltage in Stop Mode (TA = - 25 C to + 85 C, VDD = 2.0 V to 5.5 V) Parameter Data retention supply voltage Data retention supply current Symbol VDDDR IDDDR Conditions Stop mode Stop mode; VDDDR = 2.0 V Min 2.0 - Typ - 0.1 Max 5.5 5 Unit V uA
NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads.
Stop Mode Data Retention Mode
RESET Occurs
Oscillation Stabilization Time
~ ~
VDD
RESET
Execution Of Stop Instrction
NOTE: tWAIT is the same as 4096 x 16 x 1/f OSC
Figure 13-4. Stop Mode Release Timing When Initiated by a RESET
~ ~ VDDDR Normal Operating Mode tWAIT
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Table 13-7. A/D Converter Electrical Characteristics (TA = - 25 C to + 85 C, VDD = 2.0 V to 5.5 V, VSS = 0 V) Parameter Total accuracy Symbol - Test Conditions VDD = 5.12 V CPU clock = 10 MHz VSS = 0 V fOSC = 10 MHz - - VDD = 5 V VDD = 5 V VDD = 3 V VDD = 5 V power down mode - Min - Typ - Max 3 Unit LSB
Integral linearity error Differential linearity error Offset error of top Offset error of bottom Conversion time (1) Analog input voltage Analog input impedance Analog input current Analog block current (2)
ILE DLE EOT EOB tCON VIAN RAN IADIN IADC
- - - - - VSS 2 - -
- - 1 1 20 - - - 1 0.5 100
2 1 3 2 - VDD - 10 3 1.5 500 nA s V MW A mA
NOTES: 1. "Conversion time" is the time required from the moment a conversion operation starts until it ends. 2. IADC is operating current during A/D conversion.
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Table 13-8. LVR Circuit Characteristics (TA = 25 C, VDD = 2.0 V to 5.5 V) Parameter Low voltage reset Symbol VLVR Conditions - Min 2.0 3.3 3.6 Typ 2.3 3.0 3.9 Max 2.6 3.6 4.2 Unit V
VDD
VLVR,MAX VLVR VLVR,MIN
Figure 13-5. LVR Reset Timing
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NOTES
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MECHANICAL DATA
14
OVERVIEW
MECHANICAL DATA
The S3C9454B/F9454B is available in a 20-pin DIP package (Samsung: 20-DIP-300A), a 20-pin SOP package (Samsung: 20-SOP-375), a 20-pin SSOP package (Samsung: 20-SSOP-225), a 16-pin DIP package (Samsung: 16-DIP-300A), a 16-pin SOP package (Samsung: 16-SOP-BD300-SG), a 16-pin SSOP package (Samsung: 16SSOP-BD44). Package dimensions are shown in Figure 14-1, 14-2, 14-3, 14-4, 14-5 and 14-6.
#20
#11
0-15
6.40 0.20
#1
#10
26.80 MAX 26.40 0.20
0.46 0.10 (1.77) 1.52 0.10 2.54
NOTE:
Dimensions are in millimeters.
Figure 14-1. 20-DIP-300A Package Dimensions
3.30 0.30
0.51 MIN
5.08 MAX
3.25 0.20
0.2 5
+0 . - 0 10 .05
20-DIP-300A
7.62
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MECHANICAL DATA
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0-8 #20 #11
10.30 0.30
7.50 0.20
20-SOP-375
#1
#10
0.203
13.14 MAX 12.74 0.20
2.50 MAX
2.30 0.10
0.10 MAX
(0.66) 0.40
+ 0.10 - 0.05
1.27
NOTE:
Dimensions are in millimeters.
Figure 14-2. 20-SOP-375 Package Dimensions
14-2
0.05 MIN
0.85 0.20
+ 0.10 - 0.05
9.53
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MECHANICAL DATA
0-8 #20 #11
6.40 0.20
4.40 0.10
20-SSOP-225
0.15
6.90 MAX 6.50 0.20
1.85 MAX
1.50 0.10
0.10 MAX
(0.30)
+0.10
0.65 0.22 -0.05
NOTE:
Dimensions are in millimeters.
Figure 14-3. 20-SSOP-225 Package Dimensions
0.05 MIN
0.50 0.20
#1
#10
+ 0.10 - 0.05
5.72
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#16
#9
0-15
6.40 0.20
#1
#8
19.80 MAX 19.40 0.20
0.38 MIN
0.46 0.10 (0.81) 1.50 0.10 2.54
NOTE:
Dimensions are in millimeters.
Figure 14-4. 16-DIP-300A Package Dimensions
14-4
3.30 0.30
5.08 MAX
3.25 0.20
0.2 5
+0 . - 0 10 .05
16-DIP-300A
7.62
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MECHANICAL DATA
10.50 10.10 0-8 #16 #9
10.56 10.26
16-SOP-BD300-SG
0.30 0.10
#1
#8
0.32 0.23
1.27 0.40
0.75 x 45 0.50
2.65 2.35
1.27BSC 0.48 0.35
NOTE:
Dimensions are in millimeters.
Figure 14-5. 16-SOP-BD300-SG Package Dimensions
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#16
#9
6.40 0.20 0.252 0.008
4.40 0.10 0.173 0.004
16-SSOP-BD44
+0.10
0.15 -0.05 0.006 -0.002 1.50 0.10 0.059 0.004 0.50 0.20 0.019 0.008 #1 #8
+0.004
6.50 0.10 0.256 0.004 1.85 MAX 0.072
0.45 0.018
0.80 0.031
+0.10
0.30 -0.07
+0.004
0.012 -0.003
NOTE:
Dimensions are in millimeters.
Figure 14-6. 16-SSOP-BD44 Package Dimensions
14-6
0.05 MIN 0.002
0.10 MAX 0.004 MAX
5.40 0.213
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S3F9454B MTP
15
OVERVIEW
S3F9454B MTP
The S3F9454B single-chip CMOS microcontroller is the MTP (Multi Time Programmable) version of the S3C9454BB/F9454B microcontroller. It has an on-chip Flash ROM instead of masked ROM. The Flash ROM is accessed by serial data format. The S3F9454B is fully compatible with the S3C9454BB/F9454B, in function, in D.C. electrical characteristics, and in pin configuration. Because of its simple programming requirements, the S3F9454B is ideal for use as an evaluation chip for the S3C9454BB/F9454B.
VSS/VSS XIN/P1.0 XOUT/P1.1 VPP/RESET/P1.2 T0/P2.0 P2.1 P2.2 P2.3 P2.4 P2.5
1 2 3 4 5 6 7 8 9 10
20 19 18 17
VDD/VDD P0.0/ADC0/INT0/SCL P0.1/ADC1/INT1/SDA P0.2/ADC2 P0.3/ADC3 P0.4/ADC4 P0.5/ADC5 P0.6/ADC6/PWM P0.7/ADC7 P2.6/ADC8/CLO
S3F9454B
16 15 14 13 12 11
NOTE:
The bolds indicate MTP pin name.
Figure 15-1. Pin Assignment Diagram (20-Pin Package)
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VSS/VSS XIN/P1.0 XOUT/P1.1 VPP/RESET/P1.2 T0/P2.0 P2.1 P2.2 P2.3
1 2 3 4 5 6 7 8
16 15 14 13
VDD/VDD P0.0/ADC0/INT0/SCL P0.1/ADC1/INT1/SDA P0.2/ADC2 P0.3/ADC3 P0.4/ADC4 P0.5/ADC5 P0.6/ADC6/PWM
S3F9454B
12 11 10 9
NOTE:
The bolds indicate MTP pin name.
Figure 15-2. Pin Assignment Diagram (16-Pin Package)
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S3F9454B MTP
Table 15-1. Descriptions of Pins Used to Read/Write the Flash ROM Main Chip Pin Name P0.1 Pin Name SDA Pin No. 18 (20-pin) 14 (16-pin) 19 (20-pin) 15 (16-pin) 4 During Programming I/O I/O Function Serial data pin (output when reading, Input when writing) Input and push-pull output port can be assigned Serial clock pin (input only pin) Power supply pin for flash ROM cell writing (indicates that MTP enters into the writing mode). When 12.5 V is applied, MTP is in writing mode and when 5 V is applied, MTP is in reading mode. (Option) Logic power supply pin.
P0.0 RESET, P1.2
SCL VPP
I I
VDD/VSS
VDD/VSS
20 (20-pin), 16 (16-pin) 1 (20-pin), 1 (16-pin)
I
Table 15-2. Comparison of S3F9454B and S3C9454B Features Characteristic Program memory Operating voltage (VDD) MTP programming mode Pin configuration EPROM programmability S3F9454B 4 Kbyte Flash ROM 2.0 V to 5.5 V VDD = 5 V, VPP = 12.5 V 20 DIP/20 SOP/20 SSOP/16 DIP/16SOP/16 SSOP/8 DIP/8 SOP User Program multi time Programmed at the factory S3C9454B 4K byte mask ROM 2.0 V to 5.5 V
OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the VPP pin of the S3F9454B Flash ROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 15-3 below. Table 15-3. Operating Mode Selection Criteria VDD 5V VPP 5V 12.5 V 12.5 V 12.5 V REG/MEM 0 0 0 1 Address (A15-A0) 0000H 0000H 0000H 0E3FH R/W 1 0 1 0 Mode Flash ROM read Flash ROM program Flash ROM verify Flash ROM read protection
NOTE: "0" means Low level; "1" means High level.
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NOTES
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DEVELOPMENT TOOLS
16
OVERVIEW
SHINE
DEVELOPMENT TOOLS
Samsung provides a powerful and easy-to-use development support system in turnkey form. The development support system is configured with a host system, debugging tools, and support software. For the host system, any standard computer that employs Win95/98/2000 as its operating system can be used. A sophisticated debugging tool is provided both hardware and software: the powerful in-circuit emulator, SMDS2+ or SK-1000, for S3C7, S3C9, S3C8 families of microcontrollers. The SMDS2+ is a new and improved version of SMDS2, and SK-1000 is supported by a third party tool vendor. Samsung also offers support software that includes debugger, assembler, and a program for setting options.
Samsung Host Interface for in-circuit Emulator, SHINE, is a multi-window based debugger for SMDS2+. SHINE provides pull-down and pop-up menus, mouse support, function/hot keys, and context-sensitive hyper-linked help. It has an advanced, multiple-windowed user interface that emphasizes ease of use. Each window can be sized, moved, scrolled, highlighted, added, or removed completely. SAMA ASSEMBLER The Samsung Arrangeable Microcontroller (SAM) Assembler, SAMA, is a universal assembler, and generates object code in standard hexadecimal format. Assembled program code includes the object code that is used for ROM data and required SMDS program control data. To assemble programs, SAMA requires a source file and an auxiliary definition (DEF) file with device specific information. SASM86 The SASM86 is an relocatable assembler for Samsung's S3C9-series microcontrollers. The SASM86 takes a source file containing assembly language statements and translates into a corresponding source code, object code and comments. The SASM86 supports macros and conditional assembly. It runs on the MS-DOS operating system. It produces the relocatable object code only, so the user should link object file. Object files can be linked with other object files and loaded into memory. HEX2ROM HEX2ROM file generates ROM code from HEX file which has been produced by assembler. ROM code must be needed to fabricate a microcontroller which has a mask ROM. When generating the ROM code (.OBJ file) by HEX2ROM, the value "FF" is filled into the unused ROM area upto the maximum ROM size of the target device automatically.
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TARGET BOARDS Target boards are available for all S3C9-series microcontrollers. All required target system cables and adapters are included with the device-specific target board. MTPs Multi times programmable microcontrollers (MTPs) are under development for S3C9454B/F9454B microcontroller.
IBM-PC AT or Compatible
RS-232C
Emulator (SMDS2+ or SK-1000)
EPROM Writer Unit
Target Application System
RAM Break/Display Unit Probe Adapter Bus Trace/Timer Unit
SAM8 Base Unit
POD
TB9454B Target Board EVA Chip
Power Supply Unit
Figure 16-1. SMDS2+ or SK-1000 Product Configuration
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TB9454B TARGET BOARD The TB9454B target board is used for the S3C9454B/F9454B microcontrollers. It is supported by the SK1000/SMDS2+ development systems.
TB9454B
To User_VCC Off RESET U2 On VCC 1 CN1 128 QFP S3E9450 EVA Chip 20-Pin Connector 24 8 pin DIP switch 10 11 SMDS2+ SM1333A GND J101 20 Idle Stop
+
+
25 100-Pin Connector
1 1 External Triggers CH1 CH2 SMDS
Figure 16-2. TB9454B Target Board Configuration
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Table 16-1. Power Selection Settings for TB9454B "To User_Vcc" Settings
To user_Vcc off on
TB9454B External VCC VSS VCC SK-1000/SMDS2+ Target System
Operating Mode
Comments The SK1000/SMDS2+ main board supplies VCC to the target board (evaluation chip) and the target system.
To user_Vcc off on
TB9454B External VCC VSS VCC SK-1000/SMDS2+ Target System
The SK1000/SMDS2+ main board supplies VCC only to the target board (evaluation chip). The target system must have its own power supply.
NOTE: The following symbol in the "To User_Vcc" Setting column indicates the electrical short (off) configuration:
SMDS2+ Selection (SAM8) In order to write data into program memory that is available in SMDS2+, the target board should be selected to be for SMDS2+ through a switch as follows. Otherwise, the program memory writing function is not available. Table 16-2. The SMDS2+ Tool Selection Setting "SW1" Setting
SMDS SMDS2+
R/W* SMDS2+ R/W* Target System
Operating Mode
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Table 16-3. Using Single Header Pins as the Input Path for External Trigger Sources Target Board Part
External Triggers Ch1 Ch2
Comments
Connector from External Trigger Sources of the Application System
You can connect an external trigger source to one of the two external trigger channels (CH1 or CH2) for the SK-1000/SMDS2+ breakpoint and trace functions.
ON OFF 3EH.7 3EH.6 3EH.5 3EH.4 3EH.3 3EH.2 3FH.1 3FH.0
ON OFF
NOTE:
Low High
About EVA chip, smart option is determined by DIP switch not software.
Figure 16-3. DIP Switch for Smart Option
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J101
VSS P1.0 P1.1 RESET/P1.2 T0/P2.0 P2.1 P2.2 P2.3 P2.4 P2.5
1 2
20 19
VDD P0.0/ADC0/INT0 P0.1/ADC1/INT1 P0.2/ADC2 P0.3/ADC3 P0.4/ADC4 P0.5/ADC5 P0.6/ADC6/PWM P0.7/ADC7 P2.6/ADC8/CLO
20-PIN DIP SOCKET
3 4 5 6 7 8 9 10
18 17 16 15 14 13 12 11
Figure 16-4. 20-Pin Connector for TB9454B
Target Board J101 1 20 1
Target System
20
Figure 16-5. S3C9454B/F9454B Probe Adapter for 20-DIP Package
20-Pin Connector
20-Pin Connector
Part Name: AS20D Order Cods: SM6304
10
11
10
11
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