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APA2035
Stereo 2.6W Audio Amplifier(With Gain Control)
Features
* *
Low operating current with 6mA Improved depop circuitry to eliminate turn-on transients in outputs
General Description
APA2035 is a monolithic integrated circuit, which provides internal gain control, and a stereo bridged audio power amplifiers capable of producing 2.6W (1.9W) into 3 with less than 10% (1.0%) THD+N. By control the two gain setting pins, Gain0 and Gain1, The amplifier can provide 6dB, 15.6dB, 21.6dB and 27dB gain settings. The advantage of internal gain setting can be less components and PCB area. Both of the depop circuitry and the thermal shutdown protection circuitry are integrated in APA2035, that reduces pops and clicks noise during power up or shutdown mode operation. It also improved the power off pop noise and protects the chip from being destroyed by over temperature and short current failure. To simplify the audio system design APA2035 combines a stereo bridge-tied loads (BTL) mode for speaker drive and a stereo single-end (SE) mode for headphone drive into a single chip, where both modes are easily switched by the SE/BTL input control pin signal. Besides the multiple input selections is used for portable audio system.
* High PSRR * www..com Internal gain control, eliminate external
components.
* * * * * * *
2.6W per channel output power into 3 load at 5V, BTL mode Multiple input modes allowable selected by HP/LINE pin Two output modes allowable with BTL and SE modes selected by SE/BTL pin Low current consumption in shutdown mode (50A) Short Circuit Protection TSSOP-24-P with thermal pad package Lead Free Available (RoHS Compliant)
Applications
* * NoteBook PC LCD Monitor
Ordering and Marking Information
APA2035 Lead Free Code Handling Code Temp. Range Package Code APA2035 XXXXX Package Code R : TSSOP-P * Temp. Range I : - 40 to 85 C Handling Code TU : Tube TR : Tape & Reel TY : Tray Lead Free Code L : Lead Free Device Blank : Original Device XXXXX - Date Code
APA2035 R :
* TSSOP-P is a standard TSSOP package with thermal pad exposure on bottom of the package. Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS and compatible with both SnPb and lead-free soldiering operations. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J STD-020C for MSL classification at lead-free peak reflow temperature.
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright (c) ANPEC Electronics Corp. Rev. A.1 - Aug., 2006 1 www.anpec.com.tw
APA2035
Pinouts
GND 1 GAIN0 2 GAIN1 3 LOUT+ 4 LLINEIN 5 LHPIN 6 PVDD 7 RIN+ 8 LOUT- 9 LIN+ 10 BYPASS 11 GND 12 24 23 22 21 TOP View (APA2035) GND RLINEIN SHUTDOWN ROUT+
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20 RHPIN 19 VDD 18 PVDD 17 HP/LINE 16 ROUT15 SE/BTL 14 PCBEEP 13 GND
APA2035_PinOut
Block Diagram
LLINEIN LHPIN
MUX
LOUT+
LIN+ BYPASS
Vbias
LOUTGAIN0 GAIN1 RLINEIN RHPIN
Gain selectable
MUX
ROUT+
RIN+ HP/LINE
HP/LINE
Vbias
SE/BTL SHUTDOWN
SE/BTL
Shutdown ckt
ROUT-
PCBEEP
PC-BEEP ckt
APA2035_Block
APA2035
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APA2035
Absolute Maximum Ratings
(Over operating free-air temperature range unless otherwise noted.)
Parameter Supply voltage range, VDD, PVDD Input voltage range at SE/BTL, HP/LINE, SHUTDOWN, Operating ambient temperature range, TA Maximum junction temperature, TJ Storage temperature range, TSTG Soldering Temperature, 10 seconds, TS www..com Electrostatic Discharge, VESD Power dissipation, PD
Notes: *1.Human body model:C=100pF, R=1500 , 3 positives pulse plus 3 negative pulses *2. Machine model: C=200pF, L=0.5mH, 3 positive pulses plus 3 negative pulses
Rating -0.3V to 6V -0.3V to VDD -40 C to 85 C Internal Limited -65 C to 150 C 260 C -3000 to 3000*1 -200 to 200*2 Internal Limited
Recommended Operating Conditions
Supply Voltage, VDD... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... .... ... ... ... ..4.5V to 5.5V
Thermal Characteristics
Symbol RTHJA Parameter Thermal Resistance from Junction to Ambient in Free Air TSSOP-P24* Value 45 Unit C/W
* 5 in2 printed circuit board with 2oz trace and copper pad through 9 25mil diameter vias. The thermal pad on the TSSOP_P package with solder on the printed circuit board.
Electrical Characteristics
(VDD=5V,-40CSymbol VDD IDD ISD VIH
Parameter Supply Voltage Supply current Supply current in shutdown mode High level threshold Voltage
Test Condition
APA2035 Min. 3.3 Typ. 6 4 50 2 4 Max. 5.5 12 8 300
Unit V mA mA A V V
SE/BTL = 0V SE/BTL = 5V SHUTDOWN = 0V SHUTDOWN, GAIN0, GAIN1 SE/BTL, HP/LINE
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APA2035
Electrical Characteristics (Cont.)
(VDD=5V,-40CSymbol VIL
Parameter Low level threshold Voltage
Test Condition SHUTDOWN, GAIN0, GAIN1 SE/BTL, HP/LINE
Min.
APA2035 Typ. Max. 0.8 3 5
Unit V V nA V
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Input current Common mode Input voltage Output differential voltage PC_beep trigger level
SHUTDOWN, SE/BTL, HP/LINE, GAIN0, GAIN1 VDD-1.0
5 1
mV Vp.p
Operating Characteristics, BTL mode Vdd=5V, TA=25C, Rl=4, Gain=6dB, (Unless otherwise noted)
Symbol
Parameter
Test Condition THD=10%, Fin=1khz, RL=3 THD=10%, Fin=1khz, RL=4 THD=10%, Fin=1khz, RL=8 THD=1%, Fin=1khz, RL=3 THD=1%, Fin=1khz, RL=4 THD=1%, Fin=1khz, RL=8 Po=1.1W, RL=4 Fin=1khz Po=0.7W, RL=8, Fin=1khz Vin=0.2Vrms, Rl=8, Cb=0.47f, f=120Hz f=1khz, Cb=0.47f, f=1khz, Cb=0.47f, Po=1.1W, Rl=8 , A_weight
APA2035 Min. Typ. 2.6 2.3 1.5 1.9 1.7 1.1 0.05 0.04 85 95 80 105 Max.
Unit W W W W W W % % dB dB dB dB
PO
Maximum output power
1
THD+N PSRR xtalk S/N
Total harmonic distortion plus noise Power ripple rejection ratio Channel separation HP/LINE input separation Signal to noise ratio
Operating Characteristics, SE mode Vdd=5V, TA=25C, Rl=32, Gain=0dB, (Unless otherwise noted)
Symbol PO
Parameter Maximum output power
Test Condition
APA2035 Min. Typ. Max. 110 90 0.03
Unit mW mW %
THD=10%, Fin=1khz, RL=32 THD=1%, Fin=1khz, RL=32 THD+N Total harmonic distortion plus noise Po=75mW, RL=32 .Fin=1khz
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APA2035
Electical Characteristics (Cont.)
Operating Characteristics, SE mode Vdd=5V, TA=25C, Rl=32, Gain=0dB, (Unless otherwise noted)
Symbol PSRR
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Parameter Power ripple rejection ratio SE/BTL attenuation Channel separation HP/LINE input separation Signal to noise ratio
Test Condition Vin=0.2Vrms, Rl=32, Cb=0.47f, f=120, f=1khz, Cb=0.47f, f=1khz, Cb=0.47f, BTL Po=75mW, Rl=32, A_weight,
APA2035 Min. Typ. 55 80 65 80 100 Max.
Unit dB dB dB dB dB
xtalk S/N
Pin Descriptions
Pin name GND GAIN0 GAIN1 LOUT+ LLINEIN RLINEIN LHPIN PVDD RIN+ LOUTLIN+ BYPASS PCBEEP SE/BTL ROUTHP/LINE VDD RHPIN ROUT+ SHUTDOWN RLINEIN Pin no. Config. 1, 12, 13, 24 2 3 4 5 23 6 7, 18 8 9 10 11 14 15 16 17 19 20 21 22 23 I/P I/P O/P I/P I/P O/P I/P O/P I/P I/P I/P O/P I/P I/P O/P I/P I/P Function Description Ground connection, Connected to thermal pad. Input signal for internal gain setting Input signal for internal gain setting Left channel positive output in BTL mode and SE mode Left channel line input terminal, selected when HP/LINE is held low. Right channel line input terminal, selected when HP/LINE is held low. Left channel headphone input terminal, selected when HP/LINE is held high. Supply voltage only for power amplifier Right channel positive signal input, when differential signal is accepted. Left channel negative output in BTL mode and high impedance in SE mode Left channel positive signal input, when differential signal is accepted. Bypass voltage PC-beep signal input Output mode control input pin, high for SE output mode and low for BTL mode Right channel negative output in BTL mode and high impedance in SE mode Multi-input selection input, headphone mode when held high, line-in mode when held low Supply voltage for internal circuit excepting power amplifier. Right channel headphone input terminal, selected when HP/LINE is held high. Right channel positive output in BTL mode and SE mode It will be into shutdown mode when pull low Right channel line input terminal, selected when HP/LINE is held low
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APA2035
Truth Table for Logic Inputs
HP/ LINE X L H L H
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SE/BTL X L L H H X
SHUTDOWN L H H H H X
PCBEEP Disable Disable Disable Disable Disable Enable
Operating mode Shutdown mode Line input, BTL out HP input, BTL out Line input, SE out HP input, SE out PCBEEP input, BTL out
X
Gain Setting Table
GAIN0 0 0 1 1 GAIN1 0 1 0 1 Ri 90K 45K 25.7K Rf 90K 135K 154.3K Av 6dB 15.6dB 21.6dB 27.6dB
13.85K 166.15K
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APA2035
Typical Application Circuit
(f (using SE input signal)
VDD
0
0.1F VDD 0.47F L-LINE L-HP 0.47F 0.47F 0.47F LLINEIN LHPIN GND
100F
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PVDD
MUX
LOUT+ 220F
LIN+ BYPASS
1k
Vbias
4 SE/BTL Signal GAIN0 GAIN1
Gain selectable
Control Pin Ring
LOUT-
Sleeve Tip Headphone Jack
0.47F R-LINE R-HP 0.47F 0.47F
RLINEIN RHPIN
MUX
ROUT+ 220F
RIN+ HP/LINE
HP/LINE
1k
Vbias
HP/LINE Control Signal 100k SE/BTL Signal Shutdown Signal
VDD 100k SE/BTL
SE/BTL
4 ROUT-
SHUTDOWN
Shutdown ckt
BEEP Signal 0.47F
PCBEEP
PC-BEEP ckt APA2035 AppCkt
APA 2035
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APA2035
Typical Characteristics
THD+N vs. Output Power
10
THD+N vs. Output Power
10
VDD=5V AV=6dB f=1kHz BTL
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VDD=5V AV=0dB f=1kHz COUT=330F SE
THD+N (%)
THD+N (%)
1
RL=8
RL=4
RL=3
1
RL=32
RL=16
0.1
0.1
0.01 0 0.5 1 1.5 2 2.5 3
0.01 0 50 100 150 200 250
Output Power (W)
Output Power (mW)
THD+N vs. Output Power
10
10
THD+N vs. Output Power
VDD=5V AV=6dB RL=3 BTL f=15kHz
f=15kHz
1
THD+N (%)
1
THD+N (%)
f=1kHz
0.1
f=1kHz
0.1
f=30Hz
f=30Hz VDD=5V AV=15.6dB RL=3 BTL
1 5
0.01 10m 100m 1 2 5
0.01 10m
100m
Output Power (W)
Output Power (W)
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APA2035
Typical Characteristics (Cont.)
THD+N vs. Output Power
10
10
THD+N vs. Output Power
VDD=5V AV=6dB RL=4 BTL
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f=15kHz f=15kHz
1
1
THD+N (%)
THD+N (%)
f=1kHz
0.1
f=1kHz
0.1
f=30Hz
0.0 1 10m
VDD=5V AV=15.6dB RL=4 BTL
1 2 5
0.01 10m 100m
f=30Hz
100m
1
2
5
Output Power (W)
Output Power (W)
THD+N vs. Output Power
10
THD+N vs. Frequency
10
VDD=5V AV=6dB RL=8 BTL
1
VDD=5V AV=15.6dB RL=8 BTL f=15kHz
THD+N (%)
f=15kHz
1
THD+N (%)
f=30Hz
0.1
0.1
f=1kHz
f=1kHz f=30Hz
0.01 10m
0.01 10m
100m
1
2
5
100m
1
2
5
Output Power (W)
Output Power (W)
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APA2035
Typical Characteristics (Cont.)
THD+N vs. Output Power
10
THD+N vs. Output Power
10
VDD=5V AV=0dB RL=16 COUT=1000F SE
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1
VDD=5V AV=0dB RL=32 COUT=1000F SE f=30Hz f=15kHz
1
THD+N (%)
THD+N (%)
f=15kHz
0.1
0.1
f=30Hz f=1kHz f=1kHz
0.01 10m 50m 100m 200m 300m
0.01 10m
50m
100m
200m 300m
Output Power (W)
Output Power (W)
THD+N vs. Frequency
10
10
THD+N vs. Frequency
VDD=5V PO=1.75W RL=3 BTL
1
VDD=5V AV=6dB RL=3 BTL
THD+N (%)
THD+N (%)
1
AV=15.6dB
PO=1.75W
0.1
0.1
AV=6dB
PO=1W
0.01 20
100
1k
10k 20k
0.01 20
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
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APA2035
Typical Characteristics (Cont.)
THD+N vs. Frequency
10
10
THD+N vs. Frequency
VDD=5V PO=1.5W RL=4 BTL
1
VDD=5V AV=6dB RL=4 BTL
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1
THD+N (%)
THD+N (%)
AV=15.6dB
PO=1.5W
0.1
0.1
AV=6dB
PO=0.75W
0.01 20 100 1k 10k 20k
0.01 20 100 1k 10k 20k
Frequency (Hz)
Frequency (Hz)
THD+N vs. Frequency
10
THD+N vs. Frequency
10
VDD=5V AV=6dB RL=8 BTL
VDD=5V PO=1W RL=8 BTL
1
THD+N (%)
PO=1W
0.1
THD+N (%)
1
AV=6dB
0.1
PO=0.5W
AV=15.6dB
0.01 20 100 1k 10k 20k
0.01 20 100 1k 10k 20k
Frequency (Hz)
Frequency (Hz)
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APA2035
Typical Characteristics (Cont.)
THD+N vs. Frequency
10
THD+N vs. Frequency
10
VDD=5V AV=0dB RL=16 COUT=1000F SE
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VDD=5V AV=0dB RL=32 COUT=1000F SE
THD+N (%)
1
0.1
THD+N (%)
PO=75mW
1
0.1
PO=25mW
PO=150mW
0.01 20 100 1k 10k 20k
PO=75mW
0.01 20 100 1k 10k 20k
Frequency (Hz)
Frequency (Hz)
Frequency Response
+6 +240
Frequency Response
+20 +18 +16 +270 +260 +250
+220 +210 +230
+4
Gain
Phase (Degress)
+14
+200
+220 +210 +200 +190 +180
-0 +190 -2 +180
Gain (dB)
+12 +10 +8 +6 +4 +2 -0
Phase
-4
+170 +160
Phase VDD=5V RL=4 AV=15.6dB PO=1W BTL
10 100 1k 10k
+170 +160 +150 +140 +130 +120 100k 200k
-6
-8
VDD=5V RL=4 AV=6dB PO=1W BTL
10 100 1k 10k
+150 +140 +130 +120 100k 200k
-10
Frequency (Hz)
Frequency (Hz)
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Phase (Degress)
+2
Gain
+240 +230
Gain (dB)
APA2035
Typical Characteristics (Cont.)
Frequency Response
+1 0 -1 +300
Crosstalk vs. Frequency
+0
Gain
+280
-20
+260 +240 +220 +200
-3 -4 -5 -6 -7 -8 -9 10 100 1k 10k
Crosstalk (dB)
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-2
Phase (Degress)
-40
VDD=5V RL=4 AV=6dB PO=1.5W BTL
T
T
Gain (dB)
-60
Phase
Vdd = 5V RL = 32 Av = 0dB Vin = 1V SE
+180 +160 +140 +120 +100 100k 200k
-80
Left to Right
-100
-120
Right to Left
20 100 1k 10k 20k
-140
Frequency (Hz)
Frequency (Hz)
Crosstalk vs. Frequency
+0 -10 -20 -30
PSRR vs. Frequency
+0
VDD=5V RL=32 AV=0dB VIN=1V COUT=330F SE
VDD=5V RL=4 CB=0.47F -20 BTL
-10 -30
Crosstalk (dB)
-50 -60
PSRR (dB)
10k 20k
-40
-40 -50 -60 -70 -80 -90 -100
Left to Right
-70 -80 -90 -100 20
Right to Left
100
1k
20
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
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APA2035
Typical Characteristics (Cont.)
PSRR vs. Frequency
+0 -10 -20
100
Output Noise Voltage vs. Frequency
Output Noise Voltage (V)
VDD=5V RL=32 CB=0.47F SE
50
Filter BW < 22kHz
20
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-30 -40 -50 -60 -70 -80 -90 -100 20
PSRR (dB)
10
A-Weight
5
2
VDD=5V RL=4 AV=6dB BTL
100 1k 10k 20k
100
1k
10k 20k
1 20
Frequency (Hz)
Frequency (Hz)
Output Noise Voltage vs. Frequency
100
7
Supply Current vs. Supply Voltage
No Load
50
Filter BW < 22kHz
6
BTL
Output Noise Voltage (V)
Supply Current (mA)
5
20
4
10
A-Weight
SE
3
5
2
2
VDD=5V RL=32 AV=0dB SE
20 100 1k 10k 20k
1
1
0 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Frequency (Hz)
Supply Voltage (V)
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APA2035
Typical Characteristics (Cont.)
Power Dissipation vs. Output Power
2.0 1.8 1.6
Power Dissipation vs. Output Power
200
VDD=5V BTL RL=3
180
VDD=5V SE RL=8
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1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0.0 0.5 1.0 1.5 2.0 2.5
Power Dissipation (mW)
Power Dissipation (W)
160 140 120 100 80 60 40 20 0 0 50
RL=4
RL=16
RL=8
RL=32
100
150
200
250
300
Output Power (W)
Output Power (mW)
Application Descriptions
BTL Operation The APA2035 has two pairs of operational amplifiers internally, allowed for different amplifier configurations. 2X(Gain of SE mode). By driving the load differentially through outputs OUT+ and OUT-, an amplifier configuration commonly referred to as bridged mode is established. BTL mode operation
INPUTINPUT+
is different from the classical single-ended SE amplifier
OUT+ OP1
Figure 1: APA2035 internal configuration (each channel) The OP1 and OP2 are all differential drive configuration, The differential drive configuration doubling the voltage swing on the load compare to the single-ending configuration, the differential gain for each channel is
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+ V bias + DIFF_AMP_CONFIG OUTOP2
-
configuration where one side of its load is connected to ground. A BTL amplifier design has a few distinct advantages over the SE configuration, as it provides differential drive to the load, thus doubling the output swing for a specified supply voltage. Four times the output power is possible as compared to a SE amplifier under the same conditions. A BTL configuration, such as the one used in APA2035, also creates a second advantage over SE amplifiers. Since the differential outputs, ROUT+, ROUT-, LOUT+, and LOUT-, are biased at halfsupply, no need DC voltage exists across the load.
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APA2035
Application Descriptions (Cont.)
BTL Operation (Cont.) This eliminates the need for an output coupling capacitor which is required in a single supply, SE configuration. Single-Ended Operation
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Control of the SE/BTL input can be a logic-level TTL source or a resistor divider network or the stereo headphone jack with switch pin as shown in Application Circuit.
Vdd 1K Control Pin
the single-supply SE configuration shown
SE/BTL
Ring
Application Circuit. A coupling capacitor is required to block the DC offset voltage from reaching the load. These capacitors can be quite large (approximately 33F to 1000F) so they tend to be expensive, occupy valuable PCB area, and have the additional drawback of limiting low-frequency performance of the system (refer to the Output Coupling Capacitor). The rules described should be following relationship:
1 Cbypass x160k
100K
100K
SE/BTL_Switch
Tip
Sleeve
Headphone Jack
Figure 2: SE/BTL input selection by phonejack plug In Figure 2, input SE/BTL operates as follows: When the phonejack plug is inserted, the 1k resistor is disconnected and the SE/BTL input is pulled high and enables the SE mode. When the input goes high level, the OUT- amplifier is shutdown causing the speaker to mute. The OUT+ amplifier then drives through the output capacitor (CO) into the headphone jack. When there is no headphone plugged into the system, the contact pin of the headphone jack is connected from the signal pin, the voltage divider set up by resistors 100k and 1k. Resistor 1k then pulls low the SE/BTL pin, enabling the BTL function. Input HP/LINE Operation APA2035 amplifier has two separate inputs for each of the left and right stereo channels. An internal multiplexer selects which input will be connected to the amplifier based on the state of the HP/LINE pin on the IC. * * To select the line inputs, set HP/LINE pin tied to low level To enable the headphone inputs, set HP/ LINE pin tied to high level
1 << R 1 RiCi LCC
(1)
Output SE/BTL Operation The ability of the APA2035 to easily switch between BTL and SE modes is one of its most important costs saving features. This feature eliminates the requirement for an additional headphone amplifier in applications where internal stereo speakers are driven in BTL mode but external headphone or speakers must be accommodated. Internal to the APA2035, two separate amplifiers drive OUT+ and OUT- (see Figure 1). The SE/BTL input controls the operation of the follower amplifier that drives LOUT- and ROUT-. * * When SE/BTL is held low, the OP2 is actived and the APA2035 is in the BTL mode. When SE/BTL is held high, the OP2 is in a high output impedance state, which configures the APA2035 as SE driver from OUT+. IDD is reduced by approximately one-half in SE mode.
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APA2035
Application Descriptions
Input HP/LINE Operation (Cont.) Refer to the application circuit, the voltage divider of 100k and 1k sets the voltage at the HP/LINE pin to be approximately 50mV when there are no headphones plugged into the system. This logic low voltage at the HP/LINE pin enables the APA2035 and places it LINE input mode operation. BTL mode operation brings about the factor 2 in the gain equation due to the inverting amplifier mirroring the voltage swing across the load. The input resistance has wide variation (+/-10%) caused by manufacture. Input Capacitor, Ci In the typical application an input capacitor, Ci, is required to allow the amplifier to bias the input signal to the proper DC level for optimum operation. In this case, Ci and the minimum input impedance Ri form a high-pass filter with the corner frequency determined in the follow equation: fC (highpass)=
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When a set of headphones is plugged into the system, the contact pin of the headphone jack is disconnected from the signal pin, interrupting the voltage divider set up by resistors 100k. Resistor 100k then pulls-up the HP/LINE pin, enabling the headphone input function. Differential Input Operation APA2035 can accepted the differential input signal, and it' can improve the CMRR (Common Mode s Rejection ratio). For example: when apply differential input signals to APA2035, connect positive input signals to the IN+ (LIN+ and RIN+) of APA2035 and negative input signals to the IN- (LIN- and RIN-) of APA2035. When input signals are single-end, just connect IN+ (LIN+ and RIN+) to ground via a capacitor. Input Resistance, Ri
1 2Ri(min)xCi
(2)
The value of Ci is important to consider as it directly affects the low frequency performance of the circuit. Consider the example where Ri is 90k when 6dB gain is setting and the specification calls for a flat bass response down to 40Hz . Equation is reconfigured as follow:
1
(3) 2Rifc Consider to input resistance variation, the Ci is 0.04F so one would likely choose a value in the range of 0.1F to 1.0F. A further consideration for this capacitor is the leakage
Ci=
The APA2035 provides four gain setting decided by GAIN0 and GAIN1 input ins in Differential mode and it become 0dB fixed gain when SE mode is selected. In table 1,internal resistors Ri and Rf according to BTL operation set the gain for each audio input of the APA2035.
GAIN0 0 0 1 1 X GAIN1 0 1 0 1 X Ri 90K 45K 25.7K Rf 90K 135K 154.3K SE/BTL 0 0 0 0 1 Av 6dB 15.6dB 21.6dB 27.6dB 0dB
path from the input source through the input network (Ri+Rf, Ci) to the load. This leakage current creates a DC offset voltage at the input to the amplifier that reduces useful headroom, especially in high gain applications. For this reason a low-leakage tantalum or ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most applications as the DC level there is held at VDD/2, which is likely higher that the source DC level. Please note that it is important to confirm the capacitor polarity in the application.
13.85K 166.15K 90K 90K
Table 1: The close loop gain setting resistance Ri/Rf
Copyright (c) ANPEC Electronics Corp. Rev. A.1 - Aug., 2006 17 www.anpec.com.tw
APA2035
Application Descriptions
Effective Bypass Capacitor, Cbypass As with any power amplifier, proper supply bypassing is critical for low noise performance and high power supply rejection. The capacitor location on both the bypass and power supply pins should be as close to the device as www..com possible. The effect of a larger half supply bypass capacitor is improved PSRR due to increased halfsupply stability. Typical applications employ a 5V regulator with 1.0F and a 0.1F bypass capacitors which aid in supply filtering. This does not eliminate the need for bypassing the supply nodes of the APA2035. The selection of bypass capacitors, especially Cb, is thus dependent upon desired PSRR requirements, click and pop performance. To avoid start-up pop noise occurred, the bypass voltage should be rise slower then the input bias voltage and the relationship shown in equation should be maintained. 1 << Cbypass x160k For example, a 330F capacitor with an 8 speaker would attenuate low frequencies below 60.6Hz. The main disadvantage, from a performance standpoint, is the load impedance is typically small, which drives the low-frequency corner higher degrading the bass response. Large values of CC are required to pass low frequencies into the load. Power Supply Decoupling, Cs The APA2035 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to ensure the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also prevents the oscillations causing by long lead length between the amplifier and the speaker. The optimum decoupling is achieved by using two different type capacitors that target on different type of noise on the power supply leads. For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance(ESR) ceramic capacitor, typically 0.1F placed as close as possible to the device VDD lead works best. For filtering lowerfrequency noise signals, a large aluminum electrolytic capacitor of 10F or greater placed near the audio power amplifier is recommended. (5) Shutdown Function In order to reduce power consumption while not in use, the APA2035 contains a shutdown pin to externally turn off the amplifier bias circuitry. This shutdown feature turns the amplifier off when a logic low is placed on the SHUTDOWN pin. The trigger point between a logic high and logic low level is typically 2.0V. It is best to switch between ground and the supply VDD to
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1
fc(highpass)=
2 RLCC
(6)
1 Ci x Ri
(4)
The capacitor is fed from a 125k source inside the amplifier. Bypass capacitor, Cb, values of 3.3F to 10F ceramic or tantalum low-ESR capacitors are r ec o m m e n d e d for the best THD and noise performance. The bypass capacitance also effect to the start up time. It is determined in the follow equation: Tstart up =5x(Cbypassx125k) Output Coupling Capacitor, Cc In the typical single-supply SE configuration, an output coupling capacitor (Cc) is required to block the DC bias at the output of the amplifier thus preventing DC currents in the load. As with the input coupling capacitor, the output coupling capacitor and impedance of the load form a high-pass filter governed by equation.
Copyright (c) ANPEC Electronics Corp. Rev. A.1 - Aug., 2006
APA2035
Application Descriptions
Shutdown Function (Cont.) provide maximum device performance. switching the SHUTDOWN pin to low, the amplifier enters a lowof Cb, turn-on pop can be reduced. However, the tradeoff for using a larger bypass capacitor is to increase the turn-on time for this device. There is a linear relationship between the size of Cb and the turn-on time. In a SE configuration, the output coupling capacitor, CC, is of particular concern. This capacitor discharges through the internal 10k resistors. Depending on the size of CC, the time constant can be relatively large. To reduce transients in SE mode, an external 1k resistor can be placed in parallel with the internal 10k APA2035 integrates a PCBEEP detect circuit for NOTEBOOK PC used. When PC-BEEP signal drive to PCBEEP input pin, and PCBEEP mode is active. APA2035 will force to BTL mode and the internal gain fixed as -10dB. The PCBEEP signal becomes the amplifier input signal and play on the speaker without coupling capacitor. If the amplifier in the shutdown mode, it will out of shutdown mode whenever PCBEEP mode enable. The APA2035 will return to previous setting when it is out of PC-BEEP mode. The input impedance is 100k on PCBEEP input pin. Optimizing Depop Circuitry Circuitry has been included in the APA2035 to minimize the amount of popping noise at power-up and when coming out of shutdown mode. Popping occurs whenever a voltage step is applied to the speaker. In order to eliminate clicks and pops, all capacitors must be fully discharged before turn-on. Rapid on/off switching of the device or the shutdown function will cause the click and pop circuitry. The value of Ci will also affect turn-on pops. (Refer to Effective Bypass Capacitance) The bypass voltage rise up should be slower than input bias voltage. Although the bypass pin current source cannot be modified, the size of Cb can be changed to alter the device turn-on time and the amount of clicks and pops. By increasing the value In the most cases, choosing a small value of Ci in the range of 0.33F to 1F, Cb being equal to 0.47F and an external 1k resistor should be placed in parallel with the internal 10k resistor should produce a virtually clickless and popless turn-on. A high gain amplifier intensifies the problem as the small delta in voltage is multiplied by the gain. So it is advantageous to use low-gain configurations. BTL Amplifier Efficiency An easy-to-use equation to calculate efficiency starts out as being equal to the ratio of power from the power supply to the power delivered to the load. The following equations are the basis for calculating amplifier efficiency. Efficiency = Where: PO =
PO PSUP
cur entstate, IID <50A. APA2035 is in shutdown r at DD current st e, D
mode, except PC-BEEP detect circuit. On normal operating, SHUTDOWN pin pull to high level to keeping
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the IC out of the shutdown mode. The SHUTDOWN pin should be tied to a definite voltage to avoid unwanted state changes. PC-BEEP Detection
resistor. The tradeoff for using this resistor is an increase in quiescent current.
(7)
VP x VP 2RL
VOrmsx VOrms RL
=
VOrms =
VP 2
2VP RL
(8)
Psup = VDD * IDDAVG =
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APA2035
Application Descriptions
BTL Amplifier Efficiency (Cont.) Efficiency of a BTL configuration: PO VP x VP 2VP VP =( ) / (VDD x )= PSUP 2RL RL 4VDD tion10 states the maximum power dissipation point for a SE mode operating at a given supply voltage and driving a specified load. (9) SE mode : PD,MAX =
Table 2 calculates efficiencies for four different output power levels. Note that the efficiency of the amplifier is
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VDD 2 RL
(10)
In BTL mode operation, the output voltage swing is doubled as in SE mode. Thus the maximum power dissipation point for a BTL mode operating at the same given conditions is 4 times as in SE mode. 2 BTL mode : PD,MAX = 4V DD 2 2 R L (11)
quite low for lower power levels and rises sharply as power to the load is increased resulting in a nearly flat internal power dissipation over the normal operating
range. Note that the internal dissipation at full output power is less than in the half power range. Calculating the efficiency for a specific system is the key to proper power supply design. For a stereo 1W audio system with 8 loads and a 5V supply, the maximum draw on the power supply is almost 3W.
Po (W) 0.25 0.50 1.00 1.25 Efficiency (%) 31.25 47.62 66.67 78.13 IDD(A) 0.16 0.21 0.30 0.32 VPP(V) 2.00 2.83 4.00 4.47 PD (W) 0.55 0.55 0.5
Since the APA2035 is a dual channel power amplifier, the maximum internal power dissipation is 2 times that both of equations depending on the mode of operation. Even with this substantial increase in power dissipation, the APA2035 does not require extra heatsink. The power dissipation from equation11, assuming a 5V-power supply and an 8 load, must not be greater than the power dissipation that results from the equation13: PD,MAX =
TJ.MAX - TA JA
(12)
0.35
**High peak voltages cause the THD to increase. Table 2. Efficiency Vs Output Power in 5V/8 BTL Systems
For TSSOP-24 package with and without thermal pad, the thermal resistance (JA) is equal to 45oC/W. Since the maximum junction temperature (TJ,MAX) of APA2035 is 150oC and the ambient temperature (TA) is defined by the power system design, the maximum power dissipation which the IC package is able to handle can be obtained from equation12. Once the power dissipation is greater than the maximum limit (P D,MAX), either the supply voltage (V DD ) must bedecreased, the load impedance (RL) must be increased or the ambient temperature should be reduced. Thermal Pad Considerations The thermal pad must be connected to ground. The
A final point to remember about linear amplifiers (either SE or BTL) is how to manipulate the terms in the efficiency equation to utmost advantage whenpossible. Note that in equation, VDD is in the dominator. This indicates that as VDD goes down,efficiency goes up. In other words, use the efficiency analysis to choose the correct supply voltage and speaker impedance for the application. Power Dissipation Whether the power amplifier is operated in BTL or SE modes, power dissipation is a major concern. In equa
Copyright (c) ANPEC Electronics Corp. Rev. A.1 - Aug., 2006
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APA2035
Application Descriptions
the following equation. The maximum recommended Thermal Pad Considerations (Cont.) package with thermal pad of the APA2035 requires special attention on thermal design. If the thermal design issues are not properly addressed, the APA2035 4 will go into thermal shutdown when driving a 4 load.
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junction temperature for the APA2035 is 150C. The internal dissipation figures are taken from the Power Dissipation vs. Output Power graphs (Page15). TA,Max = TJ,Max -APD 150 - 45(0.8*2) = 78C (TSSOP-P24) The APA2035 is designed with a thermal shutdown protection that turns the device off when the junction temperature surpasses 150C to prevent damaging the IC. (13)
The thermal pad on the bottom of the APA2035 should be soldered down to a copper pad on the circuit board. Heat can be conducted away from the thermal pad through the copper plane to ambient. If the copper plane is not on the top surface of the circuit board, 8 to 10 vias of 13 mil or smaller in diameter should be used to thermally couple the thermal pad to the bottom plane. For good thermal conduction, the vias must be plated through and solder filled. The copper plane used to conduct heat away from the thermal pad should be as large as practical. If the ambient temperature is higher than 25C, a larger copper plane or forced-air cooling will be required to keep the APA2035 junction temperature below the thermal shutdown temperature (150C). In higher ambient temperature, higher airflow rate and/ or larger copper area will be required to keep the IC out of thermal shutdown. Thermal Considerations Linear power amplifiers dissipate a significant amount of heat in the package under normal operating conditions. To calculate maximum ambient temperatures, first consideration is that the numbers from the Power Dissipation vs. Output Power graphs (page15) are per channel values, so the dissipation of the IC heat needs to be doubled for two-channel operation. Given JA, the maximum allowable junction temperature (T J,MAX), and the total internal dissipation (PD), the maximum ambient temperature can be calculated with
Copyright (c) ANPEC Electronics Corp. Rev. A.1 - Aug., 2006 21
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APA2035
Packaging Information
TSSOP/ TSSOP-P (Reference JEDEC Registration MO-153)
e N
2x E/2
D A2 E1 E b A1 A
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1 23 e/2
D1 b
(
2) GAUGE PLANE
EXPOSED THERMAL PAD ZONE E2
S
0.25
L (L1)
1
BOTTOM VIEW (THERMALLY ENHANCED VARIATIONDS ONLY)
( 3)
Dim A A1 A2 b D
Millimeters Max. 1.2 0.00 0.15 0.80 1.05 0.19 0.30 6.6 (N=20PIN) 6.4 (N=20PIN) 7.9 (N=24PIN) 7.7 (N=24PIN) 9.6 (N=28PIN) 9.8 (N=28PIN) 4.2 BSC (N=20PIN) 4.7 BSC (N=24PIN) 3.8 BSC (N=28PIN) 0.65 BSC 6.40 BSC 4.30 4.50 3.0 BSC (N=20PIN) 3.2 BSC (N=24PIN) 2.8 BSC (N=28PIN) 0.45 0.75 1.0 REF 0.09 0.09 0.2 0 8 12 REF 12 REF
22
Inches Max. 0.047 0.000 0.006 0.031 0.041 0.007 0.012 0.260 (N=20PIN) 0.252 (N=20PIN) 0.311 (N=24PIN) 0.303 (N=24PIN) 0.386 (N=28PIN) 0.378 (N=28PIN) 0.165 BSC (N=20PIN) 0.188 BSC (N=24PIN) 0.150 BSC (N=28PIN) 0.026 BSC 0.252 BSC 0.169 0.177 0.118 BSC (N=20PIN) 0.127 BSC (N=24PIN) 0.110 BSC (N=28PIN) 0.018 0.030 0.039REF 0.004 0.004 0.008 0 8 12 REF 12 REF
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Min.
Min.
D1 e E E1 E2 L L1 R R1 S 1 2 3
Copyright (c) ANPEC Electronics Corp. Rev. A.1 - Aug., 2006
APA2035
Physical Specifications
Terminal Material Lead Solderability Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb), 100%Sn Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3.
Reflow Condition
TP
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(IR/Convection or VPR Reflow)
tp Critical Zone T L to T P
Ramp-up
Temperature
TL Tsmax
tL
Tsmin Ramp-down ts Preheat
25
t 25 C to Peak
Tim e
Classificatin Reflow Profiles
Profile Feature Average ramp-up rate (TL to TP) Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) Time maintained above: - Temperature (TL) - Time (tL) Peak/Classificatioon Temperature (Tp) Time within 5C of actual Peak Temperature (tp) Ramp-down Rate Sn-Pb Eutectic Assembly 3C/second max. 100C 150C 60-120 seconds 183C 60-150 seconds See table 1 10-30 seconds Pb-Free Assembly 3C/second max. 150C 200C 60-180 seconds 217C 60-150 seconds See table 2 20-40 seconds
6C/second max. 6C/second max. 6 minutes max. 8 minutes max. Time 25C to Peak Temperature Notes: All temperatures refer to topside of the package .Measured on the body surface.
Copyright (c) ANPEC Electronics Corp. Rev. A.1 - Aug., 2006 23 www.anpec.com.tw
APA2035
Classification Reflow Profiles (Cont.)
Table 1. SnPb Entectic Process - Package Peak Reflow Temperatures 3 Package Thickness Volume mm <350 <2.5 mm 240 +0/-5C 2.5 mm 225 +0/-5C Volume mm 350 225 +0/-5C 225 +0/-5C
3
Table 2. Pb-free Process - Package Classification Reflow Temperatures 3 3 3 Volume mm Volume mm Volume mm www..com Package Thickness <350 350-2000 >2000 <1.6 mm 260 +0C* 260 +0C* 260 +0C* 1.6 mm - 2.5 mm 260 +0C* 250 +0C* 245 +0C* 2.5 mm 250 +0C* 245 +0C* 245 +0C* *Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means Peak reflow temperature +0C. For example 260C+0C) at the rated MSL level.
Reliability Test Program
Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B,A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78 Description 245C, 5 SEC 1000 Hrs Bias @125C 168 Hrs, 100%RH, 121C -65C~150C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms, 1tr > 100mA
Carrier Tape & Reel Dimensions
t P P1 D
Po E
F W
Bo
Ao
Ko D1
Copyright (c) ANPEC Electronics Corp. Rev. A.1 - Aug., 2006
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APA2035
Carrier Tape & Reel Dimensions (Cont.)
T2
J C A B
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T1
Reel Dimensions
Application A 330 1 TSSOP- 24 F 7.5 0.1 B 100 ref D 1.5 +0.1 C 13 0.5 D1 1.5 min J 2 0.5 Po 4.0 0.1 T1 16.4 0.2 P1 2.0 0.1 T2 2 0.2 Ao 6.9 0.1 W 16 0.3 Bo 8.3 0.1 P 12 0.1 Ko 1.5 0.1 E 1.750.1 t 0.30.05
(mm)
Cover Tape Dimensions
Application TSSOP- 24 Carrier Width 16 Cover Tape Width 21.3 Devices Per Reel 2000
Customer Service
Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 7F, No. 137, Lane 235, Pac Chiao Rd., Hsin Tien City, Taipei Hsien, Taiwan, R. O. C. Tel : 886-2-89191368 Fax : 886-2-89191369
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