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Features

Applications

Bidirectional EMI filtering Four individual TVS diodes ESD protection >25k volts Protects 8 lines (4+4)
Cell phones PDAs and notebooks Digital cameras MP3 players and GPS
2FAK-C15R - Integrated Passive & Active Device using CSP
General Information The 2FAK-C15R device, manufactured using Thin Film on Silicon technology, provides ESD protection and EMI filtering for the data port of portable electronic devices such as cell phones, modems and PDAs. The device incorporates four low pass filter channels where each channel has a series 100 ohm resistor assuring a minimum of -30 dB attenuation from 800 MHz to 3 GHz. The device is suitable for EMI filtering of GSM, CDMA, W-CDMA, WLAN and Bluetooth frequencies. In addition, four individual TVS diodes are provided for ESD protection. Each internal and external port of the six channels includes a TVS diode for ESD protection. The ESD protection provided by the component enables a data port to withstand a minimum 8 KV Contact / 15 KV Air Discharge per the ESD test method specified in IEC 61000-4-2. The device measures 1.33 mm x 2.96 mm and is available in a 15 bump CSP package intended to be mounted directly onto an FR4 printed circuit board. The CSP device meets typical thermal cycle and bend test specifications without the use of an underfill material.
Electrical & Thermal Characteristics
SOLDER BUMPS SILICON DIE
Electrical Characteristics
(TA = 25 C unless otherwise noted) Per Line Specification Resistance Capacitance @ 2.5 V 1 MHz Rated Standoff Voltage Breakdown Voltage @ 1 mA Forward Voltage @ 10 mA Leakage Current @ 3.3 V Filter Attenuation @ 800 - 3000 MHz ESD Protection: IEC 61000-4-2 Contact Discharge Air Discharge
Symbol
R C VWM VBR VF IR S21
Minimum
80 24 6.0
Nominal
100 30 5.0 0.8 0.1 -35
Maximum
120 36
Unit
pF V V V A dB kV kV
0.5
-30 8 15
Thermal Characteristics
(TA = 25 C unless otherwise noted) Operating Temperature Range Storage Temperature Range Power Dissipation Per Resistor TJ TSTG PD -40 -55 25 25 +85 +150 100 C C mW
Reliable Electronic Solutions
Asia-Pacific: TEL +886- (0)2 25624117 * FAX +886- (0)2 25624116 Europe: TEL +41-41 768 5555 * FAX +41-41 768 5510 North America: TEL +1-951 781-5492 * FAX +1-951 781-5700
www.bourns.com
Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications.
2FAK-C15R - Integrated Passive & Active Device using CSP
Mechanical Characteristics This is a silicon-based device and is packaged using chip scale packaging technology. Solder bumps, formed on the silicon die, provide the interconnect medium from die to PCB. The bumps are arranged on the die in a regular grid formation. The grid pitch is 0.5 mm and the dimensions for the packaged device are shown below.
0.432 - 0.559 (0.017 - 0.022) 0.3 (0.012) DIA. 2.915 - 3.005 (0.115 - 0.118) 0.435 (0.017)
C1
C2
C3
C4
C5
C6
1.285 - 1.375 (0.051 - 0.054)
B1 B2 B3
A1
A2
A3
A4
A5
A6
0.330 - 0.457 (0.013 - 0.018)
0.50 (0.020)
0.25 (0.01) 0.180 - 0.280 (0.007 - 0.011)
0.435 (0.017) 0.180 - 0.280 (0.007 - 0.011) MILLIMETERS (INCHES)
DIMENSIONS =
Reliability Data Reliability data is gathered on an ongoing basis for Bourns(R) Integrated Passive and Active Devices. "Package level" testing of the integrity of the solder joint is carried out on an independent Daisy-Chain test device. A 25-Pin Daisy Chain component is available from Bourns for this purpose (part number 2TAD-C25R). This is a 5 x 5 array featuring 0.5 mm pitch solder bumps. The Distance to Neutral Point (DNP) on that component is similar to that of the 2FAK-C15R and is thus deemed suitable for Thermal Cycle testing. "Silicon level" reliability performance is based on similarity to other integrated passive CSP devices from Bourns.
Frequency Response
0 -10 -20 -30 -40 -50 -60 0.1
Loss - dB
1.0
10.0
100.0
1000.0
1000.0
Frequency - MHz
Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications.
2FAK-C15R - Integrated Passive & Active Device using CSP
Block Diagram The CSP device block diagram below includes the pin names and basic electrical connections associated with each channel.
EXT1 EXT8
PCB Design and SMT Processing Please consult the "Bourns Design Guide Using CSP" for notes on PCB design and SMT Processing.
How to Order
GND
2 FAK - C15R__
Thinfilm Model Chipscale
EXT2 R1: 100 ohms
INT2
No. of Solder Bumps Packaging Option R = Tape and Reel Packaged 3000 pcs. / 7 " reel
EXT3
R2: 100 ohms
INT3
GND
EXT4 R3: 100 ohms
INT4
EXT5
R4: 100 ohms
INT5
GND
EXT6
EXT7
Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications.
2FAK-C15R - Integrated Passive & Active Device using CSP
Device Pin Out The pin-out for the device is shown below with the bumps facing up.
A
EXT1
B
C
EXT8
1 2 3 4 5 6
GND x 3
EXT2
INT2
EXT3
INT3
Pin Out A1 A2 A3 A4 A5 A6 B1 B2 B3
Function EXT1 EXT2 EXT3 EXT4 EXT5 EXT6 GND GND GND
Pin Out C1 C2 C3 C4 C5 C6
Function EXT8 INT2 INT3 INT4 INT5 EXT7
EXT4
INT4
EXT5
INT5
EXT6
EXT7
Packaging The surface mount product is packaged in an 8 mm x 4 mm Tape and Reel format per EIA-481 standard.
TOP SIDE VIEW (INTO COMPONENT POCKET) DIMENSIONS = 0.3 0.05 (.01 .002) 2.00 0.05 (.08 .002) 4.0 0.1 (.16 .004) 1.5 0.1/-0 (.06 .004/-0) DIA. MILLIMETERS (INCHES)
1.75 0.10 (.07 .004)
R
0.3 MAX. (0.01)
8.0 0.3 (.31 .01) 3.5 0.05 (.14 .002) 1.52 0.1 (.06 .004) 4.0 0.1 (.16 .004) R 0.25 TYP. (0.010)
0.76 0.1 (.03 .004)
3.18 0.1 (0.13 0.004)
ORIENTATION OF COMPONENT IN POCKET BACKSIDE FACING UP
COPYRIGHT(c) 2004, BOURNS, INC. LITHO IN U.S.A. 08/04 e/IPA0411 2FAK-C15R REV. A, 8/04
Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications.

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