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| a Fast, High Voltage Drive, 6-Channel Output DecDriver(R) Decimating LCD Panel Driver AD8381 FUNCTIONAL BLOCK DIAGRAM 10 DB (0:9) 10 10 DAC VID0 2-STAGE LATCH FEATURES High Voltage Drive: Rated Settling Time to within 1.3 V of Supply Rails Output Overload Protection High Update Rates: Fast, 100 Ms/s 10-Bit Input Word Rate Low Power Dissipation: 570 mW Includes STBY Function Voltage Controlled Video Reference (Brightness) and Full-Scale (Contrast) Output Levels 3.3 V or 5 V Logic and 9 V to 18 V Analog Supplies High Accuracy: Laser Trimming Eliminates External Calibration Flexible Logic: INV Reverses Polarity of Video Signal STSQ/XFR for Parallel AD8381 Operation in 12-Channel Systems Drives Capacitive Loads: 27 ns Settling Time to 1% into 150 pF Load Slew Rate 265 V/ s with 150 pF Load Available in 48-Lead LQFP APPLICATIONS LCD Analog Column Driver 10 AD8381 10 STBY BYP BIAS 10 2-STAGE LATCH 10 DAC VID1 2-STAGE LATCH 10 DAC VID2 2-STAGE LATCH 10 DAC VID3 E/O R/L CLK STSQ XFR 10 2-STAGE LATCH 10 DAC VID4 10 SEQUENCE CONTROL 2-STAGE LATCH 10 DAC VID5 SCALING CONTROL VREFHI VREFLO INV VMID PRODUCT DESCRIPTION The AD8381 provides a fast, 10-bit latched decimating digital input, which drives six high voltage outputs. Ten-bit input words are sequentially loaded into six separate high speed, bipolar DACs. Flexible digital input format allows several AD8381s to be used in parallel for higher resolution displays. STSQ synchronizes sequential input loading, XFR controls synchronous output updating and R/L controls the direction of loading as either left-to-right or right-to-left. Six channels of high voltage output drivers drive to within 1.3 V of the rail in rated settling time. The output signal can be adjusted for brightness, signal inversion, and contrast for maximum flexibility. The AD8381 is fabricated on ADI's proprietary, fast bipolar 24 V process, providing fast input logic, bipolar DACs with trimmed accuracy and fast settling, high voltage precision drive amplifiers on the same chip. The AD8381 dissipates 570 mW nominal static power. The STBY pin reduces power to a minimum, with fast recovery. The AD8381 is offered in a 48-lead 7 mm 7 mm 1.4 mm LQFP package and operates over the commercial temperature range of 0C to 85C. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) 2003 Analog Devices, Inc. All rights reserved. AD8381-SPECIFICATIONS T Model VIDEO DC PERFORMANCE VDE VCME REFERENCE INPUTS VMID Range2 VMID Bias Current VREFHI VREFLO VREFHI Input Resistance VREFLO Bias Current VREFHI Input Current VFS Range3 RESOLUTION Coding DIGITAL INPUT CHARACTERISTICS Input Data Update Rate CLK to Data Setup Time: t1 CLK to STSQ Setup Time: t3 CLK to XFR Setup Time: t5 CLK to Data Hold Time: t2 CLK to STSQ Hold Time: t4 CLK to XFR Hold Time: t6 tCLK HIGH tCLK LOW CIN IIH IIL VIH VIL VTH VIDEO OUTPUT CHARACTERISTICS Output Voltage Swing CLK to VID Delay4: t7 INV to VID Delay Output Current Output Resistance VIDEO OUTPUT DYNAMIC PERFORMANCE Data Switching Slew Rate Invert Switching Slew Rate Data Switching Settling Time to 1% Data Switching Settling Time to 0.25% Invert Switching Settling Time to 1% Invert Switching Settling Time to 0.25% CLK and Data Feedthrough5 All-Hostile Crosstalk6 Amplitude Glitch Duration POWER SUPPLY Supply Rejection (VDE) DVCC, Operating Range DVCC, Quiescent Current AVCC, Operating Range Total AVCC Quiescent Current STBY AVCC Current STBY DVCC Current OPERATING TEMPERATURE RANGE 1 (@ 25 C, AVCC = 15.5 V, DVCC = 3.3 V, VREFLO = VMID = 7 V, VREFHI = 9.5 V, MIN = 0 C, TMAX = 85 C, unless otherwise noted.) Min -7.5 -3.5 6.25 35 VREFLO VMID - 0.5 Typ +1.0 +0.5 Max +7.5 +3.5 9.25 77 AVCC VREFHI 0.07 165 5.75 Unit mV mV V mA V V kW mA mA V Bits 100 0 0 0 5 5 5 4.5 3.5 0.6 0.05 2.0 0.8 3 0.7 0.16 Ms/s ns ns ns ns ns ns ns ns pF mA mA V V V V ns ns mA W V/ms V/ms ns ns ns ns mV p-p mV p-p ns mV/V V mA V mA mA mA C Conditions TMIN to TMAX DAC Code 450 to 800 DAC Code 450 to 800 (VREFHI - VREFLO) = 2.5 V to VREFLO 20 0.01 125 0 Binary CLK Rise and Fall Time = 5 ns NRZ 10 E/O = HIGH Threshold Voltage AVCC - VOH, VOL - AGND 50% of VIDx 50% of VIDx 1.4 1 15.5 14 75 29 265 410 27 50 33 55 5 50 45 1.3 17.5 16 13.5 12 30 TMIN to TMAX, VO = 5 V Step, CL = 150 pF 32 75 40 100 AVCCx = +15.5 V 1 V 3 0.6 18 9 33 1.8 0.03 0 5.5 25 18 40 3 0.1 85 STBY = H STBY = H NOTES 1 VDE = Differential error voltage. VCME = Common-mode error voltage. See the Theory of Operation section. 2 See Figure 6 in Theory of Operation section. 3 VFS = 2 (VREFHI - VREFLO). See the Theory of Operation section. 4 Measured from 50% of falling CLK edge to 50% of output change. Measurement is made for both states of INV. 5 Measured on one output as CLK is driven and STSQ and XFR are held low. 6 Measured on one output as the other five are changing from 0x000 to 0x3FF for both states of INV. Specifications subject to change without notice. -2- REV. B AD8381 TIMING CHARACTERISTICS Parameter t1 t2 t3 t4 t5 t6 t7 CLK to Data Setup Time CLK to Data Hold Time CLK to STSQ Setup Time CLK to STSQ Hold Time CLK to XFR Setup Time CLK to XFR Hold Time CLK to VID Delay Conditions CLK Rise and Fall Time = 5 ns CLK Rise and Fall Time = 5 ns CLK Rise and Fall Time = 5 ns CLK Rise and Fall Time = 5 ns CLK Rise and Fall Time = 5 ns CLK Rise and Fall Time = 5 ns Min 0 5 0 5 0 5 13.5 Typ Max Unit ns ns ns ns ns ns ns 15.5 17.5 DB (0:9) -1 0 t1 CLK t2 t3,t5 STSQ, XFR t4,t6 Figure 1. Timing Requirement E/O = High DB (0:9) -1 0 t1 CLK t2 t3 STSQ t4 t5 XFR t6 Figure 2. Timing Requirements E/O = Low CLK XFR t7 VIDx Figure 3. Output Timing REV. B -3- AD8381 ABSOLUTE MAXIMUM RATINGS 1 MAXIMUM POWER DISSIPATION Supply Voltages AVCCx - AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 V DVCC - DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Input Voltages Maximum Digital Input Voltages . . . . . . . . DVCC + 0.5 V Minimum Digital Input Voltages . . . . . . . . DGND - 0.5 V Maximum Analog Input Voltages . . . . . . . . . AVCC + 0.5 V Minimum Analog Input Voltages . . . . . . . . AGND - 0.5 V Internal Power Dissipation2 LQFP Package @ 25C Ambient . . . . . . . . . . . . . . . . 2.7 W Output Short Circuit Duration . . . . . . . . . . . . . . . . . . Infinite Operating Temperature Range . . . . . . . . . . . . . . 0C to 85C Storage Temperature Range . . . . . . . . . . . . -65C to +125C Lead Temperature Range (Soldering 10 sec) . . . . . . . . 300C NOTES 1 Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to the absolute maximum ratings for extended periods may reduce device reliability. 2 48-lead LQFP Package: qJA = 45C/W (Still Air, 4-Layer PCB) qJC = 19C/W The maximum power that can be safely dissipated by the AD8381 is limited by its junction temperature. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately 150C. Exceeding this limit temporarily may cause a shift in the parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of 175C for an extended period can result in device failure. To ensure proper operation within the specified operating temperature range, it is necessary to limit the maximum power dissipation as follows: PDMAX = (TJMAX - TA)/qJA where: TJMAX = 150C. 3.5 MAXIMUM POWER DISSIPATION - W 3.0 2.5 Overload Protection The AD8381 employs a two-stage overload protection circuit that consists of an output current limiter and a thermal shutdown. The maximum current at any one output of the AD8381 is internally limited to 100 mA average. In the event of a momentary short circuit between a video output and a power supply rail (VCC or AGND), the output current limit is sufficiently low to provide temporary protection. The thermal shutdown debiases the output amplifier when the junction temperature reaches the internally set trip point. In the event of an extended short circuit between a video output and a power supply rail, the output amplifier current continues to switch between 0 mA and 100 mA typ with a period determined by the thermal time constant and the hysteresis of the thermal trip point. The thermal shutdown provides long term protection by limiting the average junction temperature to a safe level. Recovery from a momentary short circuit is fast, approximately 100 ns. Recovery from a thermal shutdown is slow and is dependent on the ambient temperature. 2.0 1.5 1.0 0.5 0 10 20 30 40 50 60 70 AMBIENT TEMPERATURE - C 80 90 Figure 4. Maximum Power Dissipation vs. Temperature ORDERING GUIDE Model AD8381JST AD8381-EB Temperature Package Range Description 0C to 85C 48-Lead LQFP Package Option ST-48 Evaluation Board CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8381 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. -4- REV. B AD8381 PIN CONFIGURATION AVCCDAC AGNDDAC VREFHI VREFLO VMID AGND0 STSQ NC CLK XFR 48 47 46 45 44 43 42 41 40 39 38 37 NC 1 DB0 2 DB1 3 DB2 DB3 DB4 DB5 4 5 6 7 NC NC PIN 1 IDENTIFIER 36 35 34 33 VID0 AVCC0, 1 VID1 AGND1, 2 VID2 AVCC2, 3 VID3 AGND3, 4 VID4 AVCC4, 5 VID5 AGND5 AD8381 TOP VIEW (Not to Scale) 32 31 30 29 28 27 26 25 DB6 8 DB7 9 DB8 10 DB9 11 NC 12 13 14 15 16 17 18 19 20 21 22 23 24 NC = NO CONNECT PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function No Connect Data Input Even/Odd Select 10-Bit Data Input MSB = DB (9). The active CLK edge is the rising edge when this input is held high, and it is the falling edge when this input is held low. Data is loaded sequentially on the rising edges of CLK when this input is high and loaded on the falling edges when this input is low. A new data loading sequence begins on the left, with Channel 0, when this input is low, and on the right, with Channel 5, when this input is high. When this pin is high, the analog output voltages are above VMID. When low, the analog output voltages are below VMID. This pin is normally connected to the analog ground plane. Digital Power Supply. Analog Power Supplies. When high, the internal circuits are debiased and the power dissipation drops to a minimum. A 0.1 mF capacitor connected between this pin and AGND ensures optimum settling time. These pins are normally connected to the analog ground plane. These pins are directly connected to the analog inputs of the LCD panel. The voltage applied between this pin and AGND sets the midpoint reference of the analog outputs. This pin is normally connected to VCOM. The voltage applied between Pins 39 and 40 sets the full-scale output voltage. The voltage applied between Pins 39 and 40 sets the full-scale output voltage. A new data loading sequence begins on the rising edge of CLK when this input was high on the preceding rising edge of CLK and the E/O input is held high. A new data loading sequence begins on the falling edge of CLK when this input was high on the preceding falling edge of CLK and the E/O input is held low. Data is transferred to the outputs on the immediately following falling edge of CLK when this input is high on the rising edge of CLK. Clock Input. Description 1, 12, 19, 23, NC 24, 43-45 2-11 DB (0:9) 13 E/O 14 15 16 17 18, 27, 31 35, 42 20 21 22, 25, 29 33, 37, 41 26, 28, 30, 32, 34, 36 38 39 40 46 R/L INV DGND DVCC AVCCx STBY BYP AGNDx VID5, VID4, VID3, VID2, VID1, VID0 VMID VREFLO VREFHI STSQ Right/Left Select Invert Digital Supply Return Digital Power Supply Analog Power Supplies Standby Bypass Analog Supply Returns Analog Outputs Midpoint Reference Full-Scale Reference Full-Scale Reference Start Sequence 47 48 XFR CLK Data Transfer Clock REV. B -5- STBY BYP AGNDBIAS NC NC E/O R/L INV DGND AVCCBIAS DVCC NC AD8381-Typical Performance Characteristics 12V 12V VMID = 7V VFS = 5V VIDx CL 150pF VMID = 7V VFS = 5V VIDx CL 150pF 2V 20ns/DIV 2V 20ns/DIV TPC 1. Invert Switching 10 V Step Response (Rise) at CL TPC 4. Invert Switching 10 V Step Response (Fall) at CL 7V 7V VMID = 7V VFS = 5V VIDx CL 150pF VMID = 7V VFS = 5V VIDx CL 150pF 2V 2V 10ns/DIV 10ns/DIV TPC 2. Data Switching 5 V Step Response (Rise) at CL, INV = L TPC 5. Data Switching 5 V Step Response (Fall) at CL, INV = L 12V VMID = 7V VFS = 5V VIDx CL 150pF 12V VMID = 7V VFS = 5V VIDx CL 150pF 7V 7V 20ns/DIV 20ns/DIV TPC 3. Data Switching 5 V Step Response (Rise) at CL, INV = H TPC 6. Data Switching 5 V Step Response (Fall) at CL, INV = H -6- REV. B AD8381 0.25% 0.00% -0.25% -0.50% -0.75% -1.00% VMID = 7V VFS = 5V VIDx CL 150pF 7V 1.00% 0.75% 0.50% 0.25% 0.00% -0.25% -0.50% t=0 10ns/DIV -0.75% t = 0 -1.00% 10ns/DIV 2V VMID = 7V VFS = 5V VIDx CL 150pF TPC 7. Output Settling Time (Rising Edge) at CL, 5 V Step, INV = Low TPC 10. Output Settling Time (Falling Edge) at CL, 5 V Step, INV = Low VMID = 7V VFS = 5V 1.00% 0.00% -0.25% -0.50% -0.75% -1.00% t=0 10ns/DIV VMID = 7V VFS = 5V VIDx CL 150pF 12V 0.75% 0.50% 0.25% 0.00% -0.25% -0.50% -0.75% 10ns/DIV t=0 7V VIDx CL 150pF TPC 8. Output Settling Time (Rising Edge) at CL, 5 V Step, INV = High TPC 11. Output Settling Time (Falling Edge) at CL, 5 V Step, INV = High +30mV +20mV +10mV VID5 VMID = 7V -10mV -20mV VID0 - VID4 +10mV VMID = 7V -10mV 5V DB (0:9) 20ns/DIV 20ns/DIV TPC 9. All-Hostile Crosstalk at CL TPC 12. Data Switching Transient (Feedthrough) at CL REV. B -7- AD8381 0.5 0.4 0.3 0.2 DNL - LSB DNL - LSB 0.5 0.4 0.3 0.2 0.1 0.0 -0.1 -0.2 -0.3 -0.4 0 256 512 INPUT CODE 768 1023 -0.5 0 256 512 INPUT CODE 768 1023 0.1 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 TPC 13. Differential Nonlinearity (DNL) vs. Code, INV = H TPC 16. Differential Nonlinearity (DNL) vs. Code, INV = L 0.5 0.4 0.3 0.2 INL - LSB INL - LSB 0.5 0.4 0.3 0.2 0.1 0.0 -0.1 -0.2 -0.3 -0.4 0.1 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 0 256 512 INPUT CODE 768 1023 -0.5 0 256 512 INPUT CODE 768 1023 TPC 14. Integral Nonlinearity (INL) vs. Code, INV = H TPC 17. Integral Nonlinearity (INL) vs. Code, INV = L 5 0 NORMALIZED VDE AT CODE 0 - mV 0 -20 CODE 512, INV = LOW VFS = 4V -5 VFS = 4V PSRR - dB -40 CODE 512, INV = HIGH VFS = 5V VFS = 5V -10 -15 -60 -20 VFS = 5.75V VFS = 5.75V -80 -25 5 6 7 8 VMID - V 9 10 11 10k 100k FREQUENCY - Hz 1M 5M TPC 15. Normalized VDE at Code 0 vs. VMID, AVCC = 15.5 V TPC 18. AVCC Power Supply Rejection vs. Frequency -8- REV. B AD8381 7.5 3.50 5.0 1.75 2.5 VCME - mV VDE - mV 0.0 0.00 -2.5 -1.75 -5.0 -7.5 -3.50 0 256 512 INPUT CODE 768 1023 0 256 512 INPUT CODE 768 1023 TPC 19. Differential Error Voltage (VDE) vs. Code TPC 21. Common-Mode Error Voltage (VCME) vs. Code 7.5 3.50 5.0 1.75 2.5 CODE 512 0.0 VCME - mV VDE - mV CODE 512 0.00 -2.5 -1.75 -5.0 -7.5 -3.50 0 20 40 60 TEMPERATURE - C 80 100 0 20 40 60 TEMPERATURE - C 80 100 TPC 20. Differential Error Voltage (VDE) vs. Temperature TPC 22. Common-Mode Error (VCME) vs. Temperature REV. B -9- AD8381 FUNCTIONAL DESCRIPTION Data Transfer to Outputs (XFR Control) The AD8381 is a system building block designed to directly drive the columns of LCD panels of the type popularized for use in data projectors. It comprises six channels of precision 10-bit digital-to-analog converters loaded from a single, high speed, 10-bit-wide input. Precision current feedback amplifiers, providing well-damped pulse response and rapid voltage settling into large capacitive loads, buffer the six outputs. Laser trimming at the wafer level ensure low absolute output errors and tight channelto-channel matching. In addition, tight part-to-part matching in high channel count systems is guaranteed by the use of an external voltage reference. Input Data Loading (STart SeQuence Control--STSQ) Data transfer to all outputs is initiated by the XFR control input. When XFR is held high during a rising CLK edge, data is simultaneously transferred to all outputs on the immediately following falling CLK edge. VCOM Reference (VMID Reference Input) An external analog reference voltage connected to this input sets the reference level at the outputs. This input is normally connected to VCOM. Full-Scale Output (VREFHI, VREFLO Reference Inputs) A valid STSQ control input initiates a new six-clock pulse loading cycle, during which six input data words are loaded sequentially into six internal channels. A new loading sequence begins on the current active CLK edge only when STSQ was held high at the preceding active CLK edge. Data Loading--Expanded Systems (Even/Odd Control) The difference between two external analog reference voltages, connected to these inputs, sets the full-scale output voltage at the outputs. VREFLO is normally tied to VMID. Analog Voltage Inversion (INVert Control) To facilitate expanded, even/odd systems, the active CLK edge, at which input data is loaded, is set with the E/O control input. Input data is loaded on rising CLK edges while the E/O input is held high and loaded on falling CLK edges while the E/O input is held low. Data Loading--Inverted Images (Right/Left Control) To facilitate systems that use column, row or pixel inversion, the analog output voltage inversion is controlled by the INV control input. While INV is high, the analog voltage equivalent of the input code is subtracted from (VMID + VFS) at each output. While INV is low, the analog voltage equivalent of the input code is added to (VMID - VFS) at each output. Standby Mode (STBY Control) To facilitate image mirroring, the order in which input data is loaded is set with the R/L input. A new loading sequence begins at Channel 0 and proceeds to Channel 5 when the R/L input is held high and begins at Channel 5 and proceeding to Channel 0 when the R/L input is held low. A high applied to the STBY input debiases the internal circuitry, dropping the quiescent power dissipation to a few milliwatts. Since both digital and analog circuits are debiased, all stored data will be lost. Upon returning STBY to low, normal operation is restored. -10- REV. B AD8381 TRANSFER FUNCTION The AD8381 has two regions of operation, selected by the INV input, where the video output voltages are either above or below a reference voltage, applied externally at the VMID input. The transfer function defines the analog output voltage as the function of the digital input code as follows: E n VOUT = VMID VFS A1 - E 1023 where: n = input code VFS = 2 (VREFHI - VREFLO) VOUT (V) AVCC (VMID + VFS) VDE, the differential error voltage, measures the deviation of the rms value of the output from the rms value of the ideal. It is dependent on the difference between the output amplitudes VOUTN(n) and VOUTP(n) at a particular code. The defining expression is VDE = E E 1 n (VOUTN ( n ) - VOUTP ( n )) - AVFS A1 - E 1023 2 E where: 1 (VOUTN ( n ) - VOUTP ( n )) is the rms value of the output. 2 (VFS (1 - n/1023)) is the rms value of the ideal. VCME, the common-mode error voltage, measures the deviation of the average value of the output from the average value of the ideal. It is dependent on the average between the output amplitudes VOUTN(n) and VOUTP(n) at a particular code. The defining expression is: VCME = 1 E1 A (VOUTN ( n ) + VOUTP ( n )) - VMID 2 E2 INV = HIGH VOUTN(n) where: VMID 1 (VOUTN ( n ) + VOUTP ( n )) is the average value of the output. 2 INV = LOW VOUTP(n) VMID is the average value of the ideal. MAXIMUM FULL-SCALE OUTPUT VOLTAGE (VMID - VFS) The following conditions limit the range of usable output voltages: AGND 0 INPUT CODE 1023 The internal DACs limit the minimum allowed voltage at the VMID input to 5.3 V. The scale factor control loop limits the maximum full-scale output voltage to 5.75 V. The output amplifiers settle cleanly at voltages within 1.3 V from the supply rails. The common-mode range of the output amplifiers limit the maximum value of VMID to AVCC - 3. Figure 5. Transfer Function The region over which the output voltage varies with input code is selected by the INV input. When INV is low, the output voltage increases from (VMID - VFS), (where VFS = the full-scale output voltage), to VMID as the input code increases from 0 to 1023. When INV is high, the output voltage decreases from (VMID + VFS) to VMID with increasing input code. For each value of input code there are then two possible values of output voltage. When INV is low, the output is defined as VOUTP(n) where n is the input code and P indicates the operating region where the slope of the transfer function is positive. When INV is high, the output is defined as VOUTN(n) where N indicates the operating region where the slope of the transfer function is negative. ACCURACY At any given valid value of VMID, the voltage required to reach any one of the above limits defines the maximum usable fullscale output voltage VFSMAX. VFSMAX is the envelope in Figure 6. The valid range of VMID is the shaded area. VFS (V) AVCC/2 AVCC/2-1.3 To best correlate transfer function errors to image artifacts, the overall accuracy of the AD8381 is defined by two parameters, VDE and VCME. 5.75 4.3 VALID VMID 2 5.3 0 7 AVCC-7 AVCC/2 VMID (V) AVCC-3 AVCC Figure 6. VFSMAX vs. VMID REV. B -11- AD8381 Operating Modes--6-Channel Systems PIXEL CLK The simplest full color LCD based system is characterized by an image processor with a single 10-bit-wide data bus and a 6-channel LCD per color. Such systems usually have VGA or SVGA resolution and require a single AD8381 per color. INPUTS DB (0:9) -3 -2 -1 0 1 CLK STSQ EVEN STSQ ODD XFR R/L E/O EVEN E/O ODD 2 3 4 5 67 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 The INV input facilitates column and row inversion for these systems. DB(0:9) -1 0 1 2 3 4 5 6 7 8 9 10 11 12 INPUTS CLK STSQ XFR CH0 INTERNAL LATCHES 0 2 4 6 8 -2 -12 -10 -8 -6 -4 -2 10 0 2 4 6 8 12 14 16 18 20 22 12 14 16 18 20 22 INTERNAL LATCHES CH 0 CH 1 CH 2 CH 3 CH 4 CH 5 VID0 VID1 -1 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 0 1 2 3 4 5 6 7 8 9 12 CH1 CH2 CH3 CH4 CH5 VID0 VID1 10 11 6 7 8 9 10 11 AD8381 EVEN OUTPUT VID2 VID3 VID4 VID5 OUTPUTS VID2 VID3 VID4 VID5 10 CH0 INTERNAL LATCHES 1 3 5 7 -3 -1 -11 -9 -7 -5 -3 -1 9 11 1 3 5 7 9 11 13 15 17 19 21 23 13 15 17 19 21 23 CH1 CH2 CH3 CH4 CH5 VID0 VID1 Figure 7. 6-Channel System Timing Diagram, E/O = H, R/L = Low Single and dual data bus type 12-channel systems are commonly in use. The single data bus 12-channel system is characterized by an image processor with a single, 10-bit data bus and a 12-channel LCD per color. The maximum resolution of such a system is usually up to 85 Hz XGA or 75 Hz SXGA and requires two AD8381s per color. One AD8381 is set to run in even mode while the other is in odd mode. Both AD8381s share the same data bus and CLK. The timing diagram of such system is shown in Figure 8. The dual data bus 12-channel system is characterized by an image processor with two 10-bit parallel data buses and a 12-channel LCD. The maximum resolution of such system is usually up to 75 Hz UXGA and requires two AD8381s per color. Both AD8381s may be set to run in Even mode and may share the same CLK. The timing diagram of each AD8381 in such system is identical to that of the 6-channel system. The INV input facilitates column, row, and pixel inversion for both types of 12-channel systems. AD8381 ODD Operating Modes--12-Channel Systems OUTPUT VID2 VID3 VID4 VID5 Figure 8. Twelve-Channel Even/Odd System Timing Diagram Operating Modes--Large Channel Count Systems To facilitate 18, 24, or higher channel systems, any number of required AD8381s may be cascaded. -12- REV. B AD8381 IMAGE PROCESSOR DB(0:9) STSQ2 STSQ1 CLK CLK H. REVERSE CLK CLK 6 COUNTER DB(0:9) AD8381 PIXEL CLK +2 CLK XFR R/L STSQ1 INV1 E/O1 STSQ2 INV2 E/O2 CLK XFR R/L STSQ INV E/O VREFHI VMID VREFLO VID0 VID1 VID2 VID3 VID4 VID5 CH 0 CH 2 CH 4 CH 6 CH 8 CH 10 6 COUNTER HSTART HSYNC VSYNC INV1 INV2 12-CHANNEL LCD DB(0:9) AD8381 CLK XFR R/L STSQ INV E/O VREFHI VMID VREFLO VID0 VID1 VID2 VID3 VID4 VID5 CH 1 CH 3 CH 5 CH 7 CH 9 CH 11 REFERENCES VREFHI VCOM Figure 9. Single Data Bus 12-Channel Even/Odd System Block Diagram IMAGE PROCESSOR D(0:9) ODD D(0:9) EVEN PIXEL CLK H. REVERSE CLK 6 COUNTER HSTART "1" +2 DB1(0:9) CLK XFR R/L STSQ INV1 E/O INV2 DB(0:9) CLK XFR R/L STSQ INV E/O VREFHI VMID VREFLO AD8381 VID0 VID1 VID2 VID3 VID4 VID5 CH 0 CH 2 CH 4 CH 6 CH 8 CH 10 12-CHANNEL LCD D(0:9) EVEN D(0:9) ODD HSYNC VSYNC INV1 INV2 DB2(0:9) DB(0:9) AD8381 CLK XFR R/L STSQ INV E/O VREFHI VMID VREFLO VID0 VID1 VID2 VID3 VID4 VID5 CH 1 CH 3 CH 5 CH 7 CH 9 CH 11 REFERENCES VREFHI VCOM Figure 10. Dual Parallel Data Bus 12-Channel System Block Diagram REV. B -13- AD8381 LAYOUT CONSIDERATIONS The AD8381 is a mixed-signal, high speed, very accurate device. In order to realize its specifications, it is essential to use a properly designed printed circuit board. Layout and Grounding Each reference voltage should be distributed to each AD8381 directly from the source of the reference voltage with approximately equal trace lengths. A 0.1 mF chip capacitor should be placed as close to each reference input pin as possible and directly connected between the reference input pin and the analog ground plane. AVCCDAC AGNDDAC VREFLO VREFHI STSQ All signal trace lengths should be made as short and direct as possible to prevent signal degradation due to parasitic effects. Note that digital signals should not cross or be routed near analog signals. It is imperative to provide a solid analog ground plane under and around the AD8381. All of the ground pins of the part should be connected directly to the ground plane with no extra signal path length. For conventional operation this includes the pins DGND, AGNDDAC, AGNDBIAS, AGND0, AGND1,2, AGND3,4, and AGND5. The return traces for any of the signals should be routed close to the ground pin for that section to prevent stray signals from coupling into other ground pins. Power Supply Bypassing 48 47 XFR 46 45 44 43 40 39 38 VMID AGND0 CLK The analog outputs and the digital inputs of the AD8381 are pinned out on opposite sides of the package. When laying out the circuit board, keep these sections separate from each other to minimize crosstalk and noise and the coupling of the digital input signals into the analog outputs. 1 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 2 3 4 5 6 7 8 9 10 11 12 36 VID0 AVCC0 ,1 34 VID1 AGND1,2 32 VID2 AVCC2 ,3 30 VID3 AGND3,4 28 VID4 AVCC4 ,5 26 VID5 AGND5 All power supply and reference pins of the AD8381 must be properly bypassed to the analog ground plane for optimum performance. All analog supply pins may be connected directly to an analog supply plane located as close to the part as possible. A 0.1 mF chip capacitor should be placed as close to each analog supply pin as possible and connected directly between each analog supply pin and the analog ground plane. A minimum of 47 mF tantalum capacitor should be placed near the analog supply plane and connected directly between the supply and analog ground planes. A minimum of 10 mF tantalum capacitor should be placed near the digital supply pin and connected directly to the analog ground plane. A 0.1 mF chip capacitor should be connected between the digital supply pin and the analog ground. VREFHI, VMID, VREFLO Reference Distribution 13 14 15 17 19 20 21 23 AGNDBIAS INV 16 DGND DVCC TO ANALOG GROUND PLANE TO ANALOG SUPPLY PLANE Figure 11. To ensure well-matched video outputs, all AD8381s must operate from equal reference voltages. -14- AVCCBIAS STBY BYP E/O R/L 24 REV. B AD8381 OUTLINE DIMENSIONS 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters 0.75 0.60 0.45 1.60 MAX 48 1 9.00 BSC SQ 37 36 1.45 1.40 1.35 10 6 2 SEATING PLANE 0.20 0.09 7 3.5 0 0.08 MAX COPLANARITY PIN 1 TOP VIEW (PINS DOWN) 7.00 BSC SQ VIEW A 12 13 24 25 0.15 0.05 SEATING PLANE VIEW A ROTATED 90 CCW 0.50 BSC 0.27 0.22 0.17 COMPLIANT TO JEDEC STANDARDS MS-026BBC REV. B -15- AD8381 Revision History Location 10/03--Change from REV. A to REV. B. Page Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 C02480-0-10/03(B) 9/03--Change from REV. 0 to REV. A. -16- REV. B |
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