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| HS-0508RH, HS-0509RH Data Sheet August 1999 File Number 3977.2 Radiation Hardened Single 8/Differential 4-Channel CMOS Analog Multiplexers These radiation hardened monolithic CMOS multiplexers each include an array of eight analog switches, a digital decode circuit for channel selection, a voltage reference for logic thresholds, and an ENABLE input for device selection when several multiplexers are present. The Dielectric Isolation (DI) process used in fabrication of these devices eliminates the problem of latch-up. Also, DI offers much lower substrate leakage and parasitic capacitance than conventional junction-isolated CMOS. Switches are guaranteed to break-before-make, so that two channels are never shorted together. The switching threshold for each digital input is established by an internal +5V reference, providing a guaranteed minimum 2.4V for logic "1" and maximum 0.8 for logic "0". This allows direct interface without pull-up resistors to signals from most logic families: CMOS, TTL, DTL and some PMOS. For protection against transient overvoltage, the digital inputs include a series 200 resistor and a diode clamp to each supply. The HS-0508RH is an eight channel single-ended multiplexer, and the HS-0509RH is a four channel differential version. If input overvoltage protection is needed, the HS-0548RH and HS-0549RH multiplexers are recommended. Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed here must be used when ordering. Detailed Electrical Specifications for these devices are contained in SMD 5962-95692. A "hot-link" is provided on our homepage for downloading. http://www.intersil.com/spacedefense/space.htm Features * Electrically Screened to SMD # 5962-95692 * QML Qualified per MIL-PRF-38535 Requirements * Gamma Dose . . . . . . . . . . . . . . . . . . . . . . 1 x 104RAD(Si) * No Latch-Up * No Channel Interaction During Overvoltage * Low On Resistance . . . . . . . . . . . . . . . . . . . . <200 (Typ) * 44V Maximum Power Supply * Break-Before-Make Switch * Analog Signal Range . . . . . . . . . . . . . . . . . . . . . . . . 15V * Access Time. . . . . . . . . . . . . . . . . . . . . . . . . <300ns (Typ) Applications * Data Acquisition Systems * Control Systems * Telemetry Ordering Information ORDERING NUMBER 5962D9569201VEA 5962D9569201VEC 5962D9569202VEA 5962D9569202VEC INTERNAL MKT. NUMBER HS1-0508RH-Q HS1B-0508RH-Q HS1-0509RH-Q HS1B-0509RH-Q TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 Pinouts HS-0508RH GDIP1-T16 (CERDIP) OR CDIP2-T16 (SBDIP) TOP VIEW HS-0509RH GDIP1-T16 (CERDIP) OR CDIP2-T16 (SBDIP) TOP VIEW A0 1 ENABLE 2 -VSUPPLY 3 IN 1 4 IN 2 5 IN 3 6 IN 4 7 OUT 8 16 A1 15 A2 14 GND 13 +VSUPPLY 12 IN 5 11 IN 6 10 IN 7 9 IN 8 A0 1 ENABLE 2 -VSUPPLY 3 IN 1A 4 IN 2A 5 IN 3A 6 IN 4A 7 OUTA 8 16 A1 15 GND 14 +VSUPPLY 13 IN 1B 12 IN 2B 11 IN 3B 10 IN 4B 9 OUT B 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999 HS-0508RH, HS-0509RH Functional Diagrams HS-0508RH HS-0509RH IN1 IN2 DECODER/ DRIVER IN8 OUT IN1A IN4A IN1B IN4B DECODER/ DRIVER OUT A OUT B 5V REF LEVEL SHIFT 5V REF LEVEL SHIFT DIGITAL INPUT PROTECTION DIGITAL INPUT PROTECTION A0 A1 A2 EN A0 A1 EN HS-0508RH TRUTH TABLE A2 X L L L L H H H H A1 X L L H H L L H H A0 X L H L H L H L H EN L H H H H H H H H "ON" CHANNEL NONE 1 2 3 4 5 6 7 8 A1 X L L H H HS-0509RH TRUTH TABLE A0 X L H L H EN L H H H H "ON" CHANNEL PAIR NONE 1 2 3 4 2 HS-0508RH, HS-0509RH Schematic Diagrams V+ R9 Q1 Q4 D3 LEVEL SHIFTER V+ P P P P P P P P P LEVEL SHIFTED ADDRESS TO DECODE LEVEL SHIFTED ADDRESS TO DECODE R10 TTL REFERENCE CIRCUIT P OVERVOLTAGE PROTECTION V+ ADD IN. D2 R1 200 D1 VN N R2 R5 R3 N R4 R6 N N N N N R8 N N R7 V- FIGURE 1. ADDRESS INPUT BUFFER AND LEVEL SHIFTER +V TO P-CHANNED DEVICE OF THE SWITCH P P P P P P P FROM DECODE N18 N A0 OR A0 N N N V+ IN N19 N17 OUT N TO N-CHANNED DEVICE OF THE SWITCH A1 OR A1 P17 A2 OR A2 N A3 OR A3 V- N ENABLE DELETE A3 OR A3 INPUT FOR HI-507 DELETE A3 OR A3 INPUT FOR HI-508 DELETE A2 OR A2 INPUT FOR HI-509 P18 V- FROM DECODE FIGURE 2. ADDRESS DECODER FIGURE 3. MULTIPLEX SWITCH 3 HS-0508RH, HS-0509RH Burn-In/Life Test Circuits V1 F0 F3 V1 D1 C1 5 6 R1 7 8 12 D2 11 10 9 R1 C2 6 7 8 11 10 9 1 2 3 4 16 15 14 13 V2 D1 C1 5 12 D2 C2 F1 F2 V2 1 2 3 4 16 15 14 13 V3 HS-0508RH DYNAMIC BURN-IN AND LIFE TEST CIRCUIT V1 = V2 = R1 = C1 = D1 = F0 = F1 = F2 = F3 = -15V maximum, -16V minimum +15V minimum, +16V maximum 10k 5% 1/4W C2 = 0.01F minimum (per socket) or 0.1F minimum (per row) D2 = 1N4002 (or equivalent) 100kHz 50% duty cycle; VIL = 0.8V max; VIH = 4.0V min. F0/2 F1/2 F2/2 V1 = V2 = V3 = R1 = C1 = D1 = HS-0508RH STATIC BURN-IN TEST CIRCUIT 5V minimum, 6V maximum -15V maximum, -16V minimum +15V minimum, +16V maximum 10k 5% 1/4W C2 = 0.01F minimum (per socket) or 0.1F minimum (per row) D2 = 1N4002 (or equivalent) F0 F2 V3 D1 C1 1 2 3 4 5 6 7 8 16 15 14 13 F1 1 2 V2 V3 D1 C1 3 4 16 15 14 13 V1 V2 D1 C1 D1 12 11 10 9 R1 C1 5 6 7 8 12 11 10 9 R1 R1 R1 HS-0509RH DYNAMIC BURN-IN AND LIFE TEST CIRCUIT V2 = V3 = R1 = C1 = D1 = F0 = +15.5V, .0.5V -15.5V, 0.5V 10k, 5% 0.1F minimum (per socket) 1N4002 or equivalent (per board) 100kHz, 10%; F1 = F0/2; F2 = F1/2, 50% duty cycle, VIL = 0.8V max.; VIH = 4.0V min. V1 = V2 = V3 = R1 = C1 = D1 = HS-0509RH STATIC BURN-IN TEST CIRCUIT +5.5V, 0.5V +15.5V, 0.5V -15.5V, 0.5V 10k, 10% 0.1F minimum (per socket) 1N4002 or equivalent (per board) 4 HS-0508RH, HS-0509RH Irradiation Circuits HS-0509RH +5V 1 2 16 15 14 13 12 11 10 9 R2 +15V +1V -15V +1V 3 4 5 6 7 8 R1 R1 = R2 = 10k 5% HS-0508RH +5V 1 2 16 15 14 13 12 11 10 9 +15V +1V -15V +1V 3 4 5 6 7 8 R1 R1 = 10k 5% 5 HS-0508RH, HS-0509RH Die Characteristics DIE DIMENSIONS: 81.9mils x 90.2mils x 19mils INTERFACE MATERIALS: Glassivation: Type: Nitride Thickness: 7kA 0.7kA Top Metallization: Type: Al Thickness: 16kA 2kA Substrate: CMOS Dielectric Isolation Backside Finish: Silicon ASSEMBLY RELATED INFORMATION: Substrate Potential: Unbiased (DI) ADDITIONAL INFORMATION: Worst Case Current Density: < 2.0 x 105 A/cm2 Transistor Count: HS-0508RH HS-0509RH 243 243 Metallization Mask Layout HS-0508RH EN A0 A1 A2 GND EN A0 A1 HS-0509RH GND -VSUP +VSUP -VSUP +VSUP IN 1 IN 2 IN 5 IN 1A IN 2A IN 1B IN 6 IN 2B IN 3 IN 7 IN 4 OUT IN 8 IN 3A IN 3B IN 4A OUT A OUT B IN 4B NOTE: Pad numbers correspond to DIP pin numbers only. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 6 |
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