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| PRELIMINARY DATA SHEET MICRONAS INTERMETALL CAP 3540B, CAP 3541B Car Audio Processor Hardware www..com MICRONAS Edition May 22, 1997 6251-434-1PD CAP 3540B, CAP 3541B Contents Page 3 3 Section 1. 1.1. Title Introduction Features Functional Description Architecture DSP Block Digital Part Analog Part Operating Modes Analog Input Systems Buffers ABUF Stereo Mixer AMIX Multiplexers AMUX A/D-Converters ADC Digital Signal Processing Block Digital Filter Sections Digital Mixing Systems Pilot Demodulator PILMX ARI Mixer ARIMIX FM Noise Canceller (ASU) Analog Output Systems D/A Converters DAC Lowpass-Filters ALPF Volume Control AVOL Programmable Digital Audio Interface (PDAI) The IM-Bus Interface of the CAP 3540B Description of the IM-Bus Clock Generation Specifications Outline Dimensions Pin Connections and Short Descriptions Pin Descriptions Pin Configuration Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions Recommended Crystal Characteristics Characteristics Starting the Processor Synthesizer Application Notes Typical Application Circuit Index Data Sheet History PRELIMINARY DATA SHEET 4 2. 4 2.1. 4 2.1.1. 4 2.1.2. 4 2.1.3. 6 2.1.4. 7 2.2. 7 2.2.1. 8 2.2.2. 8 2.2.3. 8 2.2.4. 8 2.2.5. 8 2.2.5.1. 9 2.2.6. 9 2.2.6.1. 11 2.2.6.2. 12 2.2.7. 12 2.3. 12 2.3.1. 12 2.3.2. 12 2.3.3. 12 2.4. 14 2.5. 14 2.5.1. 16 2.6. www..com 17 17 18 20 22 23 23 24 26 27 31 31 32 33 34 36 2 3. 3.1. 3.2. 3.3. 3.4. 3.5. 3.5.1. 3.5.2. 3.5.3. 3.5.4. 4. 5. 6. 7. 8. 9. MICRONAS INTERMETALL PRELIMINARY DATA SHEET CAP 3540B, CAP 3541B 1.1. Features - High-quality audio A/D converters with input selectors for several analog audio sources - D/A converters with 8-fold oversampling filters - Baseband audio processing (bass/treble, loudness, volume, balance and fader control) - Stereo decoder - Noise concealment for weak FM signals, including Automatic Separation Control, Hi-Blend and VolumeBlend function - Ignition noise canceller: removes peak noise from the audio signal and interpolates the disturbed audio samples - RDS processing: demodulation of the Radio Data System signal; RDS clock and data are available via hardware pins and software control bus - Deemphasis and 19 kHz Pilot tone filter for FM - Detection of field strength, multipath and peak noise levels - Music search for tape player - Freely programmable Digital Audio Interface for CD/ DCC and coprocessor applications (only with CAP 3540B) - Synthesizer with 3 current sources for fast FM/AM tuning A more detailed overview about the integrated DSP-features is given in the additional Application Note Software CAP 3540B. Car Audio Processor 1. Introduction The CAP 3540B Car Audio Processor is a new CMOS processor and represents the one-chip solution for a highly integrated AM/FM radio concept. The CAP 3540B is designed for car radio concepts and can also be used for home stereo receivers, as well as for PC radio cards. The CAP 3541B is especially designed for applications without digital audio sources. Digital audio input is not supported in the CAP 3541B. All other features are compatible to the CAP 3540B. In the following description, only the CAP 3540B is mentioned. The typical application consists of the following components: - Car Audio Processor CAP 3540B - conventional FM tuner and FM-IF stage - conventional AM tuner and AM-IF stage - microcontroller - analog and digital (only with CAP 3540B) audio sources - power amplifiers www..com MICRONAS INTERMETALL 3 CAP 3540B, CAP 3541B 2. Functional Description 2.1. Architecture The architecture of the CAP 3540B processor comprises three main function blocks: 2.1.1. DSP Block The DSP block consists of a "General-Purpose16-Bit Digital Signal Processor" which handles 24 million instructions per second. The data word length is 16 bits and the hardware multiplier operates with an initial word length of 16@10 with a 20-bit result. The memory covers 256@16+256@10 bit RAM and 2 k instruction ROM. 2.1.2. Digital Part A main portion consists of hardwired digital filters, such as decimation filters for the A/D converters and interpolation filters for D/A converters. The modulators for ARI/ RDS and pilot tone, as well as the complete circuitry for the ignition noise canceller are realized digitally. The logical conclusion for a higher integration is the incorporation of the synthesizer for AM and FM tuning into this hardware block. Naturally, the customary serial interfaces for digital audio signals are also included. 2.1.3. Analog Part In the analog part various input switches, A/D converters and D/A converters are combined. Five A/D converters handle the conversion of analog signals into digital signals. Two of these are specially designed for high qualiwww..com the conversion of an independent ty, one in particular for signal path for ARI/RDS signals and the remaining two to be used for the evaluation of analog signals of a lower quality standard (information on field strength and information from potentiometers). Two D/A converters, each equipped with an eightfold oversampling filter, generate analog output signals. These two outputs can be split up and distributed into four output stages via four independently adjustable volume control switches. PRELIMINARY DATA SHEET 4 MICRONAS INTERMETALL www..com MICRONAS INTERMETALL 5 PRELIMINARY DATA SHEET Fig. 2-1: CAP 3540B block diagram SCLKI SDIN1 WSI ERR Programmable Digital Audio Interface (not in CAP 3541B) SCLKO SDOUT SDIN2 WSO L+R MPX0 MPX Decoder L-R A/D 0 L-R AMR AML FM-Noise Reduction DSP Core Stereo Matrix Tone Control Pilot Filter Loudness Deemphasis Noise Reduction Volume Balance Input Select A/D 1 L+R Oversampled D/A DSP Output Buffer Analog Volume LF LR FM-Noise Detection Analog Volume TAPER TAPEL AUXR AUXL Pilot Mixer DSP Input Buffer A/D 2 ARI/RDS Mixer RDS Demodulation POT1/MPX1 POT2 POT3 POT4 POT5/AVC FMLEVEL MPLEVEL AMLEVEL Input Select Multipath Detection FM/AM-Level Detection Peak Noise Detection A/D3 Stereo PLL Filter Stereo Detection Stereo Soft Blend Hi-Blend Volume Blend Blank Search Beep Generator CAP 3540B, CAP 3541B Oversampled D/A Analog Volume RF RR Analog Volume Input Select A/D 4 Synthesizer Auxiliary Digital Inputs Auxiliary Digital Outputs IM-Bus Interface Clock QX1 FMIN AMIN AMTUNOUT FM TUNOUT TI1 TI2 TI3 TO1 TO2 TO3 IMDATA IMIDENT QX2/ECLK IMCLOCK CLKOUT CAP 3540B, CAP 3541B 2.1.4. Operating Modes The CAP 3540B possesses 3 main operating modes: 1. MPX-mode In this mode, the CAP 3540B receives the multiplex signal of an FM transmission, containing sum and difference channel, the pilot tone and the signals needed for travel information (ARI, RDS). The FM-demodulation has to take place inside the conventional tuner. The mixing of the difference band is done by an analog mixer in front of the A/D-converters in order to achieve the necessary quality for FM stereo. The ARI and RDS signals and the pilot tone are extracted digitally. 2. AF-mode PRELIMINARY DATA SHEET In this mode the CAP 3540B works transparently; the incoming signals are A/D-converted and then transmitted to the DSP core. 3. XDS-mode (not in CAP 3541B) In this mode there is an external digital source (XDS, e.g. a CD player) which sends its digital data to the CAP 3540B for further processing and for the reconverting to analog signals. The CAP 3540B can be adapted to the sampling rate (32 to 44,1 kHz) prescribed by the external digital source; in addition the input systems of the CAP 3540B remain active in order to monitor the traffic and field strength information. FM Tuner www..com FM IF MPX LF FMLEVEL LR FMTUNOUT FMOSCIN AMOSCIN AMTUNOUT CAP 3540B RF AML AM Tuner & IF RR AM LEVEL Controller Fig. 2-2: CAP 3540B system overview 6 MICRONAS INTERMETALL PRELIMINARY DATA SHEET CAP 3540B, CAP 3541B 2.2. Analog Input Systems Fig. 2-3 shows all analog inputs and functions of the switches S0 to S3. 38 kHz MPX0 AML TAPEL AUXL 1 2 0 After buffering (ABUF) and switching (AMUX) in the AFmode the signals are converted into digital form by 2 A/D converters (ADCs). Their output is 1 bit at a rate of 8.208 MHz; in each of the two channels in the CAP 3540B there is a cascade of 3 lowpass filters (LPF02, LPF23 and LPF34), which suppresses the high-frequency noise produced by the ADCs. The outputs of the filters LPF34 are 16 bits wide and are sampled with 38 kHz; these samples are transmitted via the input buffer to the DSP core. After processing in the DSP, the samples are interpolated to the eightfold sampling rate and converted into analog shape by 2 D/A converters (DACs), filtered (ALPF) and optionally attenuated (AVOL) to feed the power amplifiers which produce the signals for four loudspeakers. It is assumed that the process of stereo multiplexing used in radio broadcasting is known. The main FM-modulator can be modulated by the sum signal of left and right channel (in baseband), a pilot tone, the difference channel (AM-modulated, suppressed carrier), an optional ARI signal (AM-modulated, unsuppressed carrier), an optional RDS signal (AM-modulated, suppressed carrier) and optionally up to 3 SCA signals (FM-modulated). The composite signal is the so-called MPX signal. So a variety of signals ride "piggy-back" on the main carrier, which was originally assigned only for monophonic transmission. In the CAP 3540B, the SCA signals are regarded as disturbing signals while the others are regarded as useful. In the MPX-mode there is an analog mixer AMIX in front of the ADCs. It mixes the difference band down to baseband. The sum channel and the difference channel are then treated like the other baseband signals. Digital www..com quadrature mixers ARIMX and PILMX extract the RDSinformation and the information of the pilot signal, respectively. By means of digital mixers the pilot tone and the RDS (Radio Data System) signal are mixed down to zero intermediate frequency in quadrature representation, where their information is sampled and sent to the DSP core. The demodulation of the RDS signal is done by the DSP software. Beside these main blocks, there are other systems. The analog field strength information FS delivered by AM and FM tuners is A/D-converted; after lowpass-filtering (LPF06) the samples are sent to the DSP core, where the information could be used to control some parameters of the entire system. Other input signals, such as signals from external potentiometers are selected by an analog multiplexer, A/D-converted, lowpass-filtered and sent to the DSP or to the controller via the IM-bus interface (IMIF). The IM-bus interface is also able to receive data from the external microcontroller and to control the systems on the CAP 3540B. Main 1 S0 3 0 AMR TAPER AUXR 1 2 3 S0 Main 2 0 1 S2 ARI/RDS POT1/ MPX1 POT2 POT3 POT4*) POT5/ AVC 2 3 4 1 0 S3 5 0 Pot FMLEVEL MPLEVEL AMLEVEL 1 2 S1 Level *) POT4 not available in PSDIP64 package. Fig. 2-3: Analog input systems 2.2.1. Buffers ABUF The analog input buffers have to adjust the individual desired input levels in order to cover the entire volume range of the A/D-converters. The inputs can be divided into two groups: those which have to be connected via external capacitors, and those that are DC-coupled. Two of these inputs, the POT1/ MPX1 and POT5/AVC, are DC-coupled if used as POT1 resp. POT5, and AC-coupled if used as MPX1 resp. AVC. Note: Input pins POT1 to POT5 are switchable to digital outputs via the IM-bus interface. This feature is made possible by open drain transistors and external pull-up resistors down to 1 k. MICRONAS INTERMETALL 7 CAP 3540B, CAP 3541B 2.2.2. Stereo Mixer AMIX This analog demodulator mixes the incoming multiplex signal with the PLL-synchronized 38 kHz subcarrier in order to get the difference channel in baseband. The phase of the mixer signal is locked to the phase of the digital pilot demodulator; the phase shift between the two signals has to be compensated by the signal processor's Stereo PLL software. The realized modulator consists of an analog multiplexer switching among the original input signal, the inverted input signal and zero input. The desired fundamental 38 kHz component includes an additional factor of 1.10266 which has to be taken into account in the dematrix-software of the signal processor. m(t) 1 0 -1 T_0 12 T_0+1/f_0+1 T_0/12+1/(12f_0)+1/4s PRELIMINARY DATA SHEET 2.2.5. Digital Signal Processing Block 2.2.5.1. Digital Filter Sections After analog to digital conversion, the input signals are filtered by means of digital filters in order to decimate the high frequency PDM signals to an appropriate sampling rate. The second purpose of these filters is to suppress unwanted out-of-band signals and to shape the input signals to the desired response. After being processed in the DSP section, the digital samples are interpolated to a higher rate before being converted to the analog domain. The individual filter blocks can be seen in Fig. 2-5 and 2-6. Fig. 2-5 shows filter sections for the A/D side whereas in Fig. 2-6, filter blocks for the interpolation process on the D/A side can be seen. In the text of this data sheet, the filter blocks are referred to with the names indicated in the schematics. Most of the filters are designed as multirate FIR blocks. Fig. 2-7 shows the overall (A/D to D/A) passband characteristics of the main channels in TAPE or AUX mode. The shown 3 dB bandwidth is more than 18 kHz. Fig. 2-8 shows the same for the MPX case. An additional pilot notch filter (19 kHz) suppresses higher frequencies. In case of a locked stereo PLL, the suppression is ideal. Fig. 2-9 depicts the characteristics of the ARI/RDS bandpass. The near-by difference channel is attenuated sufficiently in order to minimize disturbing effects in the weak ARI/RDS signal. An additional lowpass with roll-off characteristics is done in the DSP software. In order to suppress out-of-band signals, the CAP 3540B is equipped with digital interpolation filters. These filters attenuate alias frequencies of up to eight times the sampling frequency. The interpolation block consists of three cascaded linear phase FIR filters. A simple sample and hold filter serves for the interpolation to the operating rate of the D/A converter. The overall interpolation rate is therefore 32. See Fig. 2-10 for the passband characteristics of the interpolation filter (plotted for 44.1 kHz sampling rate) and Fig. 2-11 for the stopband characteristics. T_0 Fig. 2-4: Difference channel mixing signal 2.2.3. Multiplexers AMUX The analog multiplexers allow the selection of one of the www..com input signals for each signal path. 2.2.4. A/D-Converters ADC The A/D-converters are realized as pulse density modulators (PDMs) running at a clock frequency of f_s0+8.208 MHz. The ADC0, ADC1 and the ADC2 are high quality double-loop PDMs with one external capacitor whereas ADC3 and ADC4 are low quality PDMs without any external capacitor. 8 MICRONAS INTERMETALL PRELIMINARY DATA SHEET CAP 3540B, CAP 3541B 2.2.6. Digital Mixing Systems 2.2.6.1. Pilot Demodulator PILMX The entire system is synchronized with the pilot tone of the FM-stereo channel. In the pilot-demodulator 2 mixers working in quadrature are used. The quadrature mixer is the phase detector of the PLL; the other parts of the PLL (loop filter and VCO) are realized in the DSP. The inphase mixer outputs information concerning the level of the pilot tone to the DSP to allow a decision "FM-stereo" or "FM-mono". The time relation between the mixer sequences of stereo-demodulator and pilot-demodulators is fixed. ASU HIGH PASS ASU DETECT AMMIX Main 1 A D A D LPF 02 36 PILOT NOTCH ASU LPF 23 3 AMMIX LPF 34 2 Main 2 LPF 02 36 PILOT NOTCH ASU LPF 23 3 LPF 34 2 PILMIX LPF 23 3 PILMIX ARI/ RDS LPF 35 8 A D LPF 35 8 LPF 01 18 DSP ARI MIX LPF 12 2 ARI MIX LPF 24 6 LPF 45 4 LPF 24 6 LPF 45 4 www..com Level A D A D LPF 06 540 POT LPF 05 864 Fig. 2-5: Digital signal processing blocks, input side 2 INT 12 4 INT 28 4 3 NOISE SHAPING D A DSP 2 INT 12 4 INT 28 4 3 NOISE SHAPING D A Fig. 2-6: Digital signal processing blocks, output side MICRONAS INTERMETALL 9 CAP 3540B, CAP 3541B dB 3 gain 0 PRELIMINARY DATA SHEET -3 0 2 4 6 8 10 12 f Fig. 2-7: Overall response TAPE/AUX channel 14 16 18 19 kHz dB 3 gain 0 -3 0 2 4 6 8 10 f 12 14 16 18 19 kHz www..com Fig. 2-8: Overall MPX response sum channel dB 0 gain -50 -100 0 50 f Fig. 2-9: ARI/RDS bandpass characteristic 100 kHz 10 MICRONAS INTERMETALL PRELIMINARY DATA SHEET CAP 3540B, CAP 3541B dB 3 gain 0 -3 0.0 5.0 10.0 15.0 f 20.0 22.05 kHz Fig. 2-10: Digital interpolation filter, passband characteristic dB 0 gain -50 www..com -80 0.0 50 100 150 200 f 250 300 350 kHz Fig. 2-11: Digital interpolation filter, attenuation 2.2.6.2. ARI Mixer ARIMX The ARI-information in the range of 57 kHz is mixed down to a zero intermediate frequency by the two ARI mixers, whose mixer signals are again in quadrature. The reason for using two paths is that the demodulation is asynchronous in general; in the DSP there should be an operation which performs the square root of the sum of the squares of the two input signals. The quality requirements of the square rooting should not be very high. Because of the phase lock of pilot tone and ARI carrier in the FM-stereo-mode, a synchronous demodulation seems to be possible; in this case the demodulated ARI signal would be identical with the signal of the inphase path. MICRONAS INTERMETALL The chosen structure has another potential advantage, for processing the radio data system (RDS) in Europe. This signal is a part of the MPX-signal; its subcarrier frequency is the same as that of the ARI-signal but it is recommended that the two subcarriers are in quadrature. So the two paths of the ARI demodulation subsystem make the information of the ARI-signal and of the RDSsignal available to the DSP, where both can be demodulated if desired. Please note that in this version ARI signals are not available. ARI information is replaced by the demodulation of RDS. 11 CAP 3540B, CAP 3541B 2.2.7. FM Noise Canceller (ASU) The FM Noise Canceller removes peak noise from the audio signal. No external circuitry is required. All filters, delays and the control section are implemented digitally. The function is split into two sections: - The noise detection searches for energy in the nonaudio range by means of a highpass filter. The output of this filter is compared with a DSP-controlled threshold. If this threshold is exceeded the interpolation unit is triggered. The 19 kHz pilot tone is removed before the audio signal enters the detection highpass. Programmable delay adjustment makes sure of the correct timing between peak detection and peak interpolation. - The interpolation circuit substitutes a peak-corrupted sample by the mean value of the non-corrupted adjacent samples. Once a trigger comes from the detection circuit, a programmable number (0 to 15) of successive samples is interpolated. All functions work on a 228 kHz sampling rate. At this rate the peaks are still small enough (not widened by the final decimation filters) to be removed effectively. PRELIMINARY DATA SHEET 2.3.3. Volume Control AVOL The analog volume control together with the digital volume control implemented in the digital signal processor's software provide a large volume control range. The analog volume control itself covers a range of 45 dB in 1.5 dB steps and includes an additional mute position. The analog volume control can be adjusted for all 4 output channels individually. A sensible splitting of the total gain v_tot between the digital gain v_dig and the analog gain v_anlg is v_tot v_totw0 dB -45 dB v_dig v_tot 0 dB v_tot+45 dB 2.3. Analog Output Systems 2.3.1. D/A-Converters DAC The D/A-converters used are of the oversampling type. The samples to be converted at their sampling rate f_s are first interpolated to 8 x the sampling rate and then oversampled to a higher rate f_NS where noise shaping is performed. The output of the noise shaper is then conwww..com verted using a highly linear D/A-converter. Its noise power density increases with increasing frequency, the residual noise in the baseband is very low. Only in CAP 3540B: Within this application the DAC has to be adapted to the different modes. The digital sources (e.g. CD-player) must supply the proper clock rate in order to drive the DAC with a stable clock rate locked to the sampling rate. The clock is derived from the clock line SCLK of the PDAI bus. All control bits for the hardware section are first addressed to the DSP core program. In case of hardware read-registers the bits are transmitted to the DSP core, stored in the DSP RAM and are thus available for the controller via the DSP's IM-bus interface. 2.4. Programmable Digital Audio Interface PDAI (not included in CAP 3541B) The PDAI is the digital audio interface between the CAP 3540B and external digital sources such as CD/MD player or additional external processors. It offers a large variety of modes and should therefore cover most of the digital audio standards (I2S-compatible formats). Fig. 2-12 shows a standard application with an external digital source and a second CAP 3540B. The interface is split into the input section and the output section: Input Section: - SCLKI - SDIN1 - WSI - ERR serial clock input serial data input 1 word select input error line input Output Section: 2.3.2. Lowpass-Filters ALPF The analog lowpass-filters behind the DACs eliminate the high-frequent noise in order to avoid any distortions in the AM frequency range. - SCLKO - SDOUT - SDIN2 - WSO serial clock output serial data output serial data input 2 word select output Fig. 2-13 shows the timing of the signals and the programmable features. The programming is done by writing the correct bit patterns into the DSP output buffer. This must be handled by the DSP software. 12 MICRONAS INTERMETALL PRELIMINARY DATA SHEET CAP 3540B, CAP 3541B The modes are - 16-bit wordframe in this case the programmable delay is set to zero; - 24-bit wordframe in this case the programmable delay is set either to 0 or to 8 Tbck; this allows left or right adjusted handling of the 16 data bits - 32-bit wordframe in this case the programmable delay is set either to 0 or to 16 Tbck; this allows left or right adjusted handling of the 16 data bits. In all modes: - MSB or LSB-first can be selected, - one-bit delay between active slope of WSI/O and first wordframe bit is programmable, - the polarity of WSI/O can be programmed, - in the 24 and 32-bit wordframes the open data bit locations are MSB or LSB extended (depends on left or right adjustment). Input format and output format can be programmed separately. The restrictions are - A 24-bit wordframe can only be sent if a 24-bit wordframe is also received. In the analog input mode, the 24-bit wordframe output is not allowed. SCLKI SDIN1 analog input CD-PLAYER WSI ERR SCLKO SDOUT SDIN2 WSO CLKOUT CAP 3540B or ext. Proc. CAP 3540B analog output Fig. 2-12: System configuration Tbck www..com SCLK_IN/OUT 16, 24, 32 x Tbck polarity programmable WS_IN/OUT 1 Tbck: programmable SDATA MSB LSB ERR MSB/LSB first programmable LSB MSB 0, 8, 16 x Tbck: programmable delay Fig. 2-13: Timing of the signals Tbck+1/Fbck Fbck+32@Fsaudio or Fbck+48@Fsaudio or Fbck+64@Fsaudio MICRONAS INTERMETALL 13 CAP 3540B, CAP 3541B 2.5. The IM-Bus Interface of the CAP 3540B LSB IABF shift MSB IMDATA PRELIMINARY DATA SHEET 2.5.1. Description of the IM-Bus The IM-bus consists of three lines for the signals Ident (IMIDENT), Clock (IMCLK) and Data (IMDATA). The clock frequency range is 50 Hz to 1 MHz. Ident and clock are unidirectional from the controller to the slave ICs, Data is bidirectional. Bidirectionality is achieved by using open-drain outputs with on-resistances of 150 Ohm maximum. The 2.5 k pull-up resistor common to all outputs is incorporated in the controller. The timing of a complete IM-bus transaction is shown in Fig. 2-16. In the non-operative state the signals of all three bus lines are High. To start a transaction, the controller sets the ID signal to Low level, indicating an address transmission, sets the CL signal to Low level and switches the first bit on the Data line. Then 10 address bits are transmitted, beginning with the LSB. Data takeover in the slave ICs occurs at the positive edge of the clock signal. At the end of the address byte the ID signal goes High, initiating the address comparison in the slave circuits. In the addressed slave the IM-bus interface switches over to Data read or write, because these functions are correlated to the address. In the case of a read operation, a fixed wait period has to be observed. This period is defined by the IM-bus handler in the DSP software. For practical reasons this part of the program does not run at the full sampling rate. It is recommended to place the IM-bus handler in a "low speed" time slice in order to save processing power. For a write operation this wait period does not have to be observed, but please note that the maximum rate of IMbus transmissions is normally limited by the DSP software. Also controlled by the address the controller now transmits sixteen clock pulses, and accordingly two Bytes of data are written into the addressed IC or read out from it, beginning with the LSB. The completion of the bus transaction is signalled by a short Low state pulse of the ID signal. This initiates the storing of the transferred data. A bus transaction may be interrupted for up to 10 ms. IDBF Fig. 2-14: IM-bus interface The buffer part consists of a unidirectional address buffer IABF with a word length of 10 bit and the bidirectional data buffer IDBF with a word length of 16 bit. It is only possible to write to the address buffer from the peripheral equipment. By means of the IM-bus interface it is possible, for example, to alter the filter coefficients of the CAP 3540B. For this purpose, the microcomputer writes an address and a data word to the appropriate buffers IABF and IDBF. The 10-bit address contains an address part of 8 bits (bit 9 to bit 2), a read/write bit (bit 0) and an additional bit (bit 1) which is used for selecting one of the two address counter banks (Fig. 2-15). Bits 0 and 1 have the following effect: ABNK+0 selects address www..com counter bank 1 ABNK+1 selects address counter bank 2 R/W+0 selects Write, microcomputer wants to write R/W+1 selects Read, microcomputer wants to read MSB Address LSB ABNK R/W Fig. 2-15: Address format The following convention is applicable to the data transfer: The last bit written always becomes the MSB of IABF or IDBF. If fewer bits are transferred than the respective buffer size, the unused bits are set to zero in IDBF but remain undefined in IABF. For the output: the first bit output is always the LSB of the IDBF. 14 III III III III III III III III 10 16 Data Bus IM Bus Control shift MSB IMIDENT LSB IMCLK MICRONAS INTERMETALL PRELIMINARY DATA SHEET CAP 3540B, CAP 3541B H Ident L H Clock L H Data L LSB Address MSB LSBData MSB 1 2 3 4 5 6 7 8 9 10 11 12 13 26 A Section A B Section B C Section C tIM10 H Ident L tIM1 tIM2 H Clock L tIM7 H Data L tIM8 tIM9 tIM3 tIM4 tIM5 tIM6 Address LSB Address MSB Data MSB Fig. 2-16: IM-Bus waveforms www..com MICRONAS INTERMETALL 15 CAP 3540B, CAP 3541B 2.6. Clock Generation The CAP 3540B processor has an integrated clock oscillator which is crystal-controlled and oscillates with the frequency fECLK + 16.416 MHz. All components of the oscillator are integrated except for the quartz crystal. This is connected to the QX1 and QX2 oscillator pins. The crystal input QX2/ECLK can be used to supply the CAP 3540B externally with the required clock. In this case no crystal is needed. Following the clock oscillator is a frequency multiplier with a factor of 3. The output of the frequency multiplier delivers the fICLK internal clock frequency, by which the DSP Core is clocked. There is the possibility of pulling the fECLK oscillator frequency in a range of 350 ppm, depending on the application and the used crystal. This makes it possible to synchronize the CAP 3540B to the incoming pilot tone signal in the case of MPX reception. PRELIMINARY DATA SHEET Table 2-1: Oscillator characteristics DCO Content 011111111B 000000000B 100000000B Frequency fECLKmin fECLK fECLKmax www..com DCO Clock 9 Control Register Clock Oscillator Frequency Multiplier fICLK 12* 12* 1 nF ECLK fECLK 13* 13* 100 nF GNDD external option 1 2 3 4 Clock Pulse Shaper and Frequency Divider 55* CLKOUT Fig. 2-17: Clock generator connections *PSDIP64 package 16 MICRONAS INTERMETALL PRELIMINARY DATA SHEET CAP 3540B, CAP 3541B 3. Specifications 3.1. Outline Dimensions 15 27.7 33 SPGS0004-1/2E 64 1 32 3.8 0.1 19.3 0.1 18 0.1 4.8 0.4 57.7 0.1 (1) 3.2 0.4 1.9 3 0.27 0.1 1.778 0.05 0.457 0.1 1 0.1 20.1 0.6 1.29 31 x 1.778 = 55.118 0.1 Fig. 3-1: 64-Pin PSDIP Plastic Shrink Dual Inline Package (PSDIP64) Weight approximately 9.0 g Dimensions in mm 1+0.2 x 45 9 1 61 0.457 0.9 2.4 16 x 1.27 0.1 = 20.32 0.1 1.27 0.1 1.2 x 45 2.4 1.27 0.1 15 24.2 0.1 2 10 2 60 www..com 25 +0.25 9 0.711 23.4 24.2 0.1 9 26 27 25 +0.25 43 44 1.9 1.5 4.05 4.75 0.15 0.2 0.1 Fig. 3-2: 68-Pin Plastic Leaded Chip Carrier Package (PLCC68) Weight approximately 4.8 g Dimensions in mm SPGS7004-3/4E MICRONAS INTERMETALL 16 x 1.27 0.1 = 20.32 0.1 17 CAP 3540B, CAP 3541B 3.2. Pin Connections and Short Descriptions LV = if not used, leave vacant X = obligatory; connect as described in circuit diagram Pin No. PSDIP 64-pin PLCC 68-pin PRELIMINARY DATA SHEET Pin Name Type Connection (if not used) Short Description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 51 50 49 48 46 45 44 43 42 41 40 39 38 37 36 SDOUT WSO SCLKO TI3 TI1 REFCLK TEOSC IMIDENT IMCLK IMDATA RESET QX2/ECLK QX1 TESTEN GNDS1 FMOSCIN FMOSCREF AMOSCIN AMOSCREF VSUP1 VSUP2 AMTUNOUT TUNFB FMTUNOUT VREF2 RF RR LR OUT OUT OUT IN IN IN IN IN IN IN/OUT IN IN IN IN SUPPLY IN IN IN IN SUPPLY SUPPLY OUT IN OUT IN OUT OUT OUT LV LV LV LV1) LV1) LV GNDD X X X X X X GNDD X LV LV LV LV VREF2 VREF2 LV LV LV GNDA LV LV LV Serial data output Serial word select output Serial clock output Static digital input 3 Static digital input 1 Synthesizer Ref. Frequency input Test purpose IM-bus ident input IM-bus clock input IM-bus data input/output Reset input Crystal/External clock input Crystal Test Mode Enable Analog ground synthesizer FM oscillator signal input FMOSC capacitor connection AM oscillator signal input AMOSC capacitor connection Analog supply voltage synthesizer Analog supply voltage synthesizer AM tuning voltage output Tuning voltage feedback input FM tuning voltage output Analog ground reference synthesizer Analog output right front Analog output right rear Analog output left rear www..com 16 35 17 18 19 20 21 22 23 24 25 26 27 28 34 33 32 31 30 29 28 27 26 25 24 23 18 MICRONAS INTERMETALL PRELIMINARY DATA SHEET CAP 3540B, CAP 3541B Pin Connections and Short Descriptions, continued Pin No. PSDIP 64-pin PLCC 68-pin Pin Name Type Connection (if not used) Short Description 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 22 21 20 19 18 16 15 14 17 13 12 11 10 9 8 7 6 5 4 2 1 67 66 65 64 63 62 61 60 LF VSUPA GNDA VREF1 AGNDC PDMC2 PDMC1 PDMC3 BAGNDC TAPEL TAPER AUXL AUXR AMR AML MPX0 POT1/MPX1 POT2 POT3 POT5/AVC FMLEVEL AMLEVEL TP1 TP4 TP2 TP3 CLKOUT VSUPD GNDD OUT SUPPLY SUPPLY IN OUT IN/OUT IN/OUT IN/OUT OUT IN IN IN IN IN IN IN IN/OUT IN/OUT IN/OUT IN/OUT IN IN IN OUT OUT IN OUT SUPPLY SUPPLY LV X X X X BAGNDC BAGNDC BAGNDC LV BAGNDC BAGNDC BAGNDC BAGNDC BAGNDC BAGNDC BAGNDC GNDA GNDA GNDA GNDA GNDA GNDA GNDD LV LV GNDD LV X X Analog output left front Analog supply voltage Analog ground Analog ground reference Internal analog ground PDM capacitor connection PDM capacitor connection PDM capacitor connection Buffered internal ground Analog Tape input left Analog tape input right Auxiliary audio input left Auxiliary audio input right AM right baseband input AM left baseband input FM MPX signal input DC voltage input DC voltage input DC voltage input DC voltage input FM field strength input AM field strength input Test purpose Test purpose Test purpose Test purpose Clock output Digital supply voltage Digital ground www..com MICRONAS INTERMETALL 19 CAP 3540B, CAP 3541B Pin Connections and Short Descriptions, continued Pin No. PSDIP 64-pin PLCC 68-pin PRELIMINARY DATA SHEET Pin Name Type Connection (if not used) Short Description 58 59 60 61 62 63 64 - - - - 1) 59 58 57 56 55 54 52 3 47 53 68 TO3 TO2 TO1 SDIN1 WSI SCLKI SDIN2 POT4 TI2 ERR MPLEVEL OUT OUT OUT IN IN IN IN IN/OUT IN IN IN LV LV LV LV LV LV LV GNDA LV1) LV GNDA Digital output 3 Digital output 2 Digital output 1 Serial data input 1 Serial word select input Serial clock input Serial data input 2 DC voltage input Static digital input 2 Serial error input Multipath signal input Depending on software version 3.3. Pin Descriptions The pin numbers refer to the PSDIP64 package. Pin 1 - SDOUT www..com output. DAI-Bus: serial data Pin 2 - WSO DAI-Bus: word select output; this is a control line to separated left and right channel in the serial DAI stream. Pin 3 - SCLKO DAI-Bus: serial clock output. Pins 4 to 5 - TI1, TI3 Static digital inputs; these signals can be used as a branch condition in the DSP software. If not used, they must be connected to GND. Pin 6 - REFCLK Input for the synthesizer reference frequency. Pin 7 - TEOSC Test purpose. Pins 8 to 10 - IMDATA, IMCLK, IMIDENT Via these pins the CAP 3540B sends and receives data to and from the controller. 20 Pin 11 - RESET In the steady state, high level is required at this pin. A low level resets the CAP 3540B. Pin 12 - QX2/ECLK Crystal pin. This pin has to be connected with the crystal or with an external clock signal. Pin 13 - QX1 Crystal pin. This pin has to be connected with the crystal. Pin 14 - TESTEN Test mode enable Pin 15 - GNDS1 This pin serves as ground connection for the HF parts of the synthesizer section. Pin 16 - FMOSCIN Input for the FM oscillator signal. Pin 17 - FMOSCREF Capacitor connection for FMOSCIN reference voltage. Pin 18 - AMOSCIN Input for the AM oscillator signal. Pin 19 - AMOSCREF Capacitor connection for AMOSCIN reference voltage. MICRONAS INTERMETALL PRELIMINARY DATA SHEET CAP 3540B, CAP 3541B Pin 38 - TAPEL Input for left tape channel. Pin 39 - TAPER Input for right tape channel. Pin 40 - AUXL Input for additional audio sources, left channel. Pin 41 - AUXR Input for additional audio sources, right channel. Pin 42 - AMR Input for right channel baseband audio. Pin 43 - AML Input for left channel baseband audio (AM mono). Pin 44 - MPX0 Input for the MPX signal in case of FM reception. Pins 45 to 48 - POT5/AVC, POT3, POT2, POT1/MPX1 Inputs for a DC-control voltage (0V to VSUP). These pins can also be used as digital outputs with an external pullup resistor; the function and selection is controlled via IM-bus. POT1/MPX1 also serves as a second MPX input for ARI/ RDS signals. POT5/AVC also serves as a highly sensitive microphone input. Pin 49 - FMLEVEL Input for the FM field strength information. Pin 50 - AMLEVEL Input for the AM field strength information. Pin 51 - TP1 Test purpose. Pin 52 - TP4 Test purpose. Pin 53 - TP2 Test purpose. Pin 54 - TP3 Test purpose. Pin 55 - CLKOUT This output is used for clocking external hardware. Pin 56 - VSUPD Digital supply voltage. Power is supplied via this pin for the digital circuitry of the CAP 3540B. Pin 57 - GNDD This pin serves as ground connection for the digital signals. 21 Pin 20 - VSUP1 Synthesizer supply voltage 1; power is supplied via this pin for the synthesizer circuitry of the CAP 3540B. Pin 21 - VSUP2 Synthesizer supply voltage 2; power is supplied via this pin for the synthesizer output circuitry of the CAP 3540B. Pin 22 - AMTUNOUT Tuning voltage for the AM oscillator. Pin 23 - TUNFB Feedback input for tuning voltage amplifier. Pin 24 - FMTUNOUT Tuning voltage for the FM oscillator. Pin 25 - VREF2 This pin serves as ground connection for the synthesizer bias circuits and must be connected separately to the ground point of the tuner. Pin 26 - RF Right front speaker output. Pin 27 - RR Right rear speaker output. Pin 28 - LR Left rear speaker output. Pin 29 - LF Left front speaker output. Pin 30 - VSUPA www..com Analog supply voltage; power for the analog circuitry of the CAP 3540B is supplied via this pin. Pin 31 - GNDA This pin serves as ground connection for the analog signals and NF parts of the synthesizer section. Pin 32 - VREF1 This pin must be connected separately to the single ground point. It serves as ground connection for the analog bias circuits. Pin 33 - AGNDC This pin serves as internal ground connection for the analog circuitry. It must be connected to analog ground with a 4.7 F and a 100 nF capacitor in parallel. Pins 34 to 36 - PDMC3, PDMC2, PDMC1 Capacitor pins for the feedback loop of the high quality pulse-density modulators. Pin 37 - BAGNDC Buffered internal ground. This pin is the buffered internal ground connection for the external PDM capacitors. MICRONAS INTERMETALL CAP 3540B, CAP 3541B Pins 58 to 60 - TO1, TO2, TO3 Digital outputs; the logical state can be defined by the DSP software. Pin 61 - SDIN1 DAI-Bus: serial data input 1. Pin 62 - WSI DAI-Bus: word select input; this is a control line to separate left and right channel in the serial DAI stream. Pin 63 - SCLKI DAI-Bus: serial clock input. Pin 64 - SDIN2 DAI-Bus: serial data input 2. PRELIMINARY DATA SHEET The following pins are available only in the 68-pin PLCC package: - POT4 Input for a DC-control voltage (0 V to VSUP). This pin can also be used as digital output with an external pullup resistor; the function and selection is controlled via IM-bus. - TI2 Static digital input; this signal can be used as a branch condition in the DSP software. If not used, it must be connected to GND. - ERR DAI-Bus: error input - MPLEVEL Input for the multipath information. 3.4. Pin Configuration SDOUT WSO SCLKO TI3 TI1 REFCLK TEOSC IMIDENT IMCLK IMDATA RESET QX2/ECLK QX1 TESTEN GNDS1 FMOSCIN FMOSCREF AMOSCIN AMOSCREF VSUP1 VSUP2 AMTUNOUT TUNFB FMTUNOUT VREF2 RF RR LR LF VSUPA GNDA VREF1 1 2 3 4 5 6 7 8 9 10 11 12 13 64 63 62 61 60 59 58 57 56 55 54 53 52 FMLEVEL POT5/AVC POT4 POT3 POT2 POT1/MPX1 MPX0 AML AMR MPLEVEL AMLEVEL TP1 TP4 TP2 TP3 CLKOUT VSUPD AUXR AUXL TAPER CAP 3540B CAP 3541B 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 GNDD TO3 TO2 TO1 SDIN1 WSI SCLKI ERR SDIN2 SDOUT WSO SCLKO TI3 TI2 TI1 REFCLK TEOSC 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 www..com TAPEL PDMC3 PDMC1 PDMC2 BAGNDC AGNDC VREF1 GNDA VSUPA LF LR RR RF VREF2 CAP 3540B CAP 3541B 26 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 FMTUNOUT TUNFB AMTUNOUT VSUP2 VSUP1 AMOSCREF AMOSCIN FMOSCREF FMOSCIN QX1 TESTEN GNDS1 IMIDENT IMCLK IMDATA RESET QX2/ECLK SDIN2 SCLKI WSI SDIN1 TO1 TO2 TO3 GNDD VSUPD CLKOUT TP3 TP2 TP4 TP1 AMLEVEL FMLEVEL POT5/AVC POT3 POT2 POT1 / MPX1 MPX0 AML AMR AUXR AUXL TAPER TAPEL BAGNDC PDMC3 PDMC1 PDMC2 AGNDC Fig. 3-4: Pinning of the CAP 3540B in PSDIP64 package, top view MPLEVEL not available ERR not available POT4 not available TI2 not available (internally pushed to GND) Fig. 3-3: Pinning of the CAP 3540B in PLCC68 package, top view 22 MICRONAS INTERMETALL PRELIMINARY DATA SHEET CAP 3540B, CAP 3541B 3.5. Electrical Characteristics All voltages refer to ground. All pin numbers refer to the PSDIP64 package. 3.5.1. Absolute Maximum Ratings Symbol TA TS VSUP VSUP1 VSUP2 Pmax dVSUP dVSUP2 VI Parameter Ambient Operating Temperature Storage Temperature Supply Voltage Supply Voltage Supply Voltage Maximum Power Dissipation 68-pin PLCC without heat spreader Voltage between VSUPA, VSUPD, and VSUP1 Voltage between VSUP2 and VSUPA, VSUPD, and VSUP1 Input Voltage, all Inputs Pin No. - - 30, 56 20 21 20, 21, 30, 56 30, 56, 20 21 4 to 10, 12, 13, 16 to 19, 23, 37 to 50, 61 to 64 1 to 3, 10, 22, 24, 26 to 29, 55, 58 to 60 Min. -20 -55 -0.31) -0.31) -0.31) - -0.5 - -0.3 Max. +85 +125 +6 +6 +12 1300 +0.5 +8.5 VSUP +0.3 Unit C C V V V mW V V V IO www..com Output Current, all Outputs - 2) 3) - 1) Reversed supply 200 ms maximum. 2) The outputs are short-circuit proof (max. 5 seconds) with respect to supply 3) Total chip power dissipation must not exceed absolute maximum ratings. and ground. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in the Recommended Operating Conditions/Characteristics of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. MICRONAS INTERMETALL 23 CAP 3540B, CAP 3541B PRELIMINARY DATA SHEET 3.5.2. Recommended Operating Conditions at TA+-20 to +85 C, fECLK+16.416 MHz, typical values at Tj+27 C, duty cycle+50% Symbol VSUP VSUP1 VSUP2 VECLKL VECLKH tECLKH tECLKL fECLK VREFCLKH VREFCLKL fREFCLK VFS VPOT/ MPXI Parameter Supply Voltage Supply Voltage Supply Voltage ECLK Clock Input Low Voltage ECLK Clock Input High Voltage ECLK Clock Input High/Low Ratio ECLK Clock Input Frequency (see also section 3.5.3.) Reference Clock Input High Voltage Reference Clock Input Low Voltage Refence Clock Input Frequency DC Input Voltage FM, AM, [MP] level DC Input Voltage POT5, [POT4], POT3, POT2, POT1 High Level, Digital Inputs Low Level, Digital Inputs Input Low Voltage Pin No. 30, 56 20 21 12 Min. 4.75 4.75 7.5 - VSUP -1.5 0.9 - Typ. 5.0 5.0 9.0 - - 1.0 16.416 - - Max. 5.25 5.25 10.5 1.5 - 1.1 - - 1.5 16 VSUP VSUP Unit V V V V V - MHz V V MHz - - V 6 VSUPD -1.5 - 1 49, 50 45 to 48 2 to 5, 61 to 64 11 0 0 2.0 VIH VIL 0.8 - VSUP -0.8 V 8 to 10 - 3.0 0.05 0 0.5 0.5 0 0.25 - - - - - - - - - - 0.8 - 1.5 - 1000 - - - - - V V - V V kHz - s s - s s VREIL Reset www..com VREIH VIMIL VIMIH fI tIM1 tIM2 tIM3 tIM4 tIM5 write data Reset Input High Voltage IM Bus Input Low Voltage IM Bus Input High Voltage I IM Bus Clock Frequency I Clock Input Delay Time after IM Bus Ident Input I Clock Input Low Pulse Time I Clock Input High Pulse Time I Clock Input Setup Time before Ident Input High I Clock Input Hold Time after Ident Input High I Clock Input Hold Time after Ident Input High tIM5 read data defined by DSP software 24 MICRONAS INTERMETALL PRELIMINARY DATA SHEET CAP 3540B, CAP 3541B Recommended Operating Conditions, continued Symbol tIM6 tIM7 tIM8 tIM9 tIM10 CPDM CAGNDC Parameter I Clock Input Setup Time before Ident End-Pulse Input IM Bus Data Input Delay after I Time Clock Input IM Bus Data Input Setup Time before I Clock Input IM Bus Data Input Hold Time after I Clock Input IM Bus Ident End-Pulse Low Time PDM Capacitor (Low Loss Type) AGNDC-Filter-Capacitor Ceramic Capacitor in parallel fSCLKI tSIJ tSIW tIDS tIDH tWSS tWSH www..com Pin No. 8 to 10 Min. 1.0 0 0 0 1.0 Typ. - - - - - 680 3.3 100 Max. - - - - - +5% Unit s - - - s pF F nF 34 to 36 33 -5% Input SCLKI Frequency Input SCLKI Phase Jitter Input SCLKI Pulse Width Input Data Setup Time Input Data Hold Time Input WSI Setup Time Output WSO Setup Time Input WSI Hold Time Output WSO Hold Time 63 - - 40 - - 50 - - - - 3.1 250 60 - - - - MHz ps % ns - ns - 61, 64 40 0 2, 62 40 0 MICRONAS INTERMETALL 25 CAP 3540B, CAP 3541B 3.5.3. Recommended Crystal Characteristics Symbol TA fP fS fS fS fS Rr C0 C1 df 1) PRELIMINARY DATA SHEET Parameter Ambient Operating Temperature Parallel Resonance Frequency Accuracy of Adjustment Frequency Deviation versus Temperature Series Resistance Shunt Capacitance Motional Capacitance Frequency pulling range Min. -20 - - - - 5.5 25 3502) Typ. - 16.4161) - - - - 30 - Max. +85 - 20 40 15 7 - - Unit C MHz ppm ppm pF fF ppm at CL+10.7 pF 2) at CL+12 pF Remark on defining the external load capacitance: External capacitors at each crystal pin to ground are required. The higher the capacity, the lower the clock frequency results. Due to different layouts of customer PCBs, the matching capacitor size should be defined in the application. www..com 26 MICRONAS INTERMETALL PRELIMINARY DATA SHEET CAP 3540B, CAP 3541B 3.5.4. Characteristics at TA+-20 to +85 C, VSUP and VSUP1+4.75 to 5.25 V, VSUP2+7.5 to 10.5 V, fECLK+16.416 MHz, typical values at VSUP and VSUP1+5.0 V, VSUP2+9.0 V, Tj+27 C and duty cycle+50%. Symbol ZAII1 Parameter Analog Input Impedance (MPX1, MPX0, AM, AUX, TAPE) at Tj+27 C at TA+-20 to +85 C Analog Input Impedance FM, AM, [MP] level Analog Input Impedance (AVC) at Tj+27 C at TA+-20 to +85 C Analog Input Impedance (POT1 to 5) Open Circuit Voltage (FMOSCIN, AMOSCIN, REFCLK) Output Resistance (POT1 to 5 as outputs) Analog Input Resistance (FMOSCIN, AMOSCIN, FMOSCREF, AMOSCREF) at Tj+27 C at TA+-20 to +85 C Analog Input Capacitance (FMOSCIN, AMOSCIN, FMOSCREF, AMOSCREF) Analog Output Resistance (LF, LR, RR, RF) at Tj+27 C, at TA+-20 to+85 C Input Voltage (MPX0, MPX1) Input Voltage (AML, AMR) Input Voltage (TAPER, TAPEL) 26 to 29 470 440 44, 45 42, 43 38, 39 600 730 790 2.0 1.1 1.6 VPP VRMS VRMS VRMS mVRMS Pin No. 38 to 45, 48 27 26 49, 50 35 43 47 k k M fsignal+1 kHz, i+0.5 A 3.2 3.1 45 to 48 4.2 5.2 5.7 k k M Min. Typ. Max. Unit Test Conditions fsignal+1 kHz, i+0.5 A ZAII2 ZAVC 2 48 ZPOT VOSCI0 2 16, 18, 6 VSUP1 2 - ROPOT ROSCI 45 to 48 80 iv5 mA 16 to 19 3.2 2.1 4 3.6 3.6 4.2 6.5 pF k k COSCI RAO fsignal+1 kHz, i+1 mA VMPX0/1I www..com VAML/RI VTAPER/ TAPELI VAUXR/LI VAVCI VAICL Input Voltage (AUXR, AUXL) Input Voltage (AVC) Analog Audio Input Clipping Level (defines 0 dBr) 40, 41 48 38 to 45 Max. Input Voltage Max. Input Voltage +1 dB 1.1 14 Max. Input Voltage +2 dB ZAOL VAOV Analog Output Load 26 to 29 6 1 k nF output attenuation+0 dB, analog output loadu100 k Maximum Analog Output Voltage (LF, LR, RR, RF) Analog Input Digital Input 0.8 0.9 0.9 1.0 1.0 1.1 VRMS VRMS 1) 2) CD-Mode, fs+44.1 kHz unused analog inputs connected to ground MICRONAS INTERMETALL 27 CAP 3540B, CAP 3541B Characteristics, continued Symbol VAMOSC fAMOSCI VFMOSCI fFMOSCI SNRAD Parameter AM OSC Input Voltage AM OSC Input Frequency Range FM OSC Input Voltage FM OSC Input Frequency Range SNR A/D 38 to 44 16 Pin No. 18 Min. 40 0.5 40 60 82 85 Typ. Max. 300 20 300 150 PRELIMINARY DATA SHEET Unit mVRMS MHz mVRMS MHz dB Test Conditions Noise measurement RMS unweighted, BW+20 to 18000 Hz, input level+-20 dBr, fsignal+1 kHz RMS, unweighted, BW+20 to 20000 Hz1), input level+-20 dBFS, fsignal+1 kHz RMS, unweighted, BW+20 to 20000 Hz1), input level+-20 dBFS, fsignal+1 kHz RMS, unweighted, BW+20 to 18000, input level+-3 dBr, fsignal+1 kHz BW+20 to 20000 Hz1), input level+-3 dBFS, fsignal+1 kHz, analog attenuation+0 dB fsignal+14 kHz + 15 kHz, input level sum -3 dBr, measuring 1 kHz intermodulation2) input level+-3 dBr, fsignal+1 kHz, measuring with bandpass at 1 kHz2) input level+-3 dBr, fsignal+1 kHz, measuring with bandpass at 1 kHz2) input level+-3 dBr, fsignal+1 kHz, measuring with bandpass at 1 kHz2) coupling capacitor on MPX input at least 1 F SNRDA SNR D/A Analog Attenuation+0 dB Analog Attenuation+45 dB 26 to 29 90 60 95 65 dB dB GDAM D/A Output Attenuation in MUTE position 110 dB THDAD THD A/D 38 to 44 0.03 % THDDA THD D/A 26 to 29 0.01 % IMDAD Intermodulation Distortion A/D 38 to 44 0.01 % XTALK1 Crosstalk attenuation within www..com active audio channel pair 38 to 43 70 dB XTALK2 Crosstalk attenuation from a non-selected audio input pair 38 to 44 80 dB XTALK3 Crosstalk attenuation between audio input/output pairs 26 to 29, 38 to 44 100 dB CHSEPMPX Stereo separation MPX 250 Hz to 6.3 kHz 6.3 kHz to 12.5 kHz Suppression of unwanted signals in MPX stereo reception: at 19 kHz at 38 kHz at 57 kHz at 114 kHz 14 40 30 dB dB SNRMPX 19 kHz measuring with bandpass at fsignal 45 45 60 60 dB dB dB dB 1) 2) CD-Mode, fs+44.1 kHz unused analog inputs connected to ground 28 MICRONAS INTERMETALL PRELIMINARY DATA SHEET CAP 3540B, CAP 3541B Characteristics, continued Symbol SNRRDS1 Parameter SNR A/D selected MPX ARI/RDS channel Pin No. 44, 45 Min. Typ. 38 Max. Unit dB Test Conditions Noise measurement RMS, unweighted, BW+55 to 59 kHz, input level+55 mVPP fsignal+57 kHz fsignal+57 kHz, input level+55 mVPP 60 70 48 56 dB dB dB Noise measurement RMS unweighted, BW+0 to 4 kHz, input level+-20 dBr, fsignal+1 kHz Noise measurement RMS unweighted, BW+0 to 7 kHz, input level+-20 dBr, fsignal+1 kHz RMS unweighted, BW+0 to 4 kHz, input level+-3 dBr, fsignal+1 kHz RMS unweighted, BW+0 to 7 kHz, input level+-3 dBr, fsignal+1 kHz not provided in production test not provided in production test SNRRDS2 Alias Band Suppression in RDS Channel at 171 kHz at 285 kHz SNR A/D3 selected AVC channel SNRAVC SNRAD4 SNR A/D4 49, 50 54 dB THDAVC THD A/D3 selected AVC channel 48 0.05 % THDAD4 THD A/D4 49, 50 0.05 % BWADDA BWDA 3 dB Bandwidth A/D to D/A (TAPE, AUX) 3 dB Bandwidth D/A at fs+32 kHz at fs+44.1 kHz Channel deviation within active input pair: AUX, TAPE AM Channel deviation within each output of: RR, RF, LR, LF Analog attenuation+ 0 to -30 dB -31.5 to -45 dB Analog Volume Step Size (-45 dB to 0 dB) Reset Input Leakage Current Supply Current VSUPD VSUPA VSUP1 VSUP2 26 to 29, 38 to 41 26 to 29 18 kHz 15 20 38 to 43 0.5 0.7 26 to 29 kHz kHz www..com dGAD dB dB dGDA 0.5 0.9 1.4 1.5 1.6 dB dB dB A dGAVOL IREIL ISUP 11 -10 - +10 56 30 20 21 60 12 8 1.4 85 20 11 2.2 110 28 14 3 mA mA mA mA 1) 2) CD-Mode, fs+44.1 kHz unused analog inputs connected to ground MICRONAS INTERMETALL 29 CAP 3540B, CAP 3541B Characteristics, continued Symbol VIMOL VIMOH IIMOHL IIMIL VTOH VTOL VTIH VTIL VTUNOUT VAGNDC0 ROUTAGND Parameter IM-Bus Data Output Low Voltage IM-Bus Data Output High Voltage IM-Bus Data Output HighImpedance Leakage Current IM-Bus Input Leakage Current Digital Output High Voltage Digital Output Low Voltage Digital Input High Voltage Digital Input Low Voltage Synthesizer Output Voltage (AMTUNOUT, FMTUNOUT) AGNDC Open Circuit Voltage AGNDC Output Resistance at 27 C at -20 to +85 C Deviation of BAGNDC from AGNDC Voltage BAGNDC Output Resistance Deviation of DC Level at Audio Outputs from AGNDC Voltage 33, 37 58 to 60 Pin No. 10 Min. - 2.8 -10 Typ. - - - Max. 0.4 - +10 PRELIMINARY DATA SHEET Unit V V A A V V V V V Test Conditions -10 4.0 - - +10 0.4 4, 5 2.4 - 0.8 22, 24 1.1 - VSUP2 -1.1 2.35 33 2.15 2.25 V 110 70 -20 125 140 230 +20 k k mV fsignal+1 kHz, i+0.1 mA dVBAGNDC ROUTBAGND dVDAC 37 26 to 29, 33 22, 24 3.3 33 330 20, 21, 30, 56, 26 to 29 24 -20 6 +20 mV IOUTSYNTH Synthesizer Current Source Accuracy I+5 A I+50 A I+500 A 5 50 500 6.5 70 740 A A A PSRR Power www..com Supply Rejection Ratio 1 kHz 20 Hz to 20 kHz dVTUNOUT 1) 2) 50 40 2.2 dB dB V BW 22Hz to 22 kHz, i+5 A Residual Noise of Synthesizer Output Voltage CD-Mode, fs+44.1 kHz unused analog inputs connected to ground 30 MICRONAS INTERMETALL PRELIMINARY DATA SHEET CAP 3540B, CAP 3541B 5. Synthesizer With the synthesizer block in the CAP 3540B, a PLL tuning system can be implemented for FM and AM receivers. The signal picked up from the mixing oscillators of the FM and AM tuners can be fed to the synthesizer block by means of highly sensitive input pins. Freely programmable dividers, operating with frequencies up to and over 100 MHz, scale the incoming signals to a reference frequency of 25 kHz. This holds true even in the case of AM, which gives AM tuning a considerable speed improvement over common designs. In order to get a tuning step size of down to 300 Hz, the reference divider is also programmable. Incoming frequencies in the range of 0.5 MHz up to more than 100 MHz can be handled, so that the designer is free to choose either a 10.7 MHz or a 450 to 460 kHz IF frequency for the AM case. The common reference frequency for AM and FM allows the implementation of a common PLL filter for the tuning output. 4. Starting the Processor After power-up, the crystal oscillator has to have been started before the Reset reaches high level. An additional wait time of 0.4 ms has to be taken into account because of a DSP-internal self-test algorithm. Then the CAP 3540B can be initialized. Fig. 4-1 shows the complete start-up sequence of the typical application. The DCO register is loaded with a zero value. 4.75 V VSUPD VSUPA Crystal Oscillator 2.4 V Reset > 1 ms > 0.4 ms Fig. 4-1: Start-up sequence FMOSCIN + FMOSCREF www..com AMOSCREF - Programmable Divider (16 bit) Programmable Divider (10 bit) - AMOSCIN + FMTUNOUT Filter Current Source Filter AMTUNOUT Gain adjust Reference Clock 16.416 MHz or external REFCLK Fig. 5-1: Synthesizer block diagram MICRONAS INTERMETALL 31 CAP 3540B, CAP 3541B 6. Application Notes PRELIMINARY DATA SHEET FM Preselection Osc. 10.7 MHz FM IF FM MPX FMLEVEL FMOSCIN FMTUNOUT CAP 3540B AMTUNOUT AMOSCIN AMLEVEL Osc. AM Preselection Osc. 455 kHz AM IF AM audio 10.7 MHz Fig. 6-1: CAP 3540B application for 10.7 MHz AM-IF in detail www..com 32 MICRONAS INTERMETALL PRELIMINARY DATA SHEET CAP 3540B, CAP 3541B 7. Typical Application Circuit k. s. k. s. k. s. k. s. k. s. k. s. www..com Fig. 7-1: Typical Application Circuit These values have to be adjusted to achieve the neccessary pulling range and to define its absolute position (compensation of the parasitic board capacitors). These ground nets are connected together to the main ground under the IC, close to the pin VREF1. Pin VREF2 is the reference for the tuning synthesizer. It is connected to the tuner ground and has no direct connection to the main ground under the IC. This is the ground at the tuner. It has a separate connection to the main ground under the IC. k. s. Keep these leads as short as possible! MICRONAS INTERMETALL 33 Fig. 7-1: Typical Application Circuit k. s. CAP 3540B, CAP 3541B 8. Index M MPX Signal, 6, 7 A A/D Converters, 8 Absolute Maximum Ratings, 23 Analog Input Signals, 7 Analog Outputs, 12 Analog Volume Control, 12 ARI Travel Information, 11 ASU Noise Canceller, 12 P B Block Diagram CAP 3540B, 5 Pilot Tone, 9 Pin Configuration, 22 O Operating Modes, 6 Oscillator, 16 Outline Dimensions, 17 Oversampling, 12 PRELIMINARY DATA SHEET Pin Connections and Short Descriptions, 18 Potentiometer Inputs, 7 C Characteristics, 27 Clock Generation, 16 Crystal, 16, 27 R RDS, 6, 7, 11 D D/A Converters, 12 DCO, 16 Decimation, 8 www..com Digital Audio Interface, Power-Up Sequence, 31 Recommended Operating Conditions, 23 Reset, 31 S 12 SNR, 28, 29 Stereo Mixer, 8 Stereo PLL, 8 Synthesizer, 31 Digital Filters, 8 DSP, 4, 5 F FM/AM Tuning, 31 T THD+N, 28, 29 I I2S-bus, 12 V Volume Control, 12 Tuning System, 31, 32 IM-Bus Interface, 14 Input Signals, 7 Interpolation, 8 34 MICRONAS INTERMETALL PRELIMINARY DATA SHEET CAP 3540B, CAP 3541B www..com MICRONAS INTERMETALL 35 CAP 3540B, CAP 3541B 9. Data Sheet History: 4. Preliminary data sheet: "CAP 3540B, CAP 3541B Car Audio Processor Hardware", May 22, 1997, 6251-434-1PD. First release of the preliminary data sheet. PRELIMINARY DATA SHEET www..com MICRONAS INTERMETALL GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@intermetall.de Internet: http://www.intermetall.de Printed in Germany Order No. 6251-434-1PD All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery dates are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples delivered. By this publication, MICRONAS INTERMETALL GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Reprinting is generally permitted, indicating the source. However, our prior consent must be obtained in all cases. 36 MICRONAS INTERMETALL |
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