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| www..com Data Sheet INDT/R165B INDT/R330B Order this document by Q_DS_GigaSTaR_DDL Long Distance Digital Display Link Transmitter & Receiver The GigaSTaR Digital Display Link is an innovative high-speed interconnect featuring simultaneous transmission of digital video, audio and bi-directional sideband data over a standard shielded twisted pair cable up to 50 m (500 m with fiber optics). It supports VESA video resolution standards ranging from VGA to XGA (INDT/R165B) or to UXGA (INDT/R330B) with up to 16.7 million colors. The sideband channels provide bandwidth up to 264 Mbps to connect peripheral components like keyboard, mouse, disc drive and audio devices. Features: Supported VESA video resolutions: - INDT/R165B: VGA ... XGA - INDT/R330B: VGA ... UXGA * Flexible parallel graphics controller and LC-display interfaces: - 12-bit (1/2 pixel/clock) - Tx only - 18- / 24-bit (1 pixel/clock) - 36- / 48-bit (2 pixel/clock) * Flexible pixel data clocking on rising/falling/both clock edges * Pixel Clock frequency: 24 - 161 MHz * Easy adaptation to DVI and LDI/LVDS through standard interface devices * 4 channel audio interface (IEC958 compliant S/PDIF) * High- and low-speed bi-directional sideband data channels * Single + 3.3 V power supply * Extended temperature range: -40 - +85 C * Applications: * Long distance multimedia consoles * High resolution industrial remote terminals * Video broadcast systems * Long distance camera links * Machine vision systems * Car navigation & telematics systems * Digital TV equipment * Video Projectors * Home Cinemas Chip Max. resolution (VESA, 60 Hz) and max. available video bandwidth Video, Audio, Sideband XGA 18-bit SXGA 24-bit Video, Audio XGA 18-bit UXGA 18-bit Video XGA 24-bit UXGA 18-bit INDT/R165B INDT/R330B Typical Application: Optional Data Sources PC Graphics Controller Camera DVD HDTV DATA AUDIO VIDEO Transmitter Receiver VIDEO TFT LC-Display INDT165B or INDT330B STP-cable INDR165B or INDR330B DATA AUDIO Date: 2005-02-18 Revision: 1.1 Page 1 of 41 Data Sheet INDT/R165B INDT/R330B Index 1. General Description ............................................................................................................................ 3 1.1 Link Interface ....................................................................................................................................3 1.1.1 Link Interface Bandwidth ............................................................................................................3 1.2 Pixel Interface ...................................................................................................................................4 1.2.1 General Information....................................................................................................................4 1.2.2 Pixel Interface Modes .................................................................................................................5 1.2.3 Pixel Clock Sampling Modes ......................................................................................................5 1.2.4 Pixel Data I/O Color Bit Mapping ................................................................................................7 1.3 Sideband Interface ............................................................................................................................8 1.3.1 General Information....................................................................................................................8 1.3.2 Low-speed Upstream Sideband Data Channel (SB0)..................................................................9 1.3.3 High-speed Upstream Sideband Data Channel (SB1).................................................................9 1.3.4 Low-speed Downstream Sideband Data Channel (SB2) .............................................................9 1.3.5 High-speed Downstream Sideband Data Channel (SB3, SB4). ...................................................9 1.3.6 Sideband Interface Signals.......................................................................................................10 1.4 Audio Interface................................................................................................................................11 Device Configuration ........................................................................................................................ 12 2.1 Configuration Vectors and Configuration Data .................................................................................12 2.2 Configuration Process and Timing ...................................................................................................13 2.3 Interface Configuration Scheme ......................................................................................................14 2.4 Error Handling and Reset (INDR330 only) .......................................................................................15 Electrical Specification ..................................................................................................................... 16 3.1 External Circuits ..............................................................................................................................16 3.1.1 External Loop Filter Specification..............................................................................................16 3.1.2 Serial Transmission Cable Interconnect....................................................................................16 3.1.3 Serial Transmission Cable Termination.....................................................................................17 3.1.4 Receiver Equalizer ...................................................................................................................17 3.1.5 Reference Clock.......................................................................................................................17 3.1.6 VREF Reference Circuitry...........................................................................................................17 3.2 Power Supply..................................................................................................................................17 3.3 Absolute Maximum Ratings .............................................................................................................18 3.4 Recommended Operating Conditions ..............................................................................................18 3.5 AC-Characteristics (under recommended operating conditions, Reference Clock Freq. = 66 MHz)..19 3.6 DC-Characteristics (under recommended operating conditions) ......................................................19 3.7 Reference Clock Specification (Ta = -40 to 85 C; Vcc = 3.15 to 3.45 V)..........................................19 3.8 Timing Specification ........................................................................................................................20 Signals............................................................................................................................................... 27 4.1 INDT165B Transmitter Signal Description........................................................................................27 4.2 INDR165B Receiver Signal Description ...........................................................................................28 4.3 INDT330B Transmitter Signal Description........................................................................................30 4.4 INDR330B Receiver Signal Description ...........................................................................................32 Pin Assignment ................................................................................................................................. 34 5.1 INDT165B Transmitter ....................................................................................................................34 5.2 INDR165B Receiver ........................................................................................................................35 5.3 INDT330B Transmitter ....................................................................................................................36 5.4 INDR330B Receiver ........................................................................................................................37 Package Information ......................................................................................................................... 38 6.1 INDT/R165B....................................................................................................................................38 6.2 INDT/R330B....................................................................................................................................39 GigaSTaR Digital Display Link Evaluation Kit................................................................................ 40 Ordering and Product Availability .................................................................................................... 40 Revision History................................................................................................................................ 41 Page 2 of 41 2 3 4 5 6 7 8 9 Date: 2005-02-18 Revision: 1.1 Data Sheet INDT/R165B INDT/R330B 1. General Description The GigaSTaR Digital Display Link is a high-speed serial and long distance link for video, audio and digital data, which supports the popular VESA standard but also proprietary video formats from VGA to UXGA with color depth up to 24 bits. 1.1 Link Interface The INDT/R165B link requires one single twisted pair cable for the high-speed downlink. The INDT/R330B provides double bandwidth by using two twisted pairs. Both devices offer an uplink connection using a twisted pair. The downlink must be established before the uplink can be activated. VIDEO M U X Downlink AUDIO Only INDT/R330 D E M U X VIDEO AUDIO SIDEBAND DATA Uplink SIDEBAND DATA Figure 1.1: GigaSTaR Digital Display Link Interfaces The transmitter's and receiver's generic parallel RGB interfaces (CMOS/TTL compatible) support direct connection to the parallel data port of any graphic controller or to any flat panel display with a parallel pixel data port. The bit width of the pixel data path can be scaled to support the 18- or 24-bit mode with 1 pixel/clock, the 36- or 48-bit mode with 2 pixel/clock, or the 12-bit mode with 1/2 pixel/clock. Pixel data can be clocked into the transmitter on the rising, falling or on both edges (only 12-, 18-, 24-bit mode) of the pixel clock. Pixel data are provided at the receiver on the rising, falling or on both edges (only 18-, 24-bit mode) of the pixel clock. 1.1.1 Link Interface Bandwidth The bandwidth of the downlink is shared between video, audio and sideband data. Disabling audio and/or sideband channels, even partially, increases the available bandwidth for the video data. The video configuration required for VESA standard compatible video resolutions is shown in Table 1.1 and Table 1.2. Mode 1 2 3 INDT/R165B configurations High-speed Low-speed Audio Sideband Sideband X X X/- - X X - - - Up to VESA-Mode XGA 18 color bits XGA 18 color bits XGA 24 color bits Table 1.1: INDT/R165B Video Configuration Date: 2005-02-18 Revision: 1.1 Page 3 of 41 Data Sheet INDT/R165B INDT/R330B Up to VESA-Mode SXGA 24 color bits UXGA 18 color bits UXGA 18 color bits Mode 1 2 3 INDT/R330B configurations High-speed Low-speed Audio Sideband Sideband X X X/- - X X - - - Table 1.2: INDT/R330B Video Configuration Note: Implementation of video modes other than VESA is possible. Special modes may need evaluation. 1.2 1.2.1 Pixel Interface General Information The pixel interface is designed to support direct interfacing to any digital graphics device with a parallel data port such as graphic-cards/controllers, CCD cameras or flat panel TFT displays. With standard interface devices the data port can also be adapted to systems with non-generic parallel interfaces such as DVI or LVDS/OpenLDI. PX_CLK+ PX_CLK- PX_D[47:0] 48 PX_HSYNC PX_VSYNC PX_DE PX_CLK+ Video Downstream Video PX_D[47:0] 48 PX_HSYNC PX_VSYNC PX_DE INDT Transmitter INDR Receiver Figure 1.2: Pixel Interface Signal PX_D[47:0] PX_CLK+ PX_CLK- PX_HSYNC PX_VSYNC PX_DE Tx IN IN IN IN IN IN 1 Rx OUT OUT OUT OUT OUT OUT Description Configurable parallel pixel data interface Pixel clock 24 - 161 MHz, diff + or single-ended Pixel clock 24 - 161 MHz, diff - Pixel data framing - Horizontal sync pulse Pixel data framing - Vertical sync pulse Pixel data framing - Data enable Table 1.3: Pixel Interface Signals 1 Configurable to 3.3V or 1.8V input levels via VREF-pin. Page 4 of 41 Date: 2005-02-18 Revision: 1.1 Data Sheet INDT/R165B INDT/R330B The transmitter's pixel interface accept pixel data with a pixel clock frequency of 24 - 161 MHz (full pixel mode). In singleended mode, PX_CLK+ is the clock input and PX_CLK- has to be tied to GND. All pixel data and pixel clock inputs of the transmitter can be selected through the VREF-pin to either work with conventional graphic controllers with 3.3 V output voltage swing or to work with latest controllers with low voltage swing (1.0 - 2.0 V, see Figure 3.3 VREF Reference Circuitry). The pixel data and pixel clock outputs of the receiver provide a 3.3 V CMOS compliant output. 1.2.2 Pixel Interface Modes The pixel interface is configurable to accommodate all the various graphic interface standards in the market. The width of the pixel interface is a function of the selected operating mode. * In half-pixel mode the bit width of the pixel interface is 12-bit. In half-pixel mode the lower and upper 12 bits of a parallel video interface (24-bit) are transmitted at consecutive sampling edges. This mode is supported only at the Tx devices. * In full-pixel mode the bit width of the pixel interface can be set to support an 18- or 24-bit wide parallel video interface. 1 pixel per sampling edge is transmitted. * In double-pixel mode the bit width of the pixel interface can be set to support a 36- or 48-bit wide parallel video interface. 2 pixels per sampling edge are transmitted. 1.2.3 Pixel Clock Sampling Modes The pixel interface can be set to support data sampling at the rising, falling or at both edges of the pixel clock, depending on the selected mode. Table 1.4 and Figure 1.3, Figure 1.4, Figure 1.5 summarize the various options for configuring the pixel interface. Pixel Mode Clock Edge PX_CLK+ PX_CLK Description both 12-bit (Half Pixel) TX Only both rising rising 18-bit (Full Pixel) 24-bit (Full Pixel) 36-bit (Double Pixel) 48-bit (Double Pixel) rising falling both rising falling both rising falling rising falling - - - - - - - - - - - - 12 bits low part of pixel(n) @ rising edge of PX_CLK+ 12 bits high part of pixel(n) @ falling edge of PX_CLK+ 12 bits low part of pixel(n) @ falling edge of PX_CLK+ 12 bits high part of pixel(n) @ rising edge of PX_CLK+ 12 bits low part of pixel(n) @ rising edge of PX_CLK+ 12 bits high part of pixel(n) @ rising edge of PX_CLK 12 bits low part of pixel(n) @ rising edge of PX_CLK 12 bits high part of pixel(n) @ rising edge of PX_CLK+ 18 bits of pixel(n) sampled at rising edge of PX_CLK+ 18 bits of pixel(n) sampled at falling edge of PX_CLK+ 18 bits of pixel(n) sampled at both edges of PX_CLK+ 24 bits of pixel(n) sampled at rising edge of PX_CLK+ 24 bits of pixel(n) sampled at falling edge of PX_CLK+ 24 bits of pixel(n) sampled at both edges of PX_CLK+ 18 bits of pixel(n) and 18 bits of pixel(n+1) sampled at rising edge of PX_CLK+ 18 bits of pixel(n) and 18 bits of pixel(n+1) sampled at falling edge of PX_CLK+ 24 bits of pixel(n) and 24 bits of pixel(n+1) sampled at rising edge of PX_CLK+ 24 bits of pixel(n) and 24 bits of pixel(n+1) sampled at falling edge of PX_CLK+ Table 1.4: Overview - Pixel Interface Configurations Date: 2005-02-18 Revision: 1.1 Page 5 of 41 Data Sheet INDT/R165B INDT/R330B PX_DE P0 P1 H L H L P2 H L P3 H L P4 H L P5 H L P6 H PX_D[11:0] L 12-bit Mode (Half Pixel) Both edge clock mode low part @ rising edge PX_CLK+ PX_CLK+ Both edge clock mode low part @ falling edge PX_CLK+ PX_CLK- Differential both edge clock mode both parts @ rising edge PX_CLK+ PX_CLK- Differential both edge clock mode both parts @ rising edge Figure 1.3: Pixel Interface - Half Pixel Modes PX_DE PX_D[23:0] P0 P1 P2 P3 P4 P5 P6 18/24-bit Mode (Full Pixel) rising edge clock mode PX_CLK+ PX_CLK+ falling edge clock mode PX_CLK+ both edge clock mode Figure 1.4: Pixel Interface - Full Pixel Modes PX_DE PX_D[47:24] P1 P3 P5 P7 Odd pixel 36/48-bit Mode (Double Pixel) PX_D[23:0] P0 P2 P4 P6 Even pixel PX_CLK+ rising edge clock mode PX_CLK+ falling edge clock mode Figure 1.5: Pixel Interface - Double Pixel Modes Date: 2005-02-18 Revision: 1.1 Page 6 of 41 Data Sheet INDT/R165B INDT/R330B 1.2.4 Pixel Data I/O Color Bit Mapping The color bits are mapped to the parallel I/Os as a function of the selected pixel clock (R = Red, G = Green, B = Blue, O = Odd, E = Even). Data PX_D47 PX_D46 PX_D45 PX_D44 PX_D43 PX_D42 PX_D41 PX_D40 PX_D39 PX_D38 PX_D37 PX_D36 PX_D35 PX_D34 PX_D33 PX_D32 PX_D31 PX_D30 PX_D29 PX_D28 PX_D27 PX_D26 PX_D25 PX_D24 PX_D23 PX_D22 PX_D21 PX_D20 PX_D19 PX_D18 PX_D17 PX_D16 PX_D15 PX_D14 PX_D13 PX_D12 PX_D11 PX_D10 PX_D9 PX_D8 PX_D7 PX_D6 PX_D5 PX_D4 PX_D3 PX_D2 PX_D1 PX_D0 Half Pixel 12-bit Mode - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - G[3]; R[7] G[2]; R[6] G[1]; R[5] G[0]; R[4] B[7]; R[3] B[6]; R[2] B[5]; R[1] B[4]; R[0] B[3]; G[7] B[2]; G[6] B[1]; G[5] B[0]; G[4] Full Pixel 18-bit Mode 24-bit Mode - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - R[5] R[7] R[4] R[6] R[3] R[5] R[2] R[4] R[1] R[3] R[0] R[2] - R[1] - R[0] G[5] G[7] G[4] G[6] G[3] G[5] G[2] G[4] G[1] G[3] G[0] G[2] - G[1] - G[0] B[5] B[7] B[4] B[6] B[3] B[5] B[2] B[4] B[1] B[3] B[0] B[2] - B[1] - B[0] Double Pixel 36-bit Mode 48-bit Mode RO[5] RO[7] RO[4] RO[6] RO[3] RO[5] RO[2] RO[4] RO[1] RO[3] RO[0] RO[2] - RO[1] - RO[0] GO[5] GO[7] GO[4] GO[6] GO[3] GO[5] GO[2] GO[4] GO[1] GO[3] GO[0] GO[2] - GO[1] - GO[0] BO[5] BO[7] BO[4] BO[6] BO[3] BO[5] BO[2] BO[4] BO[1] BO[3] BO[0] BO[2] - BO[1] - BO[0] RE[5] RE[7] RE[4] RE[6] RE[3] RE[5] RE[2] RE[4] RE[1] RE[3] RE[0] RE[2] - RE[1] - RE[0] GE[5] GE[7] GE[4] GE[6] GE[3] GE[5] GE[2] GE[4] GE[1] GE[3] GE[0] GE[2] - GE[1] - GE[0] BE[5] BE[7] BE[4] BE[6] BE[3] BE[5] BE[2] BE[4] BE[1] BE[3] BE[0] BE[2] - BE[1] - BE[0] Table 1.5: Pixel Interface Bit Mapping Date: 2005-02-18 Revision: 1.1 Page 7 of 41 Data Sheet INDT/R165B INDT/R330B 1.3 1.3.1 Sideband Interface General Information The sideband interfaces provide a bi-directional data path subdivided into several logical data streams with different bandwidth in both directions: Downstream: Data direction from Transmitter (INDT) Upstream: Data direction to Transmitter (INDT) --> <-- to Receiver (INDR) from Receiver (INDR) Activating the upstream sideband data transmission necessitates an additional pair of wires to establish the physical uplink (see 1.1 Link Interface). STP cables usually contain 4 pairs of wires; thus this extra connection is available in most cases. If the upstream sideband data channel is not used, it has to be disabled. The downstream sideband data channels can be partially disabled to provide extra bandwidth for the pixel data transmission. SB4_CLKI SB4_CLKO SB4_D[1:0] SB3_CLKI SB3_CLKO SB3_D[1:0] SB2_CLK SB2_D[3:0] SB4 2 SB4 High Speed 2 High Speed SB4_CLK SB4_D[1:0] SB3_CLK SB3_D[1:0] 2 SB3 High Speed 2 Downstream SB3 High Speed SB2 Low Speed 4 SB2 Low Speed 4 SB2_CLK SB2_D[3:0] SB1_CLKI SB1_CLKO SB1_D[1:0] SB0_CLK SB0_D[3:0] 4 SB1_CLK SB1_D[1:0] 2 SB1 High Speed SB1 High Speed 2 Upstream SB0_CLK SB0_D[3:0] 4 SB0 Low Speed SB0 Low Speed INDT Transmitter INDR Receiver Figure 1.6: Sideband Data Interfaces Note: SB4 available at INDT/R330B only. Date: 2005-02-18 Revision: 1.1 Page 8 of 41 Data Sheet INDT/R165B INDT/R330B Interface SB0 SB2 SB1 SB3 SB4 2 Signals (D+Clk) INDT INDR Speed Direction 4+1 4+1 2+1 2+2 2+2 4+1 4+1 2+2 2+1 2+1 Low speed Low speed High speed High speed High speed Upstream Downstream Upstream Downstream Downstream Width [bit] 4 Bandwidth [Mbps] 4.125 Asynchronous - - X X X Synchronous X X X X X Sampling - - - X X 4 2 2 2 4.26 111.375 132 132 Table 1.6: Transfer Capabilities Sideband Data Interface Signals 1.3.2 Low-speed Upstream Sideband Data Channel (SB0) The low-speed upstream sideband data channel consists of one 4 Mbps data channel with a 4-bit parallel interface (or 4 individual 1 Mbps data channels, each consisting of a 1-bit serial interface) and one synchronous clock output (SB0_CLK). 1.3.3 High-speed Upstream Sideband Data Channel (SB1) The high-speed upstream sideband data channel has a 2-bit wide data interface. Different operating modes can be selected. The maximum bandwidth is 111 Mbps. This can be used for any generic data link e.g. a low-resolution graphics channel or a CMOS image sensor. In asynchronous clocking mode an external clock can be applied into SB1_CLKI of the INDR. The range of the external acceptable clock frequency is 0 - 55 MHz. In synchronous mode data are read into the INDR using the synchronous clock frequency of 55 MHz being output at SB1_CLKO. In both cases the transferred data are available at the INDT with a fixed clock of 55 MHz. 1.3.4 Low-speed Downstream Sideband Data Channel (SB2) The low-speed downstream sideband data channel consists of one 4 Mbps data channel with a 4-bit parallel interface (or 4 individual 1 Mbps data channels, each consisting of a 1-bit serial interface) and one synchronous clock output (SB2_CLK). 1.3.5 High-speed Downstream Sideband Data Channel (SB3, SB42). The INDT/R165B (INDT/R330B) features one (two) high-speed downstream sideband data channels, each with a 2-bit wide data interface. Different operating modes can be selected. The maximum bandwidth is 132 Mbps (2 x 132 Mbps). In asynchronous clocking mode an external clock can be feed into SB3_CLKI (and SB4_CLKI ) of the INDT. The range of the external acceptable clock frequency is 0 - 66 MHz. In synchronous mode data are read into the INDT using the 2 synchronous clock frequency of 66 MHz being output at SB3_CLKO (and SB4_CLKO ). In both cases the transferred data are available at the INDR with a fixed clock of 66 MHz. In sampling mode, the sideband data are sampled with an internal sampling clock at 66 MHz. 2 2 Sideband Data Channel 4 (SB4) only available with INDT/R330B Page 9 of 41 Date: 2005-02-18 Revision: 1.1 Data Sheet INDT/R165B INDT/R330B 1.3.6 Sideband Interface Signals Sideband SB0 SB0 SB1 SB1 SB2 SB2 SB3 SB3 SB3 SB4 3 3 3 Signal Dir SB0_CLK SB0_D[3:0] SB1_CLK SB1_D[1:0] SB2_CLK SB2_D[3:0] SB3_CLKI SB3_CLKO SB3_D[1:0] SB4_CLKI SB4_CLKO SB4_D[1:0] OUT OUT OUT OUT OUT IN IN OUT IN IN OUT IN SB4 SB4 Description Sideband Data Channel 0 Upstream Synchronous Clock Output. Data is provided aligned to rising edge. Sideband Data Channel 0 Upstream Output Sideband Data Channel 1 Upstream Synchronous Clock Output. Data is provided aligned to rising edge. Sideband Data Channel 1 Upstream Output Sideband Data Channel 2 Downstream Synchronous Clock Output. Data is registered at rising edge. Sideband Data Channel 2 Downstream Input Sideband Data Channel 3 Downstream Asynchronous Clock Input. Data is registered at rising edge. Sideband Data Channel 3 Downstream Synchronous Clock Output. Data is registered at rising edge. Sideband Data Channel 3 Downstream Input Sideband Data Channel 4 Downstream Asynchronous Clock Input. Data is registered at rising edge. Sideband Data Channel 4 Downstream Synchronous Clock Output. Data is registered at rising edge. Sideband Data Channel 4 Downstream Input. Table 1.7: Sideband Interface Signals (INDT, Transmitter) Sideband SB0 SB0 SB1 SB1 SB1 SB2 SB2 SB3 SB3 SB4 SB4 3 3 Signal Dir SB0_CLK SB0_D[3:0] SB1_CLKI SB1_CLKO SB1_D[1:0] SB2_CLK SB2_D[3:0] SB3_CLK SB3_D[1:0] SB4_CLK SB4_D[1:0] OUT IN IN OUT IN OUT OUT OUT OUT OUT OUT Description Sideband Data Channel 0 Upstream Synchronous Clock Output. Data is registered at rising edge. Sideband Data Channel 0 Upstream Input Sideband Data Channel 1 Upstream Asynchronous Clock Input. Data is registered at rising edge. Sideband Data Channel 1 Upstream Synchronous Clock Output. Data is registered at rising edge. Sideband Data Channel 1 Upstream Input Sideband Data Channel 2 Downstream Synchronous Clock Output. Data is provided aligned to rising edge. Sideband Data Channel 2 Downstream Output Sideband Data Channel 3 Downstream Synchronous Clock Output. Data is provided aligned to rising edge. Sideband Data Channel 3 Downstream Output Sideband Data Channel 4 Downstream Synchronous Clock Output. Data is provided aligned to rising edge. Sideband Data Channel 4 Downstream Output. Table 1.8: Sideband Interface Signals (INDR, Receiver) 3 Sideband Data Channel 4 (SB4) only available with INDT/R330B Page 10 of 41 Date: 2005-02-18 Revision: 1.1 Data Sheet INDT/R165B INDT/R330B 1.4 Audio Interface The audio interface provides four serial audio channels, which are compliant to the Standard IEC958 Digital audio interface from the EBU (European Broadcasting Union), also known as S/P-DIF Interface. It supports sampling frequencies of 44,1 kHz and 48,0 kHz. The audio data interface can be disabled to free up bandwidth for pixel data transmission. AI_C0 AI_C1 AI_C2 AI_C3 INDT Transmitter Figure 1.7: Audio Interface AI_C0 Audio S/P DIF Downstream Audio S/P DIF AI_C1 AI_C2 AI_C3 INDR Reveiver Signal AI_C0 AI_C1 AI_C2 AI_C3 Tx IN IN IN IN Rx OUT OUT OUT OUT Description S/P-DIF Audio Channel 0 S/P-DIF Audio Channel 1 S/P-DIF Audio Channel 2 S/P-DIF Audio Channel 3 Table 1.9: Audio Interface Signals Date: 2005-02-18 Revision: 1.1 Page 11 of 41 Data Sheet INDT/R165B INDT/R330B 2 Device Configuration The GigaSTaR Digital Display Link allows for configuring the pixel-, sideband- and audio-interface. To configure the devices, four configuration vectors (cfg0 - cfg3, 4-bit each) must be loaded into the device through the low-speed sideband data interfaces SB0 and SB2. The Tx and the Rx device must be connected via the downlink. 2.1 Configuration Vectors and Configuration Data SB0 and SB2 sideband data are multiplexed and are also used for device configuration. After de-assertion of RESET#, CFG_CYC is automatically being driven high and enables the configuration process. The configuration select signals (CFG_SEL[3:0]) are provided sequentially at SB0 (INDT) respectively at SB2 (INDR). These select signals enable e.g. an external logic which provides the configuration vectors (cfg0 - cfg3) via the configuration signals CFG_D[3:0]. These are read at SB2 (INDT) respectively at SB0 (INDR). Sequence 1 2 3 4 Vector name cfg0 cfg1 cfg2 cfg3 Configuration Select Signals CFG_SEL[3:0] 0001 0010 0100 1000 Configuration vector Requests configuration vector 0 Requests configuration vector 1 Requests configuration vector 2 Requests configuration vector 3 Table 2.1: Configuration Vector Sequence Transmitter Configuration mode (CFG_CYC = 1) Normal mode (CFG_CYC = 0) CFG_SEL[3:0] CFG_D[3:0] Receiver CFG_SEL[3:0] CFG_D[3:0] SB0_D[3:0] SB2_D[3:0] SB2_D[3:0] SB0_D[3:0] Table 2.2: Pin Naming Multiplex Matrix CFGEN SYNC1/0 SB0_D[3...0] SB1_D[1...0] SDB CFGDATA LOW LOW t>1ms t>1ms For proper initialization of the upstream channel the side band data input at the Rx needs to be kept low for >1ms after the SYNC1/0 went high. Date: 2005-02-18 Revision: 1.1 Page 12 of 41 Data Sheet INDT/R165B INDT/R330B Figure 2.1 shows how to perform the configuration with external logic. CFG_CYC CFG_CYC CFG_SEL[3:0] (SB2_D[3:0]) SB0 0 1 2 CFG_SEL[3:0] (SB0_D[3:0]) 0 1 2 3 SB2 EN2 EN1 EN1 EN2 BUF 4 EN2 EN1 4 cfg0 cfg0 4 BUF 4 EN2 EN1 BUF 4 EN2 4 EN1 cfg1 cfg1 BUF 4 EN1 EN2 4 INDT cfg2 INDR cfg2 BUF 4 4 BUF 4 EN1 EN2 4 cfg3 4 0 1 2 3 BUF 4 0 1 2 3 SB2 CFG_D[3:0] (SB2_D[3:0]) CFG_D[3:0] (SB0_D[3:0]) SB0 Figure 2.1: Configuration Logic Each configuration vector's default setting is "1111". This popular operating mode (see light gray lines on following tables) can easily be established with pull-up resistors from the configuration inputs to VCC instead of tri-state buffers. All configuration vectors are valid for transmitter and receiver, unless otherwise noted. 2.2 Configuration Process and Timing Figure 2.2 shows the configuration process. RESET# CFG_CYC CFG_SEL[3:0] 0x0 0x1 0x0 0x2 0x0 0x4 0x0 0x8 0x0 CFG_D[3:0] Internal clock registers config data cfg0 cfg1 cfg2 cfg3 Figure 2.2: Timing of Configuration Process Date: 2005-02-18 Revision: 1.1 Page 13 of 41 Data Sheet INDT/R165B INDT/R330B 2.3 Interface Configuration Scheme Note: The low-speed downstream sideband is automatically enabled, when high-speed downstream sideband OR audio is enabled. INDT and INDR must be configured within the same group. Interface Vector Name Vector Bits 1100 1101 1110 0011 1111 0100 0101 1001 1010 0000 0001 0010 0110 0111 0000 Sideband Interface Tx 11XX cfg1 1100 1111 1110 Audio + High Speed Upstream SB1 X100 X111 01XX 11XX 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Tx only Pixel Interface 12-bit (Tx only) 12-bit (Tx only) 12-bit (Tx only) 12-bit (Tx only) 24-bit 24-bit 24-bit 48-bit 48-bit 18-bit 18-bit 18-bit 36-bit 36-bit Description 12 bits low part of pixel(n) @ rising edge of PX_CLK+ 12 bits high part of pixel(n) @ falling edge of PX_CLK+ 12 bits low part of pixel(n) @ falling edge of PX_CLK+ 12 bits high part of pixel(n) @ rising edge of PX_CLK+ 12 bits low part of pixel(n) @ rising edge of PX_CLK+ 12 bits high part of pixel(n) @ rising edge of PX_CLK12 bits low part of pixel(n) @ rising edge of PX_CLK12 bits high part of pixel(n) @ rising edge of PX_CLK+ 24 bits of pixel(n) sampled at rising edge of PX_CLK+ 24 bits of pixel(n) sampled at falling edge of PX_CLK+ 24 bits of pixel(n) sampled at both edges of PX_CLK+ 24 bits of pixel(n) and 24 bits of pixel(n+1) sampled at rising edge of PX_CLK+ 24 bits of pixel(n) and 24 bits of pixel(n+1) sampled at falling edge of PX_CLK+ 18 bits of pixel(n) sampled at rising edge of PX_CLK+ 18 bits of pixel(n) sampled at falling edge of PX_CLK+ 18 bits of pixel(n) sampled at both edges of PX_CLK+ 18 bits of pixel(n) and 18 bits of pixel(n+1) sampled at rising edge of PX_CLK+ 18 bits of pixel(n) and 18 bits of pixel(n+1) sampled at falling edge of PX_CLK+ Disable high-speed downstream sideband data channel 4 SB3 and SB4 Enable high-speed downstream sideband data channel 4 SB3 and SB4 Clocking: Asynchronous mode at downstream sideband 4 data channels SB3 and SB4 Clocking: Synchronous mode at downstream sideband 4 data channels SB3 and SB4 Clocking: Sampling mode at downstream sideband data 4 channels SB3 and SB4 Disable upstream sideband data Enable upstream sideband data Disable Audio Enable Audio Inom = x1.0, Ipre = x1.3, algorithm 1 Inom = x1.0, Ipre = x1.3, algorithm 2 Inom = x1.0, Ipre = x1.6, algorithm 1 Inom = x1.0, Ipre = x1.6, algorithm 2 Inom = x1.0, Ipre = x1.9, algorithm 1 Inom = x1.0, Ipre = x1.9, algorithm 2 Inom = x1.3, Ipre = x1.6, algorithm 1 Inom = x1.3, Ipre = x1.6, algorithm 2 Inom = x1.3, Ipre = x1.9, algorithm 1 Inom = x1.3, Ipre = x1.9, algorithm 2 Inom = x1.6, Ipre = x1.9, algorithm 1 Inom = x1.6, Ipre = x1.9, algorithm 2 Inom = Ipre = x1.9 Inom = Ipre = x1.3 Inom = Ipre = x1.0 Inom = Ipre = x1.6 Group V1 Pixel Interface cfg0 V2 S1 S2 cfg2 A PreEmphasis For Serial Upstream Transmission cfg3 Rx only Table 2.3: Configuration of the Pixel Interface Mode 4 Sideband Data Channel 4 (SB4) only available with INDT/R330B Page 14 of 41 Date: 2005-02-18 Revision: 1.1 Data Sheet INDT/R165B INDT/R330B 2.4 Error Handling and Reset (INDR330 only) The receiver provides an error detection signal (ERROR-pin) indicating incorrect video timing recovery. The below circuitry ensures the retry of the timing recovery process when an error occurs. 74LVX08 RESET_EXT_N RESET_N RESET# R D Q C Qn 1 INDR330B 74LVX74 ERR ERROR Figure 2.3: Auto-Reset Circuitry RESET_N <= RESET_EXT_N AND Qn; p_dff: PROCESS (RESET_N, ERR) BEGIN IF (RESET_N = '0') THEN Qn <= '1'; ELSIF (ERR'EVENT AND ERR = '1') THEN Qn <= '0'; END IF; END PROCESS p_dff; Figure 2.4: VHDL Code For Auto-Reset Circuitry Date: 2005-02-18 Revision: 1.1 Page 15 of 41 Data Sheet INDT/R165B INDT/R330B 3 Electrical Specification 3.1 3.1.1 External Circuits External Loop Filter Specification The internal PLLs of the INDT165B/330B and the INDR165B/330B devices require an external RC loop filter (Figure 3.1). R1 CAPx C R2 CAPy Figure 3.1: External Loop Filter Circuit It is recommended to implement the 0-Ohm resistors R1 and R2 for the transmitter as real components, because their values may change in future versions. Table 3.1 shows the optimal values for the INDT/R165B, Table 3.2 for the INDT/R330B. It is recommended to use SMD ceramic chip capacitors and chip resistors. Link PLL0 Signals Pins Parameter Symbol Value Tx (INDT165B) 1F 0 0 Value Rx (INDR165B) 1F 47 47 CAP1 CAP2 C11 C12 Loop Filter Capacitor Loop Filter Resistor 1 Loop Filter Resistor 2 C R1 R2 Table 3.1: External Loop Filter Specification for INDT/R165B Link PLL0 Signals Pins Parameter Symbol Value Tx (INDT330B) 1F 0 0 1F 0 0 Value Rx (INDR330B) 1F 47 47 1F 47 47 CAP1 CAP2 CAP3 CAP4 A15 B15 A8 B8 PLL1 Loop Filter Capacitor Loop Filter Resistor 1 Loop Filter Resistor 2 Loop Filter Capacitor Loop Filter Resistor 1 Loop Filter Resistor 2 C R1 R2 C R1 R2 Table 3.2: External Loop Filter Specification for INDT/R330B 3.1.2 Serial Transmission Cable Interconnect The serial lines have to be AC-coupled through 100 nF capacitors; RF ceramic capacitors shall be used. Values for R and L are dependent on the type of cable. Decoupling capacitor Cable termination TX0+ R L RX0+ TX0- Downstream TX1+ R RX0- RX1+ L INDT TX1- Only INDT/R 330 INDR RX1- RX2+ R L TX2+ RX2- Upstream TX2- Figure 3.2: Decoupling and Cable Termination Date: 2005-02-18 Revision: 1.1 Page 16 of 41 Data Sheet INDT/R165B INDT/R330B 3.1.3 Serial Transmission Cable Termination Besides the AC coupling capacitors, a dedicated cable termination has to be provided on the receiver input (Figure 3.2). The termination values have to be matched for the type of cable and length. 3.1.4 Receiver Equalizer The equalizer inside the receiver device compensates the frequency-dependant cable attenuation. For cable lengths5 above 10m, it is recommended to activate the equalizer function (pin EQ = HIGH) to achieve optimum transmission performance. 3.1.5 Reference Clock The serial downstream bit clock frequency of 1320 MHz is generated by internal PLLs. Both, transmitter and receiver require an external clock oscillator or reference clock of 66.0 MHz with a stability of 100 ppm. To enable the INDT/R165 supporting VESA Standard XGA24, the clock frequency must be 66.6667 MHz. However, the use of 66.6667 MHz clock frequency disables the transmission of audio data of 44.1 kHz sampling frequency. Transmission of audio data of 48 kHz sampling frequency is still possible as long as there is sufficient bandwidth left. 3.1.6 VREF Reference Circuitry The VREF-pin at the transmitter device has two modes to set the threshold level at the input pixel interface. For standard 3.3 V LVTTL input level, it must be tied to VCC (3.3 V). For low swing voltage levels (VDD = 1.0 - 2.0 V), VREF must be tied to half the supply voltage (VDD/2 = 0.5 - 1.0 V) of the driver (graphics controller). Figure 3.3 shows the input thresholds at different VREF levels: VREF MIN - 0.1 + 0.1 VREF MAX - 0.1 + 0.1 L L 0 0.5 H H Low Voltage Swing 0.5 < VREF < 1.0 V Voltage [V] 1 1.5 2 2.5 3.0 3.3 L 0.8 2.0 H LVTTL VREF = 3.3 V Figure 3.3 VREF Reference Circuitry 3.2 Power Supply Each GigaSTaR Digital Display Link chip consists of a separate Bipolar and CMOS die. Therefore, the device provides 6 multiple power planes to minimize EMI. It is suggested to use an own 3.3 V regulator for the whole chip to implement optimal decoupling of the power supply lines. Table 3.3 shows the current consumption of the devices. 7 Device INDT/R165B INDT/R330B Die CMOS Bipolar CMOS Bipolar Typical Current Consumption [mA] 400 230 400 540 Table 3.3: Current Consumption 5 6 7 Refers to the GORE reference cable GGSC1608-X, other cable types may differ. Do not use two separate regulators to avoid chip damage due to latch-up. Depending on video operating modes and external circuitry Page 17 of 41 Date: 2005-02-18 Revision: 1.1 Data Sheet INDT/R165B INDT/R330B Table 3.4 shows, which planes can be tied together. Pin Name VCC_CORE GND_CORE VCC_IO GND_IO VCC_CML GND_CML VCC_SX GND_SX VCC_IA GND_IA VCC_A0 GND_A0 VCC_A1 GND_A1 Type POWER GROUND POWER GROUND POWER GROUND POWER GROUND POWER GROUND POWER GROUND POWER GROUND Description VCC Plane No. 1A 1A 2A 4A (1A) 2A 3A 3A 8 GND Plane No. 1B 1B 2B 4B (1B) 2B 3B 3B CMOS core supply CMOS digital I/O supply CMOS chip-to-chip interface supply CMOS uplink I/O supply Bipolar Chip-to-chip interface supply Bipolar downlink I/O supply Bipolar PLL supply Table 3.4: Power Supply Planes 3.3 Absolute Maximum Ratings The absolute maximum ratings define values beyond which damage may occur to the device. Inova Semiconductors may not be held liable for any product degradation or damage caused by a violation of the absolute maximum ratings. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these or any other conditions above those indicated in the recommended operating conditions is not guaranteed. Parameter DC Supply Voltage Input Voltage I/O Current (DC or transient any pin) Junction Temperature (under bias) Storage Temperature Soldering Temp./Time Static Discharge Voltage (all pins except CML-Uplink-pins) 9 Static Discharge Voltage (all CML-Uplink pins) Symbol VCC VIN ID Tj Tstg TSLD / tSLD VESD1 VESD2 Min. -0.5 -0.5 -20 -45 -55 Max. +4.2 VCC+0.5 +20 +140 +150 220 / 10 2000 800 Units V V mA C C C / sec V V Note See keynote (6) See keynote (6) Human Body Model Human Body Model Table 3.5: Absolute Maximum Ratings 3.4 Recommended Operating Conditions Symbol VCC VIN IOUTCML IOUTCMOS Tj Ta Min. +3.15 0 -10 -10 0 -40 Max. +3.45 Vcc +10 +10 +125 +85 Units V V mA mA C C Note Vcc typ. = 3.3 V VCC =3.3V 0.15V Parameter DC Supply Voltage Input Voltage CML Output Current CMOS Output Current Junction Temperature (under bias) Ambient Temperature Table 3.6: Recommended Operating Conditions 8 9 Plane #4 may be connected to plane #1, if this plane is adequately noise-free. External ESD protection should be considered Page 18 of 41 Date: 2005-02-18 Revision: 1.1 Data Sheet INDT/R165B INDT/R330B 3.5 AC-Characteristics (under recommended operating conditions, Reference Clock Freq. = 66 MHz) Min. Typ. 1.5 1.32 757.6 5 Max. 3 Units pF Gbit/s ps ns Parameter Input capacitance, any pin (@ 66 MHz) Serial Transmission Data Rate (Downstream, per Link) Serial Bit Width (Downstream) CMOS Output Rise / Fall Time (CL = 10 pF) 10 Table 3.7: AC-Characteristics 3.6 DC-Characteristics (under recommended operating conditions) Symbol VIH VIL IIH IIL IIH IIL VOH VOL IOH IOL ILH ILL ICCTX165 ICCRX165 ICCTX330 ICCRX330 Test Condition Min. 2.6 -1 -1 -10 -10 0,95Vcc -3 3.5 -1 1.5 -5 6 -2.5 3 635 620 955 935 Typ. Max. 0.7 1 1 40 10 0,05 Vcc Unit V V A A A A V V mA mA mA mA mA mA mA mA Parameter CMOS Input High Voltage CMOS Input Low Voltage CMOS Input High Current CMOS Input Low Current EQLSEL/OSC Pin High Current EQLSEL/OSC Pin Low Current CMOS Output High Voltage CMOS Output Low Voltage CMOS Output High Current CMOS Output Low Current LOCK Output High Current LOCK Output Low Current INDT165B Supply Current INDR165B Supply Current INDT330B Supply Current INDR330B Supply Current VIN = Vcc VIN = 0 V VIN = Vcc VIN = 0 V IOH = -0.5 mA IOL = 1.5 mA VOH = 0.9Vcc VOL = 0.1Vcc VOH = 0.9Vcc VOL = 0.1Vcc CMOS output load = 10 pF @ Vcc typ. = 3.3 V CMOS output load = 10 pF @ Vcc typ. = 3.3 V CMOS output load = 10 pF @ Vcc typ. = 3.3 V CMOS output load = 10 pF @ Vcc typ. = 3.3 V 675 665 985 975 Table 3.8: DC-Characteristics Note: Floating CMOS inputs can result in excessive supply current. Therefore unused inputs should be tied to Vcc or Gnd. 3.7 Reference Clock Specification (Ta = -40 to 85 C; Vcc = 3.15 to 3.45 V) Symbol fOSC fOSC FTOL Min. Typ. 66.0 66.0 -100 40 +100 60 Max. Unit MHz MHz ppm % Note 66,6667 MHz possible, see 3.1.5 Parameter Nominal Frequency (INDT/R165) Nominal Frequency (INDT/R330) Frequency Tolerance Duty Cycle Table 3.9: Reference Clock Specification Date: 2005-02-18 Revision: 1.1 Page 19 of 41 Data Sheet INDT/R165B INDT/R330B 3.8 Timing Specification t1 (a) Transmitter pixel interface PCLK+ PX_D[47:0], PX_DE, PX_HSYNC, PX_VSYNC t2 Figure 3.4: Pixel Interface Timing Diagram At Rising Edge At Tx Parameter t1 t2 Description Pixel data and ctrl signal setup time to pixel clock at Tx Pixel data and ctrl signal hold time to pixel clock at Tx Min. 0.5 1.0 Typ. 0.9 1.3 Max. - Unit ns ns Table 3.10: Pixel Interface Timing Table At Rising Edge At Tx t3 PCLK+ PX_D[47:0], PX_DE, PX_HSYNC, PX_VSYNC t4 Figure 3.5: Pixel Interface Timing Diagram At One Pixel Per Clock At Falling Edge At Tx Parameter t3 t4 Description Pixel data and ctrl signal setup time to pixel clock at Tx Pixel data and ctrl signal hold time to pixel clock at Tx Min. 0.5 0.5 Typ. 0.9 1.3 Max. - Unit ns ns Table 3.11: Pixel Interface Timing Table At One Pixel Per Clock At Falling Edge At Tx Date: 2005-02-18 Revision: 1.1 Page 20 of 41 Data Sheet INDT/R165B INDT/R330B (b) Receiver pixel interface t5/6 PCLK+ PX_D[47:0], PX_DE, PX_HSYNC, PX_VSYNC t7 Figure 3.6: Pixel Interface Timing Diagram At Rising Edge At Rx Parameter t5 t6 t7 Description Pixel data and ctrl signal setup time to pixel clock at Rx (SXGA) Pixel data and ctrl signal setup time to pixel clock at Rx (UXGA) Pixel data and ctrl signal hold time to pixel clock at Rx Min. 1.8 1.6 0.5 Typ. 4.0 3.0 1.2 Max. 4.4 4.2 1.4 Unit ns ns ns Table 3.12: Pixel Interface Timing Table At Rising Edge At Rx t8/9 PCLK+ PX_D[47:0], PX_DE, PX_HSYNC, PX_VSYNC t10 Figure 3.7: Pixel Interface Timing Diagram At Falling Edge At Rx Parameter t8 t9 t10 Description Pixel data and ctrl signal setup time to pixel clock at Rx (SXGA) Pixel data and ctrl signal setup time to pixel clock at Rx (UXGA) Pixel data and ctrl signal hold time to pixel clock at Rx Min. 2.2 1.0 0.5 Typ. 3.8 2.9 1.2 Max. 4.7 3.7 1.3 Unit ns ns ns Table 3.13: Pixel Interface Timing Table At Falling Edge At Rx Date: 2005-02-18 Revision: 1.1 Page 21 of 41 Data Sheet INDT/R165B INDT/R330B (c) Transmitter sideband interface t11 SB2_CLK SB2_D[3:0] t13 t12 t14 Figure 3.8: Tx Sideband Data Interface; Low Speed Downstream Parameter t11 t12 t13 t14 Description Low speed downstream sideband data setup time to clock output at Tx Low speed downstream sideband data hold time to clock output at Tx Low speed downstream sideband data clock high time at Tx Low speed downstream sideband data clock low time at Tx Min. 40 0 29,3 900 Typ. 200 100 30 909 Max. 31,7 916 Unit ns ns ns ns Table 3.14: Tx Sideband Data Interface; Low Speed Downstream t15 SB3_CLKO SB3_D[1:0] SB3_CLKI t16 t19 t20 t17 t18 Figure 3.9: Tx Sideband Data Interface; High Speed Downstream Parameter t15 t16 t17 t18 t19 t20 Description High speed downstream sideband data setup time to clock output (synchronous mode) at Tx High speed downstream sideband data hold time to clock output (synchronous mode) at Tx High speed downstream sideband data setup time to clock input (asynchronous mode) at Tx High speed downstream sideband data hold time to clock input (asynchronous mode) at Tx High speed downstream sideband data clock output high time at Tx High speed downstream sideband data clock output low time Min. 6 0 2 2 6,1 8,6 Typ. 8.6 2.0 6.0 1.0 6.3 9.5 Max. 6,5 10,1 Unit ns ns ns ns ns ns Table 3.15: Tx Sideband Data Interface; High Speed Downstream Date: 2005-02-18 Revision: 1.1 Page 22 of 41 Data Sheet INDT/R165B INDT/R330B t21 SB0_CLK SB0_D[3:0] t24 t22 t23 Figure 3.10: Tx Sideband Data Interface; Low Speed Upstream Parameter t21 t22 t23 t24 Description Low speed upstream sideband data setup time to clock output at Tx Low speed upstream sideband data hold time to clock output at Tx Low speed upstream sideband data clock high time at Tx Low speed upstream sideband data clock low time at Tx Min. 420 520 532 430 Typ. 430 530 534 435 Max. 440 540 536 442 Unit ns ns ns ns Table 3.16: Tx Sideband Data Interface; Low Speed Upstream t25 SB1_CLK SB1_D[1:0] t28 t26 t27 Figure 3.11: Tx Sideband Data Interface; High Speed Upstream Parameter t25 t26 t27 t28 Description High speed upstream sideband data setup time to clock output at Tx High speed upstream sideband data hold time to clock output at Tx High speed upstream sideband data clock high time at Tx High speed upstream sideband data clock low time at Tx Min. 9,4 4,4 9,6 3,8 Typ. 10,2 5.5 10.5 9.7 Max. 11,5 6,0 11,5 10,2 Unit ns ns ns ns Table 3.17: Tx Sideband Data Interface; High Speed Upstream Date: 2005-02-18 Revision: 1.1 Page 23 of 41 Data Sheet INDT/R165B INDT/R330B (d) Receiver sideband interface t29 SB2_CLK SB2_D[3:0] t31 t30 t32 Figure 3.12: Rx Sideband Data Interface; Low Speed Downstream Parameter t29 t30 t31 t32 Description Low speed downstream sideband data setup time to clock output at Rx Low speed downstream sideband data hold time to clock output at Rx Low speed downstream sideband data clock high time at Rx Low speed downstream sideband data clock low time at Rx Min. 478 450 450 480 Typ. 484 455 454 484 Max. 490 460 458 490 Unit ns ns ns ns Table 3.18: Rx Sideband Data Interface; Low Speed Downstream t33 SB3_CLK SB3_D[1:0] t35 t34 t36 Figure 3.13: Rx Sideband Data Interface; High Speed Downstream Parameter t33 t34 t35 t36 Description High speed downstream sideband data setup time to clock output at Rx High speed downstream sideband data hold time to clock output at Rx High speed downstream sideband data clock high time at Rx High speed downstream sideband data clock low time at Rx Min. 5,5 7,2 9,8 5,5 Typ. 6.0 7,5 10.6 6.4 Max. 6,4 8,4 11,1 6,8 Unit ns ns ns ns Table 3.19: Rx Sideband Data Interface; High Speed Downstream Date: 2005-02-18 Revision: 1.1 Page 24 of 41 Data Sheet INDT/R165B INDT/R330B t37 SB0_CLK SB0_D[3:0] t39 t38 t40 Figure 3.14: Rx Sideband Data Interface; Low Speed Upstream Parameter t37 t38 t39 t40 Description Low speed upstream sideband data setup time to clock output at Rx Low speed upstream sideband data hold time to clock output at Rx Low speed upstream sideband data clock high time at Rx Low speed upstream sideband data clock low time at Rx Min. 20 0 47,9 912 Typ. 100 10 48,8 922 Max. 49,7 932 Unit ns ns ns ns Table 3.20: Rx Sideband Data Interface; Low Speed Upstream t41 SB1_CLKO SB1_D[1:0] SB1_CLKI t42 t45 t46 t43 t44 Figure 3.15: Rx Sideband Data Interface; High Speed Upstream Parameter t41 t42 t43 t44 t45 t46 Description High speed upstream sideband data setup time to clock output (synchronous mode) at Rx High speed upstream sideband data hold time to clock output (synchronous mode) at Rx High speed upstream sideband data setup time to clock output (asynchronous mode) at Rx High speed upstream sideband data hold time to clock output (asynchronous mode) at Rx High speed upstream sideband data clock high time at Rx High speed upstream sideband data clock low time at Rx Min. 4,0 0 0 1,0 7,2 9,7 Typ. 6,0 1,0 2,5 2,5 10,1 10,1 Max. - Unit ns ns ns ns 11,3 10,6 ns ns Table 3.21: Rx Sideband Data Interface; High Speed Upstream Date: 2005-02-18 Revision: 1.1 Page 25 of 41 Data Sheet INDT/R165B INDT/R330B t49 RESET# CFG_CYC CFG_SEL[3:0] CFG_D[3:0] 0000 0001 cfg0 0000 0010 cfg1 0000 0100 cfg2 0000 1000 cfg3 0000 t47 t48 configuration data sideband data Figure 3.16: Configuration Interface Timing Parameter t47 t48 t49 Description Configuration Select High Phase Configuration Select High to Configuration Data valid Configuration data valid after Configuration Select high to low transition Min. - Typ. 350 100 0 Max. - Unit ns ns ns Table 3.22: Configuration Interface Timing Date: 2005-02-18 Revision: 1.1 Page 26 of 41 Data Sheet INDT/R165B INDT/R330B 4 Signals 4.1 INDT165B Transmitter Signal Description Pin Dir Type Description Pin Name Link Interface TX0+ TX0- RX2+ RX2- LOCK0 SYNC2 Pixel Interface PX_CLK+ PX_CLK- B8 B9 A5 A4 B6 B2 K14 J14 (see Table 4.3) J13 H13 H14 G13 A13 A11,B11,A 12,B12 E14 D14,D13 C13 A14,B14,B 13,C14 G14 F13 E13,F14 C2 C1 D2 D1 B3 A2 A1 A6 C11 C12 B1 OUT OUT IN IN OUT OUT IN IN IN IN IN IN IN OUT OUT OUT OUT OUT IN IN OUT IN IN IN IN IN IN OUT OUT IN IN IN - CML CML CML CML LVTTL LVTTL LVTTL* LVTTL* LVTTL* LVTTL* LVTTL* LVTTL* A LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL A A - Serial Data Output (Downlink) Serial Data Input (Uplink) Lock Indicator. HIGH when PLL of Downlink is properly locked HIGH when the Uplink is frame synchronous Pixel clock 24 - 161 MHz, diff + or single-ended Pixel clock 24 - 161 MHz, diff - pull to GND in single ended mode Configurable parallel pixel data interface Pixel data framing - Horizontal sync pulse (active HIGH) Pixel data framing - Vertical sync pulse (active HIGH) Pixel data framing - Data enable (active HIGH) Configures the input level of the pixel interface Sideband Data Channel 0 Upstream Synchronous Clock Output. Data is provided aligned to rising edge. If CFG_CYC=0: Sideband Data Channel 0 Upstream Output If CFG_CYC=1: Configuration vector output Sideband Data Channel 1 Upstream Synchronous Clock Output. Data is provided aligned to rising edge. Sideband Data Channel 1 Upstream Output Sideband Data Channel 2 Downstream Synchronous Clock Output. Data is registered at rising edge. If CFG_CYC=0: Sideband Data Channel 2 Downstream Input If CFG_CYC=1: Configuration data input Sideband Data Channel 3 Downstream Asynchronous Clock Input. Data is registered at rising edge. Sideband Data Channel 3 Downstream Synchronous Clock Output. Data is registered at rising edge. Sideband Data Channel 3 Downstream Input S/P-DIF Audio Channel 0 S/P-DIF Audio Channel 1 S/P-DIF Audio Channel 2 S/P-DIF Audio Channel 3 Asynchronous Hardware Reset (active LOW) Pixel Buffer Overrun Indicates that the configuration process is active Reference Oscillator Input (see chapter 3.7) Loop filter pin of Downlink Loop filter pin of Downlink Not connected PX_D[47:0] PX_HSYNC PX_VSYNC PX_DE VREF Sideband Interface SB0_CLK SB0_D[3:0] (CFG_SEL[3:0]) SB1_CLK SB1_D[1:0] SB2_CLK SB2_D[3:0] (CFG_D[3:0]) SB3_CLKI SB3_CLKO SB3_D[1:0] Audio Interface AI_C0 AI_C1 AI_C2 AI_C3 Other Signals RESET# ERROR CFG_CYC OSC CAP1 CAP2 NC Table 4.1: INDT165B Transmitter Signals * Configurable to LVTTL or Low Voltage Swing via VREF-pin Date: 2005-02-18 Revision: 1.1 Page 27 of 41 Data Sheet INDT/R165B INDT/R330B Dir Type Description Pin Name Pin Power Supply C3,D3,E4,G7,G8,G10,H3,H8,J3,J4,J8,J11,L5,L6,L10,M3,M8,M11, VCC_CORE M12 D5,E5,E11,F4,F6,F11,G4,G6,H5,H6,H10,H12,J10,K3,K7,K8,K11, GND_CORE L3,L11,M9 C4,D4,E2,E3,G9,G11,H4,H7,H11,J7,J12,K5,K6,K9,K10,L9,L12,M4, VCC_IO M7 A3,C5,E12,F3,F5,F12,G3,G5,G12,H9,J5,J6,J9,K4,K12,L4,L7,L8,M5, GND_IO M6,M10 VCC_CML F7,F8 GND_CML F9,F10 VCC_SX B4 GND_SX B5 VCC_IA E8,E10 GND_IA E7,E9 VCC_A0 A7,A10,C6,C7,C10,D6,D12 GND_A0 A8,A9,B7,B10,C8,C9,D11,E6 VCC_A1 D9,D10 GND_A1 D7,D8 IN IN IN IN IN IN IN IN IN IN IN IN IN IN POWER CMOS core supply GROUND POWER GROUND POWER GROUND POWER GROUND POWER GROUND POWER GROUND POWER GROUND CMOS digital I/O supply CMOS chip-to-chip interface supply CMOS uplink I/O supply Bipolar Chip-to-chip interface supply Bipolar downlink I/O supply Bipolar PLL supply Table 4.2: INDT165B Transmitter Power Supply Pin Name PX_D47 PX_D46 PX_D45 PX_D44 PX_D43 PX_D42 PX_D41 PX_D40 PX_D39 PX_D38 PX_D37 PX_D36 Pin K13 L14 L13 M14 M13 N14 N13 P14 P13 P12 N12 P11 Pin Name PX_D35 PX_D34 PX_D33 PX_D32 PX_D31 PX_D30 PX_D29 PX_D28 PX_D27 PX_D26 PX_D25 PX_D24 Pin N11 P10 N10 P9 N9 P8 N8 P7 N7 P6 N6 P5 Pin Name PX_D23 PX_D22 PX_D21 PX_D20 PX_D19 PX_D18 PX_D17 PX_D16 PX_D15 PX_D14 PX_D13 PX_D12 Pin N5 P4 N4 P3 N3 P2 P1 N1 N2 M1 M2 L1 Pin Name PX_D11 PX_D10 PX_D9 PX_D8 PX_D7 PX_D6 PX_D5 PX_D4 PX_D3 PX_D2 PX_D1 PX_D0 Pin L2 K1 K2 J1 J2 H1 H2 G1 G2 F1 F2 E1 Table 4.3: INDT165B Transmitter Pixel Data Pin Numbers 4.2 INDR165B Receiver Signal Description Pin Dir Type Description Pin Name Link Interface RX0+ RX0- TX2+ TX2- LOCK0 SYNC0 EQ Pixel Interface PX_CLK+ PX_CLK- B8 B9 A5 A4 B6 B2 C5 J14 H14 (see Table 4.6) G13 H13 J13 A13 A11,B11,A 12,B12 E13 IN IN OUT OUT OUT OUT IN OUT OUT OUT OUT OUT OUT OUT IN IN CML CML CML CML LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL Serial Data Input (Downlink 0) Serial Data Output (Uplink) Lock Indicator. HIGH when PLL of Downlink is properly locked High, when the Downlink is frame synchronous Selects the Downlink equalizer (LOW=OFF; HIGH=ON) Pixel clock 24 - 161 MHz, diff + or single-ended Pixel clock 24 - 161 MHz, diff - pull to GND in single ended mode Configurable parallel pixel data interface Pixel data framing - Horizontal sync pulse (active HIGH) Pixel data framing - Vertical sync pulse (active HIGH) Pixel data framing - Data enable (active HIGH) Sideband Data Channel 0 Upstream Synchronous Clock Output. Data is registered at rising edge. If CFG_CYC=0: Sideband Data Channel 0 Upstream Input If CFG_CYC=1: Configuration data input Sideband Data Channel 1 Upstream Asynchronous Clock Input. Data is registered at rising edge. Page 28 of 41 PX_D[47:0] PX_HSYNC PX_VSYNC PX_DE Sideband Interface SB0_CLK SB0_D[3:0] (CFG_D[3:0]) SB1_CLKI Date: 2005-02-18 Revision: 1.1 Data Sheet INDT/R165B INDT/R330B Pin Name Pin Dir Type SB1_CLKO SB1_D[1:0] SB2_CLK SB2_D[3:0] (CFG_SEL[3:0]) SB3_CLK SB3_D[1:0] Audio Interface AI_C0 AI_C1 AI_C2 AI_C3 Other Signals RESET# ERROR CFG_CYC OSC CAP1 CAP2 NC E14 D14,D13 C13 A14,B14,B 13,C14 G14 F14,F13 C2 C1 D2 D1 B3 A2 A1 A6 C11 C12 B1 OUT IN OUT OUT OUT OUT OUT OUT OUT OUT IN OUT OUT IN IN IN - LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL A A - Description Sideband Data Channel 1 Upstream Synchronous Clock Output. Data is registered at rising edge. Sideband Data Channel 1 Upstream Input Sideband Data Channel 2 Downstream Synchronous Clock Output. Data is provided aligned to rising edge. If CFG_CYC=0: Sideband Data Channel 2 Downstream Output If CFG_CYC=1: Configuration vector output Sideband Data Channel 3 Downstream Synchronous Clock Output. Data is provided aligned to rising edge. Sideband Data Channel 3 Downstream Output S/P-DIF Audio Channel 0 S/P-DIF Audio Channel 1 S/P-DIF Audio Channel 2 S/P-DIF Audio Channel 3 Asynchronous Hardware Reset (active LOW) Pixel Clock Recovery Error Indicates that the configuration process is active Reference Oscillator Input (see chapter 3.7) Loop filter pin of Downlink Loop filter pin of Downlink Not connected Table 4.4: INDR165B Receiver Signals Pin Name Pin Power Supply VCC_CORE C3,E3,G8,G10,J3,J4,J7,J11,L5,L6,L10,M8,M11 GND_CORE E4,E11,F4,F11,F12,G4,G6,H6,H10,J10,K8,K11,L3,L8,M9 C4,D3,D4,E2,F2,G7,G9,G11,H3,H4,H7,H8,H11,J8,J12,K5,K6,K9, VCC_IO K10,L9,L12,M3,M4,M7,M12 A3,D5,E5,E12,F3,F5,F6,G3,G5,G12,H5,H9,H12,J5,J6,J9,K3,K4,K7, GND_IO K12,L4,L7,L11,M5,M6,M10 VCC_CML F7,F8 GND_CML F9,F10 VCC_SX B4 GND_SX B5 VCC_IA E8,E10 GND_IA E7,E9 VCC_A0 A7,A10,C6,C7,C10,D6,D12 GND_A0 A8,A9,B7,B10,C8,C9,D11,E6 VCC_A1 D9,D10 GND_A1 D7,D8 Dir Type Description IN IN IN IN IN IN IN IN IN IN IN IN IN IN POWER GROUND POWER GROUND POWER GROUND POWER GROUND POWER GROUND POWER GROUND POWER GROUND CMOS core supply CMOS digital I/O supply CMOS chip-to-chip interface supply CMOS uplink I/O supply Bipolar Chip-to-chip interface supply Bipolar downlink I/O supply Bipolar PLL supply Table 4.5: INDR165B Receiver Power Supply Pin Name PX_D47 PX_D46 PX_D45 PX_D44 PX_D43 PX_D42 PX_D41 PX_D40 PX_D39 PX_D38 PX_D37 PX_D36 Pin K14 K13 L14 L13 M14 M13 N14 N13 P14 P13 P12 N12 Pin Name PX_D35 PX_D34 PX_D33 PX_D32 PX_D31 PX_D30 PX_D29 PX_D28 PX_D27 PX_D26 PX_D25 PX_D24 Pin P11 N11 P10 N10 P9 N9 P8 N8 P7 N7 P6 N6 Pin Name PX_D23 PX_D22 PX_D21 PX_D20 PX_D19 PX_D18 PX_D17 PX_D16 PX_D15 PX_D14 PX_D13 PX_D12 Pin P5 N5 P4 N4 P3 N3 P2 P1 N1 N2 M1 M2 Pin Name PX_D11 PX_D10 PX_D9 PX_D8 PX_D7 PX_D6 PX_D5 PX_D4 PX_D3 PX_D2 PX_D1 PX_D0 Pin L1 L2 K1 K2 J1 J2 H1 H2 G1 G2 F1 E1 Table 4.6: INDR165B Receiver Pixel Data Pin Numbers Date: 2005-02-18 Revision: 1.1 Page 29 of 41 Data Sheet INDT/R165B INDT/R330B 4.3 INDT330B Transmitter Signal Description Pin Dir Type Description Pin Name Link Interface TX0+ TX0- TX1+ TX1- RX2+ RX2- LOCK0 LOCK1 SYNC2 Pixel Interface PX_CLK+ PX_CLK- B12 B13 B5 B6 A10 A9 B10 B3 C2 T18 R18 (see Table 4.9) R17 P18 P17 N18 C18 A16,A17,A 18,B18 G18 F18,F17 E17 C17,D18, D17,E18 J18 H17 G17,H18 N17 M18 K18,L18 D2 D1 E1 F1 A2 B2 B1 A3 A15 B15 A8 B8 C1 OUT OUT OUT OUT IN IN OUT OUT OUT IN IN IN IN IN IN IN OUT OUT OUT OUT OUT IN IN OUT IN IN OUT IN IN IN IN IN IN OUT OUT IN IN IN IN IN - CML CML CML CML CML CML LVTTL LVTTL LVTTL LVTTL* LVTTL* LVTTL* LVTTL* LVTTL* LVTTL* A LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL A A A A - Serial Data Output (Downlink 0) Serial Data Output (Downlink 1) Serial Data Input (Uplink) Lock Indicator 0. HIGH when PLL of Downlink 0 is properly locked Lock Indicator 1. HIGH when PLL of Downlink 1 is properly locked HIGH when the Uplink is frame synchronous Pixel clock 24 - 161 MHz, diff + or single-ended Pixel clock 24 - 161 MHz, diff - pull to GND in single ended mode Configurable parallel pixel data interface Pixel data framing - Horizontal sync pulse (active HIGH) Pixel data framing - Vertical sync pulse (active HIGH) Pixel data framing - Data enable (active HIGH) Configures the input level of the pixel interface Sideband Data Channel 0 Upstream Synchronous Clock Output. Data is provided aligned to rising edge. If CFG_CYC=0: Sideband Data Channel 0 Upstream Output If CFG_CYC=1: Configuration vector output Sideband Data Channel 1 Upstream Synchronous Clock Output. Data is provided aligned to rising edge. Sideband Data Channel 1 Upstream Output Sideband Data Channel 2 Downstream Synchronous Clock Output. Data is registered at rising edge. If CFG_CYC=0: Sideband Data Channel 2 Downstream Input If CFG_CYC=1: Configuration data input Sideband Data Channel 3 Downstream Asynchronous Clock Input. Data is registered at rising edge. Sideband Data Channel 3 Downstream Synchronous Clock Output. Data is registered at rising edge. Sideband Data Channel 3 Downstream Input Sideband Data Channel 4 Downstream Asynchronous Clock Input. Data is registered at rising edge. Sideband Data Channel 4 Downstream Synchronous Clock Output. Data is registered at rising edge. Sideband Data Channel 1 Downstream Input S/P-DIF Audio Channel 0 S/P-DIF Audio Channel 1 S/P-DIF Audio Channel 2 S/P-DIF Audio Channel 3 Asynchronous Hardware Reset. Active LOW Pixel Buffer Overrun Indicates that the configuration process is active Reference Oscillator Input (see chapter 3.7) Loop filter pin Downlink 0 Loop filter pin Downlink 0 Loop filter pin Downlink 1 Loop filter pin Downlink 1 Not connected PX_D[47:0] PX_HSYNC PX_VSYNC PX_DE VREF Sideband Interface SB0_CLK SB0_D[3:0] (CFG_SEL[3:0]) SB1_CLK SB1_ D[1:0] SB2_CLK SB2_D[3:0] (CFG_D[3:0]) SB3_CLKI SB3_CLKO SB3_D[1:0] SB4_CLKI SB4_CLKO SB4_D[1:0] Audio Interface AI_C0 AI_C1 AI_C2 AI_C3 Other Signals RESET# ERROR CFG_CYC OSC CAP1 CAP2 CAP3 CAP4 NC Table 4.7: INDT330B Transmitter Signals * Configurable to LVTTL or Low Voltage Swing via VREF-pin Date: 2005-02-18 Revision: 1.1 Page 30 of 41 Data Sheet INDT/R165B INDT/R330B Dir Type Description Pin Name Pin Power Supply G3,G4,G9,G12,H4,J4,J8,J12,J15,J16,J17,L6,L10,L14,N2,N3,N4,N8, VCC_CORE N12,R6,R10,R14,T6,T10,T14 F2,G7,G13,G14,H6,H10,H14,J2,J3,K2,K4,K8,K12,K15,K16,K17,L2, GND_CORE M6,M10,M14,P4,P8,P12,P15,P16,T3,T4 G2,G5,G8,G10,G11,G15,G16,H2,H3,H7,H8,H11,H12,H15,H16,J7, J11,K5,K6,K9,K10,K13,K14,L5,L9,L13,M2,M3,M4,M7,M8,M11,M12, VCC_IO M15,M16,M17,N7,N11,N15,N16,P5,P6,P9,P10,P13,P14,R5,R9, R13,T5,T9,T13 A1,B16,B17,C16,D9,D16,E2,E3,E9,E15,E16,F3,F8,F9,F10,F15,F16, G6,H5,H9,H13,J5,J6,J9,J10,J13,J14,K3,K7,K11,L3,L4,L7,L8,L11, GND_IO L12,L15,L16,L17,M5,M9,M13,N5,N6,N9,N10,N13,N14,P3,P7,P11, R3,R4,R7,R8,R11,R12,R15,R16,T2,T7,T8,T11,T12,T15,T16,U2 VCC_CML F4,F5,F11,F12 GND_CML F6,F7,F13,F14 VCC_SX B9 GND_SX C9 VCC_IA E6,E8,E12,E14 GND_IA E5,E7,E11,E13 VCC_A0 A4,A7,A11,A14,C3,C4,C8,C10,C11,C15,D3,D8,D10,D15 GND_A0 A5,A6,A12,A13,B4,B7,B11,B14,C5,C6,C7,C12,C13,C14,E4,E10 VCC_A1 D6,D7,D13,D14 GND_A1 D4,D5,D11,D12 IN IN IN POWER CMOS core supply GROUND POWER CMOS digital I/O supply IN IN IN IN IN IN IN IN IN IN IN GROUND POWER GROUND POWER GROUND POWER GROUND POWER GROUND POWER GROUND CMOS chip-to-chip interface supply CMOS uplink I/O supply Bipolar Chip-to-chip interface supply Bipolar downlink I/O supply Bipolar PLL supply Table 4.8: INDT330B Transmitter Power Supply Pin Name PX_D47 PX_D46 PX_D45 PX_D44 PX_D43 PX_D42 PX_D41 PX_D40 PX_D39 PX_D38 PX_D37 PX_D36 Pin T17 U18 U17 V18 V17 V16 U16 V15 U15 V14 U14 V13 Pin Name PX_D35 PX_D34 PX_D33 PX_D32 PX_D31 PX_D30 PX_D29 PX_D28 PX_D27 PX_D26 PX_D25 PX_D24 Pin U13 V12 U12 V11 U11 V10 U10 V9 U9 V8 U8 V7 Pin Name PX_D23 PX_D22 PX_D21 PX_D20 PX_D19 PX_D18 PX_D17 PX_D16 PX_D15 PX_D14 PX_D13 PX_D12 Pin U7 V6 U6 V5 U5 V4 U4 V3 U3 V2 V1 U1 Pin Name PX_D11 PX_D10 PX_D9 PX_D8 PX_D7 PX_D6 PX_D5 PX_D4 PX_D3 PX_D2 PX_D1 PX_D0 Pin T1 R1 R2 P1 P2 N1 M1 L1 K1 J1 H1 G1 Table 4.9: INDT330B Transmitter Pixel Data Pin Numbers Date: 2005-02-18 Revision: 1.1 Page 31 of 41 Data Sheet INDT/R165B INDT/R330B 4.4 INDR330B Receiver Signal Description Pin Dir Type Description Pin Name Link Interface RX0+ RX0- RX1+ RX1- TX2+ TX2- LOCK0 LOCK1 SYNC0 SYNC1 EQ Pixel Interface PX_CLK+ PX_CLK- B12 B13 B5 B6 A10 A9 B10 B3 C1 D1 A2 R18 P18 (see Table 4.12) N18 N17 P17 C18 A16,A17,A 18,B18 G17 G18 F18,F17 E17 C17,D18, D17,E18 M18 K18,L18 J18 H18,H17 E1 F1 G1 H1 A1 B1 C2 A3 A15 B15 A8 B8 IN IN IN IN OUT OUT OUT OUT OUT OUT IN OUT OUT OUT OUT OUT OUT OUT IN IN OUT IN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT IN OUT OUT IN IN IN IN IN CML CML CML CML CML CML LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL A A A A Serial Data Input (Downlink 0) Serial Data Input (Downlink 1) Serial Data Output (Uplink) Lock Indicator 0. HIGH when PLL of Downlink 0 is properly locked Lock Indicator 1. HIGH when PLL of Downlink 1 is properly locked HIGH when the Downlink 0 is frame synchronous HIGH when the Downlink 1 is frame synchronous Selects the Downlink equalizer (LOW=OFF; HIGH=ON) Pixel clock 24 - 161 MHz, diff + or single-ended Pixel clock 24 - 161 MHz, diff - pull to GND in single ended mode Configurable parallel pixel data interface Pixel data framing - Horizontal sync pulse (active HIGH) Pixel data framing - Vertical sync pulse (active HIGH) Pixel data framing - Data enable (active HIGH) Sideband Data Channel 0 Upstream Synchronous Clock Output. Data is registered at rising edge. If CFG_CYC=0: Sideband Data Channel 0 Upstream Input If CFG_CYC=1: Configuration data input Sideband Data Channel 1 Upstream Asynchronous Clock Input. Data is registered at rising edge. Sideband Data Channel 1 Upstream Synchronous Clock Output. Data is registered at rising edge. Sideband Data Channel 1 Upstream Input Sideband Data Channel 2 Downstream Synchronous Clock Output. Data is provided aligned to rising edge. If CFG_CYC=0: Sideband Data Channel 2 Downstream Output If CFG_CYC=1: Configuration vector output Sideband Data Channel 3 Downstream Synchronous Clock Output. Data is provided aligned to rising edge. Sideband Data Channel 3 Downstream Output Sideband Data Channel 4 Downstream Synchronous Clock Output. Data is provided aligned to rising edge. Sideband Data Channel 4 Downstream Output S/P-DIF Audio Channel 0 S/P-DIF Audio Channel 1 S/P-DIF Audio Channel 2 S/P-DIF Audio Channel 3 Asynchronous Hardware Reset (active LOW) Pixel Clock Recovery Error Indicates that the configuration process is active Reference Oscillator Input (see chapter 3.7) Loop filter pin Downlink 0 Loop filter pin Downlink 0 Loop filter pin Downlink 1 Loop filter pin Downlink 1 PX_D[47:0] PX_HSYNC PX_VSYNC PX_DE Sideband Interface SB0_CLK SB0_D[3:0] (CFG_D[3:0]) SB1_CLKI SB1_CLKO SB1_ D[1:0] SB2_CLK SB2_D[3:0] (CFG_SEL[3:0]) SB3_CLK SB3_D[1:0] SB4_CLK SB4_D[1:0] Audio Interface AI_C0 AI_C1 AI_C2 AI_C3 Other Signals RESET# ERROR CFG_CYC OSC CAP1 CAP2 CAP3 CAP4 Table 4.10: INDR330B Receiver Signals Date: 2005-02-18 Revision: 1.1 Page 32 of 41 Data Sheet INDT/R165B INDT/R330B Dir Type Description Pin Name Pin Power Supply G4,G9,G12,H3,H4,J3,J4,J8,J12,J15,J16,J17,L6,L10,L14,N3,N4,N8, VCC_CORE N12,R6,R10,R14,T6,T10,T14 E3,F15,G7,G13,H6,H10,H14,K3,K4,K8,K12,K15,K16,K17,L3,L4,M6, GND_CORE M10,M14,P4,P8,P12,P15,P16,R4,R16,T4 G2,G3,G5,G8,G10,G11,G15,G16,H2,H7,H8,H11,H12,H15,H16,J2, VCC_IO J7,J11,K5,K6,K9,K10,K13,K14,L5,L9,L13,M3,M4,M7,M8,M11,M12,M15,M16 ,M17,N2,N7,N11,N15,N16,P5,P6,P9,P10,P13,P14,R5,R9,R13,T5,T9,T13 B2,B16,B17,C16,D2,D9,D16,E2,E9,E15,E16,F2,F3,F8,F9,F10,F16, G6,G14,H5,H9,H13,J5,J6,J9,J10,J13,J14,K2,K7,K11,L2,L7,L8,L11, GND_IO L12,L15,L16,L17,M2,M5,M9,M13,N5,N6,N9,N10,N13,N14,P3,P7, P11,R3,R7,R8,R11,R12,R15,T2,T3,T7,T8,T11,T12,T15,T16,U2 VCC_CML F4,F5,F11,F12 GND_CML F6,F7,F13,F14 VCC_SX B9 GND_SX C9 VCC_IA E6,E8,E12,E14 GND_IA E5,E7,E11,E13 VCC_A0 A4,A7,A11,A14,C3,C4,C8,C10,C11,C15,D3,D8,D10,D15 GND_A0 A5,A6,A12,A13,B4,B7,B11,B14,C5,C6,C7,C12,C13,C14,E4,E10 VCC_A1 D6,D7,D13,D14 GND_A1 D4,D5,D11,D12 IN IN IN POWER CMOS core supply GROUND POWER CMOS digital I/O supply IN IN IN IN IN IN IN IN IN IN IN GROUND POWER GROUND POWER GROUND POWER GROUND POWER GROUND POWER GROUND CMOS chip-to-chip interface supply CMOS uplink I/O supply Bipolar Chip-to-chip interface supply Bipolar downlink I/O supply Bipolar PLL supply Table 4.11: INDR330B Receiver Power Supply Pin Name PX_D47 PX_D46 PX_D45 PX_D44 PX_D43 PX_D42 PX_D41 PX_D40 PX_D39 PX_D38 PX_D37 PX_D36 Pin R17 T18 T17 U18 U17 V18 V17 V16 U16 V15 U15 V14 Pin Name PX_D35 PX_D34 PX_D33 PX_D32 PX_D31 PX_D30 PX_D29 PX_D28 PX_D27 PX_D26 PX_D25 PX_D24 Pin U14 V13 U13 V12 U12 V11 U11 V10 U10 V9 U9 V8 Pin Name PX_D23 PX_D22 PX_D21 PX_D20 PX_D19 PX_D18 PX_D17 PX_D16 PX_D15 PX_D14 PX_D13 PX_D12 Pin U8 V7 U7 V6 U6 V5 U5 V4 U4 V3 U3 V2 Pin Name PX_D11 PX_D10 PX_D9 PX_D8 PX_D7 PX_D6 PX_D5 PX_D4 PX_D3 PX_D2 PX_D1 PX_D0 Pin V1 U1 T1 R1 R2 P1 P2 N1 M1 L1 K1 J1 Table 4.12: INDR330B Receiver Pixel Data Pin Numbers Date: 2005-02-18 Revision: 1.1 Page 33 of 41 Data Sheet INDT/R165B INDT/R330B 5 Pin Assignment 5.1 INDT165B Transmitter 1 A B C D E F G H J K L M N P CFG_ CYC 2 ERROR 3 GND_ IO 4 RX2- 5 RX2+ 6 OSC 7 VCC_ A0 GND_ A0 VCC_ A0 GND_ A1 GND_ IA VCC_ CML VCC_ CORE VCC_ IO VCC_ IO GND_ CORE GND_ IO VCC_ IO 8 GND_ A0 9 GND_ A0 10 VCC_ A0 GND_ A0 VCC_ A0 VCC_ A1 VCC_ IA GND_ CML VCC_ CORE GND_ CORE GND_ CORE VCC_ IO VCC_ CORE GND_ IO 11 SB0_ D3 SB0_ D2 12 SB0_ D1 SB0_ D0 13 SB0_ CLK SB2_ D1 SB2_ CLK SB1_ D0 SB3_ D1 SB3_ CLKO 14 SB2_ D3 SB2_ D2 SB2_ D0 SB1_ D1 SB1_ CLK SB3_ D0 SB3_ CLKI PX_ DE PX_ CLK- PX_ CLK+ NC SYNC2 RESET# VCC_ SX VCC_ IO VCC_ IO VCC_ CORE GND_ CORE GND_ CORE VCC_ IO VCC_ CORE GND_ IO GND_ IO VCC_ IO GND_ SX GND_ IO GND_ CORE GND_ CORE GND_ IO GND_ IO GND_ CORE GND_ IO VCC_ IO VCC_ CORE GND_ IO LOCK0 TX0+ TX0- AI_C1 AI_C0 VCC_ CORE VCC_ CORE VCC_ IO GND_ IO GND_ IO VCC_ CORE VCC_ CORE GND_ CORE GND_ CORE VCC_ CORE VCC_ A0 VCC_ A0 GND_ A0 GND_ CORE GND_ CORE GND_ CORE GND_ IO VCC_ IO VCC_ CORE GND_ IO GND_ A0 GND_ A1 VCC_ IA VCC_ CML VCC_ CORE VCC_ CORE VCC_ CORE GND_ CORE GND_ IO VCC_ CORE GND_ A0 VCC_ A1 GND_ IA GND_ CML VCC_ IO GND_ IO GND_ IO VCC_ IO VCC_ IO GND_ CORE CAP1 CAP2 AI_C3 AI_C2 GND_ A0 GND_ CORE GND_ CORE VCC_ IO VCC_ IO VCC_ CORE GND_ CORE GND_ CORE VCC_ CORE VCC_ A0 GND_ IO GND_ IO GND_ IO GND_ CORE VCC_ IO GND_ IO VCC_ IO VCC_ CORE PX_D0 VCC_ IO PX_D2 PX_D1 PX_D4 PX_D3 VREF PX_D6 PX_D5 PX_ VSYNC PX_ HSYNC PX_D8 PX_D7 PX_D10 PX_D9 PX_D47 PX_D12 PX_D11 PX_D45 PX_D46 PX_D14 PX_D13 PX_D43 PX_D44 PX_D16 PX_D15 PX_D19 PX_D21 PX_D23 PX_D25 PX_D27 PX_D29 PX_D31 PX_D33 PX_D35 PX_D37 PX_D41 PX_D42 PX_D17 PX_D18 PX_D20 PX_D22 PX_D24 PX_D26 PX_D28 PX_D30 PX_D32 PX_D34 PX_D36 PX_D38 PX_D39 PX_D40 Table 5.1: INDT165B GigaSTaR Digital Display Link Transmitter Pin Assignment (Top View) = Pin A1 Identifier Date: 2005-02-18 Revision: 1.1 Page 34 of 41 Data Sheet INDT/R165B INDT/R330B 5.2 INDR165B Receiver 1 A B C D E F G H J K L M N P CFG_ CYC 2 ERROR 3 GND_ IO 4 TX2- 5 TX2+ 6 OSC 7 VCC_ A0 GND_ A0 VCC_ A0 GND_ A1 GND_ IA VCC_ CML VCC_ IO VCC_ IO VCC_ CORE GND_ IO GND_ IO VCC_ IO 8 GND_ A0 9 GND_ A0 10 VCC_ A0 GND_ A0 VCC_ A0 VCC_ A1 VCC_ IA GND_ CML VCC_ CORE GND_ CORE GND_ CORE VCC_ IO VCC_ CORE GND_ IO 11 SB0_ D3 SB0_ D2 12 SB0_ D1 SB0_ D0 13 SB0_ CLK SB2_ D1 SB2_ CLK SB1_ D0 SB1_ CLKI SB3_ D0 PX_ HSYNC PX_ VSYNC 14 SB2_ D3 SB2_ D2 SB2_ D0 SB1_ D1 SB1_ CLKO SB3_ D1 SB3_ CLK PX_ CLK- PX_ CLK+ NC SYNC0 RESET# VCC_ SX VCC_ IO VCC_ IO GND_ CORE GND_ CORE GND_ CORE VCC_ IO VCC_ CORE GND_ IO GND_ IO VCC_ IO GND_ SX LOCK0 RX0+ RX0- AI_C1 AI_C0 VCC_ CORE VCC_ IO VCC_ CORE GND_ IO GND_ IO VCC_ IO VCC_ CORE GND_ IO GND_ CORE VCC_ IO EQ VCC_ A0 VCC_ A0 GND_ A0 GND_ IO GND_ CORE GND_ CORE GND_ IO VCC_ IO VCC_ CORE GND_ IO GND_ A0 GND_ A1 VCC_ IA VCC_ CML VCC_ CORE VCC_ IO VCC_ IO GND_ CORE GND_ CORE VCC_ CORE GND_ A0 VCC_ A1 GND_ IA GND_ CML VCC_ IO GND_ IO GND_ IO VCC_ IO VCC_ IO GND_ CORE CAP1 CAP2 AI_C3 AI_C2 GND_ IO GND_ IO GND_ IO GND_ IO GND_ IO GND_ IO VCC_ IO VCC_ CORE GND_ IO GND_ A0 GND_ CORE GND_ CORE VCC_ IO VCC_ IO VCC_ CORE GND_ CORE GND_ IO VCC_ CORE VCC_ A0 GND_ IO GND_ CORE GND_ IO GND_ IO VCC_ IO GND_ IO VCC_ IO VCC_ IO PX_D0 VCC_ IO VCC_ IO PX_D1 PX_D3 PX_D2 PX_D5 PX_D4 PX_D7 PX_D6 PX_DE PX_D9 PX_D8 PX_D46 PX_D47 PX_D11 PX_D10 PX_D44 PX_D45 PX_D13 PX_D12 PX_D42 PX_D43 PX_D15 PX_D14 PX_D18 PX_D20 PX_D22 PX_D24 PX_D26 PX_D28 PX_D30 PX_D32 PX_D34 PX_D36 PX_D40 PX_D41 PX_D16 PX_D17 PX_D19 PX_D21 PX_D23 PX_D25 PX_D27 PX_D29 PX_D31 PX_D33 PX_D35 PX_D37 PX_D38 PX_D39 Table 5.2: INDR165B GigaSTaR Digital Display Link Receiver Pin Assignment (Top View) Date: 2005-02-18 Revision: 1.1 Page 35 of 41 Data Sheet INDT/R165B INDT/R330B 5.3 INDT330B Transmitter 1 2 RESET# 3 OSC 4 VCC_ A0 GND_ A0 VCC_ A0 GND_ A1 GND_ A0 VCC_ CML VCC_ CORE VCC_ CORE VCC_ CORE GND_ CORE GND_ IO VCC_ IO VCC_ CORE GND_ CORE GND_ IO GND_ CORE 5 GND_ A0 6 GND_ A0 7 VCC_ A0 GND_ A0 GND_ A0 VCC_ A1 GND_ IA GND_ CML GND_ CORE VCC_ IO VCC_ IO GND_ IO GND_ IO VCC_ IO VCC_ IO GND_ IO GND_ IO GND_ IO 8 CAP3 9 RX2- 10 RX2+ 11 VCC_ A0 GND_ A0 VCC_ A0 GND_ A1 GND_ IA VCC_ CML VCC_ IO VCC_ IO VCC_ IO GND_ IO GND_ IO VCC_ IO VCC_ IO GND_ IO GND_ IO GND_ IO 12 GND_ A0 13 GND_ A0 14 VCC_ A0 GND_ A0 GND_ A0 VCC_ A1 VCC_ IA GND_ CML GND_ CORE GND_ CORE GND_ IO VCC_ IO VCC_ CORE GND_ CORE GND_ IO VCC_ IO VCC_ CORE VCC_ CORE 15 CAP1 16 SB0_ D3 GND_ IO GND_ IO GND_ IO GND_ IO GND_ IO VCC_ IO VCC_ IO VCC_ CORE GND_ CORE GND_ IO VCC_ IO VCC_ IO GND_ CORE GND_ IO GND_ IO 17 SB0_ D2 GND_ IO SB2_ D3 SB2_ D1 SB2_ CLK SB1_ D0 SB3_ D1 SB3_ CLKO VCC_ CORE GND_ CORE GND_ IO VCC_ IO SB4_ CLKI 18 SB0_ D1 SB0_ D0 SB0_ CLK SB2_ D2 SB2_ D0 SB1_ D1 SB1_ CLK SB3_ D0 SB3_ CLKI SB4_ D1 SB4_ D0 SB4_ CLKO A B C D E F G H J K L M N P R T U V GND_ IO CFG_ CYC ERROR LOCK1 TX1+ TX1- CAP4 VCC_ SX GND_ SX GND_ IO GND_ IO GND_ IO VCC_ CORE GND_ IO GND_ IO VCC_ IO VCC_ IO GND_ IO GND_ IO VCC_ IO VCC_ IO VCC_ IO LOCK0 TX0+ TX0- CAP2 NC SYNC2 VCC_ A0 VCC_ A0 GND_ IO GND_ IO VCC_ CORE VCC_ IO GND_ CORE GND_ IO GND_ IO VCC_ IO VCC_ CORE GND_ IO GND_ IO GND_ CORE GND_ A0 GND_ A1 GND_ IA VCC_ CML VCC_ IO GND_ IO GND_ IO VCC_ IO VCC_ IO GND_ IO GND_ IO VCC_ IO VCC_ IO VCC_ IO GND_ A0 VCC_ A1 VCC_ IA GND_ CML GND_ IO GND_ CORE GND_ IO VCC_ IO VCC_ CORE GND_ CORE GND_ IO VCC_ IO VCC_ CORE VCC_ CORE VCC_ A0 VCC_ A0 VCC_ IA GND_ IO VCC_ IO VCC_ IO VCC_ CORE GND_ CORE GND_ IO VCC_ IO VCC_ CORE GND_ CORE GND_ IO GND_ IO VCC_ A0 VCC_ A0 GND_ A0 GND_ IO VCC_ IO GND_ CORE GND_ IO VCC_ IO VCC_ CORE GND_ CORE GND_ IO VCC_ IO VCC_ CORE VCC_ CORE GND_ A0 GND_ A1 VCC_ IA VCC_ CML VCC_ CORE VCC_ IO VCC_ CORE GND_ CORE GND_ IO VCC_ IO VCC_ CORE GND_ CORE GND_ IO GND_ IO GND_ A0 VCC_ A1 GND_ IA GND_ CML GND_ CORE GND_ IO GND_ IO VCC_ IO VCC_ IO GND_ IO GND_ IO VCC_ IO VCC_ IO VCC_ IO VCC_ A0 VCC_ A0 GND_ IO GND_ IO VCC_ IO VCC_ IO VCC_ CORE GND_ CORE GND_ IO VCC_ IO VCC_ IO GND_ CORE GND_ IO GND_ IO AI_C1 AI_C0 AI_C2 GND_ IO GND_ CORE VCC_ IO VCC_ IO GND_ CORE GND_ CORE GND_ CORE VCC_ IO VCC_ CORE AI_C3 PX_D0 PX_D1 PX_D2 PX_D3 PX_D4 PX_D5 PX_D6 VREF PX_D8 PX_D7 PX_DE PX_ VSYNC PX_ CLK- PX_ CLK+ PX_D10 PX_D9 PX_ HSYNC PX_D11 GND_ IO GND_ IO PX_D47 PX_D12 PX_D15 PX_D17 PX_D19 PX_D21 PX_D23 PX_D25 PX_D27 PX_D29 PX_D31 PX_D33 PX_D35 PX_D37 PX_D39 PX_D41 PX_D45 PX_D46 PX_D13 PX_D14 PX_D16 PX_D18 PX_D20 PX_D22 PX_D24 PX_D26 PX_D28 PX_D30 PX_D32 PX_D34 PX_D36 PX_D38 PX_D40 PX_D42 PX_D43 PX_D44 Table 5.3: INDT330B GigaSTaR Digital Display Link Transmitter Pin Assignment (Top View) Date: 2005-02-18 Revision: 1.1 Page 36 of 41 Data Sheet INDT/R165B INDT/R330B 5.4 INDR330B Receiver 1 2 EQ 3 OSC 4 VCC_ A0 GND_ A0 VCC_ A0 GND_ A1 GND_ A0 VCC_ CML VCC_ CORE VCC_ CORE VCC_ CORE GND_ CORE GND_ CORE VCC_ IO VCC_ CORE GND_ CORE GND_ CORE GND_ CORE 5 GND_ A0 6 GND_ A0 7 VCC_ A0 GND_ A0 GND_ A0 VCC_ A1 GND_ IA GND_ CML GND_ CORE VCC_ IO VCC_ IO GND_ IO GND_ IO VCC_ IO VCC_ IO GND_ IO GND_ IO GND_ IO 8 CAP3 9 TX2- 10 TX2+ 11 VCC_ A0 GND_ A0 VCC_ A0 GND_ A1 GND_ IA VCC_ CML VCC_ IO VCC_ IO VCC_ IO GND_ IO GND_ IO VCC_ IO VCC_ IO GND_ IO GND_ IO GND_ IO 12 GND_ A0 13 GND_ A0 14 VCC_ A0 GND_ A0 GND_ A0 VCC_ A1 VCC_ IA GND_ CML GND_ IO GND_ CORE GND_ IO VCC_ IO VCC_ CORE GND_ CORE GND_ IO VCC_ IO VCC_ CORE VCC_ CORE 15 CAP1 16 SB0_ D3 GND_ IO GND_ IO GND_ IO GND_ IO GND_ IO VCC_ IO VCC_ IO VCC_ CORE GND_ CORE GND_ IO VCC_ IO VCC_ IO GND_ CORE GND_ CORE GND_ IO 17 SB0_ D2 GND_ IO SB2_ D3 SB2_ D1 SB2_ CLK SB1_ D0 SB1_ CLKI SB4_ D0 VCC_ CORE GND_ CORE GND_ IO VCC_ IO PX_ VSYNC 18 SB0_ D1 SB0_ D0 SB0_ CLK SB2_ D2 SB2_ D0 SB1_ D1 SB1_ CLKO SB4_ D1 SB4_ CLK SB3_ D1 SB3_ D0 SB3_ CLK PX_ HSYNC PX_ CLK- PX_ CLK+ A B C D E F G H J K L M N P R T U V RESET# ERROR GND_ IO CFG_ CYC GND_ IO GND_ IO GND_ IO VCC_ IO VCC_ IO VCC_ IO GND_ IO GND_ IO GND_ IO VCC_ IO LOCK1 RX1+ RX1- CAP4 VCC_ SX GND_ SX GND_ IO GND_ IO GND_ IO VCC_ CORE GND_ IO GND_ IO VCC_ IO VCC_ IO GND_ IO GND_ IO VCC_ IO VCC_ IO VCC_ IO LOCK0 RX0+ RX0- CAP2 SNYC0 VCC_ A0 VCC_ A0 GND_ CORE GND_ IO VCC_ IO VCC_ CORE VCC_ CORE GND_ CORE GND_ CORE VCC_ IO VCC_ CORE GND_ IO GND_ IO GND_ IO GND_ A0 GND_ A1 GND_ IA VCC_ CML VCC_ IO GND_ IO GND_ IO VCC_ IO VCC_ IO GND_ IO GND_ IO VCC_ IO VCC_ IO VCC_ IO GND_ A0 VCC_ A1 VCC_ IA GND_ CML GND_ IO GND_ CORE GND_ IO VCC_ IO VCC_ CORE GND_ CORE GND_ IO VCC_ IO VCC_ CORE VCC_ CORE VCC_ A0 VCC_ A0 VCC_ IA GND_ IO VCC_ IO VCC_ IO VCC_ CORE GND_ CORE GND_ IO VCC_ IO VCC_ CORE GND_ CORE GND_ IO GND_ IO VCC_ A0 VCC_ A0 GND_ A0 GND_ IO VCC_ IO GND_ CORE GND_ IO VCC_ IO VCC_ CORE GND_ CORE GND_ IO VCC_ IO VCC_ CORE VCC_ CORE GND_ A0 GND_ A1 VCC_ IA VCC_ CML VCC_ CORE VCC_ IO VCC_ CORE GND_ CORE GND_ IO VCC_ IO VCC_ CORE GND_ CORE GND_ IO GND_ IO GND_ A0 VCC_ A1 GND_ IA GND_ CML GND_ CORE GND_ IO GND_ IO VCC_ IO VCC_ IO GND_ IO GND_ IO VCC_ IO VCC_ IO VCC_ IO VCC_ A0 VCC_ A0 GND_ IO GND_ CORE VCC_ IO VCC_ IO VCC_ CORE GND_ CORE GND_ IO VCC_ IO VCC_ IO GND_ CORE GND_ IO GND_ IO SYNC1 AI_C0 AI_C1 AI_C2 AI_C3 PX_D0 PX_D1 PX_D2 PX_D3 PX_D4 PX_D6 PX_D5 PX_DE PX_D8 PX_D7 PX_D47 PX_D9 GND_ IO GND_ IO PX_D45 PX_D46 PX_D10 PX_D13 PX_D15 PX_D17 PX_D19 PX_D21 PX_D23 PX_D25 PX_D27 PX_D29 PX_D31 PX_D33 PX_D35 PX_D37 PX_D39 PX_D43 PX_D44 PX_D11 PX_D12 PX_D14 PX_D16 PX_D18 PX_D20 PX_D22 PX_D24 PX_D26 PX_D28 PX_D30 PX_D32 PX_D34 PX_D36 PX_D38 PX_D40 PX_D41 PX_D42 Table 5.4: INDR330B GigaSTaR Digital Display Link Receiver Pin Assignment (Top View) Date: 2005-02-18 Revision: 1.1 Page 37 of 41 Data Sheet INDT/R165B INDT/R330B 6 Package Information 6.1 INDT/R165B Figure 6.1: Package: BGA 196, 15 x 15 mm, 196 balls, 1 mm ball pitch Dim Min Nom Max A - 1.9 A1 0.36 0.46 A2 0.38 REF A3 1.0 REF b 0.44 0.64 D 15 BSC E 15 BSC e 1.0 BSC D1 13 BSC E1 13 BSC All dimensions and tolerances in mm! Figure 6.2: BGA 196 - Dimensions and Tolerances Date: 2005-02-18 Revision: 1.1 Page 38 of 41 Data Sheet INDT/R165B INDT/R330B 6.2 INDT/R330B Figure 6.3: Package: BGA 324, 19 x 19 mm, 324 balls, 1 mm ball pitch Dim Min Nom Max A - 2.0 A1 0.4 0.6 A2 0.38 Ref A3 1.0 Ref b 0.55 0.7 D 19 BSC E 19 BSC e 1.0 BSC D1 17 BSC E1 17 BSC All dimensions and tolerances in mm! Figure 6.4: BGA 324 - Dimensions and Tolerances Date: 2005-02-18 Revision: 1.1 Page 39 of 41 Data Sheet INDT/R165B INDT/R330B 7 GigaSTaR Digital Display Link Evaluation Kit The evaluation kit IND330_AK adapts DVI-monitors and displays to DVI-sources (PCs, DVD-players, etc.). A DVI-to-LVDS-version is available on request. The INDT/R330-based ANACONDA evaluation kit consists of two boards (Tx, Rx), one 5 m CAT-cable, wall power supplies and programming software for configuration of the RS232 return path (PS/2 on request) through the on-board Z8microprocessor and the Lattice CPLD. 8 Ordering and Product Availability Ordering Code INDT165B INDR165B IND165SK INDT330B INDR330B IND330SK IND330_AK Delivery Package Tray (in sealed dry pack) Tray (in sealed dry pack) Sample Kit (5 x Tx, 5 x Rx) Tray (in sealed dry pack) Tray (in sealed dry pack) Sample Kit (2 x Tx, 2 x Rx) Eval Kit Minimum Packing Quantity 126 units 126 units 10 units 84 units 84 units 4 units 1 unit Status Full Production Full Production Full Production Full Production Full Production Full Production Full Production Table 8.1: Product Availability Date: 2005-02-18 Revision: 1.1 Page 40 of 41 Data Sheet INDT/R165B INDT/R330B 9 Revision History The information contained in this data sheet supersedes information published in previous versions. The following changes were made: * v 1.0 Data Sheet Minor changes in line with the product status change from "Pre-Production" to "Fully Released" Updates/Changes: Chapter 1.3 Side Band Interface Chapter 2.1 Configuration Vectors Chapter 3.3 Absolute Maximum Ratings Chapter 7 GigaSTaR Digital Display Evaluation Kit Chapter 8 Ordering and Product Availability * v1.1 Data Sheet Adjustment of supply current statements Chapter 3.2 Power Supply Chapter 3.4 Recommended Operating Conditions Chapter 3.6 DC Characteristics Inova Semiconductors GmbH Grafinger Str. 26 D-81675 Munich, Germany Phone: +49 (0)89 / 45 74 75 - 60 Fax: +49 (0)89 / 45 74 75 - 88 Email: mailto:info@inova-semiconductors.de URL: http://www.inova-semiconductors.com is a registered trademark of Inova Semiconductors GmbH. All other trademarks or registered trademarks are the property of their respective holders. Inova Semiconductors products are not designed, intended or authorized for use as components in systems to support or sustain life, or for any other application in which the failure of the product could create a situation where personal injury or death may occur. The information contained in this document is believed to be current and accurate as of the publication date. Inova Semiconductors GmbH reserves the right to make changes at any time in order to improve reliability, function or performance to supply the best product possible. Inova Semiconductors GmbH assumes no obligation to correct any errors contained herein or to advise any user of this text of any correction if such be made. (c) Inova Semiconductors 2005 Date: 2005-02-18 Revision: 1.1 Page 41 of 41 |
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