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| PRELIMINARY CY8CNP102B, CY8CNP102E Nonvolatile Programmable System-on-Chip (PSoC(R) NV) Overview The Cypress nonvolatile Programmable System-on-Chip (PSoC(R) NV) processor combines a versatile Programmable System-on-ChipTM (PSoC) core with an infinite endurance nvSRAM in a single package. The PSoC NV combines an 8-bit MCU core (M8C), configurable analog and digital functions, a uniquely flexible IO interface, and a high density nvSRAM. This creates versatile data logging solutions that provide value through component integration and programmability. The flexible core and a powerful development environment work to reduce design complexity, component count, and development time. Precision, Programmable Clocking Internal 2.5% 24 and 48 MHz Oscillator 24 and 48 MHz with optional 32.768 kHz Crystal Optional External Oscillator, up to 24 MHz Internal Oscillator for Watchdog and Sleep Flexible On-Chip Memory 32K Bytes Flash Program Storage 2K Bytes SRAM Data Storage 256K Bytes secure store nvSRAM with data throughput between 100 KBPS and 1 MBPS In-System Serial Programming (ISSP) Partial Flash Updates Flexible Protection Modes EEPROM Emulation in Flash Programmable Pin Configurations 33 GPIOs 25 mA Sink on all GPIO Pull up, Pull down, High Z, Strong, or Open Drain Drive Modes on all GPIO Up to 12 Analog Inputs on GPIOs Analog Outputs with 40 mA on 4 GPIOs Configurable Interrupt on all GPIOs Additional System Resources 2 I C Slave, Master, and MultiMaster to 100 Kbps and 400 Kbps Watchdog and Sleep Timers Integrated Supervisory Circuit On-Chip Precision Voltage Reference Complete Development Tools Free Development Software (PSoC DesignerTM) Full Featured, In Circuit Emulator and Programmer Full Speed Emulation C Compilers, Assembler, and Linker Temperature and Packaging Industrial Temperature Range: -40C to +85C Packaging: 100-pin TQFP Features Powerful Harvard Architecture Processor M8C processor speeds * Up to 12 MHz for 3.3V operation * Up to 24 MHz for 5V operation Two 8x8 multiply, 32 bit accumulate Low power at high speed Operating Voltage 3.3V (CY8CNP102B) 5V (CY8CNP102E) Advanced Peripherals 12 Rail-to-Rail Analog PSoC blocks provide: * Up to 14 bit ADCs * Up to 9 bit DACs * Programmable Gain Amplifiers * Programmable Filters and Comparators * 8 Analog channels for simultaneous sampling * Up to 820 SPS for each channel with 8 channel sampling and logging 16 Digital PSoC Blocks provide: * 8 to 32 bit timers, counters, and PWMs * CRC and PRS Modules * Up to 4 Full Duplex UARTs * Multiple SPITM Masters and Slaves Complex Peripherals by Combining Blocks Cypress Semiconductor Corporation Document #: 001-43991 Rev. *D * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised October 20, 2008 [+] Feedback PRELIMINARY CY8CNP102B, CY8CNP102E Logic Block Diagram Document #: 001-43991 Rev. *D Page 2 of 38 [+] Feedback PRELIMINARY CY8CNP102B, CY8CNP102E Pinouts Figure 1. Pin Diagram - 100-Pin TQFP Package (14 x 14 x 1.4 mm) Table 1. Pin Definitions - 100-Pin TQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Pin Name P0_5 P0_3 P0_1 P2_7 P2_5 P2_3 P2_1 Vcc DNU DNU DNU DNU DNU NC P3_5 EN_W P3_1 IO IO Type Digital IO IO IO IO IO IO IO Power I I Analog IO IO I Pin Definition Analog Column Mux Input and Column Output Analog Column Mux Input and Column Output Analog Column Mux Input, GPIO GPIO GPIO Direct Switched Capacitor Block Input Direct Switched Capacitor Block Input Supply Voltage Reserved for test modes - Do Not Use Reserved for test modes - Do Not Use Reserved for test modes - Do Not Use Reserved for test modes - Do Not Use Reserved for test modes - Do Not Use Not connected on the die GPIO Connect to Pin 26 (EN_W to NV_W) GPIO Document #: 001-43991 Rev. *D Page 3 of 38 [+] Feedback PRELIMINARY CY8CNP102B, CY8CNP102E Table 1. Pin Definitions - 100-Pin TQFP (continued) Pin Number 18 19 20 21 22 23 24 25 26 27 - 34 35 - 39 40 - 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72-73 74 75 76 77 78 Pin Name P5_7 P5_5 P5_3 P5_1 P1_7 P1_5 P1_3 P1_1 NV_W NC Vss NC DNU NV_A1 NV_A2 P1_0 P1_2 P1_6 P5_0 P5_2 P5_4 P5_6 EN_A1 EN_A2 EN_O EN_C XRES VCAP Vcc P2_0 P2_2 P2_4 P2_6 P0_0 P0_2 P0_4 NC P0_6 Vcc NV_O DNU NC IO Power I IO IO IO IO IO IO IO I IO IO Input Power Power I I IO IO IO IO IO IO IO Power Type Digital IO IO IO IO IO IO IO IO Analog GPIO GPIO GPIO GPIO I2C Serial Clock (SCL), GPIO I2C Serial Data (SDA), GPIO GPIO Serial Clock (SCL), Crystal (XTALin), GPIO Connect to pin 16 (NV_W to EN_W) Not connected on the die Ground Not connected on the die Reserved for test modes - Do Not Use Connect to pin 58 (NV_A1 to EN_A1) Connect to pin 59 (NV_A2 to EN_A2) Serial Data (SDA), Crystal (XTALout), GPIO GPIO GPIO GPIO GPIO GPIO GPIO Connect to Pin 49 (EN_A1 to NV_A1) Connect to Pin 50 (EN_A2 to NV_A2) Connect to Pin 76 (EN_O to NV_O) Connect to Pin 99 (EN_C to NV_C) Active high external reset (Internal Pull down) External Capacitor connection for nvSRAM Supply Voltage Direct Switched Capacitor Block Input, GPIO Direct Switched Capacitor Block Input, GPIO External Analog GND, GPIO External Voltage Ref, GPIO Analog Column Mux Input, GPIO Analog Column Mux Input and Column Output Analog Column Mux Input and Column Output Not connected on the die Analog Column Mux Input, GPIO Supply Voltage Connect to Pin 60 (NV_O to EN_O) Reserved for test modes - Do Not Use Not connected on the die Page 4 of 38 Pin Definition Document #: 001-43991 Rev. *D [+] Feedback PRELIMINARY CY8CNP102B, CY8CNP102E Table 1. Pin Definitions - 100-Pin TQFP (continued) Pin Number 79 80 81 - 85 86 - 90 91 - 98 99 100 Pin Name HSB# Vcc NC Vss NC NV_C P0_7 IO I Power Power Type Digital Analog Supply Voltage Not connected on the die Ground Not connected on the die Connect to Pin 61 (NV_C to EN_C).Weak Pull up. Connect 10k to Vcc. Analog Column Mux Input, GPIO interfacing. Every pin also has the capability to generate a system interrupt on high level, low level, and change from last read. Pin Definition Weak Pull up. Connect 10k to Vcc. PSoC NV Functional Overview The PSoC NV provides a versatile microcontroller core (M8C), Flash program memory, nvSRAM data memory, and configurable analog and digital peripheral blocks in a single package. The flexible digital and analog IOs and routing matrix create a powerful embedded and flexible mixed signal System-on-Chip (SoC). The device incorporates configurable analog and digital blocks, interconnect circuitry around an MCU subsystem, and an infinite endurance nvSRAM. This enables high level integration in consumer, industrial, and automotive applications, where preventing data loss under all conditions is vital. nvSRAM Data Memory The nvSRAM memory block is byte addressable fast static RAM with a nonvolatile element in each memory cell. The embedded nonvolatile elements incorporate QuantumTrap(R) technology producing the world's most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, when independent nonvolatile data resides in the highly reliable QuantumTrap cell. Data transfers from the SRAM to the nonvolatile elements (the STORE operation) takes place automatically at power down, and data is restored to the SRAM (the RECALL operation) from the nonvolatile memory on power up. All cells store and recall data in parallel. Both the STORE and RECALL operations may be initiated under software control. The PSoC NV user module embedded in the PSoC Designer Tool provides all necessary APIs to initiate software STORE and RECALL function from the user program. PSoC NV Core The PSoC NV core is a powerful PSoC engine that supports a rich feature set. The core includes a M8C CPU, memory, clocks, and configurable GPIO (General Purpose IO). The M8C CPU core is a powerful processor with speeds up to 24 MHz, providing a four MIPS 8-bit Harvard architecture microprocessor. The CPU uses an interrupt controller with 25 vectors, to simplify programming of real time embedded events. Program execution is timed and protected using the included Sleep and Watch Dog Timers (WDT). On-chip memory encompasses 32 KB Flash for program storage, 2 KB SRAM for data storage, 256 KB nvSRAM for data logging, and up to 2 KB EEPROM emulated using Flash. Program Flash uses four protection levels on blocks of 64 bytes, allowing customized software IP protection. The nvSRAM combines a static RAM cell and a SONOS cell to provide an infinite endurance nonvolatile memory block. The memory is random access and is accessed using a user module provided with the device. The device incorporates flexible internal clock generators, including a 24 MHz Internal Main Oscillator (IMO) accurate to 2.5 percent over temperature and voltage. The 24 MHz IMO can also be doubled to 48 MHz for use by the digital system. A low power 32 kHz Internal Low speed Oscillator (ILO) is provided for the Sleep timer and WDT. The clocks, together with programmable clock dividers (as a System Resource), provide the flexibility to integrate almost any timing requirement into the PSoC NV device. GPIOs provide connection to the CPU, and digital and analog resources of the device. Each pin's drive mode may be selected from eight options, allowing great flexibility in external Document #: 001-43991 Rev. *D nvSRAM Operation The nvSRAM is made up of an SRAM memory cell, and a nonvolatile QuantumTrap cell paired in the same physical cell. The SRAM memory cell operates as a standard fast static, and all READ and WRITE takes place from the SRAM during normal operation. During the STORE and RECALL operations, SRAM READ and WRITE operations are inhibited, and internal operations transfer data between the SRAM and nonvolatile cells. The nvSRAM provides infinite RECALL operations from the nonvolatile cells and up to 200,000 STORE operations. To reduce unnecessary nonvolatile stores, AutoStore(R) is ignored unless at least one WRITE operation is complete after the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether a WRITE operation has taken place. Embedded APIs provide a seamless interface to the nvSRAM. During normal operation, the embedded nvSRAM draws current from Vcc to charge a capacitor connected to the VCAP pin. This stored charge is used by the chip to perform a STORE operation. If the voltage on the Vcc pin drops below VSWITCH, the part automatically disconnects the VCAP pin from Vcc and STORE operation is initiated. Page 5 of 38 [+] Feedback PRELIMINARY CY8CNP102B, CY8CNP102E Programmable Digital System The digital system contains 16 digital PSoC blocks. Each block is an 8-bit resource that is used alone or combined with other blocks to form 8, 16, 24, and 32-bit peripherals, which are called user module references. The digital peripheral configurations are: Peak Detectors Other possible topologies Analog blocks are provided in columns of three, which includes one CT (Continuous Time) and two SC (Switched Capacitor) blocks. PWMs (8 to 32 bit) PWMs with dead band (8 to 32 bit) Counters (8 to 32 bit) Timers (8 to 32 bit) UART 8 bit with selectable parity (up to 4) SPI master and slave (up to 4 each) I2C slave and multimaster (1 available as a System Resource) Cyclical Redundancy Checker and Generator (8 to 32 bit) IrDA (up to 4) Pseudo Random Sequence Generators (8 to 32 bit) Additional System Resources System Resources, some of which are listed in the previous sections, provide additional capability useful to complete systems. Resources include a multiplier, decimator, switch mode pump, low voltage detection, and power on reset. The merits of each system resource are: Digital clock dividers provide three customizable clock frequencies for use in applications. The clocks may be routed to both the digital and analog systems. Additional clocks are generated using digital PSoC blocks as clock dividers. Multiply Accumulate (MAC) provides fast 8-bit multiplier with 32-bit accumulate, to assist in general math and digital filters. The decimator provides a custom hardware filter for digital signal, and processing applications including the creation of Delta Sigma ADCs. The I2C module provides 100 and 400 kHz communication over two wires. Slave, master, and multi master modes are all supported. Low Voltage Detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced POR (Power On Reset) circuit eliminates the need for a system supervisor. The digital blocks connect to any GPIO through a series of global buses that route any signal to any pin. The buses also enable signal multiplexing and performing logic operations. This configurability frees your designs from the constraints of a fixed peripheral controller. Digital blocks are provided in rows of four, where the number of blocks varies with PSoC device family. This gives you the optimum choice of system resources for your application. Programmable Analog System The analog system consists 12 configurable blocks, each having an opamp circuit enabling the creation of complex analog signal flows. Analog peripherals are very flexible and may be customized to support specific application requirements. Some of the more common analog functions (most available as user modules) are: Analog-to-digital converters (up to 4, with 6 to 14 bit resolution, selectable as Incremental, Delta Sigma, and SAR) Filters (2, 4, 6, or 8 pole band pass, low pass, and notch) Amplifiers (up to 4, with selectable gain to 48x) Instrumentation amplifiers (up to 2, with selectable gain to 93x) Comparators (up to 4, with 16 selectable thresholds) DACs (up to 4, with 6 to 9 bit resolution) Multiplying DACs (up to 4, with 6 to 9 bit resolution) High current output drivers (four with 40 mA drive as a Core Resource) 1.3V reference (as a System Resource) DTMF Dialer Modulators Correlators Document #: 001-43991 Rev. *D Page 6 of 38 [+] Feedback PRELIMINARY CY8CNP102B, CY8CNP102E Development Tools PSoC Designer is a Microsoft(R) Windows based, integrated development environment for Programmable System-on-Chip (PSoC) devices. The PSoC Designer IDE and application run on Windows NT 4.0, Windows 2000, Windows Millennium (Me), Microsoft Vista, and Windows XP. PSoC Designer helps the customer to select an operating configuration for the PSoC, write application code that uses the PSoC, and debug the application. This system provides design database management by project, an integrated debugger with In-Circuit Emulator, in-system programming support, and the CYASM macro assembler for the CPUs. PSoC Designer also supports a high level C language compiler developed specifically for the devices in this family. Figure 2. PSoC Designer Subsystem PSoC Designer Software Subsystems Device Editor The Device Editor subsystem enables the user to select different onboard analog and digital components called user modules, using the PSoC blocks. Examples of user modules are ADCs, DACs, nvSRAM, Amplifiers, and Filters. The device editor also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic configuration enables changing configurations at run time. PSoC Designer sets up power on initialization tables for selected PSoC block configurations and creates source code for an application framework. The framework contains software to operate the selected components. Also, if the project uses more than one operating configuration, the framework contains routines to switch between different sets of PSoC block configurations at run time. PSoC Designer can print out a configuration sheet for a given project configuration, for use during application programming in conjunction with the Device Data Sheet. After the framework is generated, the user can add application specific code to flesh out the framework. It is also possible to change the selected components and regenerate the framework. Design Browser The Design Browser enables users to select and import preconfigured designs into their project. Users can easily browse a catalog of preconfigured designs to facilitate time to design. Examples provided in the tools include a 300 baud modem, LIN Bus master and slave, fan controller, and magnetic card reader. Application Editor M a n ufactu ring In fo rm a tio n F ile PSoC D esign er G ra phical D e signer Interface C o n te xt S e nsitive H e lp Commands Results Im p orta b le D e sign D a ta b ase D e vice D a ta b ase A pp licatio n D a ta b ase P ro je ct D a ta b ase U se r M o d u le s Lib ra ry P S oC C o n figu ra tio n S he e t P S oC D esigner C ore E ngine In the Application Editor you can edit C language and Assembly language source code. You can also assemble, compile, link, and build. Assembler. The macro assembler seamlessly merges the assembly code with C code. The link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. C Language Compiler. A C language compiler that supports Cypress PSoC family devices is available. Even if you have never worked in the C language before, the product quickly enables you to create complete C programs for the PSoC family devices. The embedded, optimizing C compiler provides all the features of C tailored to the PSoC architecture. It is complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. Debugger The PSoC Designer Debugger subsystem provides hardware in-circuit emulation, which enables the designer to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands enable the designer to read and program, read and write data memory, read and write IO registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also enables the designer to create a trace buffer of registers and memory locations of interest. E m u la tion Pod In -C ircuit E m u la to r D e vice P ro g ra m m e r Document #: 001-43991 Rev. *D Page 7 of 38 [+] Feedback PRELIMINARY CY8CNP102B, CY8CNP102E Online Help System The online help system displays online, context sensitive help for the user. Designed for procedural and quick reference, each functional subsystem has its own context sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started. Hardware Tools In-Circuit Emulator A low cost, high functionality ICE (In-Circuit Emulator) is available for development support. This hardware has the capability to program single devices. The emulator consists of a base unit that connects to the PC through the USB port. The base unit is universal and operates with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full speed (24 MHz) operation. The development process starts when you open a new project and bring up the Device Editor, which is a graphical user interface (GUI) for configuring the hardware. Pick the user modules required for your project and map them onto the PSoC blocks with point and click simplicity. Next, build signal chains by interconnecting user modules to each other and to the IO pins. At this stage, configure the clock source connections and enter parameter values directly or by selecting values from drop down menus. When you are ready to test the hardware configuration or develop code for the project, perform the "Generate Application" step. PSoC Designer generates source code that automatically configures the device to your specification and provides high level user module API functions. User Module and Source Code Development Flows The next step is to write the main program, and any subroutine using PSoC Designer's Application Editor subsystem. The Application Editor includes a Project Manager that enables you to open the project source code files (including all generated code files) from a hierarchal view. The source code editor provides syntax coloring and advanced edit features for C and assembly language. File search capabilities include simple string searches and recursive "grep-style" patterns. A single mouse click invokes the Build Manager. It employs a professional strength "makefile" system to automatically analyze all file dependencies and run the compiler and assembler as necessary. Project level options control optimization strategies used by the compiler and linker. Syntax errors are displayed in a console window. Double clicking the error message takes you directly to the offending line of source code. After correction, the linker builds a HEX file image suitable for programming. Figure 3. User Module and Source Code Development Flows Device Editor User Module Selection Placement and Parameter -ization Source Code Generator Designing with User Modules The development process for the PSoC device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that manages specification change during development and lowers inventory costs. These configurable resources, called PSoC Blocks, implement a wide variety of user-selectable functions. Each block has several registers that determine its function and connectivity to other blocks, multiplexers, buses, and to the IO pins. Iterative development cycles permit you to adapt the hardware and the software. This substantially lowers the risk of selecting a different part to meet the final design requirements. To speed the development process, the PSoC Designer IDE provides a library of prebuilt, pretested hardware peripheral functions, called "User Modules." User modules simplify selecting and implementing peripheral devices, and come in analog, digital, and mixed signal varieties. The standard User Module library contains over 50 peripherals such as ADCs, DACs, Timers, Counters, UARTs, nvSRAM, DTMF Generators, and Bi-Quad analog filter sections. Each user module establishes the basic register settings that implement the selected function. It also provides parameters that enable you to tailor its precise configuration to your particular application. For example, a Pulse Width Modulator User Module configures one or more digital PSoC blocks, one for each 8 bits of resolution. The user module parameters permit you to establish the pulse width and duty cycle. User modules also provide tested software to cut your development time. The user module Application Programming Interface (API) provides high level functions to control and respond to hardware events at run time. The API also provides optional interrupt service routines that you can adapt as needed. The API functions are documented in user module data sheets that are viewed directly in the PSoC Designer IDE. These data sheets explain the internal operation of the user module and provide performance specifications. Each data sheet describes the use of each user module parameter and documents the setting of each register controlled by the user module. Generate Application Application Editor Project Manager Source Code Editor Build Manager Build All Debugger Interface to ICE Storage Inspector Event & Breakpoint Manager Document #: 001-43991 Rev. *D Page 8 of 38 [+] Feedback PRELIMINARY CY8CNP102B, CY8CNP102E The last step in the development process takes place inside the PSoC Designer's Debugger subsystem. The Debugger downloads the HEX image to the In-Circuit Emulator (ICE) where it runs at full speed. The Debugger capabilities rival those of systems costing much more. In addition to traditional single step, run to breakpoint, and watch variable features, the Debugger provides a large trace buffer enabling you to define complex breakpoint events that include monitoring address and data bus values, memory locations, and external signals. Cypress nvSRAM user Module The nvSRAM user module is integrated with the PSoC Designer tool and contains APIs that facilitate nvSRAM access and control. The user module provides high level access to the nvSRAM without user developed code. The user module API also provides the ability to read and write arbitrary data structures to or from the nvSRAM, and initiate nvSRAM Store or Recall operations. Electrical Specifications This section lists the PSoC NV device DC and AC electrical specifications. Specifications are valid for -40oC TA 85oC, and TJ 100oC, except where noted. Refer Table 14 on page 17 for electrical specifications on the Internal Main Oscillator (IMO) using SLIMO mode. Figure 4. Voltage versus CPU Frequency 5.25 Operating Region (CY8CNP102E) Figure 5. IMO Frequency Trim Options 5.25 4.75 Vdd Voltage 4.75 3.60 Operating Region (CY8CNP102B) 3.60 3.00 SLIMO Mode=1 SLIMO Mode = 0 SLIMO Mode=1 SLIMO Mode=0 on gi Re The following table lists the units of measure that are used in this data sheet. Table 2. Units of Measure Symbol oC Document #: 001-43991 Rev. *D Vdd Voltage SLIMO Mode=0 3.00 93 kHz CPU Frequency 12 MHz 24 MHz 93 kHz 6 MHz IMO Frequency 12 MHz 24 MHz Unit of Measure degree Celsius decibels femto farad hertz 1024 bytes 1024 bits kilohertz kilohm megahertz megaohm microampere microfarad microhenry microsecond microvolts microvolts root-mean-square Symbol W mA ms mV nA ns nV pA pF pp ppm ps sps V Unit of Measure microwatts milli-ampere milli-second milli-volts nanoampere nanosecond nanovolts ohm picoampere picofarad peak-to-peak parts per million picosecond samples per second sigma: one standard deviation volts Page 9 of 38 dB fF Hz KB Kbit kHz k MHz M A F H s V Vrms [+] Feedback PRELIMINARY CY8CNP102B, CY8CNP102E 3.3V Operation Absolute Maximum Ratings Table 3. 3.3V Absolute Maximum Ratings (CY8CNP102B) Symbol TSTG Description Storage Temperature Min -55 Typ 25 Max +100 Units o Notes Higher storage temperatures reduce data retention time. Recommended storage temperature is 25oC. Extended duration storage temperatures above 65oC degrade reliability. C TA Vcc VIO VIOZ IMIO IMAIO ESD LU Ambient Temperature with Power Applied Supply Voltage on Vcc Relative to Vss DC Input Voltage DC Voltage Applied to Tri-state Maximum Current into any Port Pin Maximum Current into any Port Pin Configured as Analog Driver Electro Static Discharge Voltage Latch-up Current -40 -0.5 Vss - 0.5 Vss - 0.5 -25 -50 2000 - - - - - - - - - +85 +4.1 Vcc + 0.5 Vcc + 0.5 +50 +50 - 200 oC V V V mA mA V mA Human Body Model ESD. Operating Temperature Table 4. 3.3V Operating Temperature (CY8CNP102B) Symbol TA TJ Description Ambient Temperature Junction Temperature Min -40 -40 Typ - - Max +85 +100 Units oC oC Notes Document #: 001-43991 Rev. *D Page 10 of 38 [+] Feedback PRELIMINARY CY8CNP102B, CY8CNP102E DC Electrical Characteristics The following DC electrical specifications list the guaranteed maximum and minimum specifications for the voltage and temperature range: 3.0V to 3.6V over the Temperature range of -40C TA 85C. Typical parameters apply to 3.3V at 25C and are for design guidance only. DC Chip Level Specifications Table 5. 3.3V DC Chip Level Specifications (CY8CNP102B) Symbol Vcc IDD Description Supply Voltage Supply Current Min 3.00 - Typ - 36 Max 3.6 40 Units V mA TA = 25 oC, CPU = 3 MHz, SYSCLK doubler disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 0.366 kHz, continuous nvSRAM access TA = 25 oC, CPU = 0.75 MHz, SYSCLK doubler disabled, VC1=0.375 MHz, VC2=23.44 kHz, VC3 = 0.09 kHz, continuous nvSRAM access nvSRAM in standby. Notes IDDP Supply current when IMO = 6 MHz using SLIMO mode. - 27 28 mA ISB VREF Vcap Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and internal slow oscillator active. Reference Voltage (Bandgap) Storage Capacitor between Vcap and Vss - - 5 mA 1.28 61 1.3 68 1.32 82 V uF Trimmed for appropriate Vcc. 5V rated (minimum) DC General Purpose IO Specifications Table 6. 3.3V DC GPIO Specifications (CY8CNP102B) Symbol RPU RPD VOH Description Pull up Resistor Pull down Resistor High Output Level Min 4 4 Vcc - 1.0 Typ 5.6 5.6 - Max 8 8 - Units K K V IOH = 10 mA, Vcc = 3.0 to 3.6V. 8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5]). 80 mA maximum combined IOH budget. IOL = 25 mA, Vcc = 3.0 to 3.6V 8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5]). 150 mA maximum combined IOL budget. Vcc = 3.0 to 3.6 Vcc = 3.0 to 3.6 Gross tested to 1 A. Pin dependent. Temp = 25oC. Pin dependent. Temp = 25oC. Notes VOL Low Output Level - - 0.75 V VIL VIH VH IIL CIN COUT Input Low Level Input High Level Input Hysterisis Input Leakage (Absolute Value) Capacitive Load on Pins as Input Capacitive Load on Pins as Output - 1.6 - - - - - - 60 1 3.5 3.5 0.8 - - 10 10 V V mV nA pF pF Document #: 001-43991 Rev. *D Page 11 of 38 [+] Feedback PRELIMINARY CY8CNP102B, CY8CNP102E DC Operational Amplifier Specifications The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Capacitor PSoC blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block. Table 7. 3.3V DC Operational Amplifier Specifications (CY8CNP102B) Symbol VOSOA Description Input Offset Voltage (absolute value) Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High TCVOSOA IEBOA CINOA VCMOA CMRROA GOLOA VOHIGHOA VOLOWOA ISOA Average Input Offset Voltage Drift Input Leakage Current (Port 0 Analog Pins) Input Capacitance (Port 0 Analog Pins) Common Mode Voltage Range Common Mode Rejection Ratio Open Loop Gain High Output Voltage Swing (internal signals) Low Output Voltage Swing (internal signals) Supply Current (including associated AGND buffer) Power = Low, Opamp Bias = Low Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = Low Power = High, Opamp Bias = High PSRROA Supply Voltage Rejection Ratio - - - - - - 54 150 300 600 1200 2400 - 80 200 400 800 1600 3200 - - A A A A A A dB Not Allowed for 3.3V operation Vss VIN (Vcc - 2.25) or (Vcc - 1.25V) VIN Vcc - - - - - 0 60 80 Vcc - 0.01 - 1.65 1.32 7.0 200 4.5 - - - - - 10 8 35.0 - 9.5 Vcc - - - 0.01 mV mV V/oC pA pF V dB dB V V Gross tested to 1 A. Pin dependent. Temp = 25 oC. Min Typ Max Units Notes High Power is 5 Volts Only DC Low Power Comparator Specifications Table 8. 3.3V DC Low Power Comparator Specifications (CY8CNP102B) Symbol VREFLPC ISLPC VOSLPC LPC supply current LPC voltage offset Description Low power comparator (LPC) reference voltage range Min 0.2 - - Typ - 10 2.5 Max Vcc - 1.0 40 30 Units V A mV Document #: 001-43991 Rev. *D Page 12 of 38 [+] Feedback PRELIMINARY CY8CNP102B, CY8CNP102E DC Analog Output Buffer Specifications Table 9. 3.3V DC Analog Output Buffer Specifications (CY8CNP102B) Symbol VOSOB TCVOSOB VCMOB ROUTOB Description Input Offset Voltage (Absolute Value) Average Input Offset Voltage Drift Common-Mode Input Voltage Range Output Resistance Power = Low Power = High VOHIGHOB High Output Voltage Swing (Load = 1K to Vcc/2) Power = Low Power = High VOLOWOB Low Output Voltage Swing (Load = 1K to Vcc/2) Power = Low Power = High ISOB Supply Current Including Bias Cell (No Load) Power = Low Power = High PSRROB Supply Voltage Rejection Ratio - - 60 0.8 2.0 64 1 5 - mA mA dB - - - - 0.5 x Vcc - 1.0 0.5 x Vcc - 1.0 V V 0.5 x Vcc + 1.0 0.5 x Vcc + 1.0 - - - - V V - - - - 10 10 Min - - 0.5 Typ 3 +6 Max 12 - Vcc - 1.0 Units mV V/C V Document #: 001-43991 Rev. *D Page 13 of 38 [+] Feedback PRELIMINARY CY8CNP102B, CY8CNP102E DC Analog Reference Specifications The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block. Reference control power is high. Table 10. 3.3V DC Analog Reference Specifications (CY8CNP102B) Symbol VBG33 - - - - - - - - - - - - - - - - - - AGND = Vcc/2 [1] Description Bandgap Voltage Reference 3.3V AGND = 2 x BandGap[1] AGND = P2[4] (P2[4] = Vcc/2) AGND = BandGap[1] AGND = 1.6 x BandGap[1] AGND Block to Block Variation (AGND = Vcc/2)[1] RefHi = Vcc/2 + BandGap RefHi = 3 x BandGap RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V) RefHi = P2[4] + BandGap (P2[4] = Vcc/2) RefHi = 2 x BandGap RefHi = 3.2 x BandGap RefLo = Vcc/2 - BandGap RefLo = BandGap RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V) RefLo = P2[4] - BandGap (P2[4] = Vcc/2) Min 1.28 Vcc/2 - 0.02 P2[4] - 0.009 1.27 2.03 -0.034 Not Allowed Not Allowed Not Allowed Not Allowed Typ 1.30 Vcc/2 Not Allowed P2[4] 1.30 2.08 0.000 Max 1.32 Vcc/2 + 0.02 P2[4] + 0.009 1.34 2.13 0.034 Units V V V V V mV RefHi = P2[4] + P2[6] (P2[4] = Vcc/2, P2[6] = 0.5V) P2[4] + P2[6] - 0.042 P2[4] + P2[6] P2[4] + P2[6] + 0.042 2.50 Not Allowed Not Allowed Not Allowed Not Allowed Not Allowed P2[4] - P2[6] P2[4] - P2[6] + 0.036 2.60 2.70 V V RefLo = P2[4]-P2[6] (P2[4] = Vcc/2, P2[6] = 0.5V) P2[4] - P2[6] - 0.036 V DC Analog PSoC NV Block Specifications Table 11. 3.3V DC Analog PSoC NV Block Specifications (CY8CNP102B) Symbol RCT CSC Description Resistor Unit Value (Continuous Time) Capacitor Unit Value (Switch Cap) Min - - Typ 12.2 80 Max - - Units k fF Note 1. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V 0.02V. Document #: 001-43991 Rev. *D Page 14 of 38 [+] Feedback PRELIMINARY CY8CNP102B, CY8CNP102E DC POR, SMP, and LVD Specifications Table 12. 3.3V DC POR, SMP, and LVD Specifications (CY8CNP102B) Symbol Description Vdd Value for PPOR Trip (positive ramp) VPPOR0R PORLEV[1:0] = 00b Vdd Value for PPOR Trip (negative ramp) VPPOR0 VPH0 VPH1 VPH2 VLVD0 VLVD1 VLVD2 VPUMP0 VPUMP1 VPUMP2 PORLEV[1:0] = 00b PPOR Hysteresis PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b Vdd Value for LVD Trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b Vdd Value for SMP Trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b 2.96 3.03 3.18 3.02 3.10 3.25 3.08 3.16 3.32 V V V 2.86 2.96 3.07 2.92 3.02 3.13 2.98[2] 3.08 3.20 V V V 92 0 0 mV mV mV 2.82 V 2.91 V Min Typ Max Units Note 2. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply. Document #: 001-43991 Rev. *D Page 15 of 38 [+] Feedback PRELIMINARY CY8CNP102B, CY8CNP102E DC Programming Specifications Table 13. 3.3V DC Programming Specifications (CY8CNP102B) Symbol IDDPV VILP VIHP IILP IIHP VOLV VOHV Description Supply Current During Programming or Verify Input Low Voltage During Programming or Verify Input High Voltage During Programming or Verify Input Current when Applying Vilp to P1[0] or P1[1] During Programming or Verify Input Current when Applying Vihp to P1[0] or P1[1] During Programming or Verify Output Low Voltage During Programming or Verify Output High Voltage During Programming or Verify Min - - 2.2 - - - Vcc - 1.0 50,000 1,800,000 10 Typ 10 - - - - - - - - - Max 30 0.8 - 0.2 1.5 Vss + 0.75 Vcc - - - Units mA V V mA mA V V - - Years Erase/write cycles per block. Erase/write cycles. Driving internal pull down resistor. Driving internal pull down resistor. Notes FlashENPB Flash Endurance (per block) FlashENT FlashDR Flash Endurance (total)[3] Flash Data Retention Note 3. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single lock ever sees more than 50,000 cycles). For the full industrial range, the user must employ a temperature sensor user module (Flash Temp) and feed the result to the temperature argument before timing. Refer to the Flash APIs Application Note AN2015 at http//www.cypress.com under Application Notes for more information. Document #: 001-43991 Rev. *D Page 16 of 38 [+] Feedback PRELIMINARY CY8CNP102B, CY8CNP102E AC Electrical Characteristics The following AC electrical specifications list the guaranteed maximum and minimum specifications for the voltage and temperature range: 3.0V to 3.6V over the temperature range of -40C TA 85C. Typical parameters apply to 3.3V at 25C and are for design guidance only. AC Chip Level Specifications Table 14. 3.3V AC Chip Level Specifications (CY8CNP102B) Symbol FIMO24 FIMO6 Description Internal Main Oscillator Frequency for 24 MHz Internal Main Oscillator Frequency for 6 MHz Min 23.4 Typ 24 Max 24.6[4, 5, 6] 6.35[4 , 5, 6] Units MHz Notes Trimmed for 3.3V operation using factory trim values. See the figure on page 10. SLIMO Mode = 0. Trimmed for 3.3V operation using factory trim values. See the figure on page 10. SLIMO Mode = 1. Refer to section AC Digital Block Specifications on page 19. 5.75 6 MHz FCPU2 F48M F24M F32K1 F32K2 FPLL Jitter24M2 TPLLSLEW TOS TOSACC CPU Frequency (3.3V Nominal) Digital PSoC Block Frequency Digital PSoC Block Frequency Internal Low Speed Oscillator Frequency External Crystal Oscillator PLL Frequency 24 MHz Period Jitter (PLL) PLL Lock Time External Crystal Oscillator Startup to 1% External Crystal Oscillator Startup to 100 ppm 0.93 0 0 15 - - - 0.5 0.5 - - 12 48 24 32 32.768 23.986 - - - 250 300 12.3[5, 6] 49.2[4, 5, 7] 24.6[5, 7] 64 - - 600 10 50 500 600 MHz MHz MHz kHz kHz MHz ps ms ms ms ms The crystal oscillator frequency is within 100 ppm of its final value by the end of the Tosacc period. Correct operation assumes a properly loaded 1 uW maximum drive level 32.768 kHz crystal. Accuracy is capacitor and crystal dependent. 50% duty cycle. A multiple (x732) of crystal frequency. TPLLSLEWLOW PLL Lock Time for Low Gain Setting Jitter32k TXRST DC24M Step24M Fout48M Jitter24M1 FMAX TRAMP 32 kHz Period Jitter External Reset Pulse Width 24 MHz Duty Cycle 24 MHz Trim Step Size 48 MHz Output Frequency 24 MHz Period Jitter (IMO) Maximum frequency of signal on row input or row output. Supply Ramp Time - 10 40 - 46.8 - - 0 100 - 50 50 48.0 600 - - 12.3 - - 60 - 49.2[4,6] ns s % kHz MHz ps MHz s Trimmed. Using factory trim values. Notes 4. 4.75V < Vcc < 5.25V. 5. Accuracy derived from Internal Main Oscillator with appropriate trim for Vcc range. 6. 3.0V < Vcc < 3.6V. See Application Note AN2012 "Adjusting PSoC Micro controller Trims for Dual Voltage-Range Operation" for information on trimming for operation at 3.3V. 7. See individual user module data sheets for information on maximum frequencies for user modules. Document #: 001-43991 Rev. *D Page 17 of 38 [+] Feedback PRELIMINARY CY8CNP102B, CY8CNP102E In the following table, tHRECALL starts from the time Vcc rises above VSWITCH. If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE occurs. Industrial grade devices require 15 ms maximum. Table 15.3.3V nvSRAM AutoStore/Power Up RECALL (CY8CNP102B) Parameter tHRECALL tSTORE VSWITCH tVccRISE Description Power Up RECALL Duration STORE Cycle Duration Low Voltage Trigger Level VCC Rise Time 150 nvSRAM Min Max 20 12.5 2.65 Unit ms ms V s AC General Purpose IO Specifications Table 16. 3.3V AC GPIO Specifications (CY8CNP102B) Symbol FGPIO TRiseS TFallS Description GPIO Operating Frequency Rise Time, Slow Strong Mode, Cload = 50 pF Fall Time, Slow Strong Mode, Cload = 50 pF Min 0 10 10 Typ - 27 22 Max 12.3 - - Units ns ns Notes Vcc = 3V to 3.6V 10% - 90% Vcc = 3V to 3.6V 10% - 90% MHz Normal Strong Mode Figure 6. GPIO Timing Diagram 90% GPIO Pin Output Voltage 10% TRiseF TRiseS TFallF TFallS Document #: 001-43991 Rev. *D Page 18 of 38 [+] Feedback PRELIMINARY CY8CNP102B, CY8CNP102E AC Operational Amplifier Specifications Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block. Table 17. 3.3V AC Operational Amplifier Specifications (CY8CNP102B) Symbol TROA Description Rising Settling Time to 0.1% of a 1V Step (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High TSOA Falling Settling Time to 0.1% of a 1V Step (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High SRROA Rising Slew Rate (20% to 80%) of a 1V Step (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High SRFOA Falling Slew Rate (20% to 80%) of a 1V Step (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High BWOA Gain Bandwidth Product Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High ENOA Noise at 1 kHz (Power = Medium, Opamp Bias = High) 0.67 2.8 - - - 100 - - - MHz MHz nV/rt-Hz 0.24 1.8 - - - - V/s V/s 0.31 2.7 - - - - V/s V/s - - - - 5.41 0.72 s s - - - - 3.92 0.72 s s Min Typ Max Units Notes Power = High and Opamp Bias = High is not supported at 3.3V. AC Digital Block Specifications Table 18. 3.3V AC Digital Block Specifications (CY8CNP102B) Function Description Min Typ Max 24.6 50[8] - - 50 [8] Units MHz ns MHz MHz ns MHz MHz ns ns ns MHz Notes 3.0V Vcc 3.6V All Functions Maximum Block Clocking Frequency Timer Capture Pulse Width Maximum Frequency, No Capture Maximum Frequency, With Capture Counter Enable Pulse Width Maximum Frequency, No Enable Input Maximum Frequency, Enable Input Dead Band Kill Pulse Width: Asynchronous Restart Mode Synchronous Restart Mode Disable Mode Maximum Frequency 20 50[8] 50 [8] - - - - - - - - - - - 24.6 24.6 - 24.6 24.6 - - - 24.6 3.0V Vcc 3.6V. 3.0V Vcc 3.6V. 3.0V Vcc 3.6V. 3.0V Vcc 3.6V. - - - 3.0V Vcc 3.6V Note 8. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period). Document #: 001-43991 Rev. *D Page 19 of 38 [+] Feedback PRELIMINARY CY8CNP102B, CY8CNP102E Table 18. 3.3V AC Digital Block Specifications (CY8CNP102B) (continued) Function Description Min - - - Typ - - - Max 24.6 24.6 8.2 Units MHz MHz MHz Notes 3.0V Vcc 3.6V 3.0V Vcc 3.6V. Maximum data rate at 4.1 MHz due to 2 x over clocking. CRCPRS Maximum Input Clock Frequency (PRS Mode) CRCPRS Maximum Input Clock Frequency (CRC Mode) SPIM Maximum Input Clock Frequency SPIS Transmitter Maximum Input Clock Frequency Width of SS_ Negated Between Transmissions Maximum Input Clock Frequency Vcc 3.0V, 2 Stop Bits - 50 [8] - - - 4.1 - 24.6 ns ns MHz Maximum data rate at 3.08 MHz due to 8 x over clocking. Maximum data rate at 6.15 MHz due to 8 x over clocking. Maximum data rate at 3.08 MHz due to 8 x over clocking. Maximum data rate at 6.15 MHz due to 8 x over clocking. - - - 49.2 MHz Receiver Maximum Input Clock Frequency - - 24.6 MHz Vcc 3.0V, 2 Stop Bits - - 49.2 MHz AC Analog Output Buffer Specifications Table 19. 3.3V AC Analog Output Buffer Specifications (CY8CNP102B) Symbol TROB Power = Low Power = High TSOB Falling Settling Time to 0.1%, 1V Step, 100pF Load Power = Low Power = High SRROB Rising Slew Rate (20% to 80%), 1V Step, 100pF Load Power = Low Power = High SRFOB Falling Slew Rate (80% to 20%), 1V Step, 100pF Load Power = Low Power = High BWOB Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load Power = Low Power = High BWOB Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load Power = Low Power = High 200 200 - - - - kHz kHz 0.7 0.7 - - - - MHz MHz 0.4 0.4 - - - - V/s V/s 0.36 0.36 - - - - V/s V/s - - - - 4 4 s s Description Rising Settling Time to 0.1%, 1V Step, 100pF Load - - - - 4.7 4.7 s s Min Typ Max Units Document #: 001-43991 Rev. *D Page 20 of 38 [+] Feedback PRELIMINARY CY8CNP102B, CY8CNP102E AC Programming Specifications Table 20. 3.3V AC Programming Specifications (CY8CNP102B) Symbol TRSCLK TFSCLK TSSCLK THSCLK FSCLK TERASEB TWRITE TDSCLK3 Rise Time of SCLK Fall Time of SCLK Data Set up Time to Falling Edge of SCLK Data Hold Time from Falling Edge of SCLK Frequency of SCLK Flash Erase Time (Block) Flash Block Write Time Data Out Delay from Falling Edge of SCLK Description Min 1 1 40 40 0 - - - Typ - - - - - 10 10 - Max 20 20 - - 8 - - 50 Units ns ns ns ns MHz ms ms ns 3.0V Vcc 3.6V Notes AC I2C Specifications Table 21. 3.3V AC Characteristics of the I2C SDA and SCL Pins (CY8CNP102B) Symbol FSCLI2C THDSTAI2C TLOWI2C THIGHI2C TSUSTAI2C THDDATI2C TSUDATI2C TSUSTOI2C TBUFI2C TSPI2C SCL Clock Frequency Hold Time (repeated) START Condition. After this period, the first clock pulse is generated. LOW Period of the SCL Clock HIGH Period of the SCL Clock Setup Time for a Repeated START Condition Data Hold Time Data Setup Time Setup Time for STOP Condition Bus Free Time Between a STOP and START Condition Pulse Width of spikes are suppressed by the input filter. Description Standard Mode Min 0 4.0 4.7 4.0 4.7 0 250 4.0 4.7 - Max 100 - - - - - - - - - Fast Mode Min 0 0.6 1.3 0.6 0.6 0 100[9] 0.6 1.3 0 Max 400 - - - - - - - - 50 Units kHz s s s s s ns s s ns Note 9. A Fast Mode I2C-bus device may be used in a Standard-Mode I2C-bus system, but the requirement tSUDAT 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard Mode I2C bus specification) before the SCL line is released. Document #: 001-43991 Rev. *D Page 21 of 38 [+] Feedback PRELIMINARY CY8CNP102B, CY8CNP102E 5V Operation Absolute Maximum Ratings Table 22. 5V Absolute Maximum Ratings (CY8CNP102E) Symbol TSTG Description Storage Temperature Min -55 Typ 25 Max +100 Units o Notes Higher storage temperatures reduce data retention time. Recommended storage temperature is 25oC. Extended duration storage temperatures above 65oC degrade reliability. C TA Vcc VIO VIOZ IMIO IMAIO ESD LU Ambient Temperature with Power Applied Supply Voltage on Vcc Relative to Vss DC Input Voltage DC Voltage Applied to Tri-state Maximum Current into any Port Pin Maximum Current into any Port Pin Configured as Analog Driver Electro Static Discharge Voltage Latch-up Current -40 -0.5 Vss - 0.5 Vss - 0.5 -25 -50 - - - - - - +85 +6.0 Vcc + 0.5 Vcc + 0.5 +50 +50 o C V V V mA mA 2000 - - - - 200 V mA Human Body Model ESD. Operating Temperature Table 23. 5V Operating Temperature (CY8CNP102E) Symbol TA TJ Description Ambient Temperature Junction Temperature Min -40 -40 Typ - - Max +85 +100 Units oC oC Notes Document #: 001-43991 Rev. *D Page 22 of 38 [+] Feedback PRELIMINARY CY8CNP102B, CY8CNP102E DC Electrical Characteristics The following DC electrical specifications lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V over the Temperature range of -40C TA 85C. Typical parameters apply to 5V at 25C and are for design guidance only. DC Chip Level Specifications Table 24. 5V DC Chip-Level Specifications (CY8CNP102E) Symbol Vcc IDD Description Supply Voltage Supply Current Min 4.75 - Typ - 39 Max 5.25 45 Units V mA TA = 25 oC, CPU = 3 MHz, SYSCLK doubler disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 0.366 kHz, continuous nvSRAM access TA = 25 oC, CPU = 0.75 MHz, SYSCLK doubler disabled, VC1=0.375 MHz, VC2=23.44 kHz, VC3 = 0.09 kHz, continuous nvSRAM access nvSRAM in standby. Notes IDDP Supply current when IMO = 6 MHz using SLIMO mode. - 27 28 mA ISB VREF Vcap Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and internal slow oscillator active. Reference Voltage (Bandgap) Storage Capacitor between Vcap and Vss - - 5 mA 1.28 61 1.3 68 1.32 82 V uF Trimmed for appropriate Vcc. 5V rated (minimum) DC General Purpose IO Specifications Table 25. 5V DC GPIO Specifications (CY8CNP102E) Symbol RPU RPD VOH Description Pull up Resistor Pull down Resistor High Output Level Min 4 4 Vcc - 1.0 Typ 5.6 5.6 - Max 8 8 - Units k k V Notes VOL Low Output Level - - 0.75 V VIL VIH VH IIL CIN COUT Input Low Level Input High Level Input Hysterisis Input Leakage (Absolute Value) Capacitive Load on Pins as Input Capacitive Load on Pins as Output - 2.1 - - - - - - 60 1 3.5 3.5 0.8 - - 10 10 V V mV nA pF pF IOH = 10 mA, Vcc = 4.75 to 5.25V. 8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5]). 80 mA maximum combined IOH budget. IOL = 25 mA, Vcc = 4.75 to 5.25V 8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5]). 150 mA maximum combined IOL budget. 4.75 to 5.25. 4.75 to 5.25. Gross tested to 1 A. Pin dependent. Temp = 25oC. Pin dependent. Temp = 25oC. Document #: 001-43991 Rev. *D Page 23 of 38 [+] Feedback PRELIMINARY CY8CNP102B, CY8CNP102E DC Operational Amplifier Specifications The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Capacitor PSoC blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block. Table 26. 5V DC Operational Amplifier Specifications (CY8CNP102E) Symbol VOSOA Description Input Offset Voltage (absolute value) Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High TCVOSOA Average Input Offset Voltage Drift IEBOA CINOA VCMOA Input Leakage Current (Port 0 Analog Pins) Input Capacitance (Port 0 Analog Pins) Common Mode Voltage Range. All Cases, except highest. Power = High, Opamp Bias = High CMRROA GOLOA Common Mode Rejection Ratio Open Loop Gain - - - - - - 0.0 0.5 60 80 Vcc - 0.01 - 1.6 1.3 1.2 7.0 200 4.5 - - - - - - 10 8 7.5 35.0 - 9.5 Vcc Vcc - 0.5 - - - 0.1 mV mV mV V/oC pA pF V V dB dB V V Gross tested to 1 A. Pin dependent. Temp = 25 oC. Min Typ Max Units Notes VOHIGHOA High Output Voltage Swing (internal signals) VOLOWOA Low Output Voltage Swing (internal signals) ISOA Supply Current (including associated AGND buffer) Power = Low, Opamp Bias = Low Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = Low Power = High, Opamp Bias = High PSRROA Supply Voltage Rejection Ratio - - - - - - 67 150 300 600 1200 2400 4600 80 200 400 800 1600 3200 6400 - A A A A A A dB Vss VIN (Vcc - 2.25) or (Vcc - 1.25V) VIN Vcc. DC Low Power Comparator Specifications Table 27. 5V DC Low Power Comparator Specifications (CY8CNP102E) Symbol VREFLPC ISLPC VOSLPC LPC supply current LPC voltage offset Description Low power comparator (LPC) reference voltage range Min 0.2 - - Typ - 10 2.5 Max Vcc - 1.0 40 30 Units V A mV Document #: 001-43991 Rev. *D Page 24 of 38 [+] Feedback PRELIMINARY CY8CNP102B, CY8CNP102E DC Analog Output Buffer Specifications Table 28. 5V DC Analog Output Buffer Specifications (CY8CNP102E) Symbol VOSOB VCMOB ROUTOB Description Input Offset Voltage (Absolute Value) Common-Mode Input Voltage Range Output Resistance Power = Low Power = High VOHIGHOB High Output Voltage Swing (Load = 32 ohms to Vcc/2) Power = Low Power = High VOLOWOB Low Output Voltage Swing (Load = 32 ohms to Vcc/2) Power = Low Power = High ISOB Supply Current Including Bias Cell (No Load) Power = Low Power = High PSRROB Supply Voltage Rejection Ratio - - 40 1.1 2.6 64 2 5 - mA mA dB - - - - 0.5 x Vcc - 1.3 0.5 x Vcc - 1.3 V V 0.5 x Vcc + 1.3 0.5 x Vcc + 1.3 - - - - V V - - - - 1 1 Min - - 0.5 Typ 3 +6 - Max 12 - Vcc - 1.0 Units mV V/C V TCVOSOB Average Input Offset Voltage Drift DC Analog Reference Specifications The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block. Reference control power is high. Table 29. 5V DC Analog Reference Specifications (CY8CNP102E) Symbol VBG5 - - - - - - - - - - - - - - - - - - AGND = Vcc/2[1] [1] Description Bandgap Voltage Reference 5V AGND = 2 x BandGap[1] AGND = P2[4] (P2[4] = Vcc/2) AGND = BandGap[1] AGND = 1.6 x BandGap[1] AGND Block to Block Variation (AGND = Vcc/2)[1] RefHi = Vcc/2 + BandGap RefHi = 3 x BandGap RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V) RefHi = P2[4] + BandGap (P2[4] = Vcc/2) RefHi = P2[4] + P2[6] (P2[4] = Vcc/2, P2[6] = 1.3V) RefHi = 2 x BandGap RefHi = 3.2 x BandGap RefLo = Vcc/2 - BandGap RefLo = BandGap RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V) RefLo = P2[4] - BandGap (P2[4] = Vcc/2) RefLo = P2[4]-P2[6] (P2[4] = Vcc/2, P2[6] = 1.3V) Min 1.28 Vcc/2 - 0.02 2.52 P2[4] - 0.013 1.27 2.03 -0.034 Vcc/2 + 1.21 Typ 1.30 Vcc/2 2.60 P2[4] 1.3 2.08 0.000 Vcc/2 + 1.3 Max 1.32 Vcc/2 + 0.02 2.72 P2[4] + 0.013 1.34 2.13 0.034 Vcc/2 + 1.382 Units V V V V V V V V V V V V V V V V V V V 3.75 P2[6] + 2.478 P2[4] + 1.218 2.50 4.02 Vcc/2 - 1.369 3.9 P2[6] + 2.6 P2[4] + 1.3 2.60 4.16 Vcc/2 - 1.30 4.05 P2[6] + 2.722 P2[4] + 1.382 2.70 4.29 Vcc/2 - 1.231 P2[4] + P2[6] - 0.058 P2[4] + P2[6] P2[4] + P2[6] + 0.058 1.20 2.489 - P2[6] P2[4] - 1.368 1.30 2.6 - P2[6] P2[4] - 1.30 1.40 2.711 - P2[6] P2[4] - 1.232 P2[4] - P2[6] - 0.042 P2[4] - P2[6] P2[4] - P2[6] + 0.042 Document #: 001-43991 Rev. *D Page 25 of 38 [+] Feedback PRELIMINARY CY8CNP102B, CY8CNP102E DC Analog PSoC NV Block Specifications Table 30. 5V DC Analog PSoC NV Block Specifications (CY8CNP102E) Symbol RCT CSC Description Resistor Unit Value (Continuous Time) Capacitor Unit Value (Switch Cap) Min - - Typ 12.2 80 Max - - Units k fF DC POR, SMP, and LVD Specifications Table 31. 5V DC POR, SMP, and LVD Specifications (CY8CNP102E) Symbol VPPOR0R VPPOR1R VPPOR2R VPPOR0 VPPOR1 VPPOR2 VPH0 VPH1 VPH2 VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 VPUMP0 VPUMP1 VPUMP2 VPUMP3 VPUMP4 VPUMP5 VPUMP6 VPUMP7 Description Vdd Value for PPOR Trip (positive ramp) PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b Vdd Value for PPOR Trip (negative ramp) PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b PPOR Hysteresis PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b Vdd Value for LVD Trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b Vdd Value for SMP Trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b 2.96 3.03 3.18 4.11 4.55 4.63 4.72 4.90 3.02 3.10 3.25 4.19 4.64 4.73 4.82 5.00 3.08 3.16 3.32 4.28 4.74 4.82 4.91 5.10 V V V V V V V V 2.86 2.96 3.07 3.92 4.39 4.55 4.63 4.72 2.92 3.02 3.13 4.00 4.48 4.64 4.73 4.81 2.98[2] 3.08 3.20 4.08 4.57 4.74 4.82 4.91 V V V V V V V V 92 0 0 mV mV mV 2.82 4.39 4.55 V V V 2.91 4.39 4.55 V V V Min Typ Max Units Document #: 001-43991 Rev. *D Page 26 of 38 [+] Feedback PRELIMINARY CY8CNP102B, CY8CNP102E DC Programming Specifications Table 32. 5V DC Programming Specifications (CY8CNP102E) Symbol IDDPV VILP VIHP IILP IIHP VOLV VOHV Description Supply Current During Programming or Verify Input Low Voltage During Programming or Verify Input High Voltage During Programming or Verify Input Current when Applying Vilp to P1[0] or P1[1] During Programming or Verify Input Current when Applying Vihp to P1[0] or P1[1] During Programming or Verify Output Low Voltage During Programming or Verify Output High Voltage During Programming or Verify Min - - 2.2 - - - Vcc - 1.0 50,000 1,800,000 10 Typ 10 - - - - - - - - - Max 30 0.8 - 0.2 1.5 Vss + 0.75 Vcc - - - Units mA V V mA mA V V - - Years Erase/write cycles per block. Erase/write cycles. Driving internal pull down resistor. Driving internal pull down resistor. Notes FlashENPB Flash Endurance (per block) FlashENT FlashDR Flash Endurance (total)[3] Flash Data Retention Document #: 001-43991 Rev. *D Page 27 of 38 [+] Feedback PRELIMINARY CY8CNP102B, CY8CNP102E AC Electrical Characteristics The following AC electrical specifications lists the guaranteed maximum and minimum specifications for the voltage and temperature range: 4.75V to 5.25V over the Temperature range of -40C TA 85C. Typical parameters apply to 5V at 25C and are for design guidance only. AC Chip Level Specifications Table 33. 5V AC Chip Level Specifications (CY8CNP102E) Symbol FIMO24 Description Internal Main Oscillator Frequency for 24 MHz Min 23.4 Typ 24 Max 24.6[4, 5, 6] Units MHz Notes Trimmed for 5V operation using factory trim values. See Figure 5 on page 9. SLIMO Mode = 0. Trimmed for 5V operation using factory trim values. See Figure 5 on page 9. SLIMO Mode = 1. Refer to AC Digital Block Specifications on page 30. FIMO6 Internal Main Oscillator Frequency for 6 MHz 5.75 6 6.35[4 , 5, 6] MHz FCPU1 F48M F24M F32K1 F32K2 FPLL Jitter24M2 TPLLSLEW TOS TOSACC CPU Frequency (5V Nominal) Digital PSoC Block Frequency Digital PSoC Block Frequency Internal Low Speed Oscillator Frequency External Crystal Oscillator 0.93 0 0 15 - 24 48 24 32 32.768 24.6[4, 5] 49.2[4, 5, 7] 24.6[5, 7] 64 - MHz MHz MHz kHz kHz Accuracy is capacitor and crystal dependent. 50% duty cycle. A multiple (x732) of crystal frequency. PLL Frequency 24 MHz Period Jitter (PLL) PLL Lock Time External Crystal Oscillator Startup to 1% External Crystal Oscillator Startup to 100 ppm - - 0.5 0.5 - - 23.986 - - - 250 300 - 600 10 50 500 600 MHz ps ms ms ms ms TPLLSLEWLOW PLL Lock Time for Low Gain Setting The crystal oscillator frequency is within 100 ppm of its final value by the end of the Tosacc period. Correct operation assumes a properly loaded 1 uW maximum drive level 32.768 kHz crystal. Jitter32k TXRST DC24M Step24M Fout48M Jitter24M1 FMAX TRAMP 32 kHz Period Jitter External Reset Pulse Width 24 MHz Duty Cycle 24 MHz Trim Step Size 48 MHz Output Frequency 24 MHz Period Jitter (IMO) Maximum frequency of signal on row input or row output. Supply Ramp Time - 10 40 - 46.8 - - 0 100 - 50 50 48.0 600 - - 12.3 - - 60 - 49.2[4,6] ns s % kHz MHz ps MHz s Trimmed. Using factory trim values. Document #: 001-43991 Rev. *D Page 28 of 38 [+] Feedback PRELIMINARY CY8CNP102B, CY8CNP102E In the following table, tHRECALL starts from the time Vcc rises above VSWITCH. If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE takes place. Industrial grade devices require 15 ms maximum. Table 34. 5V nvSRAM AutoStore/Power Up RECALL (CY8CNP102E) Parameter tHRECALL tSTORE VSWITCH tVccRISE Description Power Up RECALL Duration STORE Cycle Duration Low Voltage Trigger Level VCC Rise Time 150 nvSRAM Min Max 20 12.5 4.4 Unit ms ms V s AC General Purpose IO Specifications Table 35. 5V AC GPIO Specifications (CY8CNP102E) Symbol FGPIO TRiseF TFallF Description GPIO Operating Frequency Rise Time, Normal Strong Mode, Cload = 50 pF Fall Time, Normal Strong Mode, Cload = 50 pF Min 0 3 2 Typ - - - Max 12.3 18 18 Units ns ns Notes Vcc = 4.75V to 5.25V 10% - 90% Vcc = 4.75V to 5.25V 10% - 90% MHz Normal Strong Mode Figure 7. GPIO Timing Diagram 90% GPIO Pin Output Voltage 10% TRiseF TRiseS TFallF TFallS Document #: 001-43991 Rev. *D Page 29 of 38 [+] Feedback PRELIMINARY CY8CNP102B, CY8CNP102E AC Operational Amplifier Specifications Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block. Table 36. 5V AC Operational Amplifier Specifications (CY8CNP102E) Symbol TROA Description Rising Settling Time to 0.1% for a 1V Step (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High TSOA Falling Settling Time to 0.1% for a 1V Step (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High SRROA Rising Slew Rate (20% to 80%) of a 1V Step (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High SRFOA Falling Slew Rate (20% to 80%) of a 1V Step (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High BWOA Gain Bandwidth Product Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High ENOA Noise at 1 kHz (Power = Medium, Opamp Bias = High) 0.75 3.1 5.4 - - - - 100 - - - - MHz MHz MHz nV/rt-Hz 0.01 0.5 4.0 - - - - - - V/s V/s V/s 0.15 1.7 6.5 - - - - - - V/s V/s V/s - - - - - - 5.9 0.92 0.72 s s s - - - - - - 3.9 0.72 0.62 s s s Min Typ Max Units AC Digital Block Specifications Table 37. 5V AC Digital Block Specifications (CY8CNP102E) Function All Functions Timer Description Maximum Block Clocking Frequency Capture Pulse Width Maximum Frequency, No Capture Maximum Frequency, With Capture Counter Enable Pulse Width Maximum Frequency, No Enable Input Maximum Frequency, Enable Input Dead Band Kill Pulse Width: Asynchronous Restart Mode Synchronous Restart Mode Disable Mode Maximum Frequency CRCPRS (PRS Mode) Maximum Input Clock Frequency 20 50[8] 50[8] - - - - - - - - - - 49.2 49.2 ns ns ns MHz MHz 4.75V Vcc 5.25V 4.75V Vcc 5.25V 50[8] - - 50[8] - - - - - - - - Min Typ Max 49.2 - 49.2 24.6 - 49.2 24.6 Units MHz ns MHz MHz ns MHz MHz 4.75V Vcc 5.25V. 4.75V Vcc 5.25V. 4.75V Vcc 5.25V. 4.75V Vcc 5.25V. Notes 4.75V Vcc 5.25V. Document #: 001-43991 Rev. *D Page 30 of 38 [+] Feedback PRELIMINARY CY8CNP102B, CY8CNP102E Table 37. 5V AC Digital Block Specifications (CY8CNP102E) (continued) Function CRCPRS (CRC Mode) SPIM Description Maximum Input Clock Frequency Maximum Input Clock Frequency Min - - Typ - - Max 24.6 8.2 Units MHz MHz Notes 4.75V Vcc 5.25V. Maximum data rate at 4.1 MHz due to 2 x over clocking. SPIS Maximum Input Clock Frequency Width of SS_ Negated Between Transmissions - 50 [8] - - - 4.1 - 24.6 ns ns MHz Maximum data rate at 3.08 MHz due to 8 x over clocking. Maximum data rate at 6.15 MHz due to 8 x over clocking. Maximum data rate at 3.08 MHz due to 8 x over clocking. Maximum data rate at 6.15 MHz due to 8 x over clocking. Transmitter Maximum Input Clock Frequency Vcc 4.75V, 2 Stop Bits - - - 49.2 MHz Receiver Maximum Input Clock Frequency Vcc 4.75V, 2 Stop Bits - - 24.6 MHz - - 49.2 MHz AC Analog Output Buffer Specifications Table 38. 5V AC Analog Output Buffer Specifications (CY8CNP102E) Symbol TROB Power = Low Power = High TSOB Falling Settling Time to 0.1%, 1V Step, 100 pF Load Power = Low Power = High SRROB Rising Slew Rate (20% to 80%), 1V Step, 100 pF Load Power = Low Power = High SRFOB Falling Slew Rate (80% to 20%), 1V Step, 100 pF Load Power = Low Power = High BWOB Small Signal Bandwidth, 20mVpp, 3dB BW, 100 pF Load Power = Low Power = High BWOB Large Signal Bandwidth, 1Vpp, 3dB BW, 100 pF Load Power = Low Power = High 300 300 - - - - kHz kHz 0.8 0.8 - - - - MHz MHz 0.55 0.55 - - - - V/s V/s 0.5 0.5 - - - - V/s V/s - - - - 3.4 3.4 s s Description Rising Settling Time to 0.1%, 1V Step, 100 pF Load - - - - 4 4 s s Min Typ Max Units Document #: 001-43991 Rev. *D Page 31 of 38 [+] Feedback PRELIMINARY CY8CNP102B, CY8CNP102E AC Programming Specifications Table 39. 5V AC Programming Specifications (CY8CNP102E) Symbol TRSCLK TFSCLK TSSCLK THSCLK FSCLK TERASEB TWRITE TDSCLK Rise Time of SCLK Fall Time of SCLK Data Set up Time to Falling Edge of SCLK Data Hold Time from Falling Edge of SCLK Frequency of SCLK Flash Erase Time (Block) Flash Block Write Time Data Out Delay from Falling Edge of SCLK Description Min 1 1 40 40 0 - - - Typ - - - - - 10 10 - Max 20 20 - - 8 - - 45 Units ns ns ns ns MHz ms ms ns 4.75V Vcc 5.25V Notes AC I2C Specifications Table 40. 5V AC Characteristics of the I2C SDA and SCL Pins (CY8CNP102E) Symbol FSCLI2C THDSTAI2C TLOWI2C THIGHI2C TSUSTAI2C THDDATI2C TSUDATI2C TSUSTOI2C TBUFI2C TSPI2C Description SCL Clock Frequency Hold Time (repeated) START Condition. After this period, the first clock pulse is generated. LOW Period of the SCL Clock HIGH Period of the SCL Clock Setup Time for a Repeated START Condition Data Hold Time Data Setup Time Setup Time for STOP Condition Bus Free Time Between a STOP and START Condition Pulse Width of spikes are suppressed by the input filter. Standard Mode Min 0 4.0 4.7 4.0 4.7 0 250 4.0 4.7 - Max 100 - - - - - - - - - Fast Mode Min 0 0.6 1.3 0.6 0.6 0 100[9] 0.6 1.3 0 Max 400 - - - - - - - - 50 Units kHz s s s s s ns s s ns Document #: 001-43991 Rev. *D Page 32 of 38 [+] Feedback PRELIMINARY CY8CNP102B, CY8CNP102E Switching Waveforms Figure 8. AutoStore/Power Up RECALL STORE occurs only if a SRAM write has happened No STORE occurs without atleast one SRAM write VCC VSWITCH tVCCRISE AutoStore tSTORE tSTORE POWER-UP RECALL tHRECALL Read & Write Inhibited tHRECALL Figure 9. PLL Lock Timing Diagram PLL E n a b le TP LLS LE W 24 MHz FPLL PLL G a in 0 Figure 10. PLL Lock for Low Gain Setting Timing Diagram PLL E n a b le TPLLS LE W LO W 24 MHz FPLL PLL G a in 1 Document #: 001-43991 Rev. *D Page 33 of 38 [+] Feedback PRELIMINARY CY8CNP102B, CY8CNP102E Switching Waveforms 32K S e le c t (continued) Figure 11. External Crystal Oscillator Startup Timing Diagram 3 2 kHz TO S F32K2 Figure 12. 24 MHz Period Jitter (IMO) Timing Diagram J it t e r 2 4 M 1 F 24M Figure 13. 32 kHz Period Jitter (ECO) Timing Diagram J it t e r 3 2 k F 32K2 Figure 14. Definition of Timing for Fast/Standard Mode on the I2C Bus ~ ~ ~ ~ ~ ~ SDA t SUDATI2C tf ~ ~ tf t LOWI2C tr t HDSTAI2C t SPI2C tr t BUFI2C SCL ~ ~ ~ ~ t HDSTAI2C t SUSTAI2C t SUSTOI2C S t HDDATI2C t HIGHI2C Sr P S Document #: 001-43991 Rev. *D Page 34 of 38 [+] Feedback PRELIMINARY CY8CNP102B, CY8CNP102E Part Numbering Nomenclature C Y 8 C N P 1 0 2 B A X I Cypress Microcontroller C = CMOS NP = PSoC NV Family Temp: C = Commercial I = Industrial X = Pb free A = 100TQFP B = 3.3V E = 5V Density: 01 = 1Mb 02 = 2Mb 12 = 512Kb Processor Type: 1 = M8C (PSoC1 Based) Ordering Information Ordering Code Package Diagram Package Type Operating Range CY8CNP102B-AXI CY8CNP102E-AXI 51 - 85048 51 - 85048 100-pin TQFP 100-pin TQFP Industrial All the above mentioned parts are of "Pb-free" type and contain preliminary information. Please contact your local Cypress sales representative for availability of these parts. Document #: 001-43991 Rev. *D Page 35 of 38 [+] Feedback PRELIMINARY CY8CNP102B, CY8CNP102E Packaging Information This section describes the packaging specifications for the PSoC NV device and the thermal impedances for TQFP package. Note Emulation tools may require a larger area on the target PCB than the chip's footprint. For a detailed description of the emulation tool dimensions, refer to the document "PSoC Emulator Pod Dimensions" at http://www.cypress.com/design/MR10161. Package Diagrams Figure 15. 100-Pin TQFP - 14 x 14 x 1.4 mm 51-85048 *C Thermal Impedance Table 41. Thermal Impedance Package[10] Typical JA * Typical JC * 100 TQFP 26.14 oC/W 5.81 oC/W Note 10. * TJ = TA + POWER x JA Document #: 001-43991 Rev. *D Page 36 of 38 [+] Feedback PRELIMINARY CY8CNP102B, CY8CNP102E Document History Page Document Title: CY8CNP102B/CY8CNP102E Nonvolatile Programmable System-on-Chip (PSoC(R) NV) Document Number: 001-43991 REV. ECN Orig. of Change Submission Date Description of Change ** *A *B 1941108 2378513 2512803 vsutmp8/AESA PYRS GVCH/PYRS See ECN See ECN 06/05/2008 New Data Sheet Move to external web Features: Added total no. of GPIO information in Programmable Pin configurations Changed Pin no.14 from P3_7 to NC in the Pin diagram Table 1: Updated Pin definitions Table 5: Changed Typ and max value of IDD from 25 mA and 29mA to 36 mA and 40 mA resp. Table 5: Changed Typ and max value of IDDP from 15 mA and 16 mA to 27 mA and 28 mA respectively. Table 5: Changed Min and Max value of VCAP from 56 uF and 100 uF to 61 uF and 82 uF resp. Table 6: Changed VIH min value from 2.1 mV to 1.6 mV Added Table 12: DC POR,SMP, and LVD specifications Table 13: Changed IDDP naming convention to IDDPV Table 14: Updated note references Table 17: Updated Timer, Counter, deadband and CRCPS (PRS mode) values Table 23: Changed Typ and max value of IDD from 28 mA and 34 mA to 39 mA and 45 mA resp. Table 23: Changed Typ and max value of IDDP from 15 mA and 16 mA to 27 mA and 28 mA resp. Table 23: Changed Min and Max value of VCAP from 56 uF and 100 uF to 61 uF and 82 uF resp. Added Table 30: DC POR,SMP, and LVD specifications Table 31: Changed IDDP naming convention to IDDPV table 32: Updated note references Updated Figure 14: Definition for Timing for Fast/Standard Mode on the I2C bus Updated part Numbering Nomenclature Updated Thermal Impedance table Updated data sheet template Changed Title from nvPSoC to PSoC NV Updated "Features" Added M8C processor speeds for 3.3V and 5V operation in "Features" Updated Logic block diagram Changed total GPIOs from 27 to 33 Changed pin number 53 name from P1_4 to P1_6 Changed pin definition of pin 79 and 99 Table 5: Changed ISB from 3 mA to 5 mA Updated Table 12 Table 24: Changed ISB from 3 mA to 5 mA *C *D 2571208 2594976 GVCH/PYRS GVCH/PYRS 09/23/08 10/22/08 Document #: 001-43991 Rev. *D Page 37 of 38 [+] Feedback PRELIMINARY CY8CNP102B, CY8CNP102E Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com PSoC Solutions General Low Power/Low Voltage Precision Analog LCD Drive CAN 2.0b USB psoc.cypress.com/solutions psoc.cypress.com/low-power psoc.cypress.com/precision-analog psoc.cypress.com/lcd-drive psoc.cypress.com/can psoc.cypress.com/usb (c) Cypress Semiconductor Corporation, 2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 001-43991 Rev. *D Revised October 20, 2008 Page 38 of 38 PSoC DesignerTM, Programmable System-on-ChipTM, and PSoC ExpressTM are trademarks and PSoC(R) is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. AutoStore and QuantumTrap are registered trademarks of Simtek Corporation. All products and company names mentioned in this document are the trademarks of their respective holders. [+] Feedback |
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