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DOC Title EK7308 Preliminary DATA SHEET DOC NO TDS7308-01 REV 0.1 Page 1 / 1 / Revision History www..com Eff. Date REV. Page // Revise item / Content New Issue REV. REV Date 0.1 2003/06/09 2003/06/19 EUREKA Microelectronics, Inc. www..com EK7308 240-Output TFT Gate Driver IC 6F, NO.12, INNOVATION 1 . RD., SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU CITY, TAIWAN, R.O.C. http://www.eureka.com.tw ST EUREKA EK7308 Table of Contents Page 1.GENERAL DESCRIPTION.....................................................................2 www..com 2.FEATURES...........................................................................................2 3.BLOCK DIAGRAM..............................................................................2 4 PIN FUNCTION DESCRIPTIONS..............................................................3 5.FUNCTION OPERATIONS.......................................................................4 6.ABSOLUTE MAXIMUM RATINGS...........................................................9 7.ELECTRICAL CHARACTERISTICS.......................................................10 8.DEFINITIONS......................................................................................12 June 2003 -1- Preliminary Rev 0.1 EUREKA 240- Output TFT Gate Driver IC 1. DESCRIPTION The EK7308 is a 240-output TFT gate driver IC suitable for driving TFT LCD panels. www..com EK7308 2. FEATURES Output channels240 outputs+2 pins (fixed to VEE) Driver operating frequencymax. 200 KHz LCD supply voltageVEE+40V Driver output levelsTwo Logical interface+2.7V ~ -5.5V Incorporates bi-directional shift register. COG type 3. BLOCK DIAGRAM X1 X240 VGG High voltage output and level shifters VEE VDD VSS OE3 OE2 XDON DIO1 Low voltage logic and IO OE1 DIO2 FX RL Fig. 1 Block diagram June 2003 -2- Preliminary Rev 0.1 EUREKA 4. PIN FUNCTION DESCRIPTIONS Table 1. Pad description Pad Name I/O Function TFT gate driver output Supply Supply Shift direction selection signal DESCRIPTION EK7308 X1-X240 www..com O Under the control of the shift register data, OE1 or OE2 or OE3, and DIO1 or DIO2, the driver outputs are VGG or VEE and change their value at the rising edge of FX Short internally LCD panel auxiliary pins. This pins output VEE level. Negative power supply for Level shifters. Chip ground Logic ground, Reference of the voltages RL = "H" : X1 to X240 (Shift left) RL = "L" : X240 to X1 (Shift right) DIO1 DIO2 Output Input PATH X0, X241 VEE VSS RL I DIO1 DIO2 Start pulse input I/O and output Negative active input pin RL = "H" RL = "L" Input Output XDON FX OE1 OE2 OE3 VDD VGG I I When XDON = "L" then the driver outputs are at the VGG level independence of any other input or register value. Shift register clock The start pulse is sampled at the rising edge of FX, input The carry pulse changes at the falling edge of FX. Negative active input pin Supply Supply When OEN = "H" then the associated outputs are set to VEE independent of the register data. This function is not synchronized with FX. Logic positive power High voltage power and TFT driver output high level I - June 2003 -3- Preliminary Rev 0.1 EUREKA 5. FUNCTIONAL OPERATIONS Power supplies The TFT voltage is relative to the logic ground, it can be a negative voltage value. EK7308 VGG www..com VDD VSS VEE Fig. 2 Relative position of the different supply voltages Shift direction The input signals OE1, 2, 3 and the shift data control the value of the outputs (X1 till X240). Their value can be either VGG or VEE. The signal LR controls the shift direction of the shift register. The shift register takes its value from one of the input/output pins DIO at the rising edge of the clock FX and shifts the value to the other input/output pin DIO where it is presented at the falling edge of FX. Table 2. RL shift direction relation RL RL="H" RL="L" Start pulse taken from: DIO1 DIO2 Data shift direction X1X240 X240X1 Output pulse given at: DIO2 DIO1 June 2003 -4- Preliminary Rev 0.1 EUREKA OE function EK7308 When the OE1, OE2, OE3 inputs are "H" than the outputs are driven to VEE regardless of the contents of the shift register. Each of the three inputs drives it own set of outputs. This function is not synchronized with FX. The signal XDON can override this function. In the Table below the relation between each OE1,2,3 and their related outputs is given. Table 3. OE1,2,3 to Output relation Signal input www..com Symbol X(3i+1) i =0~79 X(3i+2) i =0~79 X(3i+3) i =0~79 LCD driver outputs X1,X4,X7,X10,...............................................................,X231,X232,X235,X238 X2,X5,X8,X11, .............................................................................., X239 X3,X6,X9,X12, ..................................................................,X234,X237,X240 OE1 OE2 OE3 1 FX DIO1 OE1 OE2 OE3 X1 X2 X3 X4 2 3 4 5 238 239 240 241 X240 DIO2 Fig. 3 OE Functionality RL="H" June 2003 -5- Preliminary Rev 0.1 EUREKA 1 FX DIO2 OE1 OE2 OE3 2 3 4 5 238 239 240 241 EK7308 www..com X240 X239 X238 X237 X1 DIO1 Fig. 4 OE Functionality RL= "L" June 2003 -6- Preliminary Rev 0.1 EUREKA XDON function EK7308 When XDON input is "L" then all outputs are driven to the VGG level. This function is overriding all other inputs. With this input all TFT gates are set to high to enable a display off function. This function is not synchronized with FX. 1 FX DIO1 2 3 4 5 238 239 240 241 www..com OE1 OE2 OE3 XDON X1 X2 X3 X4 X240 DIO2 Fig. 5 XDON Functionality RL="H" June 2003 -7- Preliminary Rev 0.1 EUREKA PRECAUTIONS Precaution when connecting or disconnecting the power supply EK7308 This IC has a high-voltage LCD driver, so it may be permanently damaged by a high current which may flow, if voltage is supplied to the LCD driver power supply while the logic system power supply is floating. The detail is as follows. When connecting the power supply, connect the LCD drive power after connecting the logic system power. Furthermore, when disconnecting the power, disconnect the logic system power after disconnecting the LCD drive power. www..com Voltage VGG VDD VSS Time VEE Fig. 9 Power ON/OFF sequence June 2003 -8- Preliminary Rev 0.1 EUREKA 6. ABSOLUTE MAXIMUM RATINGS Table 4. Absolute Maximum Ratings In accordance with the Absolute Maximum Ratings System (IEC 134); See notes 1 and 2 Parameter Supply voltage(1) Symbol VDD VGG Supply voltage(2) www..com VEE Input voltage Storage temperature Notes: VI VEE EO1, EO2, EO3, DIO1 DIO2, RL, FX, XDON VGG -45 to +0.3 VSS -0.3 to VDD+0.3 V Applicable Pins VDD VGG Ratings VSS -0.3 to +7.0 -0.3 to +45.0 Unit V V EK7308 NOTE 1, 2 V Tstg -45 to +125 1. Stress above those listed under Absolute Maximum Ratings may cause permanent damage to the device 2. Parameters are valid over operating temperature range unless otherwise specified. RECOMMENDED OPERATING CONDITIONS Table 5. Recommended operating conditions Parameter Supply voltage(1) Supply voltage(2) Supply voltage(3) Operating temperature Notes: 1. All voltages are with respect to VSS unless otherwise noted (0 V). 2. Ensure that voltages are set such that VEE VSS < VDD< VGG. Symbol VDD VGG VEE TOPR Applicable pins VDD VGG VEE Min. +2.7 +7.0 -16 -20 Typ. Max. +5.5 +25 -5 +75 Unit V V V 1, 2 Notes June 2003 -9- Preliminary Rev 0.1 EUREKA 7. ELECTRICAL CHARACTERISTICS Table 6. DC Characteristics (VSS=0 V, VDD=+2.5V to +5.5V, VGG=+15.0 to +40.0 V, TOPR=-25) Parameter Symbol Conditions Applicable pins Min. Typ. EK7308 Max. Unit Note www..com Operating Supply Current IDD fFX=15.7kHz VDD=3.3V VEE=-15V VGG=15V Output with no load VDD 800 A IGG Standby Quiescent Supply Current Standby VDD=3.3V VEE=-15V VGG=15V VGG VDD VGG 0.7x VDD 0 -1 0.7x VDD IO = -100 A IO = 100 A -50 VGG=15V VEE=-15V VOM=VGG-0.5V VOM is X1~X240 VGG=15V VEE=-15V VOM=VEE+0.5V VOM is X1~X240 DIO1, DIO2 VDD -0.4 300 A IDS 600 A IGS Input pin H input voltage L input voltage Input leakage current Output pin H input voltage L input voltage H output voltage L output voltage Output leakage current VIH3 VIL3 VOH VOL VLO1 RONVGG Output ON resistance RONVEE VIH1 VIL1 VLI1 100 VDD 0.3x VDD 1 VDD 0.3x VDD 0.4 50 A V V A V V V V A XDON except RL,FX, OE1~3, Liquid crystal driving output pin 600 X1~X240 1000 600 1000 June 2003 - 10 - Preliminary Rev 0.1 EUREKA Table 7. AC Characteristics (VSS= 0 V, VDD=+2.5V to +5.5V, VGG-VEE=+30.0 to +40.0 V, TOPR=25) Parameter Clock period Pulse width of clock H level Pulse width of clock L level www..com EK7308 Symbol tFX tWH tWL tsu th tpd1 tpd2 tr tf tpd3 CL=220pF CL=20pF CL=220pF Conditions Min. 500 500 200 300 500 10 100 100 900 Typ. Max. 200 Unit KHz In cascade connection ns ns ns ns ns us ns ns ns DIO data set up time DIO data hold time DIO output delay time Xn output delay time Input Rise Time Input Fall Time OEX output delay time Timing Chart tWL 80% FX 20% 20% tsu 80% DIO Input tpd1 60% DIO Output tpd2 th tWH 80% 50% 20% tFX 90% 10% tr tf 90% 50% 10% 80% tpd1 40% Xn 60% 40% 80% OEm tpd3 20% tpd3 60% Xn 40% 80% XDON 20% tpd2 60% Xn 40% tpd2 Fig. 10 Timing June 2003 - 11 - Preliminary Rev 0.1 EUREKA 8. DEFINITIONS Data Sheet status Objective specification Preliminary specification Product specification Application information Where application www..com information is given, it is advisory and does not form part of the specification. EK7308 This data sheet contains target or goal specification for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Eureka customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Eureka for any damages resulting from such improper use or sale. June 2003 - 12 - Preliminary Rev 0.1 |
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