 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| www..com Dec. 2001 VER. 1.00 4-BIT SINGLE CHIP MICROCOMPUTERS HMS38112/39112 USERS MANUAL * HMS38112 * HMS39112 VER. 1.00 Published by MCU Application Team in MagnaChip Semiconductor Ltd. Co., Ltd. MagnaChip Semiconductor Ltd. 2004 All Right Reserved. Additional information of this manual may be served by MagnaChip Semiconductor Ltd. Offices in Korea or Distributors and Representative listed at address directory. MagnaChip Semiconductor Ltd. reserves the right to make changes to any Information here in at any time without notice. The information, diagrams, and other data in this manual are correct and reliable; however, MagnaChip Semiconductor Ltd. is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual. HMS38112 HMS39112 ARCHITECTURE INSTRUCTION APPLICATION 1 2 3 4 5 Chapter 1.HMS38112 CHAPTER 1. HMS38112 Outline of characteristics The HMS38112 is remote control transmitter which uses CMOS technology This enables transmission code outputs of different configurations, multiple custom code output, and double push key output for easy fabrication. The HMS38112 is suitable for remote control of TV, VCR, FANS, Air-conditioners, Audio Equipments, Toys, Games etc. Characteristics * * * * * * * * * * * * * * * Program memory : 1,024 bytes Data memory : 32 4 bits 43 types of instruction set 3 levels of subroutine nesting Operating frequency : 2.4MHz ~ 4MHz Instruction cycle : fOSC/48 CMOS process (Single 3.0V power supply) Stop mode (Through internal instruction) Released stop mode by key input(mask option) Built in Power-on Reset circuit Built in Transistor for I.R LED Drive : IOL=250mA at VDD=3V and VO=0.3V Built in Low Voltage reset circuit Built in a watch dog timer (WDT) Low operating voltage : 2.0 ~ 3.6V 20 pin PDIP/SOP/SSOP package O 1-1 Chapter 1.HMS38112 Block Diagram VDD GND 20 1 Power-on Reset EPROM 64word 8 10 Program counter O16page O8bit 4 3-level Stack Watchdog timer 10 8 MUX 4 4 4 MUX 4 ALU 4 16 RAM Word Selector Instruction Decoder Control Signal X-Reg 2 RAM 16word x 2page x 4bit Y-Reg 4 ACC ST 4 OSC R-Latch 10 D-Latch 4 Pulse Generator 10 4 4 4 I.R.LED Drive Tr. 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 OSC1 OSC2 K0 ~ K3 R0 ~ R3 D0 D1 D2 D3 D4 D5 PGND REMOUT Fig 1-1 Block Diagram 1-2 Chapter 1.HMS38112 Pin Assignment GND 1 OSC1 2 OSC2 3 K0 4 K1 5 K2 6 K3 7 R0 8 R1 9 R2 10 20 VDD 19 REMOUT 18 PGND 17 D5 16 D4 15 D3 14 D2 13 D1 12 D0 11 R3 Fig 1-2 HMS38112 Pin Assignment (20 PIN) 1-3 Chapter 1.HMS38112 Pin Dimension - NOTE 1. DIMENSION * MARK DOES NOT INCLUDE MOLD PROTRUSION. MAXIMUM ALLOWABLE PROTRUSION IS 0.010 INCH PER SIDE. 2. DIMENSION ** MARK DOES NOT INCLUDE MOLD PROTRUSION. MAXIMUM ALLOWABLE PROTRUSION IS 0.010 INCH PRE SIDE. 3. UNSPECIFIED IS ACCORDING TO JEDEC MS-001 VARIATION AE. Fig 1-3. 20PDIP (300MIL) Pin Dimension (UNIT : INCH) - NOTE 1. DIMENSION * MARK DOES NOT INCLUDE MOLD PROTRUSION. MAXIMUM ALLOWABLE PROTRUSION IS 0.15 mm PER SIDE. 2. DIMENSION ** MARK DOES NOT INCLUDE MOLD PROTRUSION. MAXIMUM ALLOWABLE PROTRUSION IS 0.25 mm PRE SIDE. 3. DIMENSIONING AND TOLERANCEING PER ANSI Y14.5M-1982. 4. UNSPECIFIED IS ACCORDING TO JEDEC MS-013, VARIATION "AC". Fig 1-4. 20SOP (300MIL) Pin Dimension (UNIT : mm) 1-4 Chapter 1.HMS38112 0.0098 0.0075 ** 0.157 0.150 0.244 0.230 * 0.344 0.337 0.068 0.057 0.010 0.004 - NOTE 1. DIMENSION * MARK DOES NOT INCLUDE MOLD PROTRUSION. MAXIMUM ALLOWABLE PROTRUSION IS 0.006 INCH PER SIDE. 2. DIMENSION ** MARK DOES NOT INCLUDE MOLD PROTRUSION. MAXIMUM ALLOWABLE PROTRUSION IS 0.010 INCH PRE SIDE. 0.012 0.008 0.025 BSC 3. DIMENSIONING AND TOLERANCEING PER ANSI Y14.5M-1982. 4. UNSPECIFIED IS ACCORDING TO JEDEC MO-137, VARIATION "AD". Fig 1-5. 20SSOP (150MIL) Pin Dimension (UNIT : inch) 1-5 0.035 0.016 0- 8 Chapter 1.HMS38112 Pin Description and Circuit Pin Description Pin VDD GND I/O - Function Connected to 2.0~ 3.6V power supply Connected to 0V power supply. 4-bit input port with built in pull-up resistor. STOP mode is released by "L" input of each pin. K0 ~ K3 Input D0 ~ D5 Output Each can be set and reset independently. The output is the structure of N-channel-open-drain. R0 ~ R1 Input 2-bit input port with built in pull-up resistor. STOP mode is released by "L" input of each pin. R2 ~ R3 I/O 2-bit I/O port. (Input mode is set only when each of them output "H".) In outputting, each can be set and reset independently(or at once.) The output is in the form of C-MOS. STOP mode is released by "L" input of each pin. Oscillator input. Input to the oscillator circuit and connection point for ceramic resonator. A feedback resistor is connected between this pin and OSC2. OSC1 Input OSC2 Output Connect a resonator between this pin and OSC1. PGND - Ground pin for internal high current N-channel transistor. (connected to GND) REMOUT Output High current output port for driving I.R.LED. The output is in the form N-channel open drain. 1-6 Chapter 1.HMS38112 Pin Circuit Pin I/O I/O circuit pull-up Note R0 ~ R1 I - Built in MOS Tr for pull-up, about 140I. pull-up R2 ~ R3 I/O - CMOS output. - "H" output at reset. - Built in MOS Tr for pull-up, about 140I. pull-up K0 ~ K3 I - Built in MOS Tr for pull-up, about 140I. D0 ~ D5 O - Open drain output. - "L" output at reset. - D0~D3 are "L" output at STOP MODE.. - D4 ~D5 pins "Low" or keep before stop mode at STOP MODE (option) REMOUT RESETB REMOUT O PGND DATA - Open drain output - Output Tr. Disable at reset. 1-7 Chapter 1.HMS38112 Pin I/O I/O circuit Note OSC1 OSC2 OSC2 O - Built in feedback-resistor about 1 OSC1 I Rf STOP Optional Features The HMS38112 offers the following optional features. These options are masked. * I/O terminals having pull-up resistor : R2 ~ R3 * Input terminals having STOP release mode : K0 ~ K3, R0 ~ R3 * Output form at STOP mode : D4 ~D5 pins "L" or keep before stop mode 1-8 Chapter 1.HMS38112 Electrical Characteristics Absolute maximum ratings (Ta = 25I) Parameter Supply Voltage Power dissipation Storage temperature range Input voltage Output voltage I Symbol VDD PD Tstg VIN VOUT Max. rating -0.3 ~ 5.0 700 * -55 ~ 125 -0.3 ~ VDD+0.3 -0.3 ~ VDD+0.3 Unit V mW I V V * Thermal derating above 25I : 6mW per degree I rise in temperature. Recommended operating condition Parameter Supply Voltage Operating temperature Symbol VDD Topr Condition 2.4MHz ~ 4MHz - Rating 2.0 ~ 3.6 -20 ~ +70 Unit V I 1-9 Chapter 1.HMS38112 Electrical characteristics (Ta=25I, VDD= 3V) I Limits Parameter Symbol Min. Input H current K Pull-up Resistance R Pull-up Resistance Feedback Resistance K, R input H voltage K, R input L voltage D. R output L voltage OSC2 output L voltage OSC2 output H voltage REMOUT output L current REMOUT leakage current D, R output leakage current Current on STOP mode Operating supply current System clock frequency fOSC/48 IIH RPU1 RPU2 RFD VIH1 VIL1 VOL2*1 VOL3 VOH3 IOL1 IOLK1 IOLK2 ISTP IDD *2 fOSC 70 70 0.3 2.1 2.1 Unit Typ. 140 140 1.0 0.15 0.4 2.5 250 0.5 1 1 1 1.5 Condition Max. 1 300 300 3.0 0.9 0.4 0.9 uA VI=VDD VI=GND VI=GND, Output off VOSC1=GND, VOSC2=VDD IOL=3mA IOL=150uA IOH=-150uA VOL=0.3V V0UT=VDD, Output off V0UT=VDD, Output off At STOP mode fOSC=4MHz MHZ version I I V V V V V mA uA uA uA mA 2.4 - 4 MHz *1 Refer to Fig.1-6 < IOL2 vs. VOL2 Graph> *2 IDD is measured at RESET mode. 1-10 Chapter 1.HMS38112 Fig 1-6. IOL2 vs. VOL2 Graph. ( D, R Port ) I |A} |} 1-11 HMS38112 HMS39112 ARCHITECTURE INSTRUCTION APPLICATION 1 2 3 4 5 Chapter 2.HMS39112 CHAPTER 2. HMS39112 Outline of characteristics The HMS39112 is remote control transmitter which uses CMOS technology This enables transmission code outputs of different configurations, multiple custom code output, and double push key output for easy fabrication. The HMS39112 is suitable for remote control of TV, VCR, FANS, Air-conditioners, Audio Equipments, Toys, Games etc. It is possible to structure the 8 x 7 key matrix. Characteristics * * * * * * * * * * * * * * Program memory : 1,024 bytes Data memory : 32 4 bits 43 types of instruction set 3 levels of subroutine nesting Operating frequency : 2.4MHz ~ 4MHz Instruction cycle : fOSC/48 CMOS process (Single 3.0V power supply) Stop mode (Through internal instruction) Released stop mode by key input(mask option) Built in Power-on Reset circuit Built in Low Voltage reset circuit Built in a watch dog timer (WDT) Low operating voltage : 2.0 ~ 3.6V 20 pin PDIP/SOP/SSOP package O 2-1 Chapter 2.HMS39112 Block Diagram VDD GND 20 1 Power-on Reset EPROM 64word 8 10 Program counter O16page O8bit 4 3-level Stack Watchdog timer 10 8 MUX 4 4 4 MUX 4 ALU 4 16 RAM Word Selector Instruction Decoder Control Signal X-Reg 2 RAM 16word x 2page x 4bit Y-Reg 4 ACC ST 4 OSC R-Latch 10 D-Latch 4 Pulse Generator 10 4 4 4 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 D6 19 REMOUT OSC1 OSC2 K0 ~ K3 R0 ~ R3 D0 D1 D2 D3 D4 D5 Fig 2-1 Block Diagram 2-2 Chapter 2.HMS39112 Pin Assignment GND 1 OSC1 2 OSC2 3 K0 4 K1 5 K2 6 K3/Vpp 7 R0 8 R1 9 R2 10 20 VDD 19 REMOUT 18 D6 17 D5 16 D4 15 D3 14 D2 13 D1 12 D0 11 R3 Fig 2-2 HMS39112 Pin Assignment (20 PIN) 2-3 Chapter 2.HMS39112 Pin Dimension - NOTE 1. DIMENSION * MARK DOES NOT INCLUDE MOLD PROTRUSION. MAXIMUM ALLOWABLE PROTRUSION IS 0.010 INCH PER SIDE. 2. DIMENSION ** MARK DOES NOT INCLUDE MOLD PROTRUSION. MAXIMUM ALLOWABLE PROTRUSION IS 0.010 INCH PRE SIDE. 3. UNSPECIFIED IS ACCORDING TO JEDEC MS-001 VARIATION AE. Fig 2-3. 20PDIP (300MIL) Pin Dimension (UNIT : INCH) - NOTE 1. DIMENSION * MARK DOES NOT INCLUDE MOLD PROTRUSION. MAXIMUM ALLOWABLE PROTRUSION IS 0.15 mm PER SIDE. 2. DIMENSION ** MARK DOES NOT INCLUDE MOLD PROTRUSION. MAXIMUM ALLOWABLE PROTRUSION IS 0.25 mm PRE SIDE. 3. DIMENSIONING AND TOLERANCEING PER ANSI Y14.5M-1982. 4. UNSPECIFIED IS ACCORDING TO JEDEC MS-013, VARIATION "AC". Fig 2-4. 20SOP (300MIL) Pin Dimension (UNIT : mm) 2-4 Chapter 2.HMS39112 0.0098 0.0075 ** 0.157 0.150 0.244 0.230 * 0.344 0.337 0.068 0.057 0.010 0.004 - NOTE 1. DIMENSION * MARK DOES NOT INCLUDE MOLD PROTRUSION. MAXIMUM ALLOWABLE PROTRUSION IS 0.006 INCH PER SIDE. 2. DIMENSION ** MARK DOES NOT INCLUDE MOLD PROTRUSION. MAXIMUM ALLOWABLE PROTRUSION IS 0.010 INCH PRE SIDE. 0.012 0.008 0.025 BSC 3. DIMENSIONING AND TOLERANCEING PER ANSI Y14.5M-1982. 4. UNSPECIFIED IS ACCORDING TO JEDEC MO-137, VARIATION "AD". Fig 2-5. 20SSOP (150MIL) Pin Dimension (UNIT : INCH) 2-5 0.035 0.016 0- 8 Chapter 2.HMS39112 Pin Description and Circuit Pin Description Pin VDD GND I/O - Function Connected to 2.0~ 3.6V power supply Connected to 0V power supply. K0 ~ K3 Input 4-bit input port with built in pull-up resistor. STOP mode is released by "L" input of each pin.(masked option) D0 ~ D6 Output Each can be set and reset independently. The output is the structure of N-channel-open-drain. R0 ~ R1 Input 2-bit input port with built in pull-up resistor. STOP mode is released by "L" input of each pin.(masked option) R2 ~ R3 I/O 2-bit I/O port. (Input mode is set only when each of them output "H".) In outputting, each can be set and reset independently(or at once.) The output is in the form of C-MOS. STOP mode is released by "L" input of each pin. Pull-up resistor and STOP release mode can be respectively selected as masked option for each pin.(It is released by "L" input at STOP) Oscillator input. Input to the oscillator circuit and connection point for ceramic resonator. A feedback resistor is connected between this pin and OSC2. Connect a resonator between this pin and OSC1. OSC1 Input OSC2 Output REMOUT Output High current output port for driving I.R.LED. The output is in the form N-channel open drain. 2-6 Chapter 2.HMS39112 Pin Circuit Pin I/O I/O circuit Note pull-up R0 ~ R1 I - Built in MOS Tr for pull-up, about 140I. pull-up R2 ~ R3 I/O - CMOS output. - "H" output at reset. - Built in MOS Tr for pull-up, about 140I. pull-up K0 ~ K3 I - Built in MOS Tr for pull-up, about 140I. D0 ~ D6 O - Open drain output. - "L" output at reset. - D0~D3 are "L" output at STOP MODE. -D4 ~D6 pins "L" or keep before stop mode At STOP MODE(option) REMOUT O - Open drain output - "L" output at reset. - High current output source. 2-7 Chapter 2.HMS39112 Pin I/O I/O circuit Note OSC1 OSC2 OSC2 O - Built in feedback-resistor about 1 OSC1 I Rf STOP Optional Features The HMS39112 offers the following optional features. These options are masked. * I/O terminals having pull-up resistor : R2 ~ R3 * Input terminals having STOP release mode : K0 ~ K3, R0 ~ R3 * Output form at STOP mode : D4 ~D6 pins "L" or keep before stop mode 2-8 Chapter 2.HMS39112 Electrical Characteristics Absolute maximum ratings (Ta = 25I) Parameter Supply Voltage Power dissipation Storage temperature range Input voltage Output voltage I Symbol VDD PD Tstg VIN VOUT Max. rating -0.3 ~ 5.0 700 * -55 ~ 125 -0.3 ~ VDD+0.3 -0.3 ~ VDD+0.3 Unit V mW I V V * Thermal derating above 25I : 6mW per degree I rise in temperature. Recommended operating condition Parameter Supply Voltage Operating temperature Symbol VDD Topr Condition 2.4MHz ~ 4MHz - Rating 2.0 ~ 3.6 -20 ~ +70 Unit V I 2-9 Chapter 2.HMS39112 Electrical characteristics (Ta=25I, VDD= 3V) I Limits Parameter Symbol Min. Input H current K Pull-up Resistance R Pull-up Resistance Feedback Resistance K, R input H voltage K, R input L voltage D. R output L voltage OSC2 output L voltage OSC2 output H voltage REMOUT output L current REMOUT output H current D, R output leakage current Current on STOP mode Operating supply current System clock frequency fOSC/48 IIH RPU1 RPU2 RFD VIH1 VIL1 VOL2*1 VOL3 VOH3 IOL1*2 IOH1*3 IOLK2 ISTP IDD *4 fOSC 70 70 0.3 2.1 2.1 0.5 -5 - Unit Typ. 140 140 1.0 0.15 0.4 2.5 1.1 -15 0.5 Condition Max. 1 300 300 3.0 0.9 0.4 0.9 3 -30 1 1 1.5 uA VI=VDD VI=GND VI=GND, Output off VOSC1=GND, VOSC2=VDD IOL=3mA IOL=150uA IOH=-150uA VOL1=0.4V VOH1=2V V0UT=VDD, Output off At STOP mode fOSC=4MHz MHZ version I I V V V V V mA mA uA uA mA 2.4 - 4 MHz *1 Refer to Fig.2-6 < IOL2 vs. VOL2 Graph> *2 Refer to Fig.2-7 < IOL1 vs. VOL1 Graph> *3 Refer to Fig.2-8 < IOH1 vs. VOH1 Graph> *4 IDD is measured at RESET mode. 2-10 Chapter 2.HMS39112 Fig 2-6. IOL2 vs. VOL2 Graph. ( D, R Port ) I |A} |} Fig 2-7. IOL1 vs VOL1 Graph (REMOUT Port) I |A} |} 2-11 Chapter 2.HMS39112 Fig 2-8. IOH1 vs VOH1 Graph (REMOUT Port) I |A} |} 2-12 HMS38112 HMS39112 ARCHITECTURE INSTRUCTION APPLICATION 1 2 3 4 5 Chapter 3. Architecture CHAPTER 3. Architecture Program Memory The HMS38112/39112 can incorporate maximum 1,024 words (64 wordsO16 pagesO8bits) for program memory. Program counter PC (A0~A5) and page address register (A6~A9) are used to address the whole area of program memory having an instruction (8bits) to be next executed. The program memory consists of 64 words on each page, and thus each page can hold up to 64 steps of instructions. The program memory is composed as shown below. Program capacity (pages) 01 8 23 45 67 Page 0 6 63 Page 1 Page 2 Page 15 0 A0~A5 Program counter (PC) 6 Stack 1 2 15 A6~A9 Page address register (PA) 4 register (Level "1") (Level "2") 4 Page buffer (PB) (SR) (PSR) (Level "3") Fig 3-1 Configuration of Program Memory 3-1 Chapter 3. Architecture Address Register The following registers are used to address the ROM. * Page address register (PA) : Holds ROM's page number (0~Fh) to be addressed. * Page buffer register (PB) : Value of PB is loaded by an LPBI command when newly addressing a page. Then it is shifted into the PA when rightly executing a branch instruction (BR) and a subroutine call (CAL). * Program counter (PC) : Available for addressing word on each page. * Stack register (SR) : Stores returned-word address in the subroutine call mode. (1) Page address register and page buffer register : Address one of pages #0 to #15 in the EPROM by the 4-bit binary counter. Unlike the program counter, the page address register is usually unchanged so that the program will repeat on the same page unless a page changing command is issued. To change the page address, take two steps such as (1) writing in the page buffer what page to jump (execution of LPBI) and (2) execution of BR or CAL, because instruction code is of eight bits so that page and word can not be specified at the same time. In case a return instruction (RTN) is executed within the subroutine that has been called in the other page, the page address will be changed at the same time. (2) Program counter : This 6-bit binary counter increments for each fetch to address a word in the currently addressed page having an instruction to be next executed. For easier programming, at turning on the power, the program counter is reset to the zero location. The PA is also set to "0". Then the program counter specifies the next address in random sequence. When BR, CAL or RTN instructions are decoded, the switches on each step are turned off not to update the address. Then, for BR or CAL, address data are taken in from the instruction operands (a0 to a5), or for RTN, and address is fetched from stack register No. 1. (3) Stack register : This stack register provides two stages each for the program counter (6bits) and the page address register (4bits) so that subroutine nesting can be made on two levels. 3-2 Chapter 3. Architecture Data Memory (RAM) Up to 32 nibbles (16 words 2pages 4bits) is incorporated for storing data. The whole data memory area is indirectly specified by a data pointer (X,Y). Page number is specified by zero bit of X register, and words in the page by 4 bits in Y-register. Data memory is composed in 16 nibbles/page. Figure 4-2 shows the configuration. O O D0 D9 R0 R3 REMOUT Data memory page (0~1) Output port 0 1 2 3 Page 0 Page 1 15 4 a0~a3 0 1 Y-register (Y) X-register (X) Fig 3-2 Composition of Data Memory X-register (X) X-register is consist of 2bit, X0 is a data pointer of page in the RAM, X1 is reserved. X1=0 Y=0 Y=1 D0 D1 X1=1 Reserved Reserved Table 3-1 Mapping table between X and Y register Y-register (Y) Y-register has 4 bits. It operates as a data pointer or a general-purpose register. Y-register specifies an address (a0~a3) in a page of data memory, as well as it is used to specify an output port. Further it is used to specify a mode of carrier signal outputted from the REMOUT port. It can also be treated as a generalpurpose register on a program. 3-3 Chapter 3. Architecture Accumulator (ACC) The 4-bit register for holding data and calculation results. Arithmetic and Logic Unit (ALU) In this unit, 4bits of adder/comparator are connected in parallel as it's main components and they are combined with status latch and status logic (flag.) (1) Operation circuit (ALU) : The adder/comparator serves fundamentally for full addition and data comparison. It executes subtraction by making a complement by processing an inversed output of ACC (ACC+1) (2) Status logic : This is to bring an ST, or flag to control the flow of a program. It occurs when a specified instruction is executed in three cases such as overflow or underflow in operation and two inputs unequal. State Counter (SC) A fundamental machine cycle timing chart is shown below. Every instruction is one byte length. Its execution time is the same. Execution of one instruction takes 6 clocks for fetch cycle and 6 clocks for execute cycle (12 clocks in total). Virtually these two cycles proceed simultaneously, and thus it is apparently completed in 6 clocks (one machine cycle). Exceptionally BR, CAL and RTN instructions is normal execution time since they change an addressing sequentially. Therefore, the next instruction is prefetched so that its execution is completed within the fetch cycle. T1 T2 T3 T4 T5 T6 T1 T2 T3 T4 T5 T6 Fetch cycle N Execute cycle N-1 Execute cycle N Fetch cycle N-1 Phasee Phasee Phasee Machine Cycle Machine Cycle Fig. 3-3 Fundamental timing chart 3-4 Chapter 3. Architecture Clock Generator The HMS38112/39112 have an internal clock oscillator. The oscillator circuit is designed to operate with an external ceramic resonator. Oscillator circuit is able to organize by connecting ceramic resonator to outside. * It is necessary to connect capacitor to outside in order to change ceramic resonator, you must refer to a manufacturers resonator matching guide. OSC1 OSC2 2 C1 3 C2 sx~^c\\] x}ll nz}ppns ov ^Ya_xs n~w~^xa_raXm[ n}w^Ya_x} qn}^Ya_xn _Y[[xs n~w~^xa_raXm[ n}w_Y[[x} qn}_Y[xn * All type have the built-in loading capacitors. 3-5 Chapter 3. Architecture Pulse Generator The following frequency and duty ratio are selected for carrier signal outputted from the REMOUT port depending on a PMR (Pulse Mode Register) value set in a program. T T1 PMR 0 1 2 3 4 5 6 7 * Default value is "0" T=1/fPUL = 96/fOSC, T=1/fPUL = 96/fOSC, T=1/fPUL = 64/fOSC, T=1/fPUL = 64/fOSC, T=1/fPUL = 88/fOSC, REMOUT signal T1/T = 1/2 T1/T = 1/3 T1/T = 1/2 T1/T = 1/4 T1/T = 4/11 No Pulse (same to D0 ~ D9) T=1/fPUL = 96/fOSC, No pulse (same to D0 ~ D9) T1/T = 1/4 Table 3-2 PMR selection table 3-6 Chapter 3. Architecture Reset Operation HMS38112/39112 have three reset sources. One is a built-in Power-on reset circuit, another is a built-in Low VDD Detection circuit, the other is the overflow of Watch Dog Timer (WDT). All reset operations are internal in the HMS38112. Built-in Power On Reset Circuit HMS38112/39112 has a built-in Power-on reset circuit consisting of an about 1 Resistor and a 3pF Capacitor. When the Power-on reset pulse occurs, system reset signal is latched and WDT is cleared. After the overflow time of WDT (213 x System clock time), system reset signal is released. VDD 1 Counter (WDT) System RESETB 3pF GND VCC System RESETB treset About 108msec at fosc = 3.64MHz Fig. 3-4 Power-On Reset Circuit and Timing Chart 3-7 Chapter 3. Architecture Built-in Low VDD Reset Circuit HMS38112/39112 have a Low VDD detection circuit. If VDD become Reset Voltage of Low VDD Detection circuit at a active status, system reset occur and WDT is cleared. After VDD is increased upper Reset Voltage again, WDT is re-counted and if WDT is overflowed, system reset is released. VDD Reset Voltage Internal RESETB About 108msec at fosc =3.64MHz Fig. 3-5 Low Voltage Detection diagram 3-8 Chapter 3. Architecture Watch Dog Timer (WDT) Watch dog timer is organized binary of 14 steps. The signal of fOSC/48 cycle comes in the first step of WDT after WDT reset. If this counter was overflowed, reset signal automatically come out so that internal circuit is initialized. The overflow time is 8O6O213/fOSC (108.026ms at fOSC = 3.64MHz) Normally, the binary counter must be reset before the overflow by using reset instruction (WDTR), Power-on reset pulse or Low VDD detection pulse. * It is constantly reset in STOP mode. When STOP is released, counting is restarted. (Refer to STOP Operation>) Binary counter(14 steps) fOSC/48 RESET (edge-trigger) CPU reset Reset by instruction Power-On Reset Low VDD Detection Fig 3-6 Block Diagram of Watch-dog Timer 3-9 Chapter 3. Architecture STOP Operation Stop mode can be achieved by STOP instructions. In stop mode : 1. Oscillator is stopped, the operating current is low. 2. Watch dog timer is reset, D0~D3 output and REMOUT output are "L" . 3. Part other than WDT, D0~D3 output and REMOUT output have a value before come into stop mode. Stop mode is released when one of K or R input is going to "L". 1. State of D0~D3 output and REMOUT output is return to state of before stop mode is achieved. 2. After 210 OSystem clock time for stable oscillating, first instruction start to operate. 3. In return to normal operation, WDT is counted from zero again. But, at executing stop instruction, if one of K or R input is chosen to "L", stop instruction is same to NOP instruction. 3-10 HMS38112 HMS39112 ARCHITECTURE INSTRUCTION APPLICATION 1 2 3 4 5 Chapter 4. Instruction CHAPTER 4. Instruction INSTRUCTION FORMAT All of the 43 instruction in HMS38112/39112 is format in two fields of OP code and operand which consist of eight bits. The following formats are available with different types of operands. *Formate All eight bits are for OP code without operand. *Formate Two bits are for operand and six bits for OP code. Two bits of operand are used for specifying bits of RAM and X-register (bit 1 and bit 7 are fixed at I0I) *Formate Four bits are for operand and the others are OP code. Four bits of operand are used for specifying a constant loaded in RAM or Yregister, a comparison value of compare command, or page addressing in ROM. *Format i Six bits are for operand and the others are OP code. Six bits of operand are used for word addressing in the ROM. 4-1 Chapter 4. Instruction INSTRUCTION TABLE The HMS38112/39112 provides the following 43 basic instructions. Category 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Arithmetic ROM Address RAM Bit Manipulation Immediate RAM to Register Register to Register Mnemonic LAY LYA LAZ LMA LMAIY LYM LAM XMA LYI i LMIIY i LXI n SEM n REM n TM n BR a CAL a RTN LPBI i AM SM IM DM IA IY DA Function ST*1 S S S S S S S S S S S S S E S S S S C B C B S C B aY YaA Aa0 A M(X,Y) aA M(X,Y) a A, Y a Y+1 Y a M(X,Y) A a M(X,Y) A a M(X,Y) Yai M(X,Y) a i, Y a Y+1 Xan M(n) a 1 M(n) a 0 TEST M(n) = 1 if ST = 1 then Branch if ST = 1 then Subroutine call Return from Subroutine ai A a A + M(X,Y) A a M(X,Y) - A A a M(X,Y) + 1 A a M(X,Y) - 1 A a A+1 Y a Y+1 A a A-1 PB 4-2 Chapter 4. Instruction Category 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 Control 42 43 Input / Output Comparison Arithmetic Mnemonic DY EORM NEGA ALEM ALEI i MNEZ YNEA YNEI i KNEZ RNEZ LAK LAR SO RO WDTR STOP LPY NOP Y Function ST*1 B S Z E E N N N N N S S S S S S S S a Y-1 A a A + M (X,Y) A a A+1 TEST A o M(X,Y) TEST A o i TEST M(X,Y) o 0 TEST Y o A TEST Y o i TEST K o 0 TEST R o 0 AaK AaR Output(Y) Output(Y) a 1 at HMS39112, 0 at HMS38112 a 0 at HMS39112, 1 at HMS39112 Watch Dog Timer Reset Stop operation PMR aY No operation Note) i = 0~f, n = 0~3, a = 6bit PC Address *1 Column ST indicates conditions for changing status. Symbols have the following meanings S : On executing an instruction, status is unconditionally set. C : Status is only set when carry or borrow has occurred in operation. B : Status is only set when borrow has not occurred in operation. E : Status is only set when equality is found in comparison. N : Status is only set when equality is not found in comparison. Z : Status is only set when the result is zero. 4-3 Chapter 4. Instruction Port Operation Value of X-reg Value of Y-reg 0~6 0 or 1 SO : D(Y) RO : D(Y) Operation a 1(High-Z) a0 a a 0 or 1 8 REMOUT port repeats "H" and "L" in pulse frequency. (When PMR = 5, it is fixed at "H") SO : REMOUT(PMR) 1 at HMS39112, 0 at HMS38112 RO : REMOUT(PMR) 0 at HMS39112, 1 at HMS38112 0 or 1 0 or 1 0 or 1 0 or 1 9 C~D E F SO : D0 ~ D6a 1 (High-Z) RO : D0 ~ D6a 0 SO : R(Y-Ah) RO : R(Y-Ah) SO : RO : SO : RO : a1 a0 R2 ~ R3 a 1 R2 ~ R3 a 0 D0 ~ D6 a 1(High-Z), R2 ~ R3 a 1 D0 ~ D6 a 0, R2 ~ R3 a 0 4-4 Chapter 4. Instruction DETAILS OF INSTRUCTION SYSTEM All 43 basic instructions of the HMS38112/39112 are one by one described in detail below. Description Form Each instruction is headlined with its mnemonic symbol according to the instructions table given earlier. Then, for quick reference, it is described with basic items as shown below. After that, detailed comment follows. * Items : - Naming : - Status : - Format : - Operand : - Function Full spelling of mnemonic symbol Check of status function Categorized into to Omitted for Format ei e 4-5 Chapter 4. Instruction (1) LAY Naming : Status : Format : Function : Load Accumulator from Y-Register Set I AaY Data of four bits in the Y-register is unconditionally transferred to the accumulator. Data in the Y-register is left unchanged. (2) LYA Naming : Status : Format : Function : Load Y-register from Accumulator Set I YaA Load Y-register from Accumulator Clear Accumulator Set I Aa0 Data in the accumulator is unconditionally reset to zero. Load Memory from Accumulator Set I M(X,Y) a A Data of four bits from the accumulator is stored in the RAM location addressed by the X-register and Y-register. Such data is left unchanged. (5) LMAIY Naming : Status : Format : Function : Load Memory from Accumulator and Increment Y-Register Set I M(X,Y) a A, Y a Y+1 Data of four bits from the accumulator is stored in the RAM location addressed by the X-register and Y-register. Such data is left unchanged. 4-6 Chapter 4. Instruction (6) LYM Naming : Status : Format : Function : Load Y-Register form Memory Set I Y a M(X,Y) Data from the RAM location addressed by the X-register and Y-register is loaded into the Y-register. Data in the memory is left unchanged. (7) LAM Naming : Status : Format : Function : Load Accumulator from Memory Set I A a M(X,Y) Data from the RAM location addressed by the X-register and Y-register is loaded into the Y-register. Data in the memory is left unchanged. (8) XMA Naming : Status : Format : Function : Exchanged Memory and Accumulator Set I M(X,Y) a A Data from the memory addressed by X-register and Y-register is exchanged with data from the accumulator. For example, this instruction is useful to fetch a memory word into the accumulator for operation and store current data from the accumulator into the RAM. The accumulator can be restored by another XMA instruction. (9) LYI i Naming : Status : Format : Operand : Function : Load Y-Register from Immediate Set Constant 0 o i o 15 Yai To load a constant in Y-register. It is typically used to specify Y-register in a particular RAM word address, to specify the address of a selected output line, to set Y-register for specifying a carrier signal outputted from OUT port, and to initialize Y-register for loop control. The accumulator can be restored by another XMA instruction. Data of four bits from operand of instruction is transferred to the Y-register. e 4-7 Chapter 4. Instruction (10) LMIIY i Naming : Status : Format : Operand : Function : Load Memory from Immediate and Increment Y-Register Set Constant 0 o i o 15 M(X,Y) a i, Y a Y + 1 Data of four bits from operand of instruction is stored into the RAM location addressed by the X-register and Y-register. Then data in the Y-register is incremented by one. e (11) LXI n Naming : Status : Format : Operand : Function : Load X-Register from Immediate Set X file address 0 o n o 3 Xan A constant is loaded in X-register. It is used to set X-register in an index of desired RAM page. Operand of 1 bit of command is loaded in X-register. e (12) SEM n Naming : Status : Format : Operand : Function : Set Memory Bit Set Bit address 0 o n o 3 M(X,Y,n) a 1 Depending on the selection in operand of operand, one of four bits is set as logic 1 in the RAM memory addressed in accordance with the data of the X-register and Y-register. e (13) REM n Naming : Status : Format : Operand : Function : Reset Memory Bit Set Bit address 0 o n o 3 M(X,Y,n) a 0 Depending on the selection in operand of operand, one of four bits is set as logic 0 in the RAM memory addressed in accordance with the data of the X-register and Y-register. e 4-8 Chapter 4. Instruction (14) TM n Naming : Status : Format : Operand : Function : Test Memory Bit Comparison results to status Bit address 0 o n o 3 M(X,Y,n) a 1? ST a 1 when M(X,Y,n)=1, ST a 0 when M(X,Y,n)=0 A test is made to find if the selected memory bit is logic. 1 Status is set depending on the result. e (15) BR a Naming : Status : Format : Operand : Function : Branch on status 1 Conditional depending on the status Branch address a (Addr) When ST =1 , PA a PB, PC a a(Addr) When ST = 0, PC a PC + 1, ST a 1 Note : PC indicates the next address in a fixed sequence that is actually pseudo-random count. For some programs, normal sequential program execution can be change. A branch is conditionally implemented depending on the status of results obtained by executing the previous instruction. * Branch instruction is always conditional depending on the status. a. If the status is reset (logic 0), a branch instruction is not rightly executed but the next instruction of the sequence is executed. b. If the status is set (logic 1), a branch instruction is executed as follows. * Branch is available in two types - short and long. The former is for addressing in the current page and the latter for addressing in the other page. Which type of branch to exeute is decided according to the PB register. To execute a long branch, data of the PB register should in advance be modified to a desired page address through the LPBI instruction. i 4-9 Chapter 4. Instruction (16) CAL a Naming : Status : Format : Operand : Function : Subroutine Call on status 1 Conditional depending on the status Subroutine code address a(Addr) When ST =1 , PC a a(Addr) PA a PB SR1 a PC + 1, PSR1 a PA SR2 a SR1 PSR2 a PSR1 SR3 a SR2 PSR3 a PSR2 When ST = 0 PC a PC + 1 PB a PS ST a 1 Note : PC actually has pseudo-random count against the next instruction. * In a program, control is allowed to be transferred to a mutual subroutine. Since a call instruction preserves the return address, it is possible to call the subroutine from different locations in a program, and the subroutine can return control accurately to the address that is preserved by the use of the call return instruction (RTN). Such calling is always conditional depending on the status. a. If the status is reset, call is not executed. b. If the status is set, call is rightly executed. The subroutine stack (SR) of three levels enables a subroutine to be manipulated on three levels. Besides, a long call (to call another page) can be executed on any level. * For a long call, an LPBI instruction should be executed before the CAL. When LPBI is omitted (and when PA=PB), a short call (calling in the same page) is executed. i 4-10 Chapter 4. Instruction (17) RTN Naming : Status : Format : Function : Return from Subroutine Set PA, PB a PSR1 PSR1 a PSR2 PSR2 a PSR3 PSR3 a PSR2 ST a1 Control is returned from the called subroutine to the calling program. Control is returned to its home routine by transferring to the PC the data of the return address that has been saved in the stack register (SR1). At the same time, data of the page stack register (PSR1) is transferred to the PA and PB. PC a SR1 SR1 a SR2 SR2 a SR3 SR3 a SR3 e (18) LPBI i Naming : Status : Format : Operand : Function : Load Page Buffer Register from Immediate Set ROM page address 0 o i o 15 PB a i A new ROM page address is loaded into the page buffer register (PB). This loading is necessary for a long branch or call instruction. The PB register is loaded together with three bits from 4 bit operand. e (19) AM Naming : Status : Format : Function : Add Accumulator to Memory and Status 1 on Carry Carry to status A a M(X,Y)+A, ST a 1(when total>15), ST a 0 (when total o15) Data in the memory location addressed by the X and Y-register is added to data of the accumulator. Results are stored in the accumulator. Carry data as results is transferred to status. When the total is more than 15, a carry is caused to put I1I in the status. Data in the memory is not changed. e 4-11 Chapter 4. Instruction (20) SM Naming : Status : Format : Function : Subtract Accumulator to Memory and Status 1 Not Borrow Carry to status A a M(X,Y) - A ST a 1(when A o M(X,Y)) ST a 0(when A > M(X,Y)) e (21) IM Naming : Status : Format : Function : Increment Memory and Status 1 on Carry Carry to status A a M(X,Y) + 1 ST a 1(when M(X,Y) o 15) ST a 0(when M(X,Y) < 15) e (22) DM Naming : Status : Format : Function : Decrement Memory and Status 1 on Not Borrow Carry to status A a M(X,Y) - 1 ST a 1(when M(X,Y) o1) ST a 0 (when M(X,Y) = 0) Data of the memory addressed by the X and Y-register is fetched, and one is subtracted from this word (addition of Fh)> Results are stored in the accumulator. Carry data as results is transferred to the status. If the data is more than or equal to one, the status is set to indicate that no borrow is caused. The memory is left unchanged. e 4-12 Chapter 4. Instruction (23) IA Naming : Status : Format : Function : Increment Accumulator Set A a A+1 Data of the accumulator is incremented by one. Results are returned to the accumulator. A carry is not allowed to have effect upon the status. e (24) IY Naming : Status : Format : Function : Increment Y-Register and Status 1 on Carry Carry to status Y a Y+1 ST a 1 (when Y = 15) ST a 0 (when Y < 15) Data of the Y-register is incremented by one and results are returned to the Y-register. Carry data as results is transferred to the status. When the total is more than 15, the status is set. e (25) DA Naming : Status : Format : Function : Decrement Accumulator and Status 1 on Borrow Carry to status A a A -1 ST a 1(when A o1) ST a 0 (when A = 0) Data of the accumulator is decremented by one. As a result (by addition of Fh), if a borrow is caused, the status is reset to I0I by logic. If the data is more than one, no borrow occurs and thus the status is set to I1I. e 4-13 Chapter 4. Instruction (26) DY Naming : Status : Format : Function : Decrement Y-Register and Status 1 on Not Borrow Carry to status Y a Y -1 ST a 1 (when Y o 1) ST a 0 (when Y = 0) Data of the Y-register is decremented by one. Data of the Y-register is decremented by one by addition of minus 1 (Fh). Carry data as results is transferred to the status. When the results is equal to 15, the status is set to indicate that no borrow has not occurred. e (27) EORM Naming : Status : Format : Function : A a M(X,Y) + A Data of the accumulator is, through a Exclusive OR, subtracted from the memory word addressed by X and Yregister. Results are stored into the accumulator. e Exclusive or Memory and Accumulator Set (28) NEGA Naming : Status : Format : Function : Negate Accumulator and Status 1 on Zero Carry to status A a A+1 ST a 1(when A = 0) ST a 0 (when A != 0) The 2s complement of a word in the accumulator is obtained. The 2s complement in the accumulator is calculated by adding one to the 1s complement in the accumulator. Results are stored into the accumulator. Carry data is transferred to the status. When data of the accumulator is zero, a carry is caused to set the status to I1I. e 4-14 Chapter 4. Instruction (29) ALEM Naming : Status : Format : Function : Accumulator Less Equal Memory Carry to status ST a 1 (when A o M(X,Y)) ST a 0 (when A > M(X,Y)) Data of the accumulator is, through a complemental addition, subtracted from data in the memory location addressed by the X and Y-register. Carry data obtained is transferred to the status. When the status is I1I, it indicates that the data of the accumulator is less than or equal to the data of the memory word. Neither of those data is not changed. A o M(X,Y) e (30) ALEI Naming : Status : Format : Function : Accumulator Less Equal Immediate Carry to status A oi ST a 1 (when A o i) ST a 0 (when A > i) e (31) MNEZ Naming : Status : Format : Function : Memory Not Equal Zero Comparison results to status ST a 1(when M(X,Y) o 0) ST a 0 (when M(X,Y) = 0) A memory word is compared with zero. Data in the memory addressed by the X and Y-register is logically compared with zero. Comparison data is thransferred to the status. Unless it is zero, the status is set. e M(X,Y) o 0 4-15 Chapter 4. Instruction (32) YNEA Naming : Status : Format : Function : Y-Register Not Equal Accumulator Comparison results to status ST a 1 (when Y o A) ST a 0 (when Y = A) Data of Y-register and accumulator are compared to check if they are not equal. Data of the Y-register and accumulator are logically compared. Results are transferred to the status. Unless they are equal, the status is set. YoA e (33) YNEI Naming : Status : Format : Operand : Function : Y-Register Not Equal Immediate Comparison results to status ST a 1 (when Y o i) ST a 0 (when Y = i) The constant of the Y-register is logically compared with 4bit operand. Results are transferred to the status. Unless the operand is equal to the constant, the status is set. Constant 0 o i o 15 Yoi e (34) KNEZ Naming : Status : Format : Function : When K o 0, ST a 1 A test is made to check if K is not zero. Data on K are compared with zero. Results are transferred to the status. For input data not equal to zero, the status is set. e K Not Equal Zero The status is set only when not equal (35) RNEZ Naming : Status : Format : Function : When R o 0, ST a 1 A test is made to check if R is not zero. Data on R are compared with zero. Results are transferred to the status. For input data not equal to zero, the status is set. e R Not Equal Zero The status is set only when not equal 4-16 Chapter 4. Instruction (36) LAK Naming : Status : Format : Function : Load Accumulator from K Set AaK Data on K are transferred to the accumulator e Load Accumulator from R Set e AaR Data on R are transferred to the accumulator (38) SO Naming : Status : Format : Function : D(Y) a 1 0oYo7 REMOUT a 1(PMR=5) Y=8 D0~D9 a 1 (High-Z) Y=9 R(Y) a 1 Ah o Y o Dh Ra1 Y = Eh D0~D9, R a 1 Y = Fh A single D output line is set to logic 1, if data of Y-register is between 0 to 7. Carrier frequency come out from REMOUT port, if data of Y-register is 8. All D output line is set to logic 1, if data of Y-register is 9. It is no operation, if data of Y-register between 10 to 15. When Y is between Ah and Dh, one of R output lines is set at logic 1. When Y is Eh, the output of R is set at logic 1. When Y is Fh, the output D0~D9 and R are set at logic 1. Data of Y-register is between 0 to 7, selects appropriate D output. Data of Y-register is 8, selects REMOUT port. Data of Y-register is 9, selects all D port. Data in Y-register, when between Ah and Dh, selects an appropriate R output (R0~R3). Data in Y-register, when it is Eh, selects all of R0~R3. Data in Y-register, when it is Fh, selects all of D0~D9 and R0~R3. e Set Output Register Latch Set 4-17 Chapter 4. Instruction (39) RO Naming : Status : Format : Function : Reset Output Register Latch Set D(Y) a 0 0oYo7 REMOUT a 0 Y=8 D0~D9 a 0 Y=9 R(Y) a 0 Ah o Y o Dh Ra0 Y = Eh D0~D9, R a 0 Y = Fh A single D output line is set to logic 0, if data of Y-register is between 0 to 9. REMOUT port is set to logic 0, if data of Y-register is 9. All D output line is set to logic 0, if data of Y-register is 9. When Y is between Ah and Dh, one of R output lines is set at logic 0. When Y is Eh, the output of R is set at logic 0 When Y is Fh, the output D0~D9 and R are set at logic 1. Data of Y-register is between 0 to 7, selects appropriate D output. Data of Y-register is 8, selects REMOUT port. Data of Y-register is 9, selects D port. Data in Y-register, when between Ah and Dh, selects an appropriate R output (R0~R3). Data in Y-register, when it is Eh, selects all of R0~R3. Data in Y-register, when it is Fh, selects all of D0~D9 and R0~R3. e (40) WDTR Naming : Status : Format : Function : Reset Watch Dog Timer (WDT) Normally, you should reset this counter before overflowed counter for dc watch dog timer. this instruction controls this reset signal. e Watch Dog Timer Reset Set 4-18 Chapter 4. Instruction (41) STOP Naming : Status : Format : Function : STOP Set Operate the stop function Stopped oscillator, and little current. (See 1-12 page, STOP function.) e (42) LPY Naming : Status : Format : Function : Pulse Mode Set Set PMR a Y Selects a pulse signal outputted from REMOUT port. e (43) NOP Naming : Status : Format : Function : No Operation Set No operation e 4-19 HMS38112 HMS39112 ARCHITECTURE INSTRUCTION APPLICATION 1 2 3 4 5 Chapter 5. Application Guideline for S/W 1. All rams need to be initialized to zero in reset address for proper design. 2. Make the output ports H after reset. 3. Do not use WDTR instruction in subroutine. 4. Before reading the input port the waiting time should be more than 200uS. 5. To decrease current consumption, make the output port as high in normal routine except for key scan strobe and STOP mode. 6. We recommend you do not use all 64 bytes in a page. You had better write BR $ in unused area. This will help you prevent unusual operation of MCU. 7. Be careful not to use long call or branch (CALL,BL) with arithmetic manipulation. If you want to use branch right after arithmetic manipulation, the long call or branch will be against your intention. ex) LAR ; The value of R ports -> Accumulator ALEI 14 ; Ao14 : S = 1, A :S=0 BL TRUE ; S is always 1 because BL is composed of LPBI and BR. -------------- Fail 14 LAR ; The value of R ports -> Accumulator ALEI 14 ; Ao14 : S = 1, A :S=0 BR TRUE ; When S is 1 Branch will occur. Otherwise Branch will not occur and LAK ; next instruction will be operated. -------------- Right 14 5-1 Chapter 5. Application HMS38112 Circuit Diagram 41 42 43 44 45 46 47 48 33 34 35 36 37 38 39 40 25 26 27 28 29 30 31 32 17 18 19 20 21 22 23 24 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 4 K0 3 OSC2 5 K1 6 K2 OSC1 GND 2 1 7 K3 We recommend alkaline battery HMS38112-RDXXX 8 R0 Vdd 20 + 9 10 11 12 13 14 15 16 17 R1 R2 R3 REM OUT 19 D0 D1 D2 D3 D4 D5 PGND 18 = 5-2 Chapter 5. Application HMS39112 Circuit Diagram 49 50 51 52 53 54 55 56 41 42 43 44 45 46 47 48 33 34 35 36 37 38 39 40 25 26 27 28 29 30 31 32 17 18 19 20 21 22 23 24 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 4 K0 3 OSC2 5 K1 6 K2 OSC1 GND 2 1 7 K3 We recommend alkaline battery HMS39112-REXXX 8 R0 Vdd 20 + 9 10 11 12 13 14 15 16 17 R1 R2 R3 REM OUT 19 D0 D1 D2 D3 D4 D5 18 D6 = 5-3 Chapter 5. Application Truth Table for example program CUSTOM:04H vp yzY v[\ v[] v[^ v[_ v[ v[a v[b v[c v[d v\[ v\\ v\] v\^ v\_ v\ v\a v\b v\c v\d v][ v]\ v]] v]^ v]_ v] v]a v]b v]c ollSsT [[ [\ [] [^ [_ [ [a [b [c [d [l [m [n [o [p [q \[ \\ \] \^ \_ \ \a \b \c \d \l \m vp yzY v]d v^[ v^\ v^] v^^ v^_ v^ v^a v^b v^c v^d v_[ v_\ v_] v_^ v__ v_ v_a v_b v_c v_d v[ v\ v] v^ v_ v va ollSsT \n \o \p \q ][ ]\ ]] ]^ ]_ ] ]a ]b ]c ]d ]l ]m ]n ]o ]p ]q ^[ ^\ ^] ^^ ^_ ^ ^a ^b 5-4 Chapter 5. Application Output waveform of uPD6121G A single pulse, modulated with 37.917KHz signal at 3.64MHz Tc Carrier frequency fCAR = 1/Tc = fOSC/96 T1 Duty ratio = T1/Tc = 1/3 - Configuration of Flame 1st flame Lead code 9ms Custom code Custom code Data code Data code 4.5ms C0 C1 C2 C3 C4 C5 C6 C7 C0 C1 C2 C3 C4 C5 C6 C7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D5 D7 - Repeat code 0.56ms 9ms 2.25ms - Bit Description Bit I0I 0.56ms Bit I1I 0.56ms 1.125ms 2.25ms - Flame Interval : Tf The transmitted waveform as long as a key is depressed Tf=108mS Tf=108mS 5-5 Chapter 5. Application Example program - uPD6121G (c) 1/41/2C AAEAAEA 1/2C IAAA AAEAAEA AAE 1/4 AAEAE 1/2C AAEAE | (c) (c) (c) | (c) (c) (c) (c) (c) | (c) (c) (c) (c) (c) (c) (c) (c) (c) (c) (c) | | | | | | | | | | | | (R) | | | | BL | | 1/2A |(c) | | | (R) | (c) (c) | | | | (c)|| (c) | | | (c) { (c) | (c)|(c) K E Y 12 5-6 Chapter 5. Application | || | | | | | | | || | | | | | x x | | | | | | | | | | | | | (c) (c) | | 5-7 Chapter 5. Application | (c)| (c) | | | | x | x | | | | | | | | | | | | | | | | | 5-8 Chapter 5. Application (c) (c) (c) (c) | | | | | x x | | | (c) | | | (c) (R) (R) |(R) | (c)(c) |(c) | | x 5-9 Chapter 5. Application (c) (c) | | | x (c) (c) (c) (c) (c) (c) (c) (c) (c) (c) | (c) * 1/2 A | A A | AE AE | AE | | | | x x 5-10 Chapter 5. Application | 5-11 Chapter 5. Application HMS38112 TEST B/D Example 1. Attach resonator to X1 2. Connect base and collector at Q1 3. Connect PGND and TRGND with jumper at E C B E E Q1 R3 R2 R1 X1 D6 PGND TRGND REMOUT TROUT OSC GND C A K0K1K2K3R0R1R2R3 B K0K1K2K3R0R1R2R3 DS1 DS2 D SW57~64 SW49~56 D6D7D8D9 D6D7D8D9 D4D5D6D8 D5D6D7D9 K0 D0 D1 D2 D3 D4 D5 K1 2 10 18 26 34 42 50 58 K2 3 11 19 27 35 43 51 59 K3 4 12 20 28 36 44 52 60 R0 5 13 21 29 37 45 53 61 R1 6 14 22 30 38 46 54 62 R2 7 15 23 31 39 47 55 63 R3 8 16 24 32 40 48 56 64 1 9 17 25 33 41 49 57 * DS1 is connected to A. If D6 switch is on among DS1 , A becomes D6 port. * DS2 is connected to B. If D7 switch is on among DS2 , B becomes D7 port. * If D6 switch among SW49~SW56 is on at D, the key 49~56 can be used as D6 port. * If D7 switch among SW57~SW64 is on at D, the key 57~64 can be used as D7 port. * note : the position of SW49~56 and SW57~64 in B/D is changed. The reference position is right. * If you want to increase the remote controller valid distance, you try to disconnect R2 resistor and lessen R1 resistor. 5-12 Chapter 5. Application HMS39112 TEST B/D Example 1. Attach resonator to X1 2. Attach 2222A transistor to Q1 3. Connect PGND and D6 with jumper at E 4. Attach about 150. to R3. C B E E Q1 R3 R2 R1 X1 D6 PGND TRGND REMOUT TROUT OSC GND C A K0K1K2K3R0R1R2R3 B K0K1K2K3R0R1R2R3 DS1 DS2 D SW57~64 SW49~56 D6D7D8D9 D6D7D8D9 D4D5D6D8 D5D6D7D9 K0 D0 D1 D2 D3 D4 D5 K1 2 10 18 26 34 42 50 58 K2 3 11 19 27 35 43 51 59 K3 4 12 20 28 36 44 52 60 R0 5 13 21 29 37 45 53 61 R1 6 14 22 30 38 46 54 62 R2 7 15 23 31 39 47 55 63 R3 8 16 24 32 40 48 56 64 1 9 17 25 33 41 49 57 * DS1 is connected to A. If D6 switch is on among DS1 , A becomes D6 port. * DS2 is connected to B. If D7 switch is on among DS2 , B becomes D7 port. * If D6 switch among SW49~SW56 is on at D, the key 49~56 can be used as D6 port. * If D7 switch among SW57~SW64 is on at D, the key 57~64 can be used as D7 port. * note : the position of SW49~56 and SW57~64 in B/D is changed. The reference position is right. * If you want to increase the remote controller valid distance, you try to disconnect R2 resistor and lessen R1 resistor. 5-13 MASK ORDER & VERIFICATION SHEET HMS3 112 -R 1. Customer Information Company Name Name & Signature 2. Device Information Tel: Order Date Fax: ( . RHX ) . DMP @27C256 Package 20 DIP 20 SOP 20 SSOP Mask Data File Name Check Sum 3. Mask Option Inclusion of Pull-up Register Status of D port while Stop mode Port Y/N R2 R3 Release of Stop mode Port K0 K1 K2 K3 R0 R1 R2 R3 Y/N Port D4 D5 D6 a/b 3. a: State of " L" forcibly, b: Remain the state just before stop instruction. You must select "a" option when you use Dport as key application. 4. D6 port is available for HMS38112 but not available for HMS39112 1. Don't use WDTR instruction in subroutine. 2. Use Br $ at start (except 0 page ) , end and unused address in every page. 4. Marking Specification Standard Marking MagnaChip User Marking User LOGO R 5. Delivery Schedule YWW R YWW Date Mask Sample Risk Order . . . . Quantity pcs pcs Confirmation 6. ROM CODE Verification MagnaChip Semiconductor Ltd. write in below Verification Date : Please confirm our verification data. Customer write in below Approval Date : . . Check Sum : @27c256 TEL :82-270-4037 FAX :82-270-4075 Name & MagnaChip Semiconductor Ltd. Signature MCU APPLICATION TEAM I agree with your verification data and confirm you to make mask set. TEL : Company Name : Section Name : Signature : FAX : |
Price & Availability of HMS38112
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |