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PIC16C71X
8-Bit CMOS Microcontrollers with A/D Converter
Devices included in this data sheet:
* * * * PIC16C710 PIC16C71 PIC16C711 PIC16C715
PIC16C71X Peripheral Features:
* Timer0: 8-bit timer/counter with 8-bit prescaler * 8-bit multichannel analog-to-digital converter * Brown-out detection circuitry for Brown-out Reset (BOR) * 13 I/O Pins with Individual Direction Control PIC16C7X Features Program Memory (EPROM) x 14 Data Memory (Bytes) x 8 I/O Pins Timer Modules A/D Channels In-Circuit Serial Programming Brown-out Reset Interrupt Sources 710 512 36 13 1 4 Yes 4 71 1K 36 13 1 4 -- 4 711 715 1K 68 13 1 4 2K 128 13 1 4
PIC16C71X Microcontroller Core Features:
* High-performance RISC CPU * Only 35 single word instructions to learn * All single cycle instructions except for program branches which are two cycle * Operating speed: DC - 20 MHz clock input DC - 200 ns instruction cycle * Up to 2K x 14 words of Program Memory, up to 128 x 8 bytes of Data Memory (RAM) * Interrupt capability * Eight level deep hardware stack * Direct, indirect, and relative addressing modes * Power-on Reset (POR) * Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) * Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation * Programmable code-protection * Power saving SLEEP mode * Selectable oscillator options * Low-power, high-speed CMOS EPROM technology * Fully static design * Wide operating voltage range: 2.5V to 6.0V * High Sink/Source Current 25/25 mA * Commercial, Industrial and Extended temperature ranges * Program Memory Parity Error Checking Circuitry with Parity Error Reset (PER) (PIC16C715) * Low-power consumption: - < 2 mA @ 5V, 4 MHz - 15 A typical @ 3V, 32 kHz - < 1 A typical standby current
Yes Yes Yes Yes Yes Yes 4 4
Pin Diagrams
PDIP, SOIC, Windowed CERDIP
RA2/AN2 RA3/AN3/VREF RA4/T0CKI MCLR/VPP VSS RB0/INT RB1 RB2 RB3 *1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 RA1/AN1 RA0/AN0 OSC1/CLKIN OSC2/CLKOUT VDD RB7 RB6 RB5 RB4
PIC16C710 PIC16C71 PIC16C711 PIC16C715
SSOP
RA2/AN2 RA3/AN3/VREF RA4/T0CKI MCLR/VPP VSS VSS RB0/INT RB1 RB2 RB3 *1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 RA1/AN1 RA0/AN0 OSC1/CLKIN OSC2/CLKOUT VDD VDD RB7 RB6 RB5 RB4
PIC16C710 PIC16C711 PIC16C715
(c) 1997 Microchip Technology Inc.
DS30272A-page 1
PIC16C71X
Table of Contents
1.0 General Description .................................................................................................................................................................... 3 2.0 PIC16C71X Device Varieties...................................................................................................................................................... 5 3.0 Architectural Overview................................................................................................................................................................ 7 4.0 Memory Organization ............................................................................................................................................................... 11 5.0 I/O Ports.................................................................................................................................................................................... 25 6.0 Timer0 Module.......................................................................................................................................................................... 31 7.0 Analog-to-Digital Converter (A/D) Module ................................................................................................................................ 37 8.0 Special Features of the CPU .................................................................................................................................................... 47 9.0 Instruction Set Summary .......................................................................................................................................................... 69 10.0 Development Support ............................................................................................................................................................... 85 11.0 Electrical Characteristics for PIC16C710 and PIC16C711 ....................................................................................................... 89 12.0 DC and AC Characteristics Graphs and Tables for PIC16C710 and PIC16C711.................................................................. 101 13.0 Electrical Characteristics for PIC16C715................................................................................................................................ 111 14.0 DC and AC Characteristics Graphs and Tables for PIC16C715 ............................................................................................ 125 15.0 Electrical Characteristics for PIC16C71.................................................................................................................................. 135 16.0 DC and AC Characteristics Graphs and Tables for PIC16C71 .............................................................................................. 147 17.0 Packaging Information ............................................................................................................................................................ 155 Appendix A: ...................................................................................................................................................................................... 161 Appendix B: Compatibility................................................................................................................................................................. 161 Appendix C: What's New .................................................................................................................................................................. 162 Appendix D: What's Changed .......................................................................................................................................................... 162 Index .................................................................................................................................................................................................. 163 PIC16C71X Product Identification System......................................................................................................................................... 173
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DS30272A-page 2
(c) 1997 Microchip Technology Inc.
PIC16C71X
1.0 GENERAL DESCRIPTION
The PIC16C71X is a family of low-cost, high-performance, CMOS, fully-static, 8-bit microcontrollers with integrated analog-to-digital (A/D) converters, in the PIC16CXX mid-range family. All PIC16/17 microcontrollers employ an advanced RISC architecture. The PIC16CXX microcontroller family has enhanced core features, eight-level deep stack, and multiple internal and external interrupt sources. The separate instruction and data buses of the Harvard architecture allow a 14-bit wide instruction word with the separate 8-bit wide data. The two stage instruction pipeline allows all instructions to execute in a single cycle, except for program branches which require two cycles. A total of 35 instructions (reduced instruction set) are available. Additionally, a large register set gives some of the architectural innovations used to achieve a very high performance. PIC16CXX microcontrollers typically achieve a 2:1 code compression and a 4:1 speed improvement over other 8-bit microcontrollers in their class. The PIC16C710/71 devices have 36 bytes of RAM, the PIC16C711 has 68 bytes of RAM and the PIC16C715 has 128 bytes of RAM. Each device has 13 I/O pins. In addition a timer/counter is available. Also a 4-channel high-speed 8-bit A/D is provided. The 8-bit resolution is ideally suited for applications requiring low-cost analog interface, e.g. thermostat control, pressure sensing, etc. The PIC16C71X family has special features to reduce external components, thus reducing cost, enhancing system reliability and reducing power consumption. There are four oscillator options, of which the single pin RC oscillator provides a low-cost solution, the LP oscillator minimizes power consumption, XT is a standard crystal, and the HS is for High Speed crystals. The SLEEP (power-down) feature provides a power saving mode. The user can wake up the chip from SLEEP through several external and internal interrupts and resets. A highly reliable Watchdog Timer with its own on-chip RC oscillator provides protection against software lockup. A UV erasable CERDIP packaged version is ideal for code development while the cost-effective One-TimeProgrammable (OTP) version is suitable for production in any volume. The PIC16C71X family fits perfectly in applications ranging from security and remote sensors to appliance control and automotive. The EPROM technology makes customization of application programs (transmitter codes, motor speeds, receiver frequencies, etc.) extremely fast and convenient. The small footprint packages make this microcontroller series perfect for all applications with space limitations. Low cost, low power, high performance, ease of use and I/O flexibility make the PIC16C71X very versatile even in areas where no microcontroller use has been considered before (e.g. timer functions, serial communication, capture and compare, PWM functions and coprocessor applications).
1.1
Family and Upward Compatibility
Users familiar with the PIC16C5X microcontroller family will realize that this is an enhanced version of the PIC16C5X architecture. Please refer to Appendix A for a detailed list of enhancements. Code written for the PIC16C5X can be easily ported to the PIC16CXX family of devices (Appendix B).
1.2
Development Support
PIC16C71X devices are supported by the complete line of Microchip Development tools. Please refer to Section 10.0 for more details about Microchip's development tools.
(c) 1997 Microchip Technology Inc.
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PIC16C71X
TABLE 1-1: PIC16C71X FAMILY OF DEVICES
PIC16C710 Clock Maximum Frequency of Operation (MHz) EPROM Program Memory (x14 words) Memory ROM Program Memory (14K words) Data Memory (bytes) Timer Module(s) 20 512 -- 36 TMR0 PIC16C71 20 1K -- 36 TMR0 PIC16C711 20 1K -- 68 TMR0 PIC16C715 20 2K -- 128 TMR0 PIC16C72 20 2K -- 128 TMR0, TMR1, TMR2 1 SPI/I2C -- 5 8 22 2.5-6.0 Yes Yes PIC16CR72(1) 20 -- 2K 128 TMR0, TMR1, TMR2 1 SPI/I2C -- 5 8 22 3.0-5.5 Yes Yes
Capture/Compare/PWM Peripherals Module(s) Serial Port(s) (SPI/I2C, USART) Parallel Slave Port Interrupt Sources I/O Pins Voltage Range (Volts) Features In-Circuit Serial Programming Brown-out Reset Packages
-- -- -- 4 13 2.5-6.0 Yes Yes
-- -- -- 4 4 13 3.0-6.0 Yes --
-- -- -- 4 4 13 2.5-6.0 Yes Yes
-- -- -- 4 4 13 2.5-5.5 Yes Yes
A/D Converter (8-bit) Channels 4
18-pin DIP, 18-pin DIP, 18-pin DIP, 18-pin DIP, 28-pin SDIP, 28-pin SDIP, SOIC; SOIC SOIC; SOIC; SOIC, SSOP SOIC, SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP PIC16C73A PIC16C74A 20 4K 192 TMR0, TMR1, TMR2 2 SPI/I2C, USART Yes 8 12 33 2.5-6.0 Yes Yes 40-pin DIP; 44-pin PLCC, MQFP, TQFP 20 8K 376 TMR0, TMR1, TMR2 2 SPI/I2C, USART -- 5 11 22 2.5-6.0 Yes Yes 28-pin SDIP, SOIC PIC16C76 20 8K 376 TMR0, TMR1, TMR2 2 SPI/I2C, USART Yes 8 12 33 2.5-6.0 Yes Yes 40-pin DIP; 44-pin PLCC, MQFP, TQFP PIC16C77
Clock
Maximum Frequency of Operation (MHz) EPROM Program Memory (x14 words) Data Memory (bytes) Timer Module(s)
20 4K 192 TMR0, TMR1, TMR2 2 SPI/I2C, USART -- 11 22 2.5-6.0 Yes Yes 28-pin SDIP, SOIC
Memory
Capture/Compare/PWM Peripherals Module(s) Serial Port(s) (SPI/I2C, USART) Parallel Slave Port Interrupt Sources I/O Pins Voltage Range (Volts) Features In-Circuit Serial Programming Brown-out Reset Packages
A/D Converter (8-bit) Channels 5
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC16C7XX Family devices use serial programming with clock pin RB6 and data pin RB7. Note 1: Please contact your local Microchip sales office for availability of these devices.
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(c) 1997 Microchip Technology Inc.
PIC16C71X
2.0 PIC16C71X DEVICE VARIETIES
2.3
A variety of frequency ranges and packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in the PIC16C71X Product Identification System section at the end of this data sheet. When placing orders, please use that page of the data sheet to specify the correct part number. For the PIC16C71X family, there are two device "types" as indicated in the device number: 1. C, as in PIC16C71. These devices have EPROM type memory and operate over the standard voltage range. LC, as in PIC16LC71. These devices have EPROM type memory and operate over an extended voltage range.
Quick-Turnaround-Production (QTP) Devices
Microchip offers a QTP Programming Service for factory production orders. This service is made available for users who choose not to program a medium to high quantity of units and whose code patterns have stabilized. The devices are identical to the OTP devices but with all EPROM locations and configuration options already programmed by the factory. Certain code and prototype verification procedures apply before production shipments are available. Please contact your local Microchip Technology sales office for more details.
2.4
2.
Serialized Quick-Turnaround Production (SQTPSM) Devices
2.1
UV Erasable Devices
The UV erasable version, offered in CERDIP package is optimal for prototype development and pilot programs. This version can be erased and reprogrammed to any of the oscillator modes. Microchip's PICSTART(R) Plus and PRO MATE(R) II programmers both support programming of the PIC16C71X.
Microchip offers a unique programming service where a few user-defined locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random, or sequential. Serial programming allows each device to have a unique number which can serve as an entry-code, password, or ID number.
2.2
One-Time-Programmable (OTP) Devices
The availability of OTP devices is especially useful for customers who need the flexibility for frequent code updates and small volume applications. The OTP devices, packaged in plastic packages, permit the user to program them once. In addition to the program memory, the configuration bits must also be programmed.
(c) 1997 Microchip Technology Inc.
DS30272A-page 5
PIC16C71X
NOTES:
DS30272A-page 6
(c) 1997 Microchip Technology Inc.
PIC16C71X
3.0 ARCHITECTURAL OVERVIEW
The high performance of the PIC16CXX family can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC16CXX uses a Harvard architecture, in which, program and data are accessed from separate memories using separate buses. This improves bandwidth over traditional von Neumann architecture in which program and data are fetched from the same memory using the same bus. Separating program and data buses further allows instructions to be sized differently than the 8-bit wide data word. Instruction opcodes are 14-bits wide making it possible to have all single word instructions. A 14-bit wide program memory access bus fetches a 14-bit instruction in a single cycle. A twostage pipeline overlaps fetch and execution of instructions (Example 3-1). Consequently, all instructions (35) execute in a single cycle (200 ns @ 20 MHz) except for program branches. The table below lists program memory (EPROM) and data memory (RAM) for each PIC16C71X device. Device PIC16C710 PIC16C71 PIC16C711 PIC16C715 Program Memory 512 x 14 1K x 14 1K x 14 2K x 14 Data Memory 36 x 8 36 x 8 68 x 8 128 x 8 PIC16CXX devices contain an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between the data in the working register and any register file. The ALU is 8-bits wide and capable of addition, subtraction, shift and logical operations. Unless otherwise mentioned, arithmetic operations are two's complement in nature. In two-operand instructions, typically one operand is the working register (W register). The other operand is a file register or an immediate constant. In single operand instructions, the operand is either the W register or a file register. The W register is an 8-bit working register used for ALU operations. It is not an addressable register. Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC), and Zero (Z) bits in the STATUS register. The C and DC bits operate as a borrow bit and a digit borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.
The PIC16CXX can directly or indirectly address its register files or data memory. All special function registers, including the program counter, are mapped in the data memory. The PIC16CXX has an orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. This symmetrical nature and lack of `special optimal situations' make programming with the PIC16CXX simple yet efficient. In addition, the learning curve is reduced significantly.
(c) 1997 Microchip Technology Inc.
DS30272A-page 7
PIC16C71X
FIGURE 3-1:
Device PIC16C710 PIC16C71 PIC16C711 PIC16C715
PIC16C71X BLOCK DIAGRAM
Program Memory Data Memory (RAM) 512 x 14 1K x 14 1K x 14 2K x 14 36 x 8 36 x 8 68 x 8 128 x 8
13 Program Counter EPROM Program Memory Program Bus 8 Level Stack (13-bit)
Data Bus
8
PORTA RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI PORTB
RAM File Registers RAM Addr (1) 9
14 Instruction reg Direct Addr 7
Addr MUX 8 Indirect Addr RB0/INT RB7:RB1
FSR reg STATUS reg 8 3 Power-up Timer Instruction Decode & Control Timing Generation OSC1/CLKIN OSC2/CLKOUT Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset(2) Timer0 8 W reg ALU
MUX
MCLR
VDD, VSS A/D
Note 1: Higher order bits are from the STATUS register. 2: Brown-out Reset is not available on the PIC16C71.
DS30272A-page 8
(c) 1997 Microchip Technology Inc.
PIC16C71X
TABLE 3-1:
Pin Name OSC1/CLKIN
PIC16C710/71/711/715 PINOUT DESCRIPTION
DIP SSOP Pin# Pin#(4) 16 18 SOIC Pin# 16 I/O/P Type I Buffer Type Description
ST/CMOS(3) Oscillator crystal input/external clock source input. -- Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. 4 4 4 I/P ST Master clear (reset) input or programming voltage input. This pin is MCLR/VPP an active low reset to the device. PORTA is a bi-directional I/O port. RA0/AN0 17 19 17 I/O TTL RA0 can also be analog input0 RA1/AN1 18 20 18 I/O TTL RA1 can also be analog input1 RA2/AN2 1 1 1 I/O TTL RA2 can also be analog input2 RA3/AN3/VREF 2 2 2 I/O TTL RA3 can also be analog input3 or analog reference voltage RA4/T0CKI 3 3 3 I/O ST RA4 can also be the clock input to the Timer0 module. Output is open drain type. PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs. RB0 can also be the external interrupt pin. RB0/INT 6 7 6 I/O TTL/ST(1) RB1 7 8 7 I/O TTL RB2 8 9 8 I/O TTL RB3 9 10 9 I/O TTL RB4 10 11 10 I/O TTL Interrupt on change pin. RB5 11 12 11 I/O TTL Interrupt on change pin. RB6 12 13 12 I/O TTL/ST(2) Interrupt on change pin. Serial programming clock. RB7 13 14 13 I/O TTL/ST(2) Interrupt on change pin. Serial programming data. VSS 5 4, 6 5 P -- Ground reference for logic and I/O pins. VDD 14 15, 16 14 P -- Positive supply for logic and I/O pins. Legend: I = input O = output I/O = input/output P = power -- = Not used TTL = TTL input ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in serial programming mode. 3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise. 4: The PIC16C71 is not available in SSOP package. OSC2/CLKOUT 15 17 15 O
(c) 1997 Microchip Technology Inc.
DS30272A-page 9
PIC16C71X
3.1 Clocking Scheme/Instruction Cycle 3.2 Instruction Flow/Pipelining
The clock input (from OSC1) is internally divided by four to generate four non-overlapping quadrature clocks namely Q1, Q2, Q3 and Q4. Internally, the program counter (PC) is incremented every Q1, the instruction is fetched from the program memory and latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow is shown in Figure 3-2. An "Instruction Cycle" consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g. GOTO) then two cycles are required to complete the instruction (Example 3-1). A fetch cycle begins with the program counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the "Instruction Register" (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write).
FIGURE 3-2:
CLOCK/INSTRUCTION CYCLE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1 Q1 Q2 Q3 Q4 PC OSC2/CLKOUT (RC mode)
PC PC+1 PC+2 Internal phase clock
Fetch INST (PC) Execute INST (PC-1)
Fetch INST (PC+1) Execute INST (PC)
Fetch INST (PC+2) Execute INST (PC+1)
EXAMPLE 3-1:
INSTRUCTION PIPELINE FLOW
Tcy0 Tcy1 Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3 Fetch 4 Flush Fetch SUB_1 Execute SUB_1 Tcy2 Tcy3 Tcy4 Tcy5
1. MOVLW 55h 2. MOVWF PORTB 3. CALL SUB_1
Fetch 1
4. BSF PORTA, BIT3 (Forced NOP) 5. Instruction @ address SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is "flushed" from the pipeline while the new instruction is being fetched and then executed.
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(c) 1997 Microchip Technology Inc.
PIC16C71X
4.0
4.1
MEMORY ORGANIZATION
Program Memory Organization
FIGURE 4-2:
PIC16C71/711 PROGRAM MEMORY MAP AND STACK
PC<12:0>
The PIC16C71X family has a 13-bit program counter capable of addressing an 8K x 14 program memory space. The amount of program memory available to each device is listed below: Device PIC16C710 PIC16C71 PIC16C711 PIC16C715 Program Memory 512 x 14 1K x 14 1K x 14 2K x 14 Address Range 0000h-01FFh 0000h-03FFh 0000h-03FFh 0000h-07FFh
CALL, RETURN RETFIE, RETLW
13
Stack Level 1
Stack Level 8 Reset Vector User Memory Space
0000h
For those devices with less than 8K program memory, accessing a location above the physically implemented address will cause a wraparound. The reset vector is at 0000h and the interrupt vector is at 0004h.
Interrupt Vector On-chip Program Memory
0004h 0005h 03FFh 0400h
FIGURE 4-1:
PIC16C710 PROGRAM MEMORY MAP AND STACK
PC<12:0>
1FFFh
CALL, RETURN RETFIE, RETLW
13
FIGURE 4-3:
PIC16C715 PROGRAM MEMORY MAP AND STACK
PC<12:0>
Stack Level 1
CALL, RETURN RETFIE, RETLW
Stack Level 8 Reset Vector User Memory Space
13
0000h
Stack Level 1
Stack Level 8 Interrupt Vector On-chip Program Memory 0004h 0005h 01FFh 0200h Interrupt Vector 1FFFh On-chip Program Memory 07FFh 0800h 0004h 0005h Reset Vector
0000h
1FFFh
(c) 1997 Microchip Technology Inc.
DS30272A-page 11
PIC16C71X
4.2 Data Memory Organization FIGURE 4-4:
The data memory is partitioned into two Banks which contain the General Purpose Registers and the Special Function Registers. Bit RP0 is the bank select bit. RP0 (STATUS<5>) = 1 Bank 1 RP0 (STATUS<5>) = 0 Bank 0 Each Bank extends up to 7Fh (128 bytes). The lower locations of each Bank are reserved for the Special Function Registers. Above the Special Function Registers are General Purpose Registers implemented as static RAM. Both Bank 0 and Bank 1 contain special function registers. Some "high use" special function registers from Bank 0 are mirrored in Bank 1 for code reduction and quicker access. 4.2.1 GENERAL PURPOSE REGISTER FILE
PIC16C710/71 REGISTER FILE MAP
File Address
File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch INDF(1) TMR0 PCL STATUS FSR PORTA PORTB ADCON0 ADRES PCLATH INTCON INDF(1) OPTION PCL STATUS FSR TRISA TRISB PCON(2) ADCON1 ADRES PCLATH INTCON General Purpose Register Mapped in Bank 0(3)
The register file can be accessed either directly, or indirectly through the File Select Register FSR (Section 4.5).
80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch
General Purpose Register 2Fh 30h
AFh B0h
7Fh Bank 0 Bank 1
FFh
Unimplemented data memory locations, read as '0'. Note 1: Not a physical register. 2: The PCON register is not implemented on the PIC16C71. 3: These locations are unimplemented in Bank 1. Any access to these locations will access the corresponding Bank 0 register.
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(c) 1997 Microchip Technology Inc.
PIC16C71X
FIGURE 4-5: PIC16C711 REGISTER FILE MAP
File Address INDF(1) TMR0 PCL STATUS FSR PORTA PORTB ADCON0 ADRES PCLATH INTCON INDF(1) OPTION PCL STATUS FSR TRISA TRISB PCON ADCON1 ADRES PCLATH INTCON General Purpose Register Mapped in Bank 0(2) CFh D0h 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch
FIGURE 4-6:
File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h
PIC16C715 REGISTER FILE MAP
File Address INDF(1) TMR0 PCL STATUS FSR PORTA PORTB INDF(1) OPTION PCL STATUS FSR TRISA TRISB 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h
File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch
PCLATH INTCON PIR1
PCLATH INTCON PIE1 PCON
General Purpose Register 4Fh 50h
7Fh Bank 0 Bank 1
FFh
Unimplemented data memory locations, read as '0'. Note 1: Not a physical register. 2: These locations are unimplemented in Bank 1. Any access to these locations will access the corresponding Bank 0 register.
ADRES ADCON0 General Purpose Register
ADCON1 General Purpose Register
BFh C0h
7Fh
FFh Bank 0 Bank 1
Unimplemented data memory locations, read as '0'. Note 1: Not a physical register.
(c) 1997 Microchip Technology Inc.
DS30272A-page 13
PIC16C71X
4.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers are registers used by the CPU and Peripheral Modules for controlling the desired operation of the device. These registers are implemented as static RAM. The special function registers can be classified into two sets (core and peripheral). Those registers associated with the "core" functions are described in this section, and those related to the operation of the peripheral features are described in the section of that peripheral feature.
TABLE 4-1:
Address Name
PIC16C710/71/711 SPECIAL FUNCTION REGISTER SUMMARY
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets (1)
Bank 0 00h(3) 01h 02h(3) 03h(3) 04h(3) 05h 06h 07h 08h 09h(3) 0Ah(2,3) 0Bh(3) Bank 1 80h(3) 81h 82h
(3) (3) (3)
INDF TMR0 PCL STATUS FSR PORTA PORTB -- ADCON0 ADRES PCLATH INTCON
Addressing this location uses contents of FSR to address data memory (not a physical register) Timer0 module's register Program Counter's (PC) Least Significant Byte IRP(5) RP1(5) RP0 TO PD Z DC C
0000 0000 0000 0000 xxxx xxxx uuuu uuuu 0000 0000 0000 0000 0001 1xxx 000q quuu xxxx xxxx uuuu uuuu ---x 0000 ---u 0000 xxxx xxxx uuuu uuuu -- --
Indirect data memory address pointer -- -- -- PORTA Data Latch when written: PORTA pins when read
PORTB Data Latch when written: PORTB pins when read Unimplemented ADCS1 ADCS0 (6) CHS1 CHS0 GO/DONE ADIF ADON
00-0 0000 00-0 0000 xxxx xxxx uuuu uuuu
A/D Result Register -- GIE -- ADIE -- T0IE Write Buffer for the upper 5 bits of the Program Counter INTE RBIE T0IF INTF RBIF
---0 0000 ---0 0000 0000 000x 0000 000u
INDF OPTION PCL STATUS FSR TRISA TRISB PCON ADCON1 ADRES PCLATH INTCON
Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000
Program Counter's (PC) Least Significant Byte IRP(5) RP1
(5)
83h 84h
RP0
TO
PD
Z
DC
C
0001 1xxx 000q quuu xxxx xxxx uuuu uuuu ---1 1111 ---1 1111 1111 1111 1111 1111
Indirect data memory address pointer -- -- -- PORTA Data Direction Register
85h 86h 87h(4) 88h 89h(3) 8Ah 8Bh
(2,3) (3)
PORTB Data Direction Control Register -- -- -- -- -- -- -- -- -- -- -- -- POR PCFG1 BOR PCFG0
---- --qq ---- --uu ---- --00 ---- --00 xxxx xxxx uuuu uuuu
A/D Result Register -- GIE -- ADIE -- T0IE Write Buffer for the upper 5 bits of the Program Counter INTE RBIE T0IF INTF RBIF
---0 0000 ---0 0000 0000 000x 0000 000u
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'. Shaded locations are unimplemented, read as `0'. Note 1: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset. 2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. 3: These registers can be addressed from either bank. 4: The PCON register is not physically implemented in the PIC16C71, read as '0'. 5: The IRP and RP1 bits are reserved on the PIC16C710/71/711, always maintain these bits clear. 6: Bit5 of ADCON0 is a General Purpose R/W bit for the PIC16C710/711 only. For the PIC16C71, this bit is unimplemented, read as '0'.
DS30272A-page 14
(c) 1997 Microchip Technology Inc.
PIC16C71X
TABLE 4-2:
Address Name
PIC16C715 SPECIAL FUNCTION REGISTER SUMMARY
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR, PER Value on all other resets (3)
Bank 0 00h(1) 01h 02h(1) 03h(1) 04h(1) 05h 06h 07h 08h 09h 0Ah
(1,2)
INDF TMR0 PCL STATUS FSR PORTA PORTB -- -- -- PCLATH INTCON PIR1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ADRES ADCON0
Addressing this location uses contents of FSR to address data memory (not a physical register) Timer0 module's register Program Counter's (PC) Least Significant Byte IRP(4) RP1(4) RP0 TO PD Z DC C
0000 0000 0000 0000 xxxx xxxx uuuu uuuu 0000 0000 0000 0000 0001 1xxx 000q quuu xxxx xxxx uuuu uuuu ---x 0000 ---u 0000 xxxx xxxx uuuu uuuu -- -- -- -- -- --
Indirect data memory address pointer -- -- -- PORTA Data Latch when written: PORTA pins when read
PORTB Data Latch when written: PORTB pins when read Unimplemented Unimplemented Unimplemented -- GIE -- -- PEIE ADIF -- T0IE -- Write Buffer for the upper 5 bits of the Program Counter INTE -- RBIE -- T0IF -- INTF -- RBIF --
---0 0000 ---0 0000 0000 000x 0000 000u -0-- ---- -0-- ----- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
0Bh(1) 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh
Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented A/D Result Register ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE -- ADON
xxxx xxxx uuuu uuuu 0000 00-0 0000 00-0
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'. Shaded locations are unimplemented, read as `0'. Note 1: These registers can be addressed from either bank. 2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. 3: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset. 4: The IRP and RP1 bits are reserved on the PIC16C715, always maintain these bits clear.
(c) 1997 Microchip Technology Inc.
DS30272A-page 15
PIC16C71X
TABLE 4-2:
Address Name
PIC16C715 SPECIAL FUNCTION REGISTER SUMMARY (Cont.'d)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR, PER Value on all other resets (3)
Bank 1 80h(1) 81h 82h(1) 83h
(1)
INDF OPTION PCL STATUS FSR TRISA TRISB -- -- -- PCLATH INTCON PIE1 -- PCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ADCON1
Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000
Program Counter's (PC) Least Significant Byte IRP
(4)
RP1
(4)
RP0
TO
PD
Z
DC
C
0001 1xxx 000q quuu xxxx xxxx uuuu uuuu --11 1111 --11 1111 1111 1111 1111 1111 -- -- -- -- -- --
84h(1) 85h 86h 87h 88h 89h 8Ah(1,2) 8Bh(1) 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh
Indirect data memory address pointer -- -- PORTA Data Direction Register
PORTB Data Direction Register Unimplemented Unimplemented Unimplemented -- GIE -- -- PEIE ADIE -- T0IE -- Write Buffer for the upper 5 bits of the PC INTE -- RBIE -- T0IF -- INTF -- RBIF --
---0 0000 ---0 0000 0000 000x 0000 000u -0-- ---- -0-- ----- --
Unimplemented MPEEN Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented -- -- -- -- -- -- PCFG1 PCFG0 -- -- -- -- PER POR BOR
u--- -1qq u--- -1uu -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ---- --00 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ---- --00
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'. Shaded locations are unimplemented, read as `0'. Note 1: These registers can be addressed from either bank. 2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. 3: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset. 4: The IRP and RP1 bits are reserved on the PIC16C715, always maintain these bits clear.
DS30272A-page 16
(c) 1997 Microchip Technology Inc.
PIC16C71X
4.2.2.1 STATUS REGISTER
Applicable Devices
710 71 711 715
The STATUS register, shown in Figure 4-7, contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS will clear the upper-three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged).
It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register because these instructions do not affect the Z, C or DC bits from the STATUS register. For other instructions, not affecting any status bits, see the "Instruction Set Summary." Note 1: For those devices that do not use bits IRP and RP1 (STATUS<7:6>), maintain these bits clear to ensure upward compatibility with future products. Note 2: The C and DC bits operate as a borrow and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.
FIGURE 4-7:
R/W-0 IRP bit7
STATUS REGISTER (ADDRESS 03h, 83h)
R/W-0 RP0 R-1 TO R-1 PD R/W-x Z R/W-x DC R/W-x C bit0
R/W-0 RP1
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7:
IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h - 1FFh) 0 = Bank 0, 1 (00h - FFh)
bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing) 11 = Bank 3 (180h - 1FFh) 10 = Bank 2 (100h - 17Fh) 01 = Bank 1 (80h - FFh) 00 = Bank 0 (00h - 7Fh) Each bank is 128 bytes bit 4: TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(for borrow the polarity is reversed) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) 1 = A carry-out from the most significant bit of the result occurred 0 = No carry-out from the most significant bit of the result occurred Note: For borrow the polarity is reversed. A subtraction is executed by adding the two's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register.
bit 3:
bit 2:
bit 1:
bit 0:
(c) 1997 Microchip Technology Inc.
DS30272A-page 17
PIC16C71X
4.2.2.2 OPTION REGISTER Note:
Applicable Devices
710 71 711 715
The OPTION register is a readable and writable register which contains various control bits to configure the TMR0/WDT prescaler, the External INT Interrupt, TMR0, and the weak pull-ups on PORTB.
To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the Watchdog Timer by setting bit PSA (OPTION<3>).
FIGURE 4-8:
R/W-1 RBPU bit7
OPTION REGISTER (ADDRESS 81h, 181h)
R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 PS2 R/W-1 PS1 R/W-1 PS0 bit0
R/W-1 INTEDG
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7:
RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin T0CS: TMR0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module
bit 6:
bit 5:
bit 4:
bit 3:
bit 2-0: PS2:PS0: Prescaler Rate Select bits
Bit Value 000 001 010 011 100 101 110 111 TMR0 Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 WDT Rate 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
DS30272A-page 18
(c) 1997 Microchip Technology Inc.
PIC16C71X
4.2.2.3 INTCON REGISTER Note:
Applicable Devices
710 71 711 715
The INTCON Register is a readable and writable register which contains various enable and flag bits for the TMR0 register overflow, RB Port change and External RB0/INT pin interrupts.
Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>).
FIGURE 4-9:
R/W-0 GIE bit7
INTCON REGISTER (ADDRESS 0Bh, 8Bh)
R/W-0 T0IE R/W-0 INTE R/W-0 RBIE R/W-0 T0IF R/W-0 INTF R/W-x RBIF bit0
R/W-0 ADIE
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7:
GIE:(1) Global Interrupt Enable bit 1 = Enables all un-masked interrupts 0 = Disables all interrupts ADIE: A/D Converter Interrupt Enable bit 1 = Enables A/D interrupt 0 = Disables A/D interrupt T0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt INTE: RB0/INT External Interrupt Enable bit 1 = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt T0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow INTF: RB0/INT External Interrupt Flag bit 1 = The RB0/INT external interrupt occurred (must be cleared in software) 0 = The RB0/INT external interrupt did not occur RBIF: RB Port Change Interrupt Flag bit 1 = At least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
Note 1: For the PIC16C71, if an interrupt occurs while the GIE bit is being cleared, the GIE bit may be unintentionally re-enabled by the RETFIE instruction in the user's Interrupt Service Routine. Refer to Section 8.5 for a detailed description.
Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
(c) 1997 Microchip Technology Inc.
DS30272A-page 19
PIC16C71X
4.2.2.4 PIE1 REGISTER Note:
Applicable Devices
710 71 711 715
Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt.
This register contains the individual enable bits for the Peripheral interrupts.
FIGURE 4-10: PIE1 REGISTER (ADDRESS 8Ch)
U-0 -- bit7 R/W-0 ADIE U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit0
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7: bit 6:
Unimplemented: Read as '0' ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt
bit 5-0: Unimplemented: Read as '0'
DS30272A-page 20
(c) 1997 Microchip Technology Inc.
PIC16C71X
4.2.2.5 PIR1 REGISTER Note:
Applicable Devices
710 71 711 715
This register contains the individual flag bits for the Peripheral interrupts.
Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
FIGURE 4-11: PIR1 REGISTER (ADDRESS 0Ch)
U-0 -- bit7 R/W-0 ADIF U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit0
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7: bit 6:
Unimplemented: Read as '0' ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed 0 = The A/D conversion is not complete
bit 5-0: Unimplemented: Read as '0'
(c) 1997 Microchip Technology Inc.
DS30272A-page 21
PIC16C71X
4.2.2.6 PCON REGISTER Note:
Applicable Devices
710 71 711 715
The Power Control (PCON) register contains a flag bit to allow differentiation between a Power-on Reset (POR) to an external MCLR Reset or WDT Reset. Those devices with brown-out detection circuitry contain an additional bit to differentiate a Brown-out Reset (BOR) condition from a Power-on Reset condition. For the PIC16C715 the PCON register also contains status bits MPEEN and PER. MPEEN reflects the value of the MPEEN bit in the configuration word. PER indicates a parity error reset has occurred.
BOR is unknown on Power-on Reset. It must then be set by the user and checked on subsequent resets to see if BOR is clear, indicating a brown-out has occurred. The BOR status bit is a don't care and is not necessarily predictable if the brown-out circuit is disabled (by clearing the BODEN bit in the Configuration word).
FIGURE 4-12: PCON REGISTER (ADDRESS 8Eh), PIC16C710/711
U-0 -- bit7 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 POR R/W-q BOR bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7-2: Unimplemented: Read as '0' bit 1: POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
bit 0:
FIGURE 4-13: PCON REGISTER (ADDRESS 8Eh), PIC16C715
R-U MPEEN bit7 U-0 -- U-0 -- U-0 -- U-0 -- R/W-1 PER R/W-0 POR R/W-q BOR(1) bit0
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7:
MPEEN: Memory Parity Error Circuitry Status bit Reflects the value of configuration word bit, MPEEN PER: Memory Parity Error Reset Status bit 1 = No Error occurred 0 = Program Memory Fetch Parity Error occurred (must be set in software after a Parity Error Reset) POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
bit 6-3: Unimplemented: Read as '0' bit 2:
bit 1:
bit 0:
DS30272A-page 22
(c) 1997 Microchip Technology Inc.
PIC16C71X
4.3 PCL and PCLATH
4.3.2 STACK The program counter (PC) is 13-bits wide. The low byte comes from the PCL register, which is a readable and writable register. The upper bits (PC<12:8>) are not readable, but are indirectly writable through the PCLATH register. On any reset, the upper bits of the PC will be cleared. Figure 4-14 shows the two situations for the loading of the PC. The upper example in the figure shows how the PC is loaded on a write to PCL (PCLATH<4:0> PCH). The lower example in the figure shows how the PC is loaded during a CALL or GOTO instruction (PCLATH<4:3> PCH). The PIC16CXX family has an 8 level deep x 13-bit wide hardware stack. The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation. The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on). Note 1: There are no status bits to indicate stack overflow or stack underflow conditions.
0 Instruction with PCL as Destination ALU
FIGURE 4-14: LOADING OF PC IN DIFFERENT SITUATIONS
PCH 12 PC 5 PCLATH<4:0> 8 8 7 PCL
PCLATH PCH 12 PC 2 PCLATH<4:3> 11 Opcode <10:0> PCLATH 11 10 8 7 PCL 0 GOTO, CALL
Note 2: There are no instructions/mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW, and RETFIE instructions, or the vectoring to an interrupt address.
4.4
Program Memory Paging
The PIC16C71X devices ignore both paging bits (PCLATH<4:3>, which are used to access program memory when more than one page is available. The use of PCLATH<4:3> as general purpose read/write bits for the PIC16C71X is not recommended since this may affect upward compatibility with future products.
4.3.1
COMPUTED GOTO
A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When doing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256 byte block). Refer to the application note "Implementing a Table Read" (AN556).
(c) 1997 Microchip Technology Inc.
DS30272A-page 23
PIC16C71X
Example 4-1 shows the calling of a subroutine in page 1 of the program memory. This example assumes that PCLATH is saved and restored by the interrupt service routine (if interrupts are used).
4.5
Indirect Addressing, INDF and FSR Registers
The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses the register pointed to by the File Select Register, FSR. Reading the INDF register itself indirectly (FSR = '0') will read 00h. Writing to the INDF register indirectly results in a no-operation (although status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure 4-15. However, IRP is not used in the PIC16C71X devices. A simple program to clear RAM locations 20h-2Fh using indirect addressing is shown in Example 4-2.
EXAMPLE 4-1:
ORG 0x500 BSF PCLATH,3 BCF PCLATH,4 CALL SUB1_P1 : : : ORG 0x900 SUB1_P1: : : RETURN
CALL OF A SUBROUTINE IN PAGE 1 FROM PAGE 0
;Select page 1 (800h-FFFh) ;Only on >4K devices ;Call subroutine in ;page 1 (800h-FFFh)
;called subroutine ;page 1 (800h-FFFh) ;return to Call subroutine ;in page 0 (000h-7FFh)
EXAMPLE 4-2:
movlw movwf clrf incf btfss goto :
INDIRECT ADDRESSING
0x20 FSR INDF FSR,F FSR,4 NEXT ;initialize pointer ;to RAM ;clear INDF register ;inc pointer ;all done? ;no clear next ;yes continue
NEXT
CONTINUE
FIGURE 4-15:
DIRECT/INDIRECT ADDRESSING
Direct Addressing Indirect Addressing
0 IRP
(1)
RP1:RP0
6
from opcode
7
FSR register
0
bank select
location select 00 00h 01 80h 10 100h 11 180h
bank select
location select
Data Memory
Not Used
7Fh
FFh
17Fh
1FFh
Bank 0 For register file map detail see Figure 4-4. Note 1:
Bank 1
Bank 2
Bank 3
The RP1 and IRP bits are reserved, always maintain these bits clear.
DS30272A-page 24
(c) 1997 Microchip Technology Inc.
PIC16C71X
5.0 I/O PORTS
710 71 711 715
Data bus WR Port D
FIGURE 5-1:
Applicable Devices
BLOCK DIAGRAM OF RA3:RA0 PINS
Q VDD
Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin.
CK
Q
5.1
PORTA and TRISA Registers
Data Latch D WR TRIS Q
P
PORTA is a 5-bit latch. The RA4/T0CKI pin is a Schmitt Trigger input and an open drain output. All other RA port pins have TTL input levels and full CMOS output drivers. All pins have data direction bits (TRIS registers) which can configure these pins as output or input. Setting a TRISA register bit puts the corresponding output driver in a hi-impedance mode. Clearing a bit in the TRISA register puts the contents of the output latch on the selected pin(s). Reading the PORTA register reads the status of the pins whereas writing to it will write to the port latch. All write operations are read-modify-write operations. Therefore a write to a port implies that the port pins are read, this value is modified, and then written to the port data latch. Pin RA4 is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin. Other PORTA pins are multiplexed with analog inputs and analog VREF input. The operation of each pin is selected by clearing/setting the control bits in the ADCON1 register (A/D Control Register1). Note: On a Power-on Reset, these pins are configured as analog inputs and read as '0'.
N
I/O pin(1)
CK
Q
TRIS Latch
VSS Analog input mode
RD TRIS Q D
TTL input buffer
EN RD PORT
To A/D Converter Note 1: I/O pins have protection diodes to VDD and VSS.
FIGURE 5-2:
Data bus WR PORT
BLOCK DIAGRAM OF RA4/ T0CKI PIN
D Q Q
The TRISA register controls the direction of the RA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs.
CK
N Data Latch
D Q Q
I/O pin(1)
EXAMPLE 5-1:
BCF CLRF
INITIALIZING PORTA
; ; ; ; ; ; ; ; ; ; ; ; Initialize PORTA by clearing output data latches Select Bank 1 Value used to initialize data direction Set RA<3:0> as inputs RA<4> as outputs TRISA<7:5> are always read as '0'. WR TRIS
VSS Schmitt Trigger input buffer
STATUS, RP0 PORTA
CK
TRIS Latch
BSF MOVLW
STATUS, RP0 0xCF
RD TRIS
Q D EN EN
MOVWF
TRISA
RD PORT TMR0 clock input Note 1: I/O pin has protection diodes to VSS only.
(c) 1997 Microchip Technology Inc.
DS30272A-page 25
PIC16C71X
TABLE 5-1:
Name RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI
PORTA FUNCTIONS
Bit# bit0 bit1 bit2 bit3 bit4 Buffer TTL TTL TTL TTL ST Function
Input/output or analog input Input/output or analog input Input/output or analog input Input/output or analog input/VREF Input/output or external clock input for Timer0 Output is open drain type Legend: TTL = TTL input, ST = Schmitt Trigger input
TABLE 5-2:
Address Name 05h 85h 9Fh PORTA TRISA
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Bit 7 Bit 6 -- -- -- -- -- -- Bit 5 -- -- -- Bit 4 RA4 Bit 3 RA3 Bit 2 RA2 Bit 1 RA1 Bit 0 RA0 Value on: POR, BOR ---x 0000 ---1 1111 PCFG1 PCFG0 ---- --00 Value on all other resets ---u 0000 ---1 1111 ---- --00
PORTA Data Direction Register -- -- --
ADCON1
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA.
DS30272A-page 26
(c) 1997 Microchip Technology Inc.
PIC16C71X
5.2 PORTB and TRISB Registers
PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is TRISB. Setting a bit in the TRISB register puts the corresponding output driver in a hi-impedance input mode. Clearing a bit in the TRISB register puts the contents of the output latch on the selected pin(s). Four of PORTB's pins, RB7:RB4, have an interrupt on change feature. Only pins configured as inputs can cause this interrupt to occur (i.e. any RB7:RB4 pin configured as an output is excluded from the interrupt on change comparison). The input pins (of RB7:RB4) are compared with the old value latched on the last read of PORTB. The "mismatch" outputs of RB7:RB4 are OR'ed together to generate the RB Port Change Interrupt with flag bit RBIF (INTCON<0>). This interrupt can wake the device from SLEEP. The user, in the interrupt service routine, can clear the interrupt in the following manner: a) b) Any read or write of PORTB. This will end the mismatch condition. Clear flag bit RBIF.
EXAMPLE 5-2:
BCF CLRF
INITIALIZING PORTB
; ; ; ; ; ; ; ; ; ; ; Initialize PORTB by clearing output data latches Select Bank 1 Value used to initialize data direction Set RB<3:0> as inputs RB<5:4> as outputs RB<7:6> as inputs
STATUS, RP0 PORTB
BSF MOVLW
STATUS, RP0 0xCF
MOVWF
TRISB
A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch condition, and allow flag bit RBIF to be cleared. This interrupt on mismatch feature, together with software configurable pull-ups on these four pins allow easy interface to a keypad and make it possible for wake-up on key-depression. Refer to the Embedded Control Handbook, "Implementing Wake-Up on Key Stroke" (AN552). Note: For the PIC16C71 if a change on the I/O pin should occur when the read operation is being executed (start of the Q2 cycle), then interrupt flag bit RBIF may not get set.
Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU (OPTION<7>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset.
FIGURE 5-3:
RBPU(2)
BLOCK DIAGRAM OF RB3:RB0 PINS
VDD weak P pull-up Data Latch D Q CK TRIS Latch D Q I/O pin(1)
Data bus WR Port
The interrupt on change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt on change feature. Polling of PORTB is not recommended while using the interrupt on change feature.
WR TRIS
CK
TTL Input Buffer
RD TRIS Q RD Port D EN
RB0/INT Schmitt Trigger Buffer Note 1: I/O pins have diode protection to VDD and VSS. 2: TRISB = '1' enables weak pull-up if RBPU = '0' (OPTION<7>). RD Port
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FIGURE 5-4: BLOCK DIAGRAM OF RB7:RB4 PINS (PIC16C71)
VDD RBPU(2) Data Latch D Q CK TRIS Latch D Q WR TRIS CK TTL Input Buffer WR TRIS ST Buffer RD TRIS Q RD Port Set RBIF From other RB7:RB4 pins I/O pin(1) weak P pull-up RBPU(2) Data Latch D Q CK TRIS Latch D Q CK TTL Input Buffer I/O pin(1)
FIGURE 5-5:
BLOCK DIAGRAM OF RB7:RB4 PINS (PIC16C710/711/715)
VDD weak P pull-up
Data bus WR Port
Data bus WR Port
ST Buffer
RD TRIS Q RD Port Set RBIF
Latch D EN
Latch D EN Q1
Q
D EN RD Port
From other RB7:RB4 pins
Q
D RD Port EN Q3
RB7:RB6 in serial programming mode Note 1: I/O pins have diode protection to VDD and VSS. 2: TRISB = '1' enables weak pull-up if RBPU = '0' (OPTION<7>).
RB7:RB6 in serial programming mode Note 1: I/O pins have diode protection to VDD and VSS. 2: TRISB = '1' enables weak pull-up if RBPU = '0' (OPTION<7>).
TABLE 5-3:
Name RB0/INT
PORTB FUNCTIONS
Bit# bit0 Buffer TTL/ST(1) Function
Input/output pin or external interrupt input. Internal software programmable weak pull-up. RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up. RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up. RB3 bit3 TTL Input/output pin. Internal software programmable weak pull-up. RB4 bit4 TTL Input/output pin (with interrupt on change). Internal software programmable weak pull-up. RB5 bit5 TTL Input/output pin (with interrupt on change). Internal software programmable weak pull-up. RB6 bit6 TTL/ST(2) Input/output pin (with interrupt on change). Internal software programmable weak pull-up. Serial programming clock. RB7 bit7 TTL/ST(2) Input/output pin (with interrupt on change). Internal software programmable weak pull-up. Serial programming data. Legend: TTL = TTL input, ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in serial programming mode.
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TABLE 5-4:
Address 06h, 106h 86h, 186h 81h, 181h
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Bit 7 RB7 Bit 6 RB6 Bit 5 RB5 Bit 4 RB4 Bit 3 RB3 Bit 2 RB2 Bit 1 RB1 Bit 0 RB0 Value on: POR, BOR xxxx xxxx 1111 1111 PSA PS2 PS1 PS0 1111 1111 Value on all other resets uuuu uuuu 1111 1111 1111 1111
Name PORTB TRISB OPTION
PORTB Data Direction Register RBPU INTEDG T0CS T0SE
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
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5.3
5.3.1
I/O Programming Considerations
BI-DIRECTIONAL I/O PORTS
EXAMPLE 5-3:
READ-MODIFY-WRITE INSTRUCTIONS ON AN I/O PORT
Any instruction which writes, operates internally as a read followed by a write operation. The BCF and BSF instructions, for example, read the register into the CPU, execute the bit operation and write the result back to the register. Caution must be used when these instructions are applied to a port with both inputs and outputs defined. For example, a BSF operation on bit5 of PORTB will cause all eight bits of PORTB to be read into the CPU. Then the BSF operation takes place on bit5 and PORTB is written to the output latches. If another bit of PORTB is used as a bi-directional I/O pin (e.g., bit0) and it is defined as an input at this time, the input signal present on the pin itself would be read into the CPU and rewritten to the data latch of this particular pin, overwriting the previous content. As long as the pin stays in the input mode, no problem occurs. However, if bit0 is switched to an output, the content of the data latch may now be unknown. Reading the port register, reads the values of the port pins. Writing to the port register writes the value to the port latch. When using read-modify-write instructions (ex. BCF, BSF, etc.) on a port, the value of the port pins is read, the desired operation is done to this value, and this value is then written to the port latch. Example 5-3 shows the effect of two sequential readmodify-write instructions on an I/O port.
;Initial PORT settings: PORTB<7:4> Inputs ; PORTB<3:0> Outputs ;PORTB<7:6> have external pull-ups and are ;not connected to other circuitry ; ; PORT latch PORT pins ; ---------- --------BCF PORTB, 7 ; 01pp pppp 11pp pppp BCF PORTB, 6 ; 10pp pppp 11pp pppp BSF STATUS, RP0 ; BCF TRISB, 7 ; 10pp pppp 11pp pppp BCF TRISB, 6 ; 10pp pppp 10pp pppp ; ;Note that the user may have expected the ;pin values to be 00pp ppp. The 2nd BCF ;caused RB7 to be latched as the pin value ;(high).
A pin actively outputting a Low or High should not be driven from external devices at the same time in order to change the level on this pin ("wired-or", "wired-and"). The resulting high output currents may damage the chip. 5.3.2 SUCCESSIVE OPERATIONS ON I/O PORTS
The actual write to an I/O port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (Figure 5-6). Therefore, care must be exercised if a write followed by a read operation is carried out on the same I/O port. The sequence of instructions should be such to allow the pin voltage to stabilize (load dependent) before the next instruction which causes that file to be read into the CPU is executed. Otherwise, the previous state of that pin may be read into the CPU rather than the new state. When in doubt, it is better to separate these instructions with a NOP or another instruction not accessing this I/O port.
FIGURE 5-6:
SUCCESSIVE I/O OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Note: This example shows a write to PORTB followed by a read from PORTB. Note that: data setup time = (0.25TCY - TPD)
PC Instruction fetched
PC
PC + 1
PC + 2 NOP
PC + 3 NOP
MOVWF PORTB MOVF PORTB,W write to PORTB
RB7:RB0 Port pin sampled here Instruction executed MOVWF PORTB write to PORTB TPD NOP MOVF PORTB,W
where TCY = instruction cycle TPD = propagation delay Therefore, at higher clock frequencies, a write followed by a read may be problematic.
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6.0 TIMER0 MODULE
710 71 711 715 Applicable Devices
bit T0SE selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 6.2. The prescaler is mutually exclusively shared between the Timer0 module and the Watchdog Timer. The prescaler assignment is controlled in software by control bit PSA (OPTION<3>). Clearing bit PSA will assign the prescaler to the Timer0 module. The prescaler is not readable or writable. When the prescaler is assigned to the Timer0 module, prescale values of 1:2, 1:4, ..., 1:256 are selectable. Section 6.3 details the operation of the prescaler.
The Timer0 module timer/counter has the following features: * * * * * * 8-bit timer/counter Readable and writable 8-bit software programmable prescaler Internal or external clock select Interrupt on overflow from FFh to 00h Edge select for external clock
Figure 6-1 is a simplified block diagram of the Timer0 module. Timer mode is selected by clearing bit T0CS (OPTION<5>). In timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0 register is written, the increment is inhibited for the following two instruction cycles (Figure 6-2 and Figure 6-3). The user can work around this by writing an adjusted value to the TMR0 register. Counter mode is selected by setting bit T0CS (OPTION<5>). In counter mode, Timer0 will increment either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit T0SE (OPTION<4>). Clearing
6.1
Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h. This overflow sets bit T0IF (INTCON<2>). The interrupt can be masked by clearing bit T0IE (INTCON<5>). Bit T0IF must be cleared in software by the Timer0 module interrupt service routine before re-enabling this interrupt. The TMR0 interrupt cannot awaken the processor from SLEEP since the timer is shut off during SLEEP. See Figure 6-4 for Timer0 interrupt timing.
FIGURE 6-1:
TIMER0 BLOCK DIAGRAM
Data bus FOSC/4 0 1 1 Programmable Prescaler PSout Sync with Internal clocks (2 cycle delay) Set interrupt flag bit T0IF on overflow TMR0 PSout 8
RA4/T0CKI pin T0SE
0
3 PS2, PS1, PS0 T0CS PSA
Note 1: T0CS, T0SE, PSA, PS2:PS0 (OPTION<5:0>). 2: The prescaler is shared with Watchdog Timer (refer to Figure 6-6 for detailed block diagram).
FIGURE 6-2:
PC (Program Counter) Instruction Fetch
TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC-1 PC MOVWF TMR0 PC+1 MOVF TMR0,W PC+2 MOVF TMR0,W PC+3 MOVF TMR0,W PC+4 MOVF TMR0,W PC+5 MOVF TMR0,W PC+6
TMR0 Instruction Executed
T0
T0+1
T0+2
NT0
NT0
NT0
NT0+1
NT0+2
T0
Write TMR0 executed
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0 + 1
Read TMR0 reads NT0 + 2
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FIGURE 6-3:
PC (Program Counter) Instruction Fetch TMR0 T0
TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC-1 PC MOVWF TMR0 PC+1 MOVF TMR0,W PC+2 MOVF TMR0,W PC+3 MOVF TMR0,W PC+4 MOVF TMR0,W PC+5 MOVF TMR0,W PC+6
T0+1
NT0
NT0+1
PC+6
Instruction Execute
Write TMR0 executed
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0 + 1
FIGURE 6-4:
TIMER0 INTERRUPT TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1 CLKOUT(3) Timer0 T0IF bit (INTCON<2>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC Instruction fetched Instruction executed PC Inst (PC) Inst (PC-1) PC +1 Inst (PC+1) Dummy cycle PC +1 0004h Inst (0004h) Dummy cycle 0005h Inst (0005h) Inst (0004h) FEh 1 FFh 1 00h 01h 02h
Inst (PC)
Note 1: Interrupt flag bit T0IF is sampled here (every Q1). 2: Interrupt latency = 4Tcy where Tcy = instruction cycle time. 3: CLKOUT is available only in RC oscillator mode.
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6.2 Using Timer0 with an External Clock
When an external clock input is used for Timer0, it must meet certain requirements. The requirements ensure the external clock can be synchronized with the internal phase clock (TOSC). Also, there is a delay in the actual incrementing of Timer0 after synchronization. 6.2.1 EXTERNAL CLOCK SYNCHRONIZATION caler so that the prescaler output is symmetrical. For the external clock to meet the sampling requirement, the ripple-counter must be taken into account. Therefore, it is necessary for T0CKI to have a period of at least 4Tosc (and a small RC delay of 40 ns) divided by the prescaler value. The only requirement on T0CKI high and low time is that they do not violate the minimum pulse width requirement of 10 ns. Refer to parameters 40, 41 and 42 in the electrical specification of the desired device. 6.2.2 TMR0 INCREMENT DELAY
When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks (Figure 6-5). Therefore, it is necessary for T0CKI to be high for at least 2Tosc (and a small RC delay of 20 ns) and low for at least 2Tosc (and a small RC delay of 20 ns). Refer to the electrical specification of the desired device. When a prescaler is used, the external clock input is divided by the asynchronous ripple-counter type pres-
Since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the Timer0 module is actually incremented. Figure 6-5 shows the delay from the external clock edge to the timer incrementing.
FIGURE 6-5:
TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Small pulse misses sampling
External Clock Input or Prescaler output (2)
(1) (3)
External Clock/Prescaler Output after sampling Increment Timer0 (Q4) Timer0 T0 T0 + 1 T0 + 2
Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc). Therefore, the error in measuring the interval between two edges on Timer0 input = 4Tosc max. 2: External clock if no prescaler selected, Prescaler output otherwise. 3: The arrows indicate the points in time where sampling occurs.
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6.3 Prescaler
An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the Watchdog Timer, respectively (Figure 6-6). For simplicity, this counter is being referred to as "prescaler" throughout this data sheet. Note that there is only one prescaler available which is mutually exclusively shared between the Timer0 module and the Watchdog Timer. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the Watchdog Timer, and vice-versa. The PSA and PS2:PS0 bits (OPTION<3:0>) determine the prescaler assignment and prescale ratio. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g. CLRF 1, MOVWF 1, BSF 1,x....etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction will clear the prescaler along with the Watchdog Timer. The prescaler is not readable or writable. Note: Writing to TMR0 when the prescaler is assigned to Timer0 will clear the prescaler count, but will not change the prescaler assignment.
FIGURE 6-6:
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus 8 1 0 M U X SYNC 2 Cycles TMR0 reg
CLKOUT (=Fosc/4)
0 RA4/T0CKI pin 1 T0SE
M U X
T0CS
PSA
Set flag bit T0IF on Overflow
0 M U X
8-bit Prescaler 8 8 - to - 1MUX PS2:PS0
Watchdog Timer
1
PSA 0 MUX 1 PSA
WDT Enable bit
WDT Time-out Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION<5:0>).
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6.3.1 SWITCHING PRESCALER ASSIGNMENT Note: The prescaler assignment is fully under software control, i.e., it can be changed "on the fly" during program execution. To avoid an unintended device RESET, the following instruction sequence (shown in Example 6-1) must be executed when changing the prescaler assignment from Timer0 to the WDT. This sequence must be followed even if the WDT is disabled.
EXAMPLE 6-1:
BCF CLRF BSF CLRWDT MOVLW MOVWF BCF
CHANGING PRESCALER (TIMER0WDT)
;Bank 0 ;Clear TMR0 & Prescaler ;Bank 1 ;Clears WDT ;Selects new prescale value ;and assigns the prescaler to the WDT ;Bank 0
STATUS, RP0 TMR0 STATUS, RP0 b'xxxx1xxx' OPTION_REG STATUS, RP0
To change prescaler from the WDT to the Timer0 module use the sequence shown in Example 6-2.
EXAMPLE 6-2:
CLRWDT BSF MOVLW MOVWF BCF
CHANGING PRESCALER (WDTTIMER0)
;Clear WDT and prescaler ;Bank 1 ;Select TMR0, new prescale value and ;clock source ;Bank 0
STATUS, RP0 b'xxxx0xxx' OPTION_REG STATUS, RP0
TABLE 6-1:
Address 01h 0Bh,8Bh, 81h 85h Name TMR0
REGISTERS ASSOCIATED WITH TIMER0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR xxxx xxxx INTE T0SE RBIE PSA T0IF PS2 INTF PS1 RBIF PS0 0000 000x 1111 1111 ---1 1111 Value on all other resets uuuu uuuu 0000 000u 1111 1111 ---1 1111
Timer0 module's register GIE ADIE T0IE T0CS --
INTCON
OPTION RBPU INTEDG TRISA -- --
PORTA Data Direction Register
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.
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NOTES:
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7.0 ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE
710 71 711 715
The A/D converter has a unique feature of being able to operate while the device is in SLEEP mode. To operate in sleep, the A/D conversion clock must be derived from the A/D's internal RC oscillator. The A/D module has three registers. These registers are: * A/D Result Register (ADRES) * A/D Control Register 0 (ADCON0) * A/D Control Register 1 (ADCON1) The ADCON0 register, shown in Figure 7-1 and Figure 7-2, controls the operation of the A/D module. The ADCON1 register, shown in Figure 7-3 configures the functions of the port pins. The port pins can be configured as analog inputs (RA3 can also be a voltage reference) or as digital I/O.
Applicable Devices
The analog-to-digital (A/D) converter module has four analog inputs. The A/D allows conversion of an analog input signal to a corresponding 8-bit digital number (refer to Application Note AN546 for use of A/D Converter). The output of the sample and hold is the input into the converter, which generates the result via successive approximation. The analog reference voltage is software selectable to either the device's positive supply voltage (VDD) or the voltage level on the RA3/AN3/VREF pin.
FIGURE 7-1:
ADCON0 REGISTER (ADDRESS 08h), PIC16C710/71/711
U-0 -- (1) R/W-0 CHS1 R/W-0 CHS0 R/W-0 GO/DONE R/W-0 ADIF R/W-0 ADON bit0
R/W-0 R/W-0 ADCS1 ADCS0 bit7
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n =Value at POR reset
bit 7-6: ADCS1:ADCS0: A/D Conversion Clock Select bits 00 = FOSC/2 01 = FOSC/8 10 = FOSC/32 11 = FRC (clock derived from an RC oscillation) bit 5: Unimplemented: Read as '0'. bit 4-3: CHS1:CHS0: Analog Channel Select bits 00 = channel 0, (RA0/AN0) 01 = channel 1, (RA1/AN1) 10 = channel 2, (RA2/AN2) 11 = channel 3, (RA3/AN3) bit 2: GO/DONE: A/D Conversion Status bit If ADON = 1: 1 = A/D conversion in progress (setting this bit starts the A/D conversion) 0 = A/D conversion not in progress (This bit is automatically cleared by hardware when the A/D conversion is complete) bit 1: ADIF: A/D Conversion Complete Interrupt Flag bit 1 = conversion is complete (must be cleared in software) 0 = conversion is not complete
bit 0:
ADON: A/D On bit 1 = A/D converter module is operating 0 = A/D converter module is shutoff and consumes no operating current Note 1: Bit5 of ADCON0 is a General Purpose R/W bit for the PIC16C710/711 only. For the PIC16C71, this bit is unimplemented, read as '0'.
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FIGURE 7-2: ADCON0 REGISTER (ADDRESS 1Fh), PIC16C715
R/W-0 -- R/W-0 CHS1 R/W-0 CHS0 R/W-0 GO/DONE U-0 -- R/W-0 ADON bit0
R/W-0 R/W-0 ADCS1 ADCS0 bit7
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7-6: ADCS1:ADCS0: A/D Conversion Clock Select bits 00 = FOSC/2 01 = FOSC/8 10 = FOSC/32 11 = FRC (clock derived from an RC oscillation) bit 5: Unused bit 6-3: CHS1:CHS0: Analog Channel Select bits 000 = channel 0, (RA0/AN0) 001 = channel 1, (RA1/AN1) 010 = channel 2, (RA2/AN2) 011 = channel 3, (RA3/AN3) 100 = channel 0, (RA0/AN0) 101 = channel 1, (RA1/AN1) 110 = channel 2, (RA2/AN2) 111 = channel 3, (RA3/AN3) bit 2: GO/DONE: A/D Conversion Status bit If ADON = 1 1 = A/D conversion in progress (setting this bit starts the A/D conversion) 0 = A/D conversion not in progress (This bit is automatically cleared by hardware when the A/D conversion is complete) bit 1: bit 0: Unimplemented: Read as '0' ADON: A/D On bit 1 = A/D converter module is operating 0 = A/D converter module is shutoff and consumes no operating current
FIGURE 7-3:
ADCON1 REGISTER, PIC16C710/71/711 (ADDRESS 88h), PIC16C715 (ADDRESS 9Fh)
U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 PCFG1 R/W-0 PCFG0 bit0
U-0 -- bit7
U-0 --
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n =Value at POR reset
bit 7-2: Unimplemented: Read as '0' bit 1-0: PCFG1:PCFG0: A/D Port Configuration Control bits PCFG1:PCFG0 00 01 10 11 A = Analog input D = Digital I/O RA1 & RA0 A A A D A A D D RA2 RA3 A VREF D D VREF VDD RA3 VDD VDD
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The ADRES register contains the result of the A/D conversion. When the A/D conversion is complete, the result is loaded into the ADRES register, the GO/DONE bit (ADCON0<2>) is cleared, and A/D interrupt flag bit ADIF is set. The block diagram of the A/D module is shown in Figure 7-4. After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as an input. To determine acquisition time, see Section 7.1. After this acquisition time has elapsed the A/D conversion can be started. The following steps should be followed for doing an A/D conversion: 1. Configure the A/D module: * Configure analog pins / voltage reference / and digital I/O (ADCON1) * Select A/D input channel (ADCON0) * Select A/D conversion clock (ADCON0) * Turn on A/D module (ADCON0) 2. Configure A/D interrupt (if desired): * Clear ADIF bit * Set ADIE bit * Set GIE bit Wait the required acquisition time. Start conversion: * Set GO/DONE bit (ADCON0) Wait for A/D conversion to complete, by either: * Polling for the GO/DONE bit to be cleared OR 6. 7. * Waiting for the A/D interrupt Read A/D Result register (ADRES), clear bit ADIF if required. For next conversion, go to step 1 or step 2 as required. The A/D conversion time per bit is defined as TAD. A minimum wait of 2TAD is required before next acquisition starts.
3. 4. 5.
FIGURE 7-4:
A/D BLOCK DIAGRAM
CHS1:CHS0
11 VIN (Input voltage) 10
RA3/AN3/VREF RA2/AN2
A/D Converter
01 RA1/AN1 00 VDD VREF (Reference voltage) PCFG1:PCFG0 00 or 10 or 11 01 RA0/AN0
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7.1 A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 7-5. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), Figure 7-5. The source impedance affects the offset voltage at the analog input (due to pin leakage current). The maximum recommended impedance for analog sources is 10 k. After the analog input channel is selected (changed) this acquisition must be done before the conversion can be started. To calculate the minimum acquisition time, Equation 71 may be used. This equation calculates the acquisition time to within 1/2 LSb error is used (512 steps for the A/D). The 1/2 LSb error is the maximum error allowed for the A/D to meet its specified accuracy. Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. Note 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. Note 3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leakage specification. Note 4: After a conversion has completed, a 2.0TAD delay must complete before acquisition can begin again. During this time the holding capacitor is not connected to the selected A/D input channel.
EXAMPLE 7-1:
CALCULATING THE MINIMUM REQUIRED AQUISITION TIME
TACQ = Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient TACQ = 5 s + TCAP + [(Temp - 25C)(0.05 s/C)] TCAP = -CHOLD (RIC + RSS + RS) ln(1/511) -51.2 pF (1 k + 7 k + 10 k) ln(0.0020) -51.2 pF (18 k) ln(0.0020) -0.921 s (-6.2364) 5.747 s TACQ = 5 s + 5.747 s + [(50C - 25C)(0.05 s/C)] 10.747 s + 1.25 s 11.997 s
EQUATION 7-1:
A/D MINIMUM CHARGING TIME
VHOLD = (VREF - (VREF/512)) * (1 - e(-TCAP/CHOLD(RIC + RSS + RS))) Given: VHOLD = (VREF/512), for 1/2 LSb resolution The above equation reduces to: TCAP = -(51.2 pF)(1 k + RSS + RS) ln(1/511)
Example 7-1 shows the calculation of the minimum required acquisition time TACQ. This calculation is based on the following system assumptions. CHOLD = 51.2 pF Rs = 10 k 1/2 LSb error VDD = 5V Rss = 7 k Temp (application system max.) = 50C VHOLD = 0 @ t = 0
FIGURE 7-5:
ANALOG INPUT MODEL
VDD VT = 0.6V RIC 1k Sampling Switch SS RSS CHOLD = DAC capacitance = 51.2 pF VSS Legend CPIN = input capacitance VT = threshold voltage I leakage = leakage current at the pin due to various junctions RIC SS CHOLD = interconnect resistance = sampling switch = sample/hold capacitance (from DAC)
Rs
ANx
VA
CPIN 5 pF
VT = 0.6V
I leakage 500 nA
6V 5V VDD 4V 3V 2V
5 6 7 8 9 10 11 Sampling Switch ( k )
DS30272A-page 40
(c) 1997 Microchip Technology Inc.
PIC16C71X
7.2 Selecting the A/D Conversion Clock 7.3 Configuring Analog Port Pins
The A/D conversion time per bit is defined as TAD. The A/D conversion requires 9.5TAD per 8-bit conversion. The source of the A/D conversion clock is software selectable. The four possible options for TAD are: * * * * 2TOSC 8TOSC 32TOSC Internal RC oscillator The ADCON1 and TRISA registers control the operation of the A/D port pins. The port pins that are desired as analog inputs must have their corresponding TRIS bits set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. The A/D operation is independent of the state of the CHS2:CHS0 bits and the TRIS bits. Note 1: When reading the port register, all pins configured as analog input channels will read as cleared (a low level). Pins configured as digital inputs, will convert an analog input. Analog levels on a digitally configured input will not affect the conversion accuracy. Note 2: Analog levels on any pin that is defined as a digital input (including the AN7:AN0 pins), may cause the input buffer to consume current that is out of the devices specification.
For correct A/D conversions, the A/D conversion clock (TAD) must be selected to ensure a minimum TAD time of: 2.0 s for the PIC16C71 1.6 s for all other PIC16C71X devices Table 7-1 and Table 7-2 and show the resultant TAD times derived from the device operating frequencies and the A/D clock source selected.
TABLE 7-1:
TAD vs. DEVICE OPERATING FREQUENCIES, PIC16C71
Device Frequency 20 MHz 100 ns(2) 400 ns(2)
(1,4)
AD Clock Source (TAD) Operation 2TOSC 8TOSC 32TOSC RC(5) Legend: Note 1: 2: 3: 4: 5: ADCS1:ADCS0 00 01 10 11 16 MHz 125 ns(2) 500 2.0 s ns(2)
4 MHz 500 ns(2) 2.0 s 8.0 s s(1,4)
1 MHz 2.0 s 8.0 s 32.0 s(3) s(1)
333.33 kHz 6 s 24 s(3) 96 s(3)
1.6 s(2)
2-6 2-6 2-6 2 - 6 s(1) 2 - 6 s Shaded cells are outside of recommended range. The RC source has a typical TAD time of 4 s. These values violate the minimum required TAD time. For faster conversion times, the selection of another clock source is recommended. When device frequency is greater than 1 MHz, the RC A/D conversion clock source is recommended for sleep operation only. For extended voltage devices (LC), please refer to Electrical Specifications section.
s(1,4)
TABLE 7-2:
TAD vs. DEVICE OPERATING FREQUENCIES, PIC16C710/711, PIC16C715
Device Frequency 20 MHz 100 ns(2) 400 ns(2) 1.6 s 5 MHz 400 1.6 s ns(2) 1.25 MHz 1.6 s 6.4 s 25.6 s
(3)
AD Clock Source (TAD) Operation 2TOSC 8TOSC 32TOSC RC(5) Legend: Note 1: 2: 3: 4: ADCS1:ADCS0 00 01 10 11
333.33 kHz 6 s 24 s(3) 96 s(3)
6.4 s
2 - 6 s(1,4) 2 - 6 s(1,4) 2 - 6 s(1) 2 - 6 s(1,4) Shaded cells are outside of recommended range. The RC source has a typical TAD time of 4 s. These values violate the minimum required TAD time. For faster conversion times, the selection of another clock source is recommended. When device frequency is greater than 1 MHz, the RC A/D conversion clock source is recommended for sleep operation only. 5: For extended voltage devices (LC), please refer to Electrical Specifications section.
(c) 1997 Microchip Technology Inc.
DS30272A-page 41
PIC16C71X
7.4 A/D Conversions
Note: The GO/DONE bit should NOT be set in the same instruction that turns on the A/D. Example 7-2 shows how to perform an A/D conversion. The RA pins are configured as analog inputs. The analog reference (VREF) is the device VDD. The A/D interrupt is enabled, and the A/D conversion clock is FRC. The conversion is performed on the RA0 pin (channel 0).
Clearing the GO/DONE bit during a conversion will abort the current conversion. The ADRES register will NOT be updated with the partially completed A/D conversion sample. That is, the ADRES register will continue to contain the value of the last completed conversion (or the last value written to the ADRES register). After the A/D conversion is aborted, a 2TAD wait is required before the next acquisition is started. After this 2TAD wait, an acquisition is automatically started on the selected channel.
EXAMPLE 7-2:
BSF CLRF BCF MOVLW MOVWF BSF BSF ; ; ; ;
A/D CONVERSION
RP0 RP0 ; ; ; ; ; ; ; Select Bank 1 Configure A/D inputs Select Bank 0 RC Clock, A/D is on, Channel 0 is selected Enable A/D Interrupt Enable all interrupts
STATUS, ADCON1 STATUS, 0xC1 ADCON0 INTCON, INTCON,
ADIE GIE
Ensure that the required sampling time for the selected input channel has elapsed. Then the conversion may be started. BSF : : ADCON0, GO ; Start A/D Conversion ; The ADIF bit will be set and the GO/DONE bit ; is cleared upon completion of the A/D Conversion.
DS30272A-page 42
(c) 1997 Microchip Technology Inc.
PIC16C71X
7.4.1 FASTER CONVERSION - LOWER RESOLUTION TRADE-OFF Since the TAD is based from the device oscillator, the user must use some method (a timer, software loop, etc.) to determine when the A/D oscillator may be changed. Example 7-3 shows a comparison of time required for a conversion with 4-bits of resolution, versus the 8-bit resolution conversion. The example is for devices operating at 20 MHz and 16 MHz (The A/D clock is programmed for 32TOSC), and assumes that immediately after 6TAD, the A/D clock is programmed for 2TOSC. The 2TOSC violates the minimum TAD time since the last 4-bits will not be converted to correct values.
Not all applications require a result with 8-bits of resolution, but may instead require a faster conversion time. The A/D module allows users to make the trade-off of conversion speed to resolution. Regardless of the resolution required, the acquisition time is the same. To speed up the conversion, the clock source of the A/D module may be switched so that the TAD time violates the minimum specified time (see the applicable electrical specification). Once the TAD time violates the minimum specified time, all the following A/D result bits are not valid (see A/D Conversion Timing in the Electrical Specifications section.) The clock sources may only be switched between the three oscillator versions (cannot be switched from/to RC). The equation to determine the time before the oscillator can be switched is as follows: Conversion time = 2TAD + N * TAD + (8 - N)(2TOSC) Where: N = number of bits of resolution required.
EXAMPLE 7-3:
4-BIT vs. 8-BIT CONVERSION TIMES
Freq. (MHz)(1) Resolution 4-bit 8-bit
TAD TOSC 2TAD + N * TAD + (8 - N)(2TOSC)
20 16 20 16 20 16
1.6 s 2.0 s 50 ns 62.5 ns 10 s 12.5 s
1.6 s 2.0 s 50 ns 62.5 ns 16 s 20 s
Note 1: The PIC16C71 has a minimum TAD time of 2.0 s. All other PIC16C71X devices have a minimum TAD time of 1.6 s.
(c) 1997 Microchip Technology Inc.
DS30272A-page 43
PIC16C71X
7.5 A/D Operation During Sleep
The A/D module can operate during SLEEP mode. This requires that the A/D clock source be set to RC (ADCS1:ADCS0 = 11). When the RC clock source is selected, the A/D module waits one instruction cycle before starting the conversion. This allows the SLEEP instruction to be executed, which eliminates all digital switching noise from the conversion. When the conversion is completed the GO/DONE bit will be cleared, and the result loaded into the ADRES register. If the A/D interrupt is enabled, the device will wake-up from SLEEP. If the A/D interrupt is not enabled, the A/D module will then be turned off, although the ADON bit will remain set. When the A/D clock source is another clock option (not RC), a SLEEP instruction will cause the present conversion to be aborted and the A/D module to be turned off, though the ADON bit will remain set. Turning off the A/D places the A/D module in its lowest current consumption state. Note: For the A/D module to operate in SLEEP, the A/D clock source must be set to RC (ADCS1:ADCS0 = 11). To perform an A/D conversion in SLEEP, ensure the SLEEP instruction immediately follows the instruction that sets the GO/DONE bit. full scale error is that full scale does not take offset error into account. Gain error can be calibrated out in software. Linearity error refers to the uniformity of the code changes. Linearity errors cannot be calibrated out of the system. Integral non-linearity error measures the actual code transition versus the ideal code transition adjusted by the gain error for each code. Differential non-linearity measures the maximum actual code width versus the ideal code width. This measure is unadjusted. In systems where the device frequency is low, use of the A/D RC clock is preferred. At moderate to high frequencies, TAD should be derived from the device oscillator. TAD must not violate the minimum and should be 8 s for preferred operation. This is because TAD, when derived from TOSC, is kept away from on-chip phase clock transitions. This reduces, to a large extent, the effects of digital switching noise. This is not possible with the RC derived clock. The loss of accuracy due to digital switching noise can be significant if many I/O pins are active. In systems where the device will enter SLEEP mode after the start of the A/D conversion, the RC clock source selection is required. In this mode, the digital noise from the modules in SLEEP are stopped. This method gives high accuracy.
7.6
A/D Accuracy/Error
The absolute accuracy specified for the A/D converter includes the sum of all contributions for quantization error, integral error, differential error, full scale error, offset error, and monotonicity. It is defined as the maximum deviation from an actual transition versus an ideal transition for any code. The absolute error of the A/D converter is specified at < 1 LSb for VDD = VREF (over the device's specified operating range). However, the accuracy of the A/D converter will degrade as VDD diverges from VREF. For a given range of analog inputs, the output digital code will be the same. This is due to the quantization of the analog input to a digital code. Quantization error is typically 1/2 LSb and is inherent in the analog to digital conversion process. The only way to reduce quantization error is to increase the resolution of the A/D converter. Offset error measures the first actual transition of a code versus the first ideal transition of a code. Offset error shifts the entire transfer function. Offset error can be calibrated out of a system or introduced into a system through the interaction of the total leakage current and source impedance at the analog input. Gain error measures the maximum deviation of the last actual transition and the last ideal transition adjusted for offset error. This error appears as a change in slope of the transfer function. The difference in gain error to
7.7
Effects of a RESET
A device reset forces all registers to their reset state. This forces the A/D module to be turned off, and any conversion is aborted. The value that is in the ADRES register is not modified for a Power-on Reset. The ADRES register will contain unknown data after a Power-on Reset.
7.8
Connection Considerations
If the input voltage exceeds the rail values (VSS or VDD) by greater than 0.2V, then the accuracy of the conversion is out of specification. Note: Care must be taken when using the RA0 pin in A/D conversions due to its proximity to the OSC1 pin.
An external RC filter is sometimes added for anti-aliasing of the input signal. The R component should be selected to ensure that the total source impedance is kept under the 10 k recommended specification. Any external components connected (via hi-impedance) to an analog input pin (capacitor, zener diode, etc.) should have very little leakage current at the pin.
DS30272A-page 44
(c) 1997 Microchip Technology Inc.
PIC16C71X
7.9 Transfer Function FIGURE 7-6: A/D TRANSFER FUNCTION
The ideal transfer function of the A/D converter is as follows: the first transition occurs when the analog input voltage (VAIN) is Analog VREF/256 (Figure 7-6).
Digital code output
7.10
References
FFh FEh
A very good reference for understanding A/D converters is the "Analog-Digital Conversion Handbook" third edition, published by Prentice Hall (ISBN 0-13-032848-0).
04h 03h 02h 01h 00h 256 LSb (full scale) 255 LSb
Wait 2 TAD
0.5 LSb 1 LSb
2 LSb
3 LSb
Analog input voltage
FIGURE 7-7:
FLOWCHART OF A/D OPERATION
ADON = 0
Yes ADON = 0?
No Acquire Selected Channel
Yes GO = 0?
No
A/D Clock = RC? No
Yes
Start of A/D Conversion Delayed 1 Instruction Cycle
SLEEP Yes Instruction? No
Finish Conversion GO = 0 ADIF = 1
Device in SLEEP? No
Yes
Abort Conversion GO = 0 ADIF = 0
Finish Conversion GO = 0 ADIF = 1
Wake-up Yes From Sleep?
No
Finish Conversion GO = 0 ADIF = 1
SLEEP Power-down A/D
Wait 2 TAD
Stay in Sleep Power-down A/D
Wait 2 TAD
(c) 1997 Microchip Technology Inc.
4 LSb
DS30272A-page 45
PIC16C71X
TABLE 7-3:
Address 0Bh,8Bh 89h 08h 88h 05h Name INTCON ADRES ADCON0 ADCON1 PORTA
REGISTERS/BITS ASSOCIATED WITH A/D, PIC16C710/71/711
Bit 7 GIE Bit 6 ADIE Bit 5 T0IE Bit 4 INTE Bit 3 RBIE Bit 2 T0IF Bit 1 INTF Bit 0 RBIF Value on: POR, BOR 0000 000x xxxx xxxx CHS1 -- RA4 CHS0 -- RA3 GO/DONE -- RA2 ADIF PCFG1 RA1 ADON PCFG0 RA0 00-0 0000 ---- --00 ---x 0000 ---1 1111 Value on all other Resets 0000 000u uuuu uuuu 00-0 0000 ---- --00 ---u 0000
A/D Result Register ADCS1 ADCS0 -- -- -- -- -- -- --
---1 1111 85h TRISA -- -- -- PORTA Data Direction Register Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used for A/D conversion.
TABLE 7-4:
Address Name 0Bh/8Bh INTCON PIR1 0Ch 8Ch 1Eh 1Fh 9Fh 05h 85h PIE1 ADRES ADCON 0 ADCON 1 PORTA TRISA
REGISTERS/BITS ASSOCIATED WITH A/D, PIC16C715
Bit 7 GIE -- -- Bit 6 PEIE ADIF ADIE Bit 5 T0IE -- -- Bit 4 INTE -- -- Bit 3 RBIE -- -- Bit 2 T0IF -- -- Bit 1 INTF -- -- Bit 0 RBIF -- -- Value on: POR, BOR 0000 000x -0-- ----0-- ---xxxx xxxx CHS1 -- RA4 TRISA4 CHS0 -- RA3 GO/ DONE -- RA2 -- PCFG1 RA1 ADON 0000 00-0 Value on all other Resets 0000 000u -0-- ----0-- ---uuuu uuuu 0000 00-0 ---- --00 ---u 0000 ---1 1111
A/D Result Register ADCS 1 -- -- -- ADCS 0 -- -- -- CHS2 -- -- --
PCFG0 ---- --00 RA0 ---x 0000
TRISA TRISA2 3 Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used for A/D conversion.
TRISA1 TRISA0 ---1 1111
DS30272A-page 46
(c) 1997 Microchip Technology Inc.
PIC16C71X
8.0 SPECIAL FEATURES OF THE CPU
710 71 711 715
fixed delay of 72 ms (nominal) on power-up only, designed to keep the part in reset while the power supply stabilizes. With these two timers on-chip, most applications need no external reset circuitry. SLEEP mode is designed to offer a very low current power-down mode. The user can wake-up from SLEEP through external reset, Watchdog Timer Wake-up, or through an interrupt. Several oscillator options are also made available to allow the part to fit the application. The RC oscillator option saves system cost while the LP crystal option saves power. A set of configuration bits are used to select various options.
Applicable Devices
What sets a microcontroller apart from other processors are special circuits to deal with the needs of realtime applications. The PIC16CXX family has a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection. These are: * Oscillator selection * Reset - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR) (PIC16C710/711/715) - Parity Error Reset (PER) (PIC16C715) * Interrupts * Watchdog Timer (WDT) * SLEEP * Code protection * ID locations * In-circuit serial programming The PIC16CXX has a Watchdog Timer which can be shut off only through configuration bits. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in reset until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a
8.1
Configuration Bits
The configuration bits can be programmed (read as '0') or left unprogrammed (read as '1') to select various device configurations. These bits are mapped in program memory location 2007h. The user will note that address 2007h is beyond the user program memory space. In fact, it belongs to the special test/configuration memory space (2000h 3FFFh), which can be accessed only during programming.
FIGURE 8-1:
-- bit13 --
CONFIGURATION WORD FOR PIC16C71
-- -- -- -- -- -- -- CP0 PWRTE WDTE FOSC1 FOSC0 bit0
Register: Address
CONFIG 2007h
bit 13-5: Unimplemented: Read as '1' bit 4: CP0: Code protection bit 1 = Code protection off 0 = All memory is code protected, but 00h - 3Fh is writable PWRTE: Power-up Timer Enable bit 1 = Power-up Timer enabled 0 = Power-up Timer disabled WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled FOSC1:FOSC0: Oscillator Selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator
bit 3:
bit 2:
bit 1-0:
(c) 1997 Microchip Technology Inc.
DS30272A-page 47
PIC16C71X
FIGURE 8-2:
CP0 bit13 CP0
CONFIGURATION WORD, PIC16C710/711
CP0 CP0 CP0 CP0 CP0 BODEN CP0 CP0 PWRTE WDTE FOSC1 FOSC0 bit0
Register: Address
CONFIG 2007h
bit 13-7 CP0: Code protection bits (2) 5-4: 1 = Code protection off 0 = All memory is code protected, but 00h - 3Fh is writable bit 6: BODEN: Brown-out Reset Enable bit (1) 1 = BOR enabled 0 = BOR disabled bit 3: PWRTE: Power-up Timer Enable bit (1) 1 = PWRT disabled 0 = PWRT enabled WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled FOSC1:FOSC0: Oscillator Selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator
bit 2:
bit 1-0:
Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT) regardless of the value of bit PWRTE. Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled. 2: All of the CP0 bits have to be given the same value to enable the code protection scheme listed.
FIGURE 8-3:
CP1 bit13 CP0
CONFIGURATION WORD, PIC16C715
CP1 CP0 CP1 CP0 MPEEN BODEN CP1 CP0 PWRTE WDTE FOSC1 FOSC0 bit0
Register: Address
CONFIG 2007h
bit 13-8 5-4:
CP1:CP0: Code Protection bits (2) 11 = Code protection off 10 = Upper half of program memory code protected 01 = Upper 3/4th of program memory code protected 00 = All memory is code protected MPEEN: Memory Parity Error Enable 1 = Memory Parity Checking is enabled 0 = Memory Parity Checking is disabled BODEN: Brown-out Reset Enable bit (1) 1 = BOR enabled 0 = BOR disabled PWRTE: Power-up Timer Enable bit (1) 1 = PWRT disabled 0 = PWRT enabled WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled FOSC1:FOSC0: Oscillator Selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator
bit 7:
bit 6:
bit 3:
bit 2:
bit 1-0:
Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT) regardless of the value of bit PWRTE. Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled. 2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.
DS30272A-page 48
(c) 1997 Microchip Technology Inc.
PIC16C71X
8.2
8.2.1
Oscillator Configurations
OSCILLATOR TYPES
TABLE 8-1:
Ranges Tested: Mode XT
CERAMIC RESONATORS, PIC16C71
The PIC16CXX can be operated in four different oscillator modes. The user can program two configuration bits (FOSC1 and FOSC0) to select one of these four modes: * * * * LP XT HS RC Low Power Crystal Crystal/Resonator High Speed Crystal/Resonator Resistor/Capacitor CRYSTAL OSCILLATOR/CERAMIC RESONATORS
Freq 455 kHz 2.0 MHz 4.0 MHz 8.0 MHz 16.0 MHz
OSC1 47 - 100 pF 15 - 68 pF 15 - 68 pF 15 - 68 pF 10 - 47 pF
OSC2 47 - 100 pF 15 - 68 pF 15 - 68 pF 15 - 68 pF 10 - 47 pF
HS
These values are for design guidance only. See notes at bottom of page.
8.2.2
Resonators Used: 455 kHz 2.0 MHz 4.0 MHz 8.0 MHz 16.0 MHz Panasonic EFO-A455K04B Murata Erie CSA2.00MG Murata Erie CSA4.00MG Murata Erie CSA8.00MT Murata Erie CSA16.00MX 0.3% 0.5% 0.5% 0.5% 0.5%
In XT, LP or HS modes a crystal or ceramic resonator is connected to the OSC1/CLKIN and OSC2/CLKOUT pins to establish oscillation (Figure 8-4). The PIC16CXX Oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. When in XT, LP or HS modes, the device can have an external clock source to drive the OSC1/ CLKIN pin (Figure 8-5).
All resonators used did not have built-in capacitors.
TABLE 8-2:
CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR, PIC16C71
Freq OSC1 33 - 68 pF 15 - 47 pF 47 - 100 pF 20 - 68 pF 15 - 68 pF 15 - 47 pF 15 - 33 pF 15 - 47 pF 15 - 47 pF OSC2 33 - 68 pF 15 - 47 pF 47 - 100 pF 20 - 68 pF 15 - 68 pF 15 - 47 pF 15 - 33 pF 15 - 47 pF 15 - 47 pF
FIGURE 8-4:
CRYSTAL/CERAMIC RESONATOR OPERATION (HS, XT OR LP OSC CONFIGURATION)
OSC1
Mode LP XT
C1 XTAL OSC2 C2 RS Note1 (2) RF SLEEP PIC16CXXX To internal logic
HS
32 kHz 200 kHz 100 kHz 500 kHz 1 MHz 2 MHz 4 MHz 8 MHz 20 MHz
See Table 8-1 and Table 8-1 for recommended values of C1 and C2. Note 1: A series resistor may be required for AT strip cut crystals. 2: The buffer is on the OSC2 pin.
These values are for design guidance only. See notes at bottom of page.
FIGURE 8-5:
EXTERNAL CLOCK INPUT OPERATION (HS, XT OR LP OSC CONFIGURATION)
OSC1 PIC16CXXX Open OSC2
Clock from ext. system
(c) 1997 Microchip Technology Inc.
DS30272A-page 49
PIC16C71X
TABLE 8-3:
Ranges Tested: Mode XT Freq 455 kHz 2.0 MHz 4.0 MHz 8.0 MHz 16.0 MHz OSC1 68 - 100 pF 15 - 68 pF 15 - 68 pF 10 - 68 pF 10 - 22 pF OSC2 68 - 100 pF 15 - 68 pF 15 - 68 pF 10 - 68 pF 10 - 22 pF
Osc Type LP XT Crystal Freq 32 kHz 200 kHz 200 kHz 1 MHz 4 MHz HS 4 MHz 8 MHz 20 MHz Cap. Range C1 33 pF 15 pF 47-68 pF 15 pF 15 pF 15 pF 15-33 pF 15-33 pF Cap. Range C2 33 pF 15 pF 47-68 pF 15 pF 15 pF 15 pF 15-33 pF 15-33 pF
CERAMIC RESONATORS, PIC16C710/711/715
TABLE 8-4:
CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR, PIC16C710/711/715
HS
These values are for design guidance only. See notes at bottom of page.
Resonators Used: 455 kHz 2.0 MHz 4.0 MHz 8.0 MHz 16.0 MHz Panasonic EFO-A455K04B Murata Erie CSA2.00MG Murata Erie CSA4.00MG Murata Erie CSA8.00MT Murata Erie CSA16.00MX 0.3% 0.5% 0.5% 0.5% 0.5%
These values are for design guidance only. See notes at bottom of page. Crystals Used 32 kHz 200 kHz 1 MHz 4 MHz 8 MHz 20 MHz Epson C-001R32.768K-A STD XTL 200.000KHz ECS ECS-10-13-1 ECS ECS-40-20-1 EPSON CA-301 8.000M-C EPSON CA-301 20.000M-C 20 PPM 20 PPM 50 PPM 50 PPM 30 PPM 30 PPM
All resonators used did not have built-in capacitors.
Note 1: Recommended values of C1 and C2 are identical to the ranges tested table. 2: Higher capacitance increases the stability of oscillator but also increases the start-up time. 3: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 4: Rs may be required in HS mode as well as XT mode to avoid overdriving crystals with low drive level specification.
DS30272A-page 50
(c) 1997 Microchip Technology Inc.
PIC16C71X
8.2.3 EXTERNAL CRYSTAL OSCILLATOR CIRCUIT 8.2.4 RC OSCILLATOR For timing insensitive applications the "RC" device option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (Rext) and capacitor (Cext) values, and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low Cext values. The user also needs to take into account variation due to tolerance of external R and C components used. Figure 8-8 shows how the R/C combination is connected to the PIC16CXX. For Rext values below 2.2 k, the oscillator operation may become unstable, or stop completely. For very high Rext values (e.g. 1 M), the oscillator becomes sensitive to noise, humidity and leakage. Thus, we recommend to keep Rext between 3 k and 100 k. Although the oscillator will operate with no external capacitor (Cext = 0 pF), we recommend using values above 20 pF for noise and stability reasons. With no or small external capacitance, the oscillation frequency can vary dramatically due to changes in external capacitances, such as PCB trace capacitance or package lead frame capacitance. See characterization data for desired device for RC frequency variation from part to part due to normal process variation. The variation is larger for larger R (since leakage current variation will affect RC frequency more for large R) and for smaller C (since variation of input capacitance will affect RC frequency more). See characterization data for desired device for variation of oscillator frequency due to VDD for given Rext/ Cext values as well as frequency variation due to operating temperature for given R, C, and VDD values. The oscillator frequency, divided by 4, is available on the OSC2/CLKOUT pin, and can be used for test purposes or to synchronize other logic (see Figure 3-2 for waveform).
Either a prepackaged oscillator can be used or a simple oscillator circuit with TTL gates can be built. Prepackaged oscillators provide a wide operating range and better stability. A well-designed crystal oscillator will provide good performance with TTL gates. Two types of crystal oscillator circuits can be used; one with series resonance, or one with parallel resonance. Figure 8-6 shows implementation of a parallel resonant oscillator circuit. The circuit is designed to use the fundamental frequency of the crystal. The 74AS04 inverter performs the 180-degree phase shift that a parallel oscillator requires. The 4.7 k resistor provides the negative feedback for stability. The 10 k potentiometer biases the 74AS04 in the linear region. This could be used for external oscillator designs.
FIGURE 8-6:
EXTERNAL PARALLEL RESONANT CRYSTAL OSCILLATOR CIRCUIT
To Other Devices
+5V 10k 4.7k 74AS04 74AS04 PIC16CXXX CLKIN
10k XTAL 10k 20 pF 20 pF
Figure 8-7 shows a series resonant oscillator circuit. This circuit is also designed to use the fundamental frequency of the crystal. The inverter performs a 180degree phase shift in a series resonant oscillator circuit. The 330 k resistors provide the negative feedback to bias the inverters in their linear region.
FIGURE 8-8:
VDD Rext
RC OSCILLATOR MODE
FIGURE 8-7:
EXTERNAL SERIES RESONANT CRYSTAL OSCILLATOR CIRCUIT
To Other Devices 74AS04 PIC16CXXX CLKIN
OSC1 Cext VSS Fosc/4 OSC2/CLKOUT
330 k 74AS04 0.1 F XTAL
330 k 74AS04
Internal clock PIC16CXXX
(c) 1997 Microchip Technology Inc.
DS30272A-page 51
PIC16C71X
8.3 Reset 710 71 711 715 Applicable Devices
WDT Reset, on MCLR reset during SLEEP, and Brownout Reset (BOR). They are not affected by a WDT Wake-up, which is viewed as the resumption of normal operation. The TO and PD bits are set or cleared differently in different reset situations as indicated in Table 87, Table 8-8 and Table 8-9. These bits are used in software to determine the nature of the reset. See Table 810 and Table 8-11 for a full description of reset states of all registers. A simplified block diagram of the on-chip reset circuit is shown in Figure 8-9. The PIC16C710/711/715 have a MCLR noise filter in the MCLR reset path. The filter will detect and ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low.
The PIC16CXX differentiates between various kinds of reset: * * * * * * Power-on Reset (POR) MCLR reset during normal operation MCLR reset during SLEEP WDT Reset (normal operation) Brown-out Reset (BOR) (PIC16C710/711/715) Parity Error Reset (PIC16C715)
Some registers are not affected in any reset condition; their status is unknown on POR and unchanged in any other reset. Most other registers are reset to a "reset state" on Power-on Reset (POR), on the MCLR and
FIGURE 8-9:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External Reset
MCLR/VPP Pin Program Memory Parity(3) MPEEN
WDT SLEEP Module WDT Time-out VDD rise detect VDD Brown-out Reset(2) OST/PWRT OST 10-bit Ripple-counter OSC1/ CLKIN Pin On-chip(1) RC OSC R Q Chip_Reset BODEN S Power-on Reset
PWRT 10-bit Ripple-counter
Enable PWRT Enable OST
See Table 8-6 for time-out situations.
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin. 2: Brown-out Reset is implemented on the PIC16C710/711/715. 3: Parity Error Reset is implemented on the PIC16C715.
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8.4 Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST), and Brown-out Reset (BOR)
POWER-ON RESET (POR) The power-up time delay will vary from chip to chip due to VDD, temperature, and process variation. See DC parameters for details. 8.4.3 OSCILLATOR START-UP TIMER (OST)
8.4.1
Applicable Devices
710 71 711 715
Applicable Devices
710 71 711 715
A Power-on Reset pulse is generated on-chip when VDD rise is detected (in the range of 1.5V - 2.1V). To take advantage of the POR, just tie the MCLR pin directly (or through a resistor) to VDD. This will eliminate external RC components usually needed to create a Power-on Reset. A maximum rise time for VDD is specified. See Electrical Specifications for details. When the device starts normal operation (exits the reset condition), device operating parameters (voltage, frequency, temperature, ...) must be met to ensure operation. If these conditions are not met, the device must be held in reset until the operating conditions are met. Brown-out Reset may be used to meet the startup conditions. For additional information, refer to Application Note AN607, "Power-up Trouble Shooting." 8.4.2 POWER-UP TIMER (PWRT)
The Oscillator Start-up Timer (OST) provides 1024 oscillator cycle (from OSC1 input) delay after the PWRT delay is over. This ensures that the crystal oscillator or resonator has started and stabilized. The OST time-out is invoked only for XT, LP and HS modes and only on Power-on Reset or wake-up from SLEEP. 8.4.4 BROWN-OUT RESET (BOR)
Applicable Devices
710 71 711 715
Applicable Devices
710 71 711 715
The Power-up Timer provides a fixed 72 ms nominal time-out on power-up only, from the POR. The Powerup Timer operates on an internal RC oscillator. The chip is kept in reset as long as the PWRT is active. The PWRT's time delay allows VDD to rise to an acceptable level. A configuration bit is provided to enable/disable the PWRT.
A configuration bit, BODEN, can disable (if clear/programmed) or enable (if set) the Brown-out Reset circuitry. If VDD falls below 4.0V (3.8V - 4.2V range) for greater than parameter #35, the brown-out situation will reset the chip. A reset may not occur if VDD falls below 4.0V for less than parameter #35. The chip will remain in Brown-out Reset until VDD rises above BVDD. The Power-up Timer will now be invoked and will keep the chip in RESET an additional 72 ms. If VDD drops below BVDD while the Power-up Timer is running, the chip will go back into a Brown-out Reset and the Power-up Timer will be initialized. Once VDD rises above BVDD, the Power-up Timer will execute a 72 ms time delay. The Power-up Timer should always be enabled when Brown-out Reset is enabled. Figure 8-10 shows typical brown-out situations.
FIGURE 8-10: BROWN-OUT SITUATIONS
VDD BVDD Internal Reset VDD BVDD Internal Reset <72 ms 72 ms 72 ms
VDD BVDD Internal Reset 72 ms
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8.4.5 TIME-OUT SEQUENCE
Applicable Devices
710 71 711 715
Bit1 is POR (Power-on Reset Status bit). It is cleared on a Power-on Reset and unaffected otherwise. The user must set this bit following a Power-on Reset. For the PIC16C715, bit2 is PER (Parity Error Reset). It is cleared on a Parity Error Reset and must be set by user software. It will also be set on a Power-on Reset. For the PIC16C715, bit7 is MPEEN (Memory Parity Error Enable). This bit reflects the status of the MPEEN bit in configuration word. It is unaffected by any reset of interrupt. 8.4.7 PARITY ERROR RESET (PER)
On power-up the time-out sequence is as follows: First PWRT time-out is invoked after the POR time delay has expired. Then OST is activated. The total time-out will vary based on oscillator configuration and the status of the PWRT. For example, in RC mode with the PWRT disabled, there will be no time-out at all. Figure 8-11, Figure 8-12, and Figure 8-13 depict time-out sequences on power-up. Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the time-outs will expire. Then bringing MCLR high will begin execution immediately (Figure 8-12). This is useful for testing purposes or to synchronize more than one PIC16CXX device operating in parallel. Table 8-10 and Table 8-11 show the reset conditions for some special function registers, while Table 8-12 and Table 8-13 show the reset conditions for all the registers. 8.4.6 POWER CONTROL/STATUS REGISTER (PCON)
Applicable Devices
710 71 711 715
The PIC16C715 has on-chip parity bits that can be used to verify the contents of program memory. Parity bits may be useful in applications in order to increase overall reliability of a system. There are two parity bits for each word of Program Memory. The parity bits are computed on alternating bits of the program word. One computation is performed using even parity, the other using odd parity. As a program executes, the parity is verified. The even parity bit is XOR'd with the even bits in the program memory word. The odd parity bit is negated and XOR'd with the odd bits in the program memory word. When an error is detected, a reset is generated and the PER flag bit 2 in the PCON register is cleared (logic `0'). This indication can allow software to act on a failure. However, there is no indication of the program memory location of the failure in Program Memory. This flag can only be set (logic `1') by software. The parity array is user selectable during programming. Bit 7 of the configuration word located at address 2007h can be programmed (read as `0') to disable parity. If left unprogrammed (read as `1'), parity is enabled.
Applicable Devices
710 71 711 715
The Power Control/Status Register, PCON has up to two bits, depending upon the device. Bit0 is Brown-out Reset Status bit, BOR. Bit BOR is unknown on a Power-on Reset. It must then be set by the user and checked on subsequent resets to see if bit BOR cleared, indicating a BOR occurred. The BOR bit is a "Don't Care" bit and is not necessarily predictable if the Brown-out Reset circuitry is disabled (by clearing bit BODEN in the Configuration Word).
TABLE 8-5:
TIME-OUT IN VARIOUS SITUATIONS, PIC16C71
Power-up PWRTE = 1 PWRTE = 0 72 ms + 1024TOSC 1024TOSC 72 ms -- Wake-up from SLEEP 1024 TOSC --
Oscillator Configuration XT, HS, LP RC
TABLE 8-6:
TIME-OUT IN VARIOUS SITUATIONS, PIC16C710/711/715
Power-up PWRTE = 0 PWRTE = 1 72 ms + 1024TOSC 1024TOSC 72 ms -- Brown-out 72 ms + 1024TOSC 72 ms Wake-up from SLEEP 1024TOSC --
Oscillator Configuration XT, HS, LP RC
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TABLE 8-7:
TO 1 0 x 0 0 u 1
STATUS BITS AND THEIR SIGNIFICANCE, PIC16C71
PD 1 x 0 1 0 u 0 Power-on Reset Illegal, TO is set on POR Illegal, PD is set on POR WDT Reset WDT Wake-up MCLR Reset during normal operation MCLR Reset during SLEEP or interrupt wake-up from SLEEP
TABLE 8-8:
POR 0 0 0 1 1 1 1 1 BOR x x x 0 1 1 1 1
STATUS BITS AND THEIR SIGNIFICANCE, PIC16C710/711
TO 1 0 x x 0 0 u 1 PD 1 x 0 x 1 0 u 0 Power-on Reset Illegal, TO is set on POR Illegal, PD is set on POR Brown-out Reset WDT Reset WDT Wake-up MCLR Reset during normal operation MCLR Reset during SLEEP or interrupt wake-up from SLEEP
TABLE 8-9:
PER 1 x x 1 1 1 1 1 0 0 0 POR 0 0 0 1 1 1 1 1 1 0 x
STATUS BITS AND THEIR SIGNIFICANCE, PIC16C715
BOR x x x 0 1 1 1 1 1 x 0 TO 1 0 x x 0 0 u 1 1 x x PD 1 x 0 x 1 0 u 0 1 x x Power-on Reset Illegal, TO is set on POR Illegal, PD is set on POR Brown-out Reset WDT Reset WDT Wake-up MCLR Reset during normal operation MCLR Reset during SLEEP or interrupt wake-up from SLEEP Parity Error Reset Illegal, PER is set on POR Illegal, PER is set on BOR
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TABLE 8-10: RESET CONDITION FOR SPECIAL REGISTERS, PIC16C710/71/711
Condition Power-on Reset MCLR Reset during normal operation MCLR Reset during SLEEP WDT Reset WDT Wake-up Brown-out Reset (PIC16C710/711) Interrupt wake-up from SLEEP Program Counter 000h 000h 000h 000h PC + 1 000h PC + 1
(1)
STATUS Register 0001 1xxx 000u uuuu 0001 0uuu 0000 1uuu uuu0 0uuu 0001 1uuu uuu1 0uuu
PCON Register
PIC16C710/711
---- --0x ---- --uu ---- --uu ---- --uu ---- --uu ---- --u0 ---- --uu
Legend: u = unchanged, x = unknown, - = unimplemented bit read as '0'. Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
TABLE 8-11:
RESET CONDITION FOR SPECIAL REGISTERS, PIC16C715
Condition Program Counter 000h 000h 000h 000h PC + 1 000h 000h PC + 1
(1)
STATUS Register 0001 1xxx 000u uuuu 0001 0uuu 0000 1uuu uuu0 0uuu 0001 1uuu uuu1 0uuu uuu1 0uuu
PCON Register u--- -10x u--- -uuu u--- -uuu u--- -uuu u--- -uuu u--- -uu0 u--- -0uu u--- -uuu
Power-on Reset MCLR Reset during normal operation MCLR Reset during SLEEP WDT Reset WDT Wake-up Brown-out Reset Parity Error Reset Interrupt wake-up from SLEEP
Legend: u = unchanged, x = unknown, - = unimplemented bit read as '0'. Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
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TABLE 8-12:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS, PIC16C710/71/711
Power-on Reset, Brown-out Reset(5) xxxx xxxx N/A xxxx xxxx 0000h 0001 1xxx xxxx xxxx ---x 0000 xxxx xxxx ---0 0000 0000 000x xxxx xxxx 00-0 0000 1111 1111 ---1 1111 1111 1111 ---- --0u ---- --00 MCLR Resets WDT Reset uuuu uuuu N/A uuuu uuuu 0000h 000q quuu(3) uuuu uuuu ---u 0000 uuuu uuuu ---0 0000 0000 000u uuuu uuuu 00-0 0000 1111 1111 ---1 1111 1111 1111 ---- --uu ---- --00 Wake-up via WDT or Interrupt uuuu uuuu N/A uuuu uuuu PC + 1(2) uuuq quuu(3) uuuu uuuu ---u uuuu uuuu uuuu ---u uuuu uuuu uuuu(1) uuuu uuuu uu-u uuuu uuuu uuuu ---u uuuu uuuu uuuu ---- --uu ---- --uu
W INDF TMR0 PCL STATUS FSR PORTA PORTB PCLATH INTCON ADRES ADCON0 OPTION TRISA TRISB PCON
(4)
ADCON1
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition Note 1: One or more bits in INTCON will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table 8-10 for reset value for specific condition. 4: The PCON register is not implemented on the PIC16C71. 5: Brown-out reset is not implemented on the PIC16C71.
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TABLE 8-13:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS, PIC16C715
Power-on Reset, Brown-out Reset Parity Error Reset xxxx xxxx N/A xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx ---x 0000 xxxx xxxx ---0 0000 0000 000x -0-- ---0000 00-0 1111 1111 ---1 1111 1111 1111 -0-- ------- -qqq ---- --00 MCLR Resets WDT Reset uuuu uuuu N/A uuuu uuuu 0000 0000 000q quuu(3) uuuu uuuu ---u 0000 uuuu uuuu ---0 0000 0000 000u -0-- ---0000 00-0 1111 1111 ---1 1111 1111 1111 -0-- ------- -1uu ---- --00 Wake-up via WDT or Interrupt uuuu uuuu N/A uuuu uuuu PC + 1(2) uuuq quuu(3) uuuu uuuu ---u uuuu uuuu uuuu ---u uuuu uuuu uuuu(1) -u-- ----(1) uuuu uu-u uuuu uuuu ---u uuuu uuuu uuuu -u-- ------- -1uu ---- --uu
W INDF TMR0 PCL STATUS FSR PORTA PORTB PCLATH INTCON PIR1 ADCON0 OPTION TRISA TRISB PIE1 PCON ADCON1
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition Note 1: One or more bits in INTCON and PIR1 will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table 8-11 for reset value for specific condition.
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FIGURE 8-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 8-12: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 8-13: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
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FIGURE 8-14: EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP)
VDD D R R1 MCLR C PIC16CXX
FIGURE 8-15: EXTERNAL BROWN-OUT PROTECTION CIRCUIT 1
VDD 33k 10k 40k MCLR PIC16CXX VDD
Note 1: External Power-on Reset circuit is required only if VDD power-up slope is too slow. The diode D helps discharge the capacitor quickly when VDD powers down. 2: R < 40 k is recommended to make sure that voltage drop across R does not violate the device's electrical specification. 3: R1 = 100 to 1 k will limit any current flowing into MCLR from external capacitor C in the event of MCLR/VPP pin breakdown due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS).
Note 1: This circuit will activate reset when VDD goes below (Vz + 0.7V) where Vz = Zener voltage. 2: Internal brown-out detection on the PIC16C710/711/715 should be disabled when using this circuit. 3: Resistors should be adjusted for the characteristics of the transistor.
FIGURE 8-16: EXTERNAL BROWN-OUT PROTECTION CIRCUIT 2
VDD R1 Q1
VDD
MCLR R2 40k PIC16CXX
Note 1: This brown-out circuit is less expensive, albeit less accurate. Transistor Q1 turns off when VDD is below a certain level such that: R1 = 0.7V VDD * R1 + R2 2: Internal brown-out detection on the PIC16C710/711/715 should be disabled when using this circuit. 3: Resistors should be adjusted for the characteristics of the transistor.
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8.5 Interrupts 710 71 711 715 Applicable Devices
For external interrupt events, such as the INT pin or PORTB change interrupt, the interrupt latency will be three or four instruction cycles. The exact latency depends when the interrupt event occurs (Figure 8-19). The latency is the same for one or two cycle instructions. Individual interrupt flag bits are set regardless of the status of their corresponding mask bit or the GIE bit. Note: For the PIC16C71 If an interrupt occurs while the Global Interrupt Enable (GIE) bit is being cleared, the GIE bit may unintentionally be re-enabled by the user's Interrupt Service Routine (the RETFIE instruction). The events that would cause this to occur are: 1. 2. An instruction clears the GIE bit while an interrupt is acknowledged. The program branches to the Interrupt vector and executes the Interrupt Service Routine. The Interrupt Service Routine completes with the execution of the RETFIE instruction. This causes the GIE bit to be set (enables interrupts), and the program returns to the instruction after the one which was meant to disable interrupts.
The PIC16C71X family has 4 sources of interrupt. Interrupt Sources External interrupt RB0/INT TMR0 overflow interrupt PORTB change interrupts (pins RB7:RB4) A/D Interrupt The interrupt control register (INTCON) records individual interrupt requests in flag bits. It also has individual and global interrupt enable bits. Note: Individual interrupt flag bits are set regardless of the status of their corresponding mask bit or the GIE bit.
A global interrupt enable bit, GIE (INTCON<7>) enables (if set) all un-masked interrupts or disables (if cleared) all interrupts. When bit GIE is enabled, and an interrupt's flag bit and mask bit are set, the interrupt will vector immediately. Individual interrupts can be disabled through their corresponding enable bits in various registers. Individual interrupt bits are set regardless of the status of the GIE bit. The GIE bit is cleared on reset. The "return from interrupt" instruction, RETFIE, exits the interrupt routine as well as sets the GIE bit, which re-enables interrupts. The RB0/INT pin interrupt, the RB port change interrupt and the TMR0 overflow interrupt flags are contained in the INTCON register. The peripheral interrupt flags are contained in the special function registers PIR1 and PIR2. The corresponding interrupt enable bits are contained in special function registers PIE1 and PIE2, and the peripheral interrupt enable bit is contained in special function register INTCON. When an interrupt is responded to, the GIE bit is cleared to disable any further interrupt, the return address is pushed onto the stack and the PC is loaded with 0004h. Once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid recursive interrupts.
LOOP BCF
3.
Perform the following to ensure that interrupts are globally disabled:
INTCON, GIE ; Disable global ; interrupt bit ; Global interrupt ; disabled? ; NO, try again ; Yes, continue ; with program ; flow
BTFSC INTCON, GIE GOTO : LOOP
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FIGURE 8-17: INTERRUPT LOGIC, PIC16C710, 71, 711
T0IF T0IE INTF INTE RBIF RBIE ADIF ADIE GIE Wakeup (If in SLEEP mode)
Interrupt to CPU
FIGURE 8-18: INTERRUPT LOGIC, PIC16C715
T0IF T0IE INTF INTE RBIF RBIE ADIF ADIE ADIF GIE Wakeup (If in SLEEP mode)
Interrupt to CPU
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8.5.1 INT INTERRUPT 8.5.2 TMR0 INTERRUPT External interrupt on RB0/INT pin is edge triggered: either rising if bit INTEDG (OPTION<6>) is set, or falling, if the INTEDG bit is clear. When a valid edge appears on the RB0/INT pin, flag bit INTF (INTCON<1>) is set. This interrupt can be disabled by clearing enable bit INTE (INTCON<4>). Flag bit INTF must be cleared in software in the interrupt service routine before re-enabling this interrupt. The INT interrupt can wake-up the processor from SLEEP, if bit INTE was set prior to going into SLEEP. The status of global interrupt enable bit GIE decides whether or not the processor branches to the interrupt vector following wake-up. See Section 8.8 for details on SLEEP mode. An overflow (FFh 00h) in the TMR0 register will set flag bit T0IF (INTCON<2>). The interrupt can be enabled/disabled by setting/clearing enable bit T0IE (INTCON<5>). (Section 6.0) 8.5.3 PORTB INTCON CHANGE
An input change on PORTB<7:4> sets flag bit RBIF (INTCON<0>). The interrupt can be enabled/disabled by setting/clearing enable bit RBIE (INTCON<4>). (Section 5.2) Note: For the PIC16C71 if a change on the I/O pin should occur when the read operation is being executed (start of the Q2 cycle), then the RBIF interrupt flag may not get set.
FIGURE 8-19: INT PIN INTERRUPT TIMING
Q1 OSC1 CLKOUT 3 INT pin INTF flag (INTCON<1>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC Instruction fetched Instruction executed PC Inst (PC) Inst (PC-1) PC+1 Inst (PC+1) Inst (PC) PC+1 -- Dummy Cycle 0004h Inst (0004h) Dummy Cycle 0005h Inst (0005h) Inst (0004h) 1 5 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
4 1 Interrupt Latency 2
Note 1: INTF flag is sampled here (every Q1). 2: Interrupt latency = 3-4 Tcy where Tcy = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. 3: CLKOUT is available only in RC oscillator mode. 4: For minimum width of INT pulse, refer to AC specs. 5: INTF is enabled to be set anytime during the Q4-Q1 cycles.
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8.6 Context Saving During Interrupts
During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt i.e., W register and STATUS register. This will have to be implemented in software. Example 8-1 stores and restores the STATUS and W registers. The user register, STATUS_TEMP, must be defined in bank 0. The example: a) b) c) d) e) Stores the W register. Stores the STATUS register in bank 0. Executes the ISR code. Restores the STATUS register (and bank select bit). Restores the W register.
EXAMPLE 8-1:
MOVWF SWAPF MOVWF : :(ISR) : SWAPF MOVWF SWAPF SWAPF
SAVING STATUS AND W REGISTERS IN RAM
W_TEMP STATUS,W STATUS_TEMP ;Copy W to TEMP register, could be bank one or zero ;Swap status to be saved into W ;Save status to bank zero STATUS_TEMP register
STATUS_TEMP,W STATUS W_TEMP,F W_TEMP,W
;Swap STATUS_TEMP register into W ;(sets bank to original state) ;Move W into STATUS register ;Swap W_TEMP ;Swap W_TEMP into W
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8.7 Watchdog Timer (WDT) 710 71 711 715 Applicable Devices
assigned to the WDT under software control by writing to the OPTION register. Thus, time-out periods up to 2.3 seconds can be realized. The CLRWDT and SLEEP instructions clear the WDT and the postscaler, if assigned to the WDT, and prevent it from timing out and generating a device RESET condition. The TO bit in the STATUS register will be cleared upon a Watchdog Timer time-out. 8.7.2 WDT PROGRAMMING CONSIDERATIONS
The Watchdog Timer is as a free running on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKIN pin. That means that the WDT will run, even if the clock on the OSC1/CLKIN and OSC2/CLKOUT pins of the device has been stopped, for example, by execution of a SLEEP instruction. During normal operation, a WDT time-out generates a device RESET (Watchdog Timer Reset). If the device is in SLEEP mode, a WDT time-out causes the device to wake-up and continue with normal operation (Watchdog Timer Wake-up). The WDT can be permanently disabled by clearing configuration bit WDTE (Section 8.1). 8.7.1 WDT PERIOD
It should also be taken into account that under worst case conditions (VDD = Min., Temperature = Max., and max. WDT prescaler) it may take several seconds before a WDT time-out occurs. Note: When a CLRWDT instruction is executed and the prescaler is assigned to the WDT, the prescaler count will be cleared, but the prescaler assignment is not changed.
The WDT has a nominal time-out period of 18 ms, (with no prescaler). The time-out periods vary with temperature, VDD and process variations from part to part (see DC specs). If longer time-out periods are desired, a prescaler with a division ratio of up to 1:128 can be
FIGURE 8-20: WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source (Figure 6-6) 0 WDT Timer 1 M U X Postscaler 8 8 - to - 1 MUX WDT Enable Bit PSA To TMR0 (Figure 6-6) 0 MUX 1 PSA PS2:PS0
Note: PSA and PS2:PS0 are bits in the OPTION register.
WDT Time-out
FIGURE 8-21: SUMMARY OF WATCHDOG TIMER REGISTERS
Address 2007h 81h,181h Name Config. bits OPTION Bit 7 (1) RBPU Bit 6 BODEN(1) INTEDG Bit 5 CP1 T0CS Bit 4 CP0 T0SE Bit 3 PWRTE(1) PSA Bit 2 WDTE PS2 Bit 1 FOSC1 PS1 Bit 0 FOSC0 PS0
Legend: Shaded cells are not used by the Watchdog Timer. Note 1: See Figure 8-1, Figure 8-2 and Figure 8-3 for operation of these bits.
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8.8 Power-down Mode (SLEEP)
Power-down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the PD bit (STATUS<3>) is cleared, the TO (STATUS<4>) bit is set, and the oscillator driver is turned off. The I/O ports maintain the status they had, before the SLEEP instruction was executed (driving high, low, or hi-impedance). For lowest current consumption in this mode, place all I/O pins at either VDD, or VSS, ensure no external circuitry is drawing current from the I/O pin, power-down the A/D, disable external clocks. Pull all I/O pins, that are hi-impedance inputs, high or low externally to avoid switching currents caused by floating inputs. The T0CKI input should also be at VDD or VSS for lowest current consumption. The contribution from on-chip pull-ups on PORTB should be considered. The MCLR pin must be at a logic high level (VIHMC). 8.8.1 WAKE-UP FROM SLEEP Other peripherals cannot generate interrupts since during SLEEP, no on-chip Q clocks are present. When the SLEEP instruction is being executed, the next instruction (PC + 1) is pre-fetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wake-up is regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is set (enabled), the device executes the instruction after the SLEEP instruction and then branches to the interrupt address (0004h). In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction. 8.8.2 WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: * If the interrupt occurs before the the execution of a SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT postscaler will not be cleared, the TO bit will not be set and PD bits will not be cleared. * If the interrupt occurs during or after the execution of a SLEEP instruction, the device will immediately wake up from sleep . The SLEEP instruction will be completely executed before the wake-up. Therefore, the WDT and WDT postscaler will be cleared, the TO bit will be set and the PD bit will be cleared. Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction.
The device can wake up from SLEEP through one of the following events: 1. 2. 3. External reset input on MCLR pin. Watchdog Timer Wake-up (if WDT was enabled). Interrupt from INT pin, RB port change, or some Peripheral Interrupts.
External MCLR Reset will cause a device reset. All other events are considered a continuation of program execution and cause a "wake-up". The TO and PD bits in the STATUS register can be used to determine the cause of device reset. The PD bit, which is set on power-up, is cleared when SLEEP is invoked. The TO bit is cleared if a WDT time-out occurred (and caused wake-up). The following peripheral interrupts can wake the device from SLEEP: 1. 2. TMR1 interrupt. Timer1 must be operating as an asynchronous counter. A/D conversion (when A/D clock source is RC).
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PIC16C71X
FIGURE 8-22: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 OSC1 CLKOUT(4) INT pin INTF flag (INTCON<1>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC Instruction fetched Instruction executed PC Inst(PC) = SLEEP Inst(PC - 1) PC+1 Inst(PC + 1) SLEEP PC+2 PC+2 Inst(PC + 2) Inst(PC + 1) Dummy cycle PC + 2 0004h Inst(0004h) Dummy cycle 0005h Inst(0005h) Inst(0004h) Processor in SLEEP Interrupt Latency (Note 2) TOST(2) Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Note 1: 2: 3: 4:
XT, HS or LP oscillator mode assumed. TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode. GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line. CLKOUT is not available in these osc modes, but shown here for timing reference.
8.9
Program Verification/Code Protection
If the code protection bit(s) have not been programmed, the on-chip program memory can be read out for verification purposes. Note: Microchip does not recommend code protecting windowed devices.
The device is placed into a program/verify mode by holding the RB6 and RB7 pins low while raising the MCLR (VPP) pin from VIL to VIHH (see programming specification). RB6 becomes the programming clock and RB7 becomes the programming data. Both RB6 and RB7 are Schmitt Trigger inputs in this mode. After reset, to place the device into programming/verify mode, the program counter (PC) is at location 00h. A 6bit command is then supplied to the device. Depending on the command, 14-bits of program data are then supplied to or from the device, depending if the command was a load or a read. For complete details of serial programming, please refer to the PIC16C6X/7X Programming Specifications (Literature #DS30228).
8.10
ID Locations
Four memory locations (2000h - 2003h) are designated as ID locations where the user can store checksum or other code-identification numbers. These locations are not accessible during normal execution but are readable and writable during program/verify. It is recommended that only the 4 least significant bits of the ID location are used.
8.11
In-Circuit Serial Programming
FIGURE 8-23: TYPICAL IN-CIRCUIT SERIAL PROGRAMMING CONNECTION
To Normal Connections PIC16CXX VDD VSS MCLR/VPP RB6 RB7
PIC16CXX microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for power, ground, and the programming voltage. This allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed.
External Connector Signals +5V 0V VPP CLK Data I/O
VDD To Normal Connections
(c) 1997 Microchip Technology Inc.
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PIC16C71X
NOTES:
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PIC16C71X
9.0 INSTRUCTION SET SUMMARY
Each PIC16CXX instruction is a 14-bit word divided into an OPCODE which specifies the instruction type and one or more operands which further specify the operation of the instruction. The PIC16CXX instruction set summary in Table 9-2 lists byte-oriented, bit-oriented, and literal and control operations. Table 9-1 shows the opcode field descriptions. For byte-oriented instructions, 'f' represents a file register designator and 'd' represents a destination designator. The file register designator specifies which file register is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If 'd' is zero, the result is placed in the W register. If 'd' is one, the result is placed in the file register specified in the instruction. For bit-oriented instructions, 'b' represents a bit field designator which selects the number of the bit affected by the operation, while 'f' represents the number of the file in which the bit is located. For literal and control operations, 'k' represents an eight or eleven bit constant or literal value. * Byte-oriented operations * Bit-oriented operations * Literal and control operations All instructions are executed within one single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. In this case, the execution takes two instruction cycles with the second cycle executed as a NOP. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 s. If a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 s. Table 9-2 lists the instructions recognized by the MPASM assembler. Figure 9-1 shows the general formats that the instructions can have. Note: To maintain upward compatibility with future PIC16CXX products, do not use the OPTION and TRIS instructions.
All examples use the following format to represent a hexadecimal number: 0xhh where h signifies a hexadecimal digit.
TABLE 9-1:
Field
f W b k x
OPCODE FIELD DESCRIPTIONS
Description
FIGURE 9-1:
Register file address (0x00 to 0x7F) Working register (accumulator) Bit address within an 8-bit file register Literal field, constant data or label Don't care location (= 0 or 1) The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. d Destination select; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1 label Label name TOS Top of Stack PC Program Counter
PCLATH Program Counter High Latch
GENERAL FORMAT FOR INSTRUCTIONS
0
Byte-oriented file register operations 13 876 OPCODE d f (FILE #) d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 76 OPCODE b (BIT #) f (FILE #) b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 OPCODE k = 8-bit immediate value CALL and GOTO instructions only 13 11 OPCODE 10 k (literal) 8 7 k (literal)
0
GIE WDT TO PD dest []
Global Interrupt Enable bit Watchdog Timer/Counter Time-out bit Power-down bit Destination either the W register or the specified register file location Options Contents Assigned to Register bit field In the set of User defined term (font is courier)
0
() <> italics
0
k = 11-bit immediate value
The instruction set is highly orthogonal and is grouped into three basic categories:
(c) 1997 Microchip Technology Inc.
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PIC16C71X
TABLE 9-2:
Mnemonic, Operands
PIC16CXX INSTRUCTION SET
Description Cycles MSb 14-Bit Opcode LSb Status Affected Notes
BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Swap nibbles in f Exclusive OR W with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff C,DC,Z Z Z Z Z Z Z Z Z 1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2
C C C,DC,Z Z
1,2 1,2 1,2 1,2 1,2
BIT-ORIENTED FILE REGISTER OPERATIONS BCF BSF BTFSC BTFSS f, b f, b f, b f, b Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set 1 1 1 (2) 1 (2) 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 1,2 1,2 3 3
LITERAL AND CONTROL OPERATIONS ADDLW ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW k k k k k k k k k Add literal and W AND literal with W Call subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into standby mode Subtract W from literal Exclusive OR literal with W 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk C,DC,Z Z TO,PD Z
TO,PD C,DC,Z Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 Module. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP.
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PIC16C71X
9.1
ADDLW Syntax: Operands: Operation: Status Affected: Encoding: Description:
Instruction Descriptions
Add Literal and W [label] ADDLW 0 k 255 (W) + k (W) C, DC, Z
11 111x kkkk kkkk The contents of the W register are added to the eight bit literal 'k' and the result is placed in the W register.
ANDLW Syntax: Operands: Operation: Status Affected: Encoding: Description:
AND Literal with W [label] ANDLW 0 k 255 (W) .AND. (k) (W) Z
11 1001 kkkk kkkk The contents of W register are AND'ed with the eight bit literal 'k'. The result is placed in the W register.
k
k
Words: Cycles: Q Cycle Activity:
1 1 Q1
Decode
Words: Cycles: Q2
Read literal 'k'
1 1 Q1
Decode
Q3
Process data
Q4
Write to W
Q Cycle Activity:
Q2
Read literal "k"
Q3
Process data
Q4
Write to W
Example:
ADDLW
0x15 W W = = 0x10 0x25
Example
ANDLW W W
0x5F = = 0xA3 0x03
Before Instruction After Instruction
Before Instruction After Instruction
ADDWF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Add W and f [label] ADDWF 0 f 127 d [0,1] (W) + (f) (dest) C, DC, Z
00 0111 dfff ffff Add the contents of the W register with register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'.
ANDWF f,d Syntax: Operands: Operation: Status Affected: Encoding: Description:
AND W with f [label] ANDWF 0 f 127 d [0,1] (W) .AND. (f) (dest) Z
00 0101 dfff ffff AND the W register with register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'.
f,d
Words: Cycles: Q Cycle Activity:
1 1 Q1
Decode
Words: Cycles: Q2
Read register 'f'
1 1 Q1
Decode
Q3
Process data
Q4
Write to Dest
Q Cycle Activity:
Q2
Read register 'f'
Q3
Process data
Q4
Write to Dest
Example
ADDWF
FSR, 0 W= FSR = 0x17 0xC2 0xD9 0xC2
Example
ANDWF
FSR, 1 W= FSR = 0x17 0xC2 0x17 0x02
Before Instruction
Before Instruction
After Instruction
W= FSR =
After Instruction
W= FSR =
(c) 1997 Microchip Technology Inc.
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PIC16C71X
BCF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: 1 1 Q1
Decode
Bit Clear f [label] BCF 0 f 127 0b7 0 (f) None
01 00bb bfff ffff Bit 'b' in register 'f' is cleared.
BTFSC f,b Syntax: Operands: Operation: Status Affected: Encoding: Description:
Bit Test, Skip if Clear [label] BTFSC f,b 0 f 127 0b7 skip if (f) = 0 None
01 10bb bfff ffff If bit 'b' in register 'f' is '1' then the next instruction is executed. If bit 'b', in register 'f', is '0' then the next instruction is discarded, and a NOP is executed instead, making this a 2TCY instruction.
Q2
Read register 'f'
Q3
Process data
Q4
Write register 'f'
Words: Cycles: Q Cycle Activity:
1 1(2) Q1
Decode
Example
BCF
FLAG_REG, 7 FLAG_REG = 0xC7
Q2
Read register 'f'
Q3
Process data
Q4
NOP
Before Instruction After Instruction
FLAG_REG = 0x47
If Skip:
(2nd Cycle) Q1 Q2
NOP NOP
Q3
NOP
Q4
NOP
Example
HERE FALSE TRUE
BTFSC GOTO * * * PC =
FLAG,1 PROCESS_CODE
Before Instruction
address HERE
After Instruction BSF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: 1 1 Q1
Decode
Bit Set f [label] BSF 0 f 127 0b7 1 (f) None
01 01bb bfff ffff Bit 'b' in register 'f' is set.
f,b
if FLAG<1> = 0, PC = address TRUE if FLAG<1>=1, PC = address FALSE
Q2
Read register 'f'
Q3
Process data
Q4
Write register 'f'
Example
BSF
FLAG_REG,
7
Before Instruction
FLAG_REG = 0x0A
After Instruction
FLAG_REG = 0x8A
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PIC16C71X
BTFSS Syntax: Operands: Operation: Status Affected: Encoding: Description: Bit Test f, Skip if Set [label] BTFSS f,b 0 f 127 0b<7 skip if (f) = 1 None
01 11bb bfff ffff
CALL Syntax: Operands: Operation:
Call Subroutine [ label ] CALL k 0 k 2047 (PC)+ 1 TOS, k PC<10:0>, (PCLATH<4:3>) PC<12:11> None
10 0kkk kkkk kkkk Call Subroutine. First, return address (PC+1) is pushed onto the stack. The eleven bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH. CALL is a two cycle instruction.
Status Affected: Encoding: Description:
If bit 'b' in register 'f' is '0' then the next instruction is executed. If bit 'b' is '1', then the next instruction is discarded and a NOP is executed instead, making this a 2TCY instruction.
Words: Cycles: Q Cycle Activity:
1 1(2) Q1
Decode
Words: Q2
Read register 'f'
1 2 Q1
Decode
Q3
Process data
Q4
NOP
Cycles: Q Cycle Activity: 1st Cycle
Q2
Read literal 'k', Push PC to Stack NOP
Q3
Process data
Q4
Write to PC
If Skip:
(2nd Cycle) Q1 Q2
NOP NOP
Q3
NOP
Q4
NOP
2nd Cycle Example
NOP
NOP
NOP
Example
HERE FALSE TRUE
BTFSC GOTO * * * PC =
FLAG,1 PROCESS_CODE
HERE
CALL
THERE
Before Instruction
PC = Address HERE
After Instruction
address HERE PC = Address THERE TOS = Address HERE+1
Before Instruction After Instruction
if FLAG<1> = 0, PC = address FALSE if FLAG<1> = 1, PC = address TRUE
(c) 1997 Microchip Technology Inc.
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PIC16C71X
CLRF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Clear f [label] CLRF 0 f 127 00h (f) 1Z Z
00 0001 1fff ffff The contents of register 'f' are cleared and the Z bit is set.
CLRW f Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles:
Clear W [ label ] CLRW None 00h (W) 1Z Z
00 0001 0xxx xxxx W register is cleared. Zero bit (Z) is set.
1 1 Q1
Decode
1 1 Q1
Decode
Q2
Read register 'f'
Q3
Process data
Q4
Write register 'f'
Q Cycle Activity:
Q2
NOP
Q3
Process data
Q4
Write to W
Example
CLRF
FLAG_REG FLAG_REG = = = 0x5A 0x00 1
Example
CLRW
Before Instruction After Instruction
FLAG_REG Z
Before Instruction
W W Z = = = 0x5A 0x00 1
After Instruction
CLRWDT Syntax: Operands: Operation:
Clear Watchdog Timer [ label ] CLRWDT None 00h WDT 0 WDT prescaler, 1 TO 1 PD TO, PD
00 0000 0110 0100 CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set.
Status Affected: Encoding: Description:
Words: Cycles: Q Cycle Activity:
1 1 Q1
Decode
Q2
NOP
Q3
Process data
Q4
Clear WDT Counter
Example
CLRWDT
Before Instruction
WDT counter = ? 0x00 0 1 1
After Instruction
WDT counter = WDT prescaler= TO = PD =
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PIC16C71X
COMF Syntax: Operands: Operation: Status Affected: Encoding: Description: Complement f [ label ] COMF 0 f 127 d [0,1] (f) (dest) Z
00 1001 dfff ffff The contents of register 'f' are complemented. If 'd' is 0 the result is stored in W. If 'd' is 1 the result is stored back in register 'f'.
DECFSZ f,d Syntax: Operands: Operation: Status Affected: Encoding: Description:
Decrement f, Skip if 0 [ label ] DECFSZ f,d 0 f 127 d [0,1] (f) - 1 (dest); None
00 1011 dfff ffff
The contents of register 'f' are decremented. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. If the result is 1, the next instruction, is executed. If the result is 0, then a NOP is executed instead making it a 2TCY instruction.
skip if result = 0
Words: Cycles: Q Cycle Activity:
1 1 Q1
Decode
Q2
Read register 'f'
Q3
Process data
Q4
Write to dest
Words: Cycles: Q Cycle Activity:
1 1(2) Q1
Decode
Q2
Read register 'f'
Q3
Process data
Q4
Write to dest
Example
COMF
REG1,0 REG1 = = = 0x13 0x13 0xEC
Before Instruction If Skip: After Instruction
REG1 W
(2nd Cycle) Q1 Q2
NOP NOP
Q3
NOP
Q4
NOP
DECF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Decrement f [label] DECF f,d 0 f 127 d [0,1] (f) - 1 (dest) Z
00 0011 dfff ffff Decrement register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'.
Example
HERE
DECFSZ GOTO CONTINUE * * *
CNT, 1 LOOP
Before Instruction
PC =
address HERE CNT - 1 0, address CONTINUE 0, address HERE+1
After Instruction
CNT if CNT PC if CNT PC = = = =
Words: Cycles: Q Cycle Activity:
1 1 Q1
Decode
Q2
Read register 'f'
Q3
Process data
Q4
Write to dest
Example
DECF
CNT, 1 CNT Z = = = = 0x01 0 0x00 1
Before Instruction
After Instruction
CNT Z
(c) 1997 Microchip Technology Inc.
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PIC16C71X
GOTO Syntax: Operands: Operation: Status Affected: Encoding: Description: Unconditional Branch [ label ] GOTO k 0 k 2047 k PC<10:0> PCLATH<4:3> PC<12:11> None
10 1kkk kkkk kkkk GOTO is an unconditional branch. The eleven bit immediate value is loaded into PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a two cycle instruction.
INCF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Increment f [ label ] INCF f,d 0 f 127 d [0,1] (f) + 1 (dest) Z
00 1010 dfff ffff The contents of register 'f' are incremented. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'.
Words: Cycles: Q Cycle Activity: 1st Cycle 2nd Cycle Example
1 2 Q1
Decode NOP
Words: Cycles: Q2
Read literal 'k' NOP
1 1 Q1
Decode
Q3
Process data NOP
Q4
Write to PC NOP
Q Cycle Activity:
Q2
Read register 'f'
Q3
Process data
Q4
Write to dest
Example
GOTO THERE
INCF
CNT, 1 CNT Z = = = = 0xFF 0 0x00 1
Before Instruction
Address THERE
After Instruction
PC =
After Instruction
CNT Z
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PIC16C71X
INCFSZ Syntax: Operands: Operation: Status Affected: Encoding: Description: Increment f, Skip if 0 [ label ] INCFSZ f,d 0 f 127 d [0,1] (f) + 1 (dest), skip if result = 0 None
00 1111 dfff ffff The contents of register 'f' are incremented. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. If the result is 1, the next instruction is executed. If the result is 0, a NOP is executed instead making it a 2TCY instruction.
IORLW Syntax: Operands: Operation: Status Affected: Encoding: Description:
Inclusive OR Literal with W [ label ] IORLW k 0 k 255 (W) .OR. k (W) Z
11 1000 kkkk kkkk The contents of the W register is OR'ed with the eight bit literal 'k'. The result is placed in the W register.
Words: Cycles: Q Cycle Activity:
1 1 Q1
Decode
Q2
Read literal 'k'
Q3
Process data
Q4
Write to W
Words: Cycles: Q Cycle Activity:
1 1(2) Q1
Decode
Q2
Read register 'f'
Q3
Process data
Q4
Write to dest
Example
IORLW W W Z
0x35 = = = 0x9A 0xBF 1
Before Instruction After Instruction
If Skip:
(2nd Cycle) Q1 Q2
NOP NOP
Q3
NOP
Q4
NOP
Example
INCFSZ GOTO CONTINUE * * *
HERE
CNT, 1 LOOP
Before Instruction
PC = address HERE CNT + 1 0, address CONTINUE 0, address HERE +1
After Instruction
CNT = if CNT= PC = if CNT PC =
(c) 1997 Microchip Technology Inc.
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PIC16C71X
IORWF Syntax: Operands: Operation: Status Affected: Encoding: Description: Inclusive OR W with f [ label ] IORWF f,d 0 f 127 d [0,1] (W) .OR. (f) (dest) Z
00 0100 dfff ffff Inclusive OR the W register with register 'f'. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'.
MOVLW Syntax: Operands: Operation: Status Affected: Encoding: Description:
Move Literal to W [ label ] k (W) None
11 00xx kkkk kkkk The eight bit literal 'k' is loaded into W register. The don't cares will assemble as 0's.
MOVLW k
0 k 255
Words: Cycles: Q Cycle Activity:
1 1 Q1
Decode
Words: Cycles: Q Cycle Activity:
1 1 Q1
Decode
Q2
Read literal 'k'
Q3
Process data
Q4
Write to W
Q2
Read register 'f'
Q3
Process data
Q4
Write to dest
Example
RESULT, 0
MOVLW W
0x5A = 0x5A
Example
IORWF
After Instruction
Before Instruction
RESULT = W = 0x13 0x91 0x13 0x93 1
After Instruction
RESULT = W = Z =
MOVF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Move f [ label ] MOVF f,d 0 f 127 d [0,1] (f) (dest) Z
00 1000 dfff ffff The contents of register f is moved to a destination dependant upon the status of d. If d = 0, destination is W register. If d = 1, the destination is file register f itself. d = 1 is useful to test a file register since status flag Z is affected.
MOVWF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity:
Move W to f [ label ] (W) (f) None
00 0000 1fff ffff Move data from W register to register 'f'.
MOVWF
f
0 f 127
1 1 Q1
Decode
Q2
Read register 'f'
Q3
Process data
Q4
Write register 'f'
Words: Cycles: Q Cycle Activity:
1 1 Q1
Decode
Example Q2
Read register 'f'
MOVWF
OPTION_REG OPTION = W = 0xFF 0x4F 0x4F 0x4F
Q3
Process data
Q4
Write to dest
Before Instruction
After Instruction
OPTION = W =
Example
MOVF
FSR, 0 W = value in FSR register Z =1
After Instruction
DS30272A-page 78
(c) 1997 Microchip Technology Inc.
PIC16C71X
NOP Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: 1 1 Q1
Decode
No Operation [ label ] None No operation None
00 0000 0xx0 0000
RETFIE Syntax: Operands: Operation: Status Affected: Encoding: Description:
Return from Interrupt [ label ] None TOS PC, 1 GIE None
00 0000 0000 1001 Return from Interrupt. Stack is POPed and Top of Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two cycle instruction.
NOP
RETFIE
No operation.
Q2
NOP
Q3
NOP
Q4
NOP
Words: Example
NOP
1 2 Q1
Decode NOP
Cycles: Q Cycle Activity: 1st Cycle 2nd Cycle Example
Q2
NOP NOP
Q3
Set the GIE bit NOP
Q4
Pop from the Stack NOP
RETFIE
After Interrupt
PC = GIE = TOS 1
OPTION Syntax: Operands: Operation: Encoding: Description:
Load Option Register [ label ] None (W) OPTION
00 0000 0110 0010
OPTION
Status Affected: None
The contents of the W register are loaded in the OPTION register. This instruction is supported for code compatibility with PIC16C5X products. Since OPTION is a readable/writable register, the user can directly address it.
Words: Cycles: Example
1 1
To maintain upward compatibility with future PIC16CXX products, do not use this instruction.
(c) 1997 Microchip Technology Inc.
DS30272A-page 79
PIC16C71X
RETLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Return with Literal in W [ label ] RETLW k 0 k 255 k (W); TOS PC None
11 01xx kkkk kkkk The W register is loaded with the eight bit literal 'k'. The program counter is loaded from the top of the stack (the return address). This is a two cycle instruction.
RETURN Syntax: Operands: Operation: Status Affected: Encoding: Description:
Return from Subroutine [ label ] None TOS PC None
00 0000 0000 1000 Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two cycle instruction.
RETURN
Words: Cycles: Q Cycle Activity: 1st Cycle 2nd Cycle Example
1 2 Q1
Decode NOP
Words: Cycles: Q Cycle Activity: 1st Cycle
1 2 Q1
Decode
Q2
NOP NOP
Q3
NOP NOP
Q4
Pop from the Stack NOP
Q2
Read literal 'k'
Q3
NOP
Q4
Write to W, Pop from the Stack NOP
RETURN
2nd Cycle Example
NOP
NOP
NOP
After Interrupt
PC = TOS
CALL TABLE
* * *
TABLE ADDWF PC RETLW k1 RETLW k2
;W contains table ;offset value ;W now has table value
;W = offset ;Begin table ;
* * *
RETLW kn ; End of table
Before Instruction
W W = = 0x07 value of k8
After Instruction
DS30272A-page 80
(c) 1997 Microchip Technology Inc.
PIC16C71X
RLF Syntax: Operands: Operation: Status Affected: Encoding: Description: Rotate Left f through Carry [ label ] 0 f 127 d [0,1] See description below C
00 1101 dfff ffff The contents of register 'f' are rotated one bit to the left through the Carry Flag. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is stored back in register 'f'. C Register f
RRF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Rotate Right f through Carry [ label ] RRF f,d 0 f 127 d [0,1] See description below C
00 1100 dfff ffff The contents of register 'f' are rotated one bit to the right through the Carry Flag. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. C Register f
RLF
f,d
Words: Cycles: Q Cycle Activity:
1 1 Q1
Decode
Words: Cycles: Q2
Read register 'f'
1 1 Q1
Decode
Q3
Process data
Q4
Write to dest
Q Cycle Activity:
Q2
Read register 'f'
Q3
Process data
Q4
Write to dest
Example
RLF
REG1,0 REG1 C = = = = = 1110 0110 0 1110 0110 1100 1100 1
Example
RRF REG1 C
REG1,0 = = = = = 1110 0110 0 1110 0110 0111 0011 0
Before Instruction
Before Instruction
After Instruction
REG1 W C
After Instruction
REG1 W C
(c) 1997 Microchip Technology Inc.
DS30272A-page 81
PIC16C71X
SLEEP Syntax: Operands: Operation: [ label ] None 00h WDT, 0 WDT prescaler, 1 TO, 0 PD TO, PD
00 0000 0110 0011 The power-down status bit, PD is cleared. Time-out status bit, TO is set. Watchdog Timer and its prescaler are cleared. The processor is put into SLEEP mode with the oscillator stopped. See Section 8.8 for more details.
SUBLW SLEEP Syntax: Operands: Operation: Status Affected: Encoding: Description:
Subtract W from Literal [ label ] 0 k 255 k - (W) (W) C, DC, Z 11 110x kkkk kkkk
The W register is subtracted (2's complement method) from the eight bit literal 'k'. The result is placed in the W register.
SUBLW k
Status Affected: Encoding: Description:
Words: Cycles: Q Cycle Activity:
1 1 Q1
Decode
Q2
Read literal 'k'
Q3
Process data
Q4
Write to W
Words: Cycles: Q Cycle Activity:
1 1 Q1
Decode
Example 1: Q2
NOP
SUBLW
0x02
W C Z = = = 1 ? ?
Before Instruction Q3
NOP
Q4
Go to Sleep
After Instruction Example: SLEEP
W C Z = = = 1 1; result is positive 0
Example 2:
Before Instruction
W C Z = = = 2 ? ?
After Instruction
W C Z = = = 0 1; result is zero 1
Example 3:
Before Instruction
W C Z = = = 3 ? ?
After Instruction
W= C = tive Z = 0xFF 0; result is nega0
DS30272A-page 82
(c) 1997 Microchip Technology Inc.
PIC16C71X
SUBWF Syntax: Operands: Operation: Encoding: Description: Subtract W from f [ label ] 0 f 127 d [0,1] (f) - (W) (dest) 00 0010 dfff ffff SUBWF f,d SWAPF Syntax: Operands: Operation: Status Affected: Encoding: Description: Swap Nibbles in f [ label ] SWAPF f,d 0 f 127 d [0,1] (f<3:0>) (dest<7:4>), (f<7:4>) (dest<3:0>) None
00
Status Affected: C, DC, Z
Subtract (2's complement method) W register from register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'.
1110
dfff
ffff
Words: Cycles: Q Cycle Activity:
1 1 Q1
Decode
The upper and lower nibbles of register 'f' are exchanged. If 'd' is 0 the result is placed in W register. If 'd' is 1 the result is placed in register 'f'.
Words: Q2
Read register 'f'
1 1 Q1
Decode
Q3
Process data
Q4
Write to dest
Cycles: Q Cycle Activity:
Q2
Read register 'f'
Q3
Process data
Q4
Write to dest
Example 1:
SUBWF
REG1 W C Z
REG1,1 Example
3 2 ? ? SWAPF REG, 0 = = = =
Before Instruction
Before Instruction
REG1 = 0xA5
After Instruction
REG1 W = = 0xA5 0x5A
After Instruction
REG1 W C Z = = = = 1 2 1; result is positive 0
Example 2:
Before Instruction
REG1 W C Z = = = = 2 2 ? ?
TRIS Syntax: Operands: Operation: Encoding: Description:
Load TRIS Register [label] 5f7 (W) TRIS register f;
00
TRIS
f
After Instruction
REG1 W C Z = = = = 0 2 1; result is zero 1
Status Affected: None 0000 0110 0fff
The instruction is supported for code compatibility with the PIC16C5X products. Since TRIS registers are readable and writable, the user can directly address them.
Example 3:
Before Instruction
REG1 W C Z = = = = 1 2 ? ?
Words: Cycles: Example
1 1
To maintain upward compatibility with future PIC16CXX products, do not use this instruction.
After Instruction
REG1 W C Z = = = = 0xFF 2 0; result is negative 0
(c) 1997 Microchip Technology Inc.
DS30272A-page 83
PIC16C71X
XORLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Exclusive OR Literal with W [label] XORLW k 0 k 255 (W) .XOR. k (W) Z 11 1010 kkkk kkkk
The contents of the W register are XOR'ed with the eight bit literal 'k'. The result is placed in the W register.
XORWF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Exclusive OR W with f [label] XORWF f,d 0 f 127 d [0,1] (W) .XOR. (f) (dest) Z
00 0110 dfff ffff Exclusive OR the contents of the W register with register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'.
Words: Cycles: Q Cycle Activity:
1 1 Q1
Decode
Words: Q2
Read literal 'k'
1 1 Q1
Decode
Q3
Process data
Q4
Write to W
Cycles: Q Cycle Activity:
Q2
Read register 'f'
Q3
Process data
Q4
Write to dest
Example:
XORLW
0xAF
W = 0xB5
Before Instruction Example XORWF
REG 1
After Instruction
W = 0x1A
Before Instruction
REG W = = 0xAF 0xB5
After Instruction
REG W = = 0x1A 0xB5
DS30272A-page 84
(c) 1997 Microchip Technology Inc.
PIC16C71X
10.0
10.1
DEVELOPMENT SUPPORT
Development Tools
10.3
ICEPIC: Low-Cost PIC16CXXX In-Circuit Emulator
The PICmicrTM microcontrollers are supported with a full range of hardware and software development tools: * PICMASTER/PICMASTER CE Real-Time In-Circuit Emulator * ICEPIC Low-Cost PIC16C5X and PIC16CXXX In-Circuit Emulator * PRO MATE(R) II Universal Programmer * PICSTART(R) Plus Entry-Level Prototype Programmer * PICDEM-1 Low-Cost Demonstration Board * PICDEM-2 Low-Cost Demonstration Board * PICDEM-3 Low-Cost Demonstration Board * MPASM Assembler * MPLABTM SIM Software Simulator * MPLAB-C (C Compiler) * Fuzzy Logic Development System (fuzzyTECH(R)-MP)
ICEPIC is a low-cost in-circuit emulator solution for the Microchip PIC16C5X and PIC16CXXX families of 8-bit OTP microcontrollers. ICEPIC is designed to operate on PC-compatible machines ranging from 286-AT(R) through PentiumTM based machines under Windows 3.x environment. ICEPIC features real time, non-intrusive emulation.
10.4
PRO MATE II: Universal Programmer
The PRO MATE II Universal Programmer is a full-featured programmer capable of operating in stand-alone mode as well as PC-hosted mode. The PRO MATE II has programmable VDD and VPP supplies which allows it to verify programmed memory at VDD min and VDD max for maximum reliability. It has an LCD display for displaying error messages, keys to enter commands and a modular detachable socket assembly to support various package types. In standalone mode the PRO MATE II can read, verify or program PIC12CXXX, PIC14C000, PIC16C5X, PIC16CXXX and PIC17CXX devices. It can also set configuration and code-protect bits in this mode.
10.2
PICMASTER: High Performance Universal In-Circuit Emulator with MPLAB IDE
The PICMASTER Universal In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for all microcontrollers in the PIC12CXXX, PIC14C000, PIC16C5X, PIC16CXXX and PIC17CXX families. PICMASTER is supplied with the MPLABTM Integrated Development Environment (IDE), which allows editing, "make" and download, and source debugging from a single environment. Interchangeable target probes allow the system to be easily reconfigured for emulation of different processors. The universal architecture of the PICMASTER allows expansion to support all new Microchip microcontrollers. The PICMASTER Emulator System has been designed as a real-time emulation system with advanced features that are generally found on more expensive development tools. The PC compatible 386 (and higher) machine platform and Microsoft Windows(R) 3.x environment were chosen to best make these features available to you, the end user. A CE compliant version of PICMASTER is available for European Union (EU) countries.
10.5
PICSTART Plus Entry Level Development System
The PICSTART programmer is an easy-to-use, lowcost prototype programmer. It connects to the PC via one of the COM (RS-232) ports. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. PICSTART Plus is not recommended for production programming. PICSTART Plus supports all PIC12CXXX, PIC14C000, PIC16C5X, PIC16CXXX and PIC17CXX devices with up to 40 pins. Larger pin count devices such as the PIC16C923 and PIC16C924 may be supported with an adapter socket.
(c) 1997 Microchip Technology Inc.
DS30272A-page 85
PIC16C71X
10.6 PICDEM-1 Low-Cost PIC16/17 Demonstration Board
an RS-232 interface, push-button switches, a potentiometer for simulated analog input, a thermistor and separate headers for connection to an external LCD module and a keypad. Also provided on the PICDEM-3 board is an LCD panel, with 4 commons and 12 segments, that is capable of displaying time, temperature and day of the week. The PICDEM-3 provides an additional RS-232 interface and Windows 3.1 software for showing the demultiplexed LCD signals on a PC. A simple serial interface allows the user to construct a hardware demultiplexer for the LCD signals.
The PICDEM-1 is a simple board which demonstrates the capabilities of several of Microchip's microcontrollers. The microcontrollers supported are: PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs. The users can program the sample microcontrollers provided with the PICDEM-1 board, on a PRO MATE II or PICSTART-Plus programmer, and easily test firmware. The user can also connect the PICDEM-1 board to the PICMASTER emulator and download the firmware to the emulator for testing. Additional prototype area is available for the user to build some additional hardware and connect it to the microcontroller socket(s). Some of the features include an RS-232 interface, a potentiometer for simulated analog input, push-button switches and eight LEDs connected to PORTB.
10.9
MPLAB Integrated Development Environment Software
The MPLAB IDE Software brings an ease of software development previously unseen in the 8-bit microcontroller market. MPLAB is a windows based application which contains: * A full featured editor * Three operating modes - editor - emulator - simulator * A project manager * Customizable tool bar and key mapping * A status bar with project information * Extensive on-line help MPLAB allows you to: * Edit your source files (either assembly or `C') * One touch assemble (or compile) and download to PIC16/17 tools (automatically updates all project information) * Debug using: - source files - absolute listing file * Transfer data dynamically via DDE (soon to be replaced by OLE) * Run up to four emulators on the same PC The ability to use MPLAB with Microchip's simulator allows a consistent platform and the ability to easily switch from the low cost simulator to the full featured emulator with minimal retraining due to development tools.
10.7
PICDEM-2 Low-Cost PIC16CXX Demonstration Board
The PICDEM-2 is a simple demonstration board that supports the PIC16C62, PIC16C64, PIC16C65, PIC16C73 and PIC16C74 microcontrollers. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM-2 board, on a PRO MATE II programmer or PICSTART-Plus, and easily test firmware. The PICMASTER emulator may also be used with the PICDEM-2 board to test firmware. Additional prototype area has been provided to the user for adding additional hardware and connecting it to the microcontroller socket(s). Some of the features include a RS-232 interface, push-button switches, a potentiometer for simulated analog input, a Serial EEPROM to demonstrate usage of the I2C bus and separate headers for connection to an LCD module and a keypad.
10.8
PICDEM-3 Low-Cost PIC16CXXX Demonstration Board
The PICDEM-3 is a simple demonstration board that supports the PIC16C923 and PIC16C924 in the PLCC package. It will also support future 44-pin PLCC microcontrollers with a LCD Module. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM-3 board, on a PRO MATE II programmer or PICSTART Plus with an adapter socket, and easily test firmware. The PICMASTER emulator may also be used with the PICDEM-3 board to test firmware. Additional prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket(s). Some of the features include
10.10
Assembler (MPASM)
The MPASM Universal Macro Assembler is a PChosted symbolic assembler. It supports all microcontroller series including the PIC12C5XX, PIC14000, PIC16C5X, PIC16CXXX, and PIC17CXX families. MPASM offers full featured Macro capabilities, conditional assembly, and several source and listing formats. It generates various object code formats to support Microchip's development tools as well as third party programmers. MPASM allows full symbolic debugging from PICMASTER, Microchip's Universal Emulator System.
DS30272A-page 86
(c) 1997 Microchip Technology Inc.
PIC16C71X
MPASM has the following features to assist in developing software for specific use applications. * Provides translation of Assembler source code to object code for all Microchip microcontrollers. * Macro assembly capability. * Produces all the files (Object, Listing, Symbol, and special) required for symbolic debug with Microchip's emulator systems. * Supports Hex (default), Decimal and Octal source and listing formats. MPASM provides a rich directive language to support programming of the PIC16/17. Directives are helpful in making the development of your assemble source code shorter and more maintainable.
10.14
MP-DriveWayTM - Application Code Generator
MP-DriveWay is an easy-to-use Windows-based Application Code Generator. With MP-DriveWay you can visually configure all the peripherals in a PIC16/17 device and, with a click of the mouse, generate all the initialization and many functional code modules in C language. The output is fully compatible with Microchip's MPLAB-C C compiler. The code produced is highly modular and allows easy integration of your own code. MP-DriveWay is intelligent enough to maintain your code through subsequent code generation.
10.15
SEEVAL(R) Evaluation and Programming System
10.11
Software Simulator (MPLAB-SIM)
The MPLAB-SIM Software Simulator allows code development in a PC host environment. It allows the user to simulate the PIC16/17 series microcontrollers on an instruction level. On any given instruction, the user may examine or modify any of the data areas or provide external stimulus to any of the pins. The input/ output radix can be set by the user and the execution can be performed in; single step, execute until break, or in a trace mode. MPLAB-SIM fully supports symbolic debugging using MPLAB-C and MPASM. The Software Simulator offers the low cost flexibility to develop and debug code outside of the laboratory environment making it an excellent multi-project software development tool.
The SEEVAL SEEPROM Designer's Kit supports all Microchip 2-wire and 3-wire Serial EEPROMs. The kit includes everything necessary to read, write, erase or program special features of any Microchip SEEPROM product including Smart SerialsTM and secure serials. The Total EnduranceTM Disk is included to aid in tradeoff analysis and reliability calculations. The total kit can significantly reduce time-to-market and result in an optimized system.
10.16
KEELOQ(R) Evaluation and Programming Tools
10.12
C Compiler (MPLAB-C)
KEELOQ evaluation and programming tools support Microchips HCS Secure Data Products. The HCS evaluation kit includes an LCD display to show changing codes, a decoder to decode transmissions, and a programming interface to program test transmitters.
The MPLAB-C Code Development System is a complete `C' compiler and integrated development environment for Microchip's PIC16/17 family of microcontrollers. The compiler provides powerful integration capabilities and ease of use not found with other compilers. For easier source level debugging, the compiler provides symbol information that is compatible with the MPLAB IDE memory display.
10.13
Fuzzy Logic Development System (fuzzyTECH-MP)
fuzzyTECH-MP fuzzy logic development tool is available in two versions - a low cost introductory version, MP Explorer, for designers to gain a comprehensive working knowledge of fuzzy logic system design; and a full-featured version, fuzzyTECH-MP, edition for implementing more complex systems.
Both versions include Microchip's fuzzyLABTM demonstration board for hands-on experience with fuzzy logic systems implementation.
(c) 1997 Microchip Technology Inc.
DS30272A-page 87
TABLE 10-1:
PIC12C5XX
PIC14000
PIC16C5X
PIC16CXXX
PIC16C6X PIC16C7XX PIC16C8X PIC16C9XX PIC17C4X
PIC17C75X
24CXX 25CXX 93CXX
HCS200 HCS300 HCS301
Emulator Products
Software Tools
Programmers
(c) 1997 Microchip Technology Inc.
Demo Boards
DS30272A-page 88
Available 3Q97
PICMASTER(R)/ PICMASTER-CE In-Circuit Emulator
PIC16C71X
ICEPIC Low-Cost In-Circuit Emulator
MPLABTM Integrated Development Environment
MPLABTM C Compiler
fuzzyTECH(R)-MP Explorer/Edition Fuzzy Logic Dev. Tool
MP-DriveWayTM Applications Code Generator
DEVELOPMENT TOOLS FROM MICROCHIP
Total EnduranceTM Software Model
PICSTART(R) Lite Ultra Low-Cost Dev. Kit
PICSTART(R) Plus Low-Cost Universal Dev. Kit
PRO MATE(R) II Universal Programmer
KEELOQ(R) Programmer
SEEVAL(R) Designers Kit
PICDEM-1
PICDEM-2
PICDEM-3
KEELOQ(R) Evaluation Kit
PIC16C71X
Applicable Devices 710 71 711 715
11.0
ELECTRICAL CHARACTERISTICS FOR PIC16C710 AND PIC16C711
Absolute Maximum Ratings Ambient temperature under bias................................................................................................................. -55 to +125C Storage temperature .............................................................................................................................. -65C to +150C Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4).......................................... -0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ........................................................................................................... -0.3 to +7.5V Voltage on MCLR with respect to VSS................................................................................................................0 to +14V Voltage on RA4 with respect to Vss ...................................................................................................................0 to +14V Total power dissipation (Note 1)................................................................................................................................1.0W Maximum current out of VSS pin ...........................................................................................................................300 mA Maximum current into VDD pin ..............................................................................................................................250 mA Input clamp current, IIK (VI < 0 or VI > VDD)..................................................................................................................... 20 mA Output clamp current, IOK (VO < 0 or VO > VDD) ............................................................................................................. 20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................25 mA Maximum current sunk by PORTA ........................................................................................................................200 mA Maximum current sourced by PORTA ...................................................................................................................200 mA Maximum current sunk by PORTB........................................................................................................................200 mA Maximum current sourced by PORTB...................................................................................................................200 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD - VOH) x IOH} + (VOl x IOL) NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
TABLE 11-1:
CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)
PIC16C710-10 PIC16C711-10 VDD: 4.5V to 5.5V IDD: 2.7 mA typ. at 5.5V IPD: 1.5 A typ. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 2.7 mA typ. at 5.5V IPD: 1.5 A typ. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 30 mA max. at 5.5V IPD: 1.5 A typ. at 4.5V Freq: 10 MHz max. PIC16C710-20 PIC16C711-20 VDD: 4.5V to 5.5V IDD: 2.7 mA typ. at 5.5V IPD: 1.5 A typ. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 2.7 mA typ. at 5.5V IPD: 1.5 A typ. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 30 mA max. at 5.5V IPD: 1.5 A typ. at 4.5V Freq:20 MHz max. PIC16C710/JW PIC16C711/JW VDD: 4.0V to 6.0V IDD: 5 mA max. at 5.5V IPD: 21 A max. at 4V Freq:4 MHz max. VDD: 4.0V to 6.0V IDD: 5 mA max. at 5.5V IPD: 21 A max. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 30 mA max. at Not recommended for 5.5V use in HS mode IPD: 1.5 A typ. at 4.5V Freq: 10 MHz max. VDD: 2.5V to 6.0V VDD: 2.5V to 6.0V IDD: 48 A max. at IDD: 48 A max. at 32 kHz, 3.0V 32 kHz, 3.0V IPD: 5.0 A max. at 3.0V IPD: 5.0 A max. at Freq: 200 kHz max. 3.0V Freq: 200 kHz max. PIC16LC710-04 PIC16LC711-04 VDD: 2.5V to 6.0V IDD: 3.8 mA typ. at 3.0V IPD: 5.0 A typ. at 3V Freq: 4 MHz max. VDD: 2.5V to 6.0V IDD: 3.8 mA typ. at 3.0V IPD: 5.0 A typ. at 3V Freq: 4 MHz max.
OSC
RC
XT
HS
LP
PIC16C710-04 PIC16C711-04 VDD: 4.0V to 6.0V IDD: 5 mA max. at 5.5V IPD: 21 A max. at 4V Freq:4 MHz max. VDD: 4.0V to 6.0V IDD: 5 mA max. at 5.5V IPD: 21 A max. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 13.5 mA typ. at 5.5V IPD: 1.5 A typ. at 4.5V Freq: 4 MHz max. VDD: 4.0V to 6.0V IDD: 52.5 A typ. at 32 kHz, 4.0V IPD: 0.9 A typ. at 4.0V Freq: 200 kHz max.
Not recommended for use in LP mode
Not recommended for use in LP mode
(c) 1997 Microchip Technology Inc.
DS30272A-page 89
PIC16C71X
Applicable Devices 11.1 710 71 711 715 PIC16C710-04 (Commercial, Industrial, Extended) PIC16C711-04 (Commercial, Industrial, Extended) PIC16C710-10 (Commercial, Industrial, Extended) PIC16C711-10 (Commercial, Industrial, Extended) PIC16C710-20 (Commercial, Industrial, Extended) PIC16C711-20 (Commercial, Industrial, Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature 0C TA +70C (commercial) -40C TA +85C (industrial) -40C TA +125C (extended) Sym VDD VDR VPOR Min Typ Max Units 4.0 4.5 1.5 VSS 6.0 5.5 V V V V See section on Power-on Reset for details Conditions XT, RC and LP osc configuration HS osc configuration
DC Characteristics:
DC CHARACTERISTICS
Param. No. D001 D001A D002* D003
Characteristic Supply Voltage RAM Data Retention Voltage (Note 1) VDD start voltage to ensure internal Poweron Reset signal VDD rise rate to ensure internal Power-on Reset signal Brown-out Reset Voltage Supply Current (Note 2)
D004*
SVDD
0.05
-
-
V/ms See section on Power-on Reset for details
D005 D010
BVDD IDD
3.7 3.7 -
4.0 4.0 2.7
4.3 4.4 5
V V mA
BODEN configuration bit is enabled Extended Range Only XT, RC osc configuration FOSC = 4 MHz, VDD = 5.5V (Note 4) HS osc configuration FOSC = 20 MHz, VDD = 5.5V BOR enabled VDD = 5.0V VDD = 4.0V, WDT enabled, -40C to +85C VDD = 4.0V, WDT disabled, -0C to +70C VDD = 4.0V, WDT disabled, -40C to +85C VDD = 4.0V, WDT disabled, -40C to +125C BOR enabled VDD = 5.0V
D013 D015 D020 D021 D021A D021B D023 * Note 1: 2: Brown-out Reset Current IBOR (Note 5) Power-down Current (Note 3) IPD
-
13.5
30
mA A A A A A A
300* 500 10.5 1.5 1.5 1.5 42 21 24 30
Brown-out Reset Current IBOR (Note 5)
300* 500
3: 4: 5:
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. This is the limit to which VDD can be lowered without losing RAM data. The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. The current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement.
DS30272A-page 90
(c) 1997 Microchip Technology Inc.
PIC16C71X
Applicable Devices 11.2 DC Characteristics: PIC16LC710-04 (Commercial, Industrial, Extended) PIC16LC711-04 (Commercial, Industrial, Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature 0C TA +70C (commercial) -40C TA +85C (industrial) -40C TA +125C (extended) Sym Min Typ Max Units Conditions
710 71 711 715
DC CHARACTERISTICS Param No. D001 Characteristic Supply Voltage Commercial/Industrial Extended RAM Data Retention Voltage (Note 1) VDD start voltage to ensure internal Poweron Reset signal VDD rise rate to ensure internal Power-on Reset signal Brown-out Reset Voltage Supply Current (Note 2)
VDD VDD VDR VPOR
2.5 3.0 -
1.5 VSS
6.0 6.0 -
V V V V
LP, XT, RC osc configuration (DC - 4 MHz) LP, XT, RC osc configuration (DC - 4 MHz)
D002* D003
See section on Power-on Reset for details
D004*
SVDD
0.05
-
-
V/ms See section on Power-on Reset for details
D005 D010
BVDD IDD
3.7 -
4.0 2.0
4.3 3.8
V mA A A A A A A A
BODEN configuration bit is enabled XT, RC osc configuration FOSC = 4 MHz, VDD = 3.0V (Note 4) LP osc configuration FOSC = 32 kHz, VDD = 3.0V, WDT disabled BOR enabled VDD = 5.0V VDD = 3.0V, WDT enabled, -40C to +85C VDD = 3.0V, WDT disabled, 0C to +70C VDD = 3.0V, WDT disabled, -40C to +85C VDD = 3.0V, WDT disabled, -40C to +125C BOR enabled VDD = 5.0V
D010A D015 D020 D021 D021A D021B D023 * Note 1: 2: Brown-out Reset Current (Note 5) Power-down Current (Note 3) IBOR IPD
-
22.5 300* 7.5 0.9 0.9 0.9 300*
48 500 30 5 5 10 500
Brown-out Reset Current (Note 5)
IBOR
3: 4: 5:
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. This is the limit to which VDD can be lowered without losing RAM data. The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. The current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement.
(c) 1997 Microchip Technology Inc.
DS30272A-page 91
PIC16C71X
Applicable Devices 11.3 710 71 711 715 PIC16C710-04 (Commercial, Industrial, Extended) PIC16C711-04 (Commercial, Industrial, Extended) PIC16C710-10 (Commercial, Industrial, Extended) PIC16C711-10 (Commercial, Industrial, Extended) PIC16C710-20 (Commercial, Industrial, Extended) PIC16C711-20 (Commercial, Industrial, Extended) PIC16LC710-04 (Commercial, Industrial, Extended) PIC16LC711-04 (Commercial, Industrial, Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature 0C TA +70C (commercial) -40C TA +85C (industrial) -40C TA +125C (extended) Operating voltage VDD range as described in DC spec Section 11.1 and Section 11.2. Sym Min Typ Max Units Conditions VIL VSS VSS VSS VSS VSS VIH - 0.15VDD 0.8V - 0.2VDD - 0.2VDD 0.3VDD V V V V V For entire VDD range 4.5 VDD 5.5V
DC Characteristics:
DC CHARACTERISTICS
Param No.
Characteristic Input Low Voltage I/O ports with TTL buffer with Schmitt Trigger buffer MCLR, OSC1 (in RC mode) OSC1 (in XT, HS and LP) Input High Voltage I/O ports with TTL buffer
D030 D030A D031 D032 D033
Note1
D040 D040A D041 D042 D042A D043 D070 D060 D061 D063 *
with Schmitt Trigger buffer MCLR, RB0/INT OSC1 (XT, HS and LP) OSC1 (in RC mode) PORTB weak pull-up current Input Leakage Current (Notes 2, 3) I/O ports MCLR, RA4/T0CKI OSC1
2.0 0.25VDD + 0.8V 0.8VDD 0.8VDD 0.7VDD 0.9VDD IPURB 50 250 IIL -
VDD VDD VDD VDD VDD VDD 400 1 5 5
V V
4.5 VDD 5.5V For entire VDD range
V For entire VDD range V V Note1 V A VDD = 5V, VPIN = VSS A Vss VPIN VDD, Pin at hiimpedance A Vss VPIN VDD A Vss VPIN VDD, XT, HS and LP osc configuration
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C7X be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin.
DS30272A-page 92
(c) 1997 Microchip Technology Inc.
PIC16C71X
Applicable Devices 710 71 711 715
Standard Operating Conditions (unless otherwise stated) Operating temperature 0C TA +70C (commercial) -40C TA +85C (industrial) -40C TA +125C (extended) Operating voltage VDD range as described in DC spec Section 11.1 and Section 11.2. Sym Min Typ Max Units Conditions VOL OSC2/CLKOUT (RC osc config) Output High Voltage I/O ports (Note 3) 0.6 0.6 0.6 0.6 V V V V IOL = 8.5 mA, VDD = 4.5V, -40C to +85C IOL = 7.0 mA, VDD = 4.5V, -40C to +125C IOL = 1.6 mA, VDD = 4.5V, -40C to +85C IOL = 1.2 mA, VDD = 4.5V, -40C to +125C IOH = -3.0 mA, VDD = 4.5V, -40C to +85C IOH = -2.5 mA, VDD = 4.5V, -40C to +125C IOH = -1.3 mA, VDD = 4.5V, -40C to +85C IOH = -1.0 mA, VDD = 4.5V, -40C to +125C RA4 pin
DC CHARACTERISTICS
Param No. D080 D080A D083 D083A
Characteristic Output Low Voltage I/O ports
D090 D090A D092 D092A D130*
VOH VDD - 0.7 VDD - 0.7 -
14
V V V V V
OSC2/CLKOUT (RC osc config)
VDD - 0.7 VDD - 0.7 -
D100
Open-Drain High Voltage Capacitive Loading Specs on Output Pins OSC2 pin
VOD
-
-
COSC2
-
-
15
pF
In XT, HS and LP modes when external clock is used to drive OSC1.
All I/O pins and OSC2 (in RC mode) CIO 50 pF These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C7X be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. *
D101
(c) 1997 Microchip Technology Inc.
DS30272A-page 93
PIC16C71X
Applicable Devices 11.4 710 71 711 715 Timing Parameter Symbology
The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKOUT cs CS di SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (Hi-impedance) L Low
T
Time
osc rd rw sc ss t0 t1 wr
OSC1 RD RD or WR SCK SS T0CKI T1CKI WR
P R V Z
Period Rise Valid Hi-impedance
FIGURE 11-1: LOAD CONDITIONS
Load condition 1 VDD/2 Load condition 2
RL
Pin VSS RL = 464 CL = 50 pF 15 pF
CL
Pin VSS
CL
for all pins except OSC2 for OSC2 output
DS30272A-page 94
(c) 1997 Microchip Technology Inc.
PIC16C71X
Applicable Devices 11.5 Timing Diagrams and Specifications 710 71 711 715
FIGURE 11-2: EXTERNAL CLOCK TIMING
Q4 Q1 Q2 Q3 Q4 Q1
OSC1
1 2 3 3 4 4
CLKOUT
TABLE 11-2:
Parameter No. Sym Fosc
EXTERNAL CLOCK TIMING REQUIREMENTS
Characteristic External CLKIN Frequency (Note 1) Min Typ Max Units Conditions
DC -- 4 MHz XT osc mode DC -- 4 MHz HS osc mode (-04) DC -- 10 MHz HS osc mode (-10) DC -- 20 MHz HS osc mode (-20) DC -- 200 kHz LP osc mode Oscillator Frequency DC -- 4 MHz RC osc mode (Note 1) 0.1 -- 4 MHz XT osc mode 4 -- 20 MHz HS osc mode 5 -- 200 kHz LP osc mode 1 Tosc External CLKIN Period 250 -- -- ns XT osc mode (Note 1) 250 -- -- ns HS osc mode (-04) 100 -- -- ns HS osc mode (-10) 50 -- -- ns HS osc mode (-20) 5 -- -- s LP osc mode Oscillator Period 250 -- -- ns RC osc mode (Note 1) 250 -- 10,000 ns XT osc mode 250 -- 250 ns HS osc mode (-04) 100 -- 250 ns HS osc mode (-10) 50 -- 250 ns HS osc mode (-20) 5 -- -- s LP osc mode -- DC ns TCY = 4/FOSC 2 TCY Instruction Cycle Time (Note 1) 200 3 TosL, External Clock in (OSC1) High 50 -- -- ns XT oscillator TosH or Low Time 2.5 -- -- s LP oscillator 10 -- -- ns HS oscillator 4 TosR, External Clock in (OSC1) Rise -- -- 25 ns XT oscillator TosF or Fall Time -- -- 50 ns LP oscillator -- -- 15 ns HS oscillator Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices. OSC2 is disconnected (has no loading) for the PIC16C710/711.
(c) 1997 Microchip Technology Inc.
DS30272A-page 95
PIC16C71X
Applicable Devices 710 71 711 715 FIGURE 11-3: CLKOUT AND I/O TIMING
Q4 OSC1 10 CLKOUT 13 14 I/O Pin (input) 17 I/O Pin (output) old value 20, 21 Note: Refer to Figure 11-1 for load conditions. 15 new value 19 18 12 16 11 Q1 Q2 Q3
TABLE 11-3:
Parameter Sym No. 10* 11* 12* 13* 14* 15* 16* 17* 18* 19* 20* 21* 22* 23* *
CLKOUT AND I/O TIMING REQUIREMENTS
Characteristic OSC1 to CLKOUT OSC1 to CLKOUT CLKOUT rise time CLKOUT fall time CLKOUT to Port out valid Port in valid before CLKOUT Port in hold after CLKOUT OSC1 (Q1 cycle) to Port out valid OSC1 (Q2 cycle) to Port input invalid (I/O in hold time) Port input valid to OSC1 (I/O in setup time) Port output rise time Port output fall time INT pin high or low time RB7:RB4 change INT high or low time PIC16C710/711 PIC16LC710/711 PIC16C710/711 PIC16LC710/711 Min -- -- -- -- -- 0.25TCY + 25 0 -- TBD TBD -- -- -- -- 20 20 Typ 15 15 5 5 -- -- -- -- -- -- 10 -- 10 -- -- -- Max 30 30 15 15 0.5TCY + 20 -- -- 80 - 100 -- -- 25 60 25 60 -- -- Units Conditions ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1
TosH2ckL TosH2ckH TckR TckF TckL2ioV TioV2ckH TckH2ioI TosH2ioV TosH2ioI TioV2osH TioR TioF Tinp Trbp
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. These parameters are asynchronous events not related to any internal clock edges. Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
DS30272A-page 96
(c) 1997 Microchip Technology Inc.
PIC16C71X
Applicable Devices 710 71 711 715 FIGURE 11-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING
VDD MCLR Internal POR 33 PWRT Time-out OSC Time-out Internal RESET Watchdog Timer RESET 34 I/O Pins 32 30
31 34
Note: Refer to Figure 11-1 for load conditions.
FIGURE 11-5: BROWN-OUT RESET TIMING
VDD
BVDD 35
TABLE 11-4:
Parameter No. 30 31 32 33 34 35 *
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET REQUIREMENTS
Sym TmcL Twdt Tost Tpwrt TIOZ TBOR Characteristic MCLR Pulse Width (low) Watchdog Timer Time-out Period (No Prescaler) Oscillation Start-up Timer Period Power up Timer Period I/O Hi-impedance from MCLR Low or Watchdog Timer Reset Brown-out Reset pulse width Min 1 7* -- 28* -- 100 Typ -- 18 1024TOSC 72 -- -- Max -- 33* -- 132* 1.1 -- Units s ms -- ms s s 3.8V VDD 4.2V Conditions VDD = 5V, -40C to +125C VDD = 5V, -40C to +125C TOSC = OSC1 period VDD = 5V, -40C to +125C
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
(c) 1997 Microchip Technology Inc.
DS30272A-page 97
PIC16C71X
Applicable Devices 710 71 711 715 FIGURE 11-6: TIMER0 EXTERNAL CLOCK TIMINGS
RA4/T0CKI
40 42
41
TMR0
Note: Refer to Figure 11-1 for load conditions.
TABLE 11-5:
Param No. 40 Sym Tt0H
TIMER0 EXTERNAL CLOCK REQUIREMENTS
Characteristic T0CKI High Pulse Width No Prescaler With Prescaler Min 0.5TCY + 20* 10* 0.5TCY + 20* 10* Greater of: 20 ns or TCY + 40* N 2Tosc Typ Max Units Conditions -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns Must also meet parameter 42 Must also meet parameter 42 N = prescale value (2, 4,..., 256)
41
Tt0L
T0CKI Low Pulse Width
No Prescaler With Prescaler
42
Tt0P
T0CKI Period
48 *
Tcke2tmrI Delay from external clock edge to timer increment
--
7Tosc
--
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
DS30272A-page 98
(c) 1997 Microchip Technology Inc.
PIC16C71X
Applicable Devices TABLE 11-6: A/D CONVERTER CHARACTERISTICS: PIC16C710/711-04 (COMMERCIAL, INDUSTRIAL, EXTENDED) PIC16C710/711-10 (COMMERCIAL, INDUSTRIAL, EXTENDED) PIC16C710/711-20 (COMMERCIAL, INDUSTRIAL, EXTENDED) PIC16LC710/711-04 (COMMERCIAL, INDUSTRIAL, EXTENDED)
Min -- -- -- -- -- -- -- 2.5V VSS - 0.3 -- -- 10 Typ -- -- -- -- -- -- guaranteed -- -- -- 180 -- Max 8-bits <1 <1 <1 <1 <1 -- VDD + 0.3 VREF + 0.3 10.0 -- 1000 Units bit Conditions VREF = VDD, VSS AIN VREF
710 71 711 715
Param Sym Characteristic No. A01 A02 A03 A04 A05 A06 A10 A20 A25 A30 A40 A50 NR Resolution
EABS Absolute error EIL Integral linearity error
LSb VREF = VDD, VSS AIN VREF LSb VREF = VDD, VSS AIN VREF LSb VREF = VDD, VSS AIN VREF LSb VREF = VDD, VSS AIN VREF LSb VREF = VDD, VSS AIN VREF -- V V k A A A Average current consumption when A/D is on. (Note 1) During VAIN acquisition. Based on differential of VHOLD to VAIN. To charge CHOLD see Section 7.1. During A/D Conversion cycle VSS VAIN VREF
EDL Differential linearity error EFS Full scale error EOFF Offset error -- Monotonicity
VREF Reference voltage VAIN Analog input voltage ZAIN Recommended impedance of analog voltage source IAD A/D conversion current (VDD)
IREF VREF input current (Note 2)
-- *
--
10
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes any such leakage from the A/D module. 2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input.
(c) 1997 Microchip Technology Inc.
DS30272A-page 99
PIC16C71X
Applicable Devices 710 71 711 715 FIGURE 11-7: A/D CONVERSION TIMING
BSF ADCON0, GO (TOSC/2) (1) Q4 130 A/D CLK 132 131
1 Tcy
A/D DATA
7
6
5
4
3
2
1
0
ADRES
OLD_DATA
NEW_DATA
ADIF GO SAMPLING STOPPED DONE
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
TABLE 11-7:
Param No. 130
A/D CONVERSION REQUIREMENTS
Min PIC16C710/711 PIC16LC710/711 PIC16C710/711 PIC16LC710/711 1.6 2.0 2.0* 3.0* -- Note 2 5* Typ -- -- 4.0 6.0 9.5 20 -- Max -- -- 6.0 9.0 -- -- -- Units s s s s TAD s s The minimum time is the amplifier settling time. This may be used if the "new" input voltage has not changed by more than 1 LSb (i.e., 19.5 mV @ 5.12V) from the last sampled voltage (as stated on CHOLD). If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. Conditions TOSC based, VREF 3.0V TOSC based, VREF full range A/D RC mode A/D RC mode
Sym Characteristic TAD A/D clock period
131 132
TCNV Conversion time (not including S/H time). (Note 1) TACQ Acquisition time
134
TGO
Q4 to AD clock start
--
TOSC/2
--
--
135 *
TSWC Switching from convert sample time
1.5
--
--
TAD
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. This specification ensured by design. Note 1: ADRES register may be read on the following TCY cycle. 2: See Section 7.1 for min conditions.
DS30272A-page 100
(c) 1997 Microchip Technology Inc.
PIC16C71X
Applicable Devices 710 71 711 715
12.0
DC AND AC CHARACTERISTICS GRAPHS AND TABLES FOR PIC16C710 AND PIC16C711
The graphs and tables provided in this section are for design guidance and are not tested or guaranteed. In some graphs or tables the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are guaranteed to operate properly only within the specified range. Note: The data presented in this section is a statistical summary of data collected on units from different lots over a period of time and matrix samples. 'Typical' represents the mean of the distribution at, 25C, while 'max' or 'min' represents (mean +3) and (mean -3) respectively where is standard deviation.
FIGURE 12-1: TYPICAL IPD vs. VDD (WDT DISABLED, RC MODE)
35
30
25
IPD(nA)
20
15
10
5
0 2.5
3.0
3.5
4.0 4.5 VDD(Volts)
5.0
5.5
6.0
FIGURE 12-2: MAXIMUM IPD vs. VDD (WDT DISABLED, RC MODE)
10.000 85C 70C 1.000
IPD(A)
0.100
25C
0C -40C 0.010
0.001 2.5
3.0
3.5
4.0 4.5 VDD(Volts)
5.0
5.5
6.0
(c) 1997 Microchip Technology Inc.
DS30272A-page 101
PIC16C71X
Applicable Devices 710 71 711 715 FIGURE 12-5: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD
6.0 25 20 Fosc(MHz) IPD(A) 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 5 0 2.5 1.5 1.0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0.5 0.0 2.5 3.0 3.5 4.0 4.5 VDD(Volts) 5.0 5.5 6.0 R = 100k R = 10k R = 5k Cext = 22 pF, T = 25C
FIGURE 12-3: TYPICAL IPD vs. VDD @ 25C (WDT ENABLED, RC MODE)
15 10
VDD(Volts)
FIGURE 12-4: MAXIMUM IPD vs. VDD (WDT ENABLED, RC MODE)
35 30 25 IPD(A) 20 15 10 5 0 2.5 85C -40C 0C
Shaded area is beyond recommended range.
FIGURE 12-6: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD
2.4 2.2 2.0 1.8 Fosc(MHz) R = 3.3k Cext = 100 pF, T = 25C
70C
1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 2.5 3.0 3.5 4.0 4.5 5.0 R = 10k R = 5k
3.0
3.5
4.0
4.5
5.0
5.5
6.0
R = 100k
VDD(Volts)
5.5
6.0
VDD(Volts)
FIGURE 12-7: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD
Cext = 300 pF, T = 25C 1000 900 800 Fosc(kHz) 700 600 500 400 300 200 100 0 2.5 3.0 3.5 4.0 4.5 5.0 R = 100k 5.5 6.0 R = 10k R = 5k R = 3.3k
VDD(Volts)
DS30272A-page 102
(c) 1997 Microchip Technology Inc.
PIC16C71X
Applicable Devices FIGURE 12-8: TYPICAL IPD vs. VDD BROWNOUT DETECT ENABLED (RC MODE)
1400 1200 1000 IPD(A) 800 600 400 200 0 2.5 Device in Brown-out Reset 3.0 3.5 4.0 4.5 VDD(Volts) 5.0 5.5 6.0 Device NOT in Brown-out Reset IPD(A) 30 25 20 15 10 5 0 2.5 3.0 3.5 4.0 4.5 VDD(Volts) 5.0 5.5 6.0
710 71 711 715
FIGURE 12-10: TYPICAL IPD vs. TIMER1 ENABLED (32 kHz, RC0/RC1 = 33 pF/33 pF, RC MODE)
The shaded region represents the built-in hysteresis of the brown-out reset circuitry.
FIGURE 12-9: MAXIMUM IPD vs. VDD BROWN-OUT DETECT ENABLED (85C TO -40C, RC MODE)
1600 1400 1200 1000 IPD(A) 800 600 400 200 4.3 0 2.5 3.0 3.5 4.0 4.5 VDD(Volts) 5.0 5.5 6.0 Device in Brown-out Reset Device NOT in Brown-out Reset
FIGURE 12-11: MAXIMUM IPD vs. TIMER1 ENABLED (32 kHz, RC0/RC1 = 33 pF/33 pF, 85C TO -40C, RC MODE)
45 40 35 30 IPD(A) 25 20 15 10 5 0 2.5 3.0 3.5 4.0 4.5 VDD(Volts) 5.0 5.5 6.0
The shaded region represents the built-in hysteresis of the brown-out reset circuitry.
(c) 1997 Microchip Technology Inc.
DS30272A-page 103
PIC16C71X
Applicable Devices 710 71 711 715 FIGURE 12-12: TYPICAL IDD vs. FREQUENCY (RC MODE @ 22 pF, 25C)
2000 1800 1600 1400 IDD(A) 1200 1000 800 600 400 200 0 0.0
6.0V 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
Frequency(MHz)
Shaded area is beyond recommended range
FIGURE 12-13: MAXIMUM IDD vs. FREQUENCY (RC MODE @ 22 pF, -40C TO 85C)
2000 1800 1600 1400 IDD(A) 1200 1000 800 600 400 200 0 0.0
6.0V 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
Frequency(MHz)
Shaded area is beyond recommended range
DS30272A-page 104
(c) 1997 Microchip Technology Inc.
PIC16C71X
Applicable Devices FIGURE 12-14: TYPICAL IDD vs. FREQUENCY (RC MODE @ 100 pF, 25C)
1600
6.0V
710 71 711 715
1400
5.5V 5.0V
1200
4.5V 4.0V
1000
3.5V
IDD(A)
800
3.0V
2.5V
600
400
200
0 0 200 400 Shaded area is beyond recommended range 600 800 1000 1200 1400 1600 1800 Frequency(kHz)
FIGURE 12-15: MAXIMUM IDD vs. FREQUENCY (RC MODE @ 100 pF, -40C TO 85C)
1600
6.0V
1400
5.5V 5.0V
1200
4.5V 4.0V
1000
3.5V
IDD(A)
800
3.0V
2.5V
600
400
200
0 0 200 400 600 800 1000 1200 1400 1600 1800 Shaded area is beyond recommended range Frequency(kHz)
(c) 1997 Microchip Technology Inc.
DS30272A-page 105
PIC16C71X
Applicable Devices 710 71 711 715 FIGURE 12-16: TYPICAL IDD vs. FREQUENCY (RC MODE @ 300 pF, 25C)
1200
6.0V 5.5V
1000
5.0V 4.5V
800
4.0V 3.5V
IDD(A)
3.0V
600
2.5V
400
200
0 0 100 200 300 400 500 600 700 Frequency(kHz)
FIGURE 12-17: MAXIMUM IDD vs. FREQUENCY (RC MODE @ 300 pF, -40C TO 85C)
1200
6.0V 5.5V
1000
5.0V 4.5V
800
4.0V 3.5V
IDD(A)
3.0V
600
2.5V
400
200
0 0 100 200 300 400 500 600 700 Frequency(kHz)
DS30272A-page 106
(c) 1997 Microchip Technology Inc.
PIC16C71X
Applicable Devices FIGURE 12-18: TYPICAL IDD vs. CAPACITANCE @ 500 kHz (RC MODE)
600 500 400 IDD(A) 300 200 100 0.5 0 20 pF 100 pF Capacitance(pF) 300 pF 0.0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 5.0V 4.0V 3.0V gm(mA/V)
710 71 711 715
FIGURE 12-19: TRANSCONDUCTANCE(gm) OF HS OSCILLATOR vs. VDD
4.0 Max -40C 3.5 3.0 2.5 2.0 1.5 1.0 Min 85C Typ 25C
VDD(Volts) Shaded area is beyond recommended range
TABLE 12-1:
RC OSCILLATOR FREQUENCIES
Average Rext Fosc @ 5V, 25C 5k 10k 100k 4.12 MHz 2.35 MHz 268 kHz 1.80 MHz 1.27 MHz 688 kHz 77.2 kHz 707 kHz 501 kHz 269 kHz 28.3 kHz 1.4% 1.1% 1.0% 1.0% 1.2% 1.0% 1.4% 1.2% 1.6% 1.1%
FIGURE 12-20: TRANSCONDUCTANCE(gm) OF LP OSCILLATOR vs. VDD
110 100 90 80 gm(A/V) 70 60 50 40 30 20 10 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 Min 85C Typ 25C Max -40C
Cext 22 pF
1.4%
100 pF
3.3k 5k 10k 100k
300 pF
3.3k 5k 10k 100k
VDD(Volts) Shaded areas are beyond recommended range
The percentage variation indicated here is part to part variation due to normal process distribution. The variation indicated is 3 standard deviation from average value for VDD = 5V.
FIGURE 12-21: TRANSCONDUCTANCE(gm) OF XT OSCILLATOR vs. VDD
1000 900 800 700 gm(A/V) 600 500 400 300 200 100 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 VDD(Volts) Shaded areas are beyond recommended range 7.0 Min 85C Typ 25C Max -40C
(c) 1997 Microchip Technology Inc.
DS30272A-page 107
PIC16C71X
Applicable Devices 710 71 711 715 FIGURE 12-24: TYPICAL XTAL STARTUP TIME vs. VDD (XT MODE, 25C) FIGURE 12-22: TYPICAL XTAL STARTUP TIME vs. VDD (LP MODE, 25C)
3.5 3.0 2.5 Startup Time(Seconds) 50 2.0
32 kHz, 33 pF/33 pF
70 60
Startup Time(ms)
40
200 kHz, 68 pF/68 pF
1.5 1.0 0.5 0.0 2.5
200 kHz, 15 pF/15 pF
30
200 kHz, 47 pF/47 pF
20
1 MHz, 15 pF/15 pF
10 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
4 MHz, 15 pF/15 pF
3.0
3.5
4.0 4.5 VDD(Volts)
5.0
5.5
6.0
VDD(Volts)
FIGURE 12-23: TYPICAL XTAL STARTUP TIME vs. VDD (HS MODE, 25C)
7 6 Startup Time(ms) 5 4
8 MHz, 33 pF/33 pF 20 MHz, 33 pF/33 pF
TABLE 12-2:
CAPACITOR SELECTION FOR CRYSTAL OSCILLATORS
Crystal Freq 32 kHz 200 kHz 200 kHz 1 MHz 4 MHz Cap. Range C1 33 pF 15 pF 47-68 pF 15 pF 15 pF 15 pF 15-33 pF 15-33 pF Cap. Range C2 33 pF 15 pF 47-68 pF 15 pF 15 pF 15 pF 15-33 pF 15-33 pF
Osc Type LP XT
3 2 1 4.0
20 MHz, 15 pF/15 pF 8 MHz, 15 pF/15 pF
HS
4 MHz 8 MHz 20 MHz
4.5
5.0 VDD(Volts)
5.5
6.0 Crystals Used 32 kHz 200 kHz 1 MHz 4 MHz 8 MHz 20 MHz Epson C-001R32.768K-A STD XTL 200.000KHz ECS ECS-10-13-1 ECS ECS-40-20-1 EPSON CA-301 8.000M-C EPSON CA-301 20.000M-C 20 PPM 20 PPM 50 PPM 50 PPM 30 PPM 30 PPM
DS30272A-page 108
(c) 1997 Microchip Technology Inc.
PIC16C71X
Applicable Devices FIGURE 12-25: TYPICAL IDD vs. FREQUENCY (LP MODE, 25C) 710 71 711 715 FIGURE 12-27: TYPICAL IDD vs. FREQUENCY (XT MODE, 25C)
1800 1600 120 1400 100 1200 80 IDD(A) 1000 60 40 20 0 0
6.0V 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 5.0V 4.5V 4.0V 3.5V 3.0V 6.0V 5.5V
IDD(A)
800 600 400
2.5V
50
100 Frequency(kHz)
150
200
200 0 0.0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
Frequency(MHz)
FIGURE 12-26: MAXIMUM IDD vs. FREQUENCY (LP MODE, 85C TO -40C)
140 120 100 80 IDD(A) 60 40 20 0 0
6.0V 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V
FIGURE 12-28: MAXIMUM IDD vs. FREQUENCY (XT MODE, -40C TO 85C)
1800 1600 1400 1200 1000 IDD(A) 800 600 400 200
6.0V 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V
50
100 Frequency(kHz)
150
200 0 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0
Frequency(MHz)
(c) 1997 Microchip Technology Inc.
DS30272A-page 109
PIC16C71X
Applicable Devices 710 71 711 715 FIGURE 12-30: MAXIMUM IDD vs. FREQUENCY (HS MODE, -40C TO 85C)
7.0 6.0 6.0 5.0 5.0 IDD(mA) 4.0 3.0 2.0 1.0 0.0 12
6.0V 5.5V 5.0V 4.5V 4.0V
FIGURE 12-29: TYPICAL IDD vs. FREQUENCY (HS MODE, 25C)
7.0
IDD(mA)
4.0 3.0 2.0 1.0
6.0V 5.5V 5.0V 4.5V 4.0V
4
6
8
10
12
14
16
18
20
Frequency(MHz)
0.0 12
4
6
8
10
12
14
16
18
20
Frequency(MHz)
DS30272A-page 110
(c) 1997 Microchip Technology Inc.
PIC16C71X
Applicable Devices 710 71 711 715
13.0
ELECTRICAL CHARACTERISTICS FOR PIC16C715
Absolute Maximum Ratings Ambient temperature under bias................................................................................................................ .-55 to +125C Storage temperature .............................................................................................................................. -65C to +150C Voltage on any pin with respect to VSS (except VDD and MCLR).................................................... -0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ................................................................................................................ 0 to +7.5V Voltage on MCLR with respect to VSS................................................................................................................0 to +14V Voltage on RA4 with respect to Vss ...................................................................................................................0 to +14V Total power dissipation (Note 1)................................................................................................................................1.0W Maximum current out of VSS pin ...........................................................................................................................300 mA Maximum current into VDD pin ..............................................................................................................................250 mA Input clamp current, IIK (VI < 0 or VI > VDD)..................................................................................................................... 20 mA Output clamp current, IOK (VO < 0 or VO > VDD) ............................................................................................................. 20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................25 mA Maximum current sunk by PORTA ........................................................................................................................200 mA Maximum current sourced by PORTA ...................................................................................................................200 mA Maximum current sunk by PORTB........................................................................................................................200 mA Maximum current sourced by PORTB...................................................................................................................200 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD - VOH) x IOH} + (VOl x IOL). NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
(c) 1997 Microchip Technology Inc.
DS30272A-page 111
DS30272A-page 112 PIC16C715-04 PIC16C715-10 PIC16C715-20 PIC16LC715-04 PIC16C715/JW VDD: 4.0V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 2.5V to 5.5V VDD: 4.0V to 5.5V IDD: 5 mA max. at 5.5V IDD: 2.7 mA typ. at 5.5V IDD: 2.7 mA typ. at 5.5V IDD: 2.0 mA typ. at 3.0V IDD: 5 mA max. at 5.5V RC IPD: 21 A max. at 4V IPD: 1.5 A typ. at 4V IPD: 1.5 A typ. at 4V IPD: 0.9 A typ. at 3V IPD: 21 A max. at 4V Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. VDD: 4.0V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 2.5V to 5.5V VDD: 4.0V to 5.5V IDD: 5 mA max. at 5.5V IDD: 2.7 mA typ. at 5.5V IDD: 2.7 mA typ. at 5.5V IDD: 2.0 mA typ. at 3.0V IDD: 5 mA max. at 5.5V XT IPD: 21 A max. at 4V IPD: 1.5 A typ. at 4V IPD: 1.5 A typ. at 4V IPD: 0.9 A typ. at 3V IPD: 21 A max. at 4V Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V IDD: 13.5 mA typ. at 5.5V IDD: 30 mA max. at 5.5V IDD: 30 mA max. at 5.5V IDD: 30 mA max. at 5.5V HS Do not use in HS mode IPD: 1.5 A typ. at 4.5V IPD: 1.5 A typ. at 4.5V IPD: 1.5 A typ. at 4.5V IPD: 1.5 A typ. at 4.5V Freq: 4 MHz max. Freq: 10 MHz max. Freq: 20 MHz max. Freq: 10 MHz max. VDD: 4.0V to 5.5V VDD: 2.5V to 5.5V VDD: 2.5V to 5.5V IDD: 52.5 A typ. at 32 kHz, 4.0V IDD: 48 A max. at 32 kHz, 3.0V IDD: 48 A max. at 32 kHz, 3.0V LP Do not use in LP mode Do not use in LP mode IPD: 0.9 A typ. at 4.0V IPD: 5.0 A max. at 3.0V IPD: 5.0 A max. at 3.0V Freq: 200 kHz max. Freq: 200 kHz max. Freq: 200 kHz max. The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recommended that the user select the device type that ensures the specifications required. OSC (c) 1997 Microchip Technology Inc.
TABLE 13-1: CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)
PIC16C71X
Applicable Devices 710 71 711 715
PIC16C71X
Applicable Devices 13.1 DC Characteristics: PIC16C715-04 (Commercial, Industrial, Extended) PIC16C715-10 (Commercial, Industrial, Extended) PIC16C715-20 (Commercial, Industrial, Extended))
Standard Operating Conditions (unless otherwise stated) Operating temperature 0C TA +70C (commercial) -40C TA +85C (industrial) -40C TA +125C (extended) Sym VDD VDR VPOR Min Typ Max Units 4.0 4.5 1.5 VSS 5.5 5.5 V V V V Conditions XT, RC and LP osc configuration HS osc configuration Device in SLEEP mode See section on Power-on Reset for details
710 71 711 715
DC CHARACTERISTICS
Param. No. D001 D001A D002* D003
Characteristic Supply Voltage RAM Data Retention Voltage (Note 1) VDD start voltage to ensure internal Poweron Reset signal VDD rise rate to ensure internal Power-on Reset signal Brown-out Reset Voltage Supply Current (Note 2)
D004*
SVDD
0.05
-
-
V/ms See section on Power-on Reset for details
D005 D010
BVDD IDD
3.7 -
4.0 2.7
4.3 5
V mA
BODEN configuration bit is enabled XT, RC osc configuration (PIC16C715-04) FOSC = 4 MHz, VDD = 5.5V (Note 4) HS osc configuration (PIC16C715-20) FOSC = 20 MHz, VDD = 5.5V BOR enabled VDD = 5.0V VDD = 4.0V, WDT enabled, -40C to +85C VDD = 4.0V, WDT disabled, -0C to +70C VDD = 4.0V, WDT disabled, -40C to +85C VDD = 4.0V, WDT disabled, -40C to +125C BOR enabled VDD = 5.0V
D013 D015 D020 D021 D021A D021B D023 * Note 1: 2: Brown-out Reset Current IBOR (Note 5) Power-down Current (Note 3) IPD
-
13.5
30
mA A A A A A A
300* 500 10.5 1.5 1.5 1.5 42 21 24 30
Brown-out Reset Current IBOR (Note 5)
300* 500
3: 4: 5:
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. The current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement.
(c) 1997 Microchip Technology Inc.
DS30272A-page 113
PIC16C71X
Applicable Devices 13.2 710 71 711 715 PIC16LC715-04 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature 0C TA +70C (commercial) -40C TA +85C (industrial) Sym VDD VDR VPOR Min 2.5 Typ Max Units 1.5 VSS 5.5 V V V Conditions LP, XT, RC osc configuration (DC - 4 MHz) Device in SLEEP mode See section on Power-on Reset for details
DC Characteristics:
DC CHARACTERISTICS Param No. D001 D002* D003 Characteristic Supply Voltage RAM Data Retention Voltage (Note 1) VDD start voltage to ensure internal Power-on Reset signal VDD rise rate to ensure internal Power-on Reset signal Brown-out Reset Voltage Supply Current (Note 2)
D004*
SVDD
0.05
-
-
V/ms See section on Power-on Reset for details
D005 D010
BVDD IDD
3.7 -
4.0 2.0
4.3 3.8
V mA A A A A A A
BODEN configuration bit is enabled XT, RC osc configuration FOSC = 4 MHz, VDD = 3.0V (Note 4) LP osc configuration FOSC = 32 kHz, VDD = 3.0V, WDT disabled BOR enabled VDD = 5.0V VDD = 3.0V, WDT enabled, -40C to +85C VDD = 3.0V, WDT disabled, 0C to +70C VDD = 3.0V, WDT disabled, -40C to +85C BOR enabled VDD = 5.0V
D010A D015 D020 D021 D021A D023 * Note 1: 2: Brown-out Reset Current (Note 5) Power-down Current (Note 3) Brown-out Reset Current (Note 5) IBOR IPD
-
22.5 300* 7.5 0.9 0.9 300*
48 500 30 5 5 500
IBOR
3: 4: 5:
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. The current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement.
DS30272A-page 114
(c) 1997 Microchip Technology Inc.
PIC16C71X
Applicable Devices 13.3 DC Characteristics: PIC16C715-04 (Commercial, Industrial, Extended) PIC16C715-10 (Commercial, Industrial, Extended) PIC16C715-20 (Commercial, Industrial, Extended) PIC16LC715-04 (Commercial, Industrial))
Standard Operating Conditions (unless otherwise stated) Operating temperature 0C TA +70C (commercial) -40C TA +85C (industrial) -40C TA +125C (extended) Operating voltage VDD range as described in DC spec Section 13.1 and Section 13.2. Sym Min Typ Max Units Conditions VIL VSS VSS VSS VSS VIH 0.5V 0.2VDD 0.2VDD 0.3VDD V V V V Note1
710 71 711 715
DC CHARACTERISTICS
Param No.
Characteristic Input Low Voltage I/O ports with TTL buffer with Schmitt Trigger buffer MCLR, RA4/T0CKI,OSC1 (in RC mode) OSC1 (in XT, HS and LP) Input High Voltage I/O ports with TTL buffer with Schmitt Trigger buffer MCLR, RA4/T0CKI RB0/INT OSC1 (XT, HS and LP) OSC1 (in RC mode) PORTB weak pull-up current Input Leakage Current (Notes 2, 3) I/O ports MCLR, RA4/T0CKI OSC1 Output Low Voltage I/O ports
D030 D031 D032 D033
D040 D040A D041 D042 D042A D043 D070 D060 D061 D063
2.0 0.8VDD 0.8VDD 0.8VDD 0.7VDD 0.9VDD IPURB 50 250 IIL -
VDD VDD VDD VDD VDD VDD 400 1 5 5
V V V V V V A
4.5 VDD 5.5V For VDD > 5.5V or VDD < 4.5V For entire VDD range Note1 VDD = 5V, VPIN = VSS
A Vss VPIN VDD, Pin at hiimpedance A Vss VPIN VDD A Vss VPIN VDD, XT, HS and LP osc configuration V
D080 D080A D083 D083A Note 1: 2: 3:
IOL = 8.5 mA, VDD = 4.5V, -40C to +85C 0.6 V IOL = 7.0 mA, VDD = 4.5V, -40C to +125C OSC2/CLKOUT (RC osc config) 0.6 V IOL = 1.6 mA, VDD = 4.5V, -40C to +85C 0.6 V IOL = 1.2 mA, VDD = 4.5V, -40C to +125C Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C7X be driven with external clock in RC mode. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as coming out of the pin.
VOL
-
-
0.6
(c) 1997 Microchip Technology Inc.
DS30272A-page 115
PIC16C71X
Applicable Devices 710 71 711 715
Standard Operating Conditions (unless otherwise stated) Operating temperature 0C TA +70C (commercial) -40C TA +85C (industrial) -40C TA +125C (extended) Operating voltage VDD range as described in DC spec Section 13.1 and Section 13.2. Sym Min Typ Max Units Conditions VOH VDD - 0.7 VDD - 0.7 OSC2/CLKOUT (RC osc config) VDD - 0.7 VDD - 0.7 Capacitive Loading Specs on Output Pins OSC2 pin V V V V IOH = -3.0 mA, VDD = 4.5V, -40C to +85C IOH = -2.5 mA, VDD = 4.5V, -40C to +125C IOH = -1.3 mA, VDD = 4.5V, -40C to +85C IOH = -1.0 mA, VDD = 4.5V, -40C to +125C
DC CHARACTERISTICS
Param No. D090 D090A D092 D092A
Characteristic Output High Voltage I/O ports (Note 3)
D100
COSC2
-
-
15
pF
In XT, HS and LP modes when external clock is used to drive OSC1.
D101
All I/O pins and OSC2 (in RC mode) CIO 50 pF Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C7X be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as coming out of the pin.
DS30272A-page 116
(c) 1997 Microchip Technology Inc.
PIC16C71X
Applicable Devices 13.4 Timing Parameter Symbology 710 71 711 715
The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKOUT cs CS di SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (Hi-impedance) L Low
T
Time
osc rd rw sc ss t0 t1 wr
OSC1 RD RD or WR SCK SS T0CKI T1CKI WR
P R V Z
Period Rise Valid Hi-impedance
FIGURE 13-1: LOAD CONDITIONS
Load condition 1 VDD/2 Load condition 2
RL
Pin VSS RL = 464 CL = 50 pF 15 pF
CL
Pin VSS
CL
for all pins except OSC2 for OSC2 output
(c) 1997 Microchip Technology Inc.
DS30272A-page 117
PIC16C71X
Applicable Devices 13.5 710 71 711 715 Timing Diagrams and Specifications
FIGURE 13-2: EXTERNAL CLOCK TIMING
Q4 Q1 Q2 Q3 Q4 Q1
OSC1
1 2 3 3 4 4
CLKOUT
TABLE 13-2:
Parameter No. Sym Fos
CLOCK TIMING REQUIREMENTS
Characteristic External CLKIN Frequency (Note 1) Min DC DC DC DC DC 0.1 4 4 4 5 250 250 100 50 5 250 250 250 100 Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max 4 4 20 200 4 4 4 10 20 200 -- -- -- -- -- -- 10,000 250 250 Units Conditions MHz MHz MHz kHz MHz MHz MHz MHz MHz kHz ns ns ns ns s ns ns ns ns XT osc mode HS osc mode (PIC16C715-04) HS osc mode (PIC16C715-20) LP osc mode RC osc mode XT osc mode HS osc mode (PIC16C715-04) HS osc mode (PIC16C715-10) HS osc mode (PIC16C715-20) LP osc mode XT osc mode HS osc mode (PIC16C715-04) HS osc mode (PIC16C715-10) HS osc mode (PIC16C715-20) LP osc mode RC osc mode XT osc mode HS osc mode (PIC16C715-04) HS osc mode (PIC16C715-10)
Oscillator Frequency (Note 1)
1
Tosc
External CLKIN Period (Note 1)
Oscillator Period (Note 1)
50 -- 250 ns HS osc mode (PIC16C715-20) 5 -- -- s LP osc mode -- DC ns TCY = 4/FOSC 2 TCY Instruction Cycle Time (Note 1) 200 3 TosL, External Clock in (OSC1) High 50 -- -- ns XT oscillator TosH or Low Time 2.5 -- -- s LP oscillator 10 -- -- ns HS oscillator 4 TosR, External Clock in (OSC1) Rise -- -- 25 ns XT oscillator TosF or Fall Time -- -- 50 ns LP oscillator -- -- 15 ns HS oscillator Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices. OSC2 is disconnected (has no loading) for the PIC16C715.
DS30272A-page 118
(c) 1997 Microchip Technology Inc.
PIC16C71X
Applicable Devices FIGURE 13-3: CLKOUT AND I/O TIMING
Q4 OSC1 10 CLKOUT 13 14 I/O Pin (input) 17 I/O Pin (output) old value 20, 21 Note: Refer to Figure 13-1 for load conditions. 15 new value 19 18 12 16 11 Q1 Q2 Q3
710 71 711 715
TABLE 13-3:
Parameter Sym No. 10* 11* 12* 13* 14* 15* 16* 17* 18* 19* 20* 21* 22* 23* *
CLKOUT AND I/O TIMING REQUIREMENTS
Characteristic OSC1 to CLKOUT OSC1 to CLKOUT CLKOUT rise time CLKOUT fall time CLKOUT to Port out valid Port in valid before CLKOUT Port in hold after CLKOUT OSC1 (Q1 cycle) to Port out valid OSC1 (Q2 cycle) to Port input invalid (I/O in hold time) Port input valid to OSC1 (I/O in setup time) Port output rise time Port output fall time INT pin high or low time RB7:RB4 change INT high or low time PIC16C715 PIC16LC715 PIC16C715 PIC16LC715 Min -- -- -- -- -- 0.25TCY + 25 0 -- TBD TBD -- -- -- -- 20 20 Typ 15 15 5 5 -- -- -- -- -- -- 10 -- 10 -- -- -- Max 30 30 15 15 0.5TCY + 20 -- -- 80 - 100 -- -- 25 60 25 60 -- -- Units Conditions ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1
TosH2ckL TosH2ckH TckR TckF TckL2ioV TioV2ckH TckH2ioI TosH2ioV TosH2ioI TioV2osH TioR TioF Tinp Trbp
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. These parameters are asynchronous events not related to any internal clock edges. Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
(c) 1997 Microchip Technology Inc.
DS30272A-page 119
PIC16C71X
Applicable Devices 710 71 711 715 FIGURE 13-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, AND POWER-UP TIMER TIMING
VDD MCLR Internal POR 33 PWRT Timeout OSC Timeout Internal RESET Parity Error Reset 36 Watchdog Timer RESET 32 30
34 31 34
I/O Pins
FIGURE 13-5: BROWN-OUT RESET TIMING
VDD BVDD 35
TABLE 13-4:
Parameter No. 30 31* 32 33* 34 35 36 *
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET REQUIREMENTS
Sym TmcL Twdt Tost Tpwrt TIOZ TBOR TPER Characteristic MCLR Pulse Width (low) Watchdog Timer Time-out Period (No Prescaler) Oscillation Start-up Timer Period Power up Timer Period I/O Hi-impedance from MCLR Low or Watchdog Timer Reset Brown-out Reset pulse width Parity Error Reset Min 2 7 -- 28 -- 100 -- Typ -- 18 1024TOSC 72 -- -- TBD Max -- 33 -- 132 2.1 -- -- Units s ms -- ms s s s VDD BVDD (D005) Conditions VDD = 5V, -40C to +125C VDD = 5V, -40C to +125C TOSC = OSC1 period VDD = 5V, -40C to +125C
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
DS30272A-page 120
(c) 1997 Microchip Technology Inc.
PIC16C71X
Applicable Devices FIGURE 13-6: TIMER0 CLOCK TIMINGS
RA4/T0CKI
710 71 711 715
40 42
41
TMR0
Note: Refer to Figure 13-1 for load conditions.
TABLE 13-5:
Param No. 40 Sym Tt0H
TIMER0 CLOCK REQUIREMENTS
Characteristic T0CKI High Pulse Width No Prescaler With Prescaler Min 0.5TCY + 20* 10* 0.5TCY + 20* 10* Greater of: 20s or TCY + 40* N 2Tosc Typ Max Units Conditions -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns N = prescale value (1, 2, 4,..., 256)
41
Tt0L
T0CKI Low Pulse Width
No Prescaler With Prescaler
42
Tt0P
T0CKI Period
48 *
Tcke2tmrI Delay from external clock edge to timer increment
--
7Tosc
--
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
(c) 1997 Microchip Technology Inc.
DS30272A-page 121
PIC16C71X
Applicable Devices TABLE 13-6: 710 71 711 715 A/D CONVERTER CHARACTERISTICS: PIC16C715-04 (COMMERCIAL, INDUSTRIAL, EXTENDED) PIC16C715-10 (COMMERCIAL, INDUSTRIAL, EXTENDED) PIC16C715-20 (COMMERCIAL, INDUSTRIAL, EXTENDED)
Characteristic Resolution Integral error Differential error Full scale error Offset error Monotonicity Reference voltage Analog input voltage Recommended impedance of analog voltage source A/D conversion current (VDD) VREF input current (Note 2) Min -- -- -- -- -- -- 2.5V VSS - 0.3 -- Typ -- -- -- -- -- guaranteed -- -- -- Max 8-bits less than 1 LSb less than 1 LSb less than 1 LSb less than 1 LSb -- VDD + 0.3 VREF + 0.3 10.0 Units -- -- -- -- -- -- V V k Conditions VREF = VDD, VSS AIN VREF VREF = VDD, VSS AIN VREF VREF = VDD, VSS AIN VREF VREF = VDD, VSS AIN VREF VREF = VDD, VSS AIN VREF VSS AIN VREF
Parameter No.
Sym NR NINT NDIF NFS NOFF -- VREF VAIN ZAIN
IAD IREF *
-- --
180 --
-- 1 10
A mA A
Average current consumption when A/D is on. (Note 1) During sampling All other times
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes any such leakage from the A/D module. 2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input.
DS30272A-page 122
(c) 1997 Microchip Technology Inc.
PIC16C71X
Applicable Devices TABLE 13-7:
Parameter No.
710 71 711 715
A/D CONVERTER CHARACTERISTICS: PIC16LC715-04 (COMMERCIAL, INDUSTRIAL)
Sym NR NINT NDIF NFS Characteristic Resolution Integral error Differential error Full scale error Offset error Monotonicity Reference voltage Analog input voltage Recommended impedance of analog voltage source A/D conversion current (VDD) VREF input current (Note 2) Min -- -- -- -- -- -- 2.5V VSS - 0.3 -- Typ -- -- -- -- -- guaranteed -- -- -- Max 8-bits less than 1 LSb less than 1 LSb less than 1 LSb less than 1 LSb -- VDD + 0.3 VREF + 0.3 10.0 Units -- -- -- -- -- -- V V k Conditions VREF = VDD, VSS AIN VREF VREF = VDD, VSS AIN VREF VREF = VDD, VSS AIN VREF VREF = VDD, VSS AIN VREF VREF = VDD, VSS AIN VREF VSS AIN VREF
NOFF -- VREF VAIN ZAIN
IAD IREF *
-- --
90 --
-- 1 10
A mA A
Average current consumption when A/D is on. (Note 1) During sampling All other times
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes any such leakage from the A/D module. 2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input.
(c) 1997 Microchip Technology Inc.
DS30272A-page 123
PIC16C71X
Applicable Devices 710 71 711 715 FIGURE 13-7: A/D CONVERSION TIMING
BSF ADCON0, GO (TOSC/2) (1) Q4 130 A/D CLK 132 131
1 Tcy
A/D DATA
7
6
5
4
3
2
1
0
ADRES
OLD_DATA
NEW_DATA
ADIF GO SAMPLING STOPPED DONE
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
TABLE 13-8:
Parameter No. 130 130
A/D CONVERSION REQUIREMENTS
Sym TAD TAD Characteristic A/D clock period A/D Internal RC Oscillator source 3.0 2.0 6.0 4.0 9.5TAD 9.0 6.0 -- s s -- Min 1.6 2.0 Typ Max -- -- Units s s Conditions VREF 3.0V VREF full range ADCS1:ADCS0 = 11 (RC oscillator source) PIC16LC715, VDD = 3.0V PIC16C715
131
TCNV
Conversion time (not including S/H time). Note 1 Acquisition time
--
132 *
TACQ
Note 2
20
--
s
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: ADRES register may be read on the following TCY cycle.
DS30272A-page 124
(c) 1997 Microchip Technology Inc.
PIC16C71X
Applicable Devices 710 71 711 715
14.0
DC AND AC CHARACTERISTICS GRAPHS AND TABLES FOR PIC16C715
The graphs and tables provided in this section are for design guidance and are not tested or guaranteed. In some graphs or tables the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are guaranteed to operate properly only within the specified range. Note: The data presented in this section is a statistical summary of data collected on units from different lots over a period of time and matrix samples. 'Typical' represents the mean of the distribution at, 25C, while 'max' or 'min' represents (mean +3) and (mean -3) respectively where is standard deviation.
FIGURE 14-1: TYPICAL IPD vs. VDD (WDT DISABLED, RC MODE)
35
30
25
IPD(nA)
20
15
10
Shaded area is beyond recommended range.
5
0 2.5
3.0
3.5
4.0 4.5 VDD(Volts)
5.0
5.5
6.0
FIGURE 14-2: MAXIMUM IPD vs. VDD (WDT DISABLED, RC MODE)
10.000 85C 70C 1.000
IPD(A)
0.100
25C
0C -40C 0.010
Shaded area is beyond recommended range.
0.001 2.5
3.0
3.5
4.0 4.5 VDD(Volts)
5.0
5.5
6.0
(c) 1997 Microchip Technology Inc.
DS30272A-page 125
PIC16C71X
Applicable Devices 710 71 711 715 FIGURE 14-5: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD
6.0 5.5 20 Fosc(MHz) IPD(A) 5.0 4.5 15 10 5 0 2.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0.5 0.0 2.5 3.0 3.5 4.0 4.5 VDD(Volts) 5.0 5.5 6.0 VDD(Volts) Shaded area is beyond recommended range. R = 100k R = 10k R = 5k Cext = 22 pF, T = 25C
FIGURE 14-3: TYPICAL IPD vs. VDD @ 25C (WDT ENABLED, RC MODE)
25
FIGURE 14-4: MAXIMUM IPD vs. VDD (WDT ENABLED, RC MODE)
35 30 25 IPD(A) 20 -40C
Shaded area is beyond recommended range.
FIGURE 14-6: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD
2.4 Cext = 100 pF, T = 25C 2.2 2.0 1.8 Fosc(MHz) 1.6 1.4 1.2 1.0 0.8 0.6 0.4 R = 10k R = 5k R = 3.3k
0C
70C 15 10 5 0 2.5 85C
3.0
3.5
4.0
4.5
5.0
5.5
6.0
0.2 0.0 2.5 3.0 3.5 4.0 4.5 5.0
R = 100k
VDD(Volts) Shaded area is beyond recommended range.
5.5
6.0
VDD(Volts) Shaded area is beyond recommended range.
FIGURE 14-7: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD
1000 900 800 Fosc(kHz) 700 600 500 400 300 200 100 0 2.5 3.0 3.5 4.0 4.5 5.0 R = 100k 5.5 6.0 R = 10k R = 5k R = 3.3k Cext = 300 pF, T = 25C
VDD(Volts) Shaded area is beyond recommended range.
DS30272A-page 126
(c) 1997 Microchip Technology Inc.
PIC16C71X
Applicable Devices FIGURE 14-8: TYPICAL IPD vs. VDD BROWNOUT DETECT ENABLED (RC MODE)
1400 1200 1000 IPD(A) 800 600 400 200 0 2.5 Device in Brown-out Reset 3.0 3.5 4.0 4.5 VDD(Volts) 5.0 5.5 6.0 Device NOT in Brown-out Reset IPD(A) 30 25 20 15 10 5 0 2.5 3.0 3.5 4.0 4.5 VDD(Volts) 5.0 5.5 6.0
710 71 711 715
FIGURE 14-10: TYPICAL IPD vs. TIMER1 ENABLED (32 kHz, RC0/RC1 = 33 pF/33 pF, RC MODE)
This shaded region represents the built-in hysteresis of the brown-out reset circuitry. Shaded area is beyond recommended range.
Shaded area is beyond recommended range.
FIGURE 14-9: MAXIMUM IPD vs. VDD BROWN-OUT DETECT ENABLED (85C TO -40C, RC MODE)
1600 1400 1200 1000 IPD(A) 800 600 400 200 4.3 0 2.5 3.0 3.5 4.0 4.5 VDD(Volts) 5.0 5.5 6.0 Device in Brown-out Reset Device NOT in Brown-out Reset
FIGURE 14-11: MAXIMUM IPD vs. TIMER1 ENABLED (32 kHz, RC0/RC1 = 33 pF/33 pF, 85C TO -40C, RC MODE)
45 40 35 30 IPD(A) 25 20 15 10 5 0 2.5 3.0 3.5 4.0 4.5 VDD(Volts) 5.0 5.5 6.0
This shaded region represents the built-in hysteresis of the brown-out reset circuitry. Shaded area is beyond recommended range.
Shaded area is beyond recommended range.
(c) 1997 Microchip Technology Inc.
DS30272A-page 127
PIC16C71X
Applicable Devices 710 71 711 715 FIGURE 14-12: TYPICAL IDD vs. FREQUENCY (RC MODE @ 22 pF, 25C)
2000 1800 1600 1400 IDD(A) 1200 1000 800 600 400 200 0 0.0
5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
Frequency(MHz)
Shaded area is beyond recommended range
FIGURE 14-13: MAXIMUM IDD vs. FREQUENCY (RC MODE @ 22 pF, -40C TO 85C)
2000 1800 1600 1400 IDD(A) 1200 1000 800 600 400 200 0 0.0
5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
Frequency(MHz)
Shaded area is beyond recommended range
DS30272A-page 128
(c) 1997 Microchip Technology Inc.
PIC16C71X
Applicable Devices FIGURE 14-14: TYPICAL IDD vs. FREQUENCY (RC MODE @ 100 pF, 25C)
1600
710 71 711 715
1400
5.5V 5.0V
1200
4.5V 4.0V
1000
3.5V
IDD(A)
800
3.0V
2.5V
600
400
200
0 0 200 400 Shaded area is beyond recommended range 600 800 1000 1200 1400 1600 1800 Frequency(kHz)
FIGURE 14-15: MAXIMUM IDD vs. FREQUENCY (RC MODE @ 100 pF, -40C TO 85C)
1600
1400
5.5V 5.0V
1200
4.5V 4.0V
1000
3.5V
IDD(A)
800
3.0V
2.5V
600
400
200
0 0 200 400 600 800 1000 1200 1400 1600 1800 Shaded area is beyond recommended range Frequency(kHz)
(c) 1997 Microchip Technology Inc.
DS30272A-page 129
PIC16C71X
Applicable Devices 710 71 711 715 FIGURE 14-16: TYPICAL IDD vs. FREQUENCY (RC MODE @ 300 pF, 25C)
1200
5.5V
1000
5.0V 4.5V
800
4.0V 3.5V
IDD(A)
3.0V
600
2.5V
400
200
0 0 100 200 300 400 500 600 700 Frequency(kHz)
FIGURE 14-17: MAXIMUM IDD vs. FREQUENCY (RC MODE @ 300 pF, -40C TO 85C)
1200
5.5V
1000
5.0V 4.5V
800
4.0V 3.5V
IDD(A)
3.0V
600
2.5V
400
200
0 0 100 200 300 400 500 600 700 Frequency(kHz)
DS30272A-page 130
(c) 1997 Microchip Technology Inc.
PIC16C71X
Applicable Devices FIGURE 14-18: TYPICAL IDD vs. CAPACITANCE @ 500 kHz (RC MODE)
600 500 400 IDD(A) 300 200 100 0.5 0 20 pF 100 pF Capacitance(pF) 300 pF 0.0 3.0 3.5 4.0 4.5 5.0 5.5 VDD(Volts) 6.0 6.5 7.0 5.0V 4.0V 3.0V gm(mA/V)
710 71 711 715
FIGURE 14-19: TRANSCONDUCTANCE(gm) OF HS OSCILLATOR vs. VDD
4.0 Max -40C 3.5 3.0 2.5 2.0 1.5 1.0 Min 85C Typ 25C
TABLE 14-1:
RC OSCILLATOR FREQUENCIES
Average Rext Fosc @ 5V, 25C 5k 10k 100k 4.12 MHz 2.35 MHz 268 kHz 1.80 MHz 1.27 MHz 688 kHz 77.2 kHz 707 kHz 501 kHz 269 kHz 28.3 kHz 1.4% 1.4%
Shaded area is beyond recommended range.
FIGURE 14-20: TRANSCONDUCTANCE(gm) OF LP OSCILLATOR vs. VDD
110 100 90 80 gm(A/V) 70 60 50 40 30 20 10 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 VDD(Volts) Shaded area is beyond recommended range. 7.0 Min 85C Typ 25C Max -40C
Cext 22 pF
1.1% 1.0% 1.0% 1.2% 1.0% 1.4% 1.2% 1.6% 1.1%
100 pF
3.3k 5k 10k 100k
300 pF
3.3k 5k 10k 100k
The percentage variation indicated here is part to part variation due to normal process distribution. The variation indicated is 3 standard deviation from average value for VDD = 5V.
FIGURE 14-21: TRANSCONDUCTANCE(gm) OF XT OSCILLATOR vs. VDD
1000 900 800 700 gm(A/V) 600 500 400 300 200 100 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 VDD(Volts) Shaded area is beyond recommended range. 7.0 Min 85C Typ 25C Max -40C
(c) 1997 Microchip Technology Inc.
DS30272A-page 131
PIC16C71X
Applicable Devices 710 71 711 715 FIGURE 14-24: TYPICAL XTAL STARTUP TIME vs. VDD (XT MODE, 25C) FIGURE 14-22: TYPICAL XTAL STARTUP TIME vs. VDD (LP MODE, 25C)
3.5 3.0 2.5 Startup Time(Seconds) 50 2.0
32 kHz, 33 pF/33 pF
70 60
Startup Time(ms)
40
200 kHz, 68 pF/68 pF
1.5 1.0 0.5 0.0 2.5
200 kHz, 15 pF/15 pF
30
200 kHz, 47 pF/47 pF
20
1 MHz, 15 pF/15 pF
10 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
4 MHz, 15 pF/15 pF
3.0
3.5
4.0 4.5 VDD(Volts)
5.0
5.5
6.0
VDD(Volts)
Shaded area is beyond recommended range.
Shaded area is beyond recommended range.
TABLE 14-2:
FIGURE 14-23: TYPICAL XTAL STARTUP TIME vs. VDD (HS MODE, 25C)
7 6 Startup Time(ms)
CAPACITOR SELECTION FOR CRYSTAL OSCILLATORS
Crystal Freq 32 kHz 200 kHz 200 kHz 1 MHz 4 MHz Cap. Range C1 33 pF 15 pF 47-68 pF 15 pF 15 pF 15 pF 15-33 pF 15-33 pF Cap. Range C2 33 pF 15 pF 47-68 pF 15 pF 15 pF 15 pF 15-33 pF 15-33 pF
Osc Type LP XT
5 4
8 MHz, 33 pF/33 pF
20 MHz, 33 pF/33 pF
HS
20 MHz, 15 pF/15 pF 8 MHz, 15 pF/15 pF
4 MHz 8 MHz 20 MHz
3 2 1 4.0
4.5
5.0 VDD(Volts)
5.5
6.0
Crystals Used 32 kHz 200 kHz 1 MHz 4 MHz 8 MHz 20 MHz Epson C-001R32.768K-A STD XTL 200.000KHz ECS ECS-10-13-1 ECS ECS-40-20-1 EPSON CA-301 8.000M-C EPSON CA-301 20.000M-C 20 PPM 20 PPM 50 PPM 50 PPM 30 PPM 30 PPM
Shaded area is beyond recommended range.
DS30272A-page 132
(c) 1997 Microchip Technology Inc.
PIC16C71X
Applicable Devices FIGURE 14-25: TYPICAL IDD vs. FREQUENCY (LP MODE, 25C) 710 71 711 715 FIGURE 14-27: TYPICAL IDD vs. FREQUENCY (XT MODE, 25C)
1800 1600 120 1400 100 1200 80 IDD(A) 1000 60 40 20 0 0
5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 5.0V 4.5V 4.0V 3.5V 3.0V 5.5V
IDD(A)
800 600 400
2.5V
50
100 Frequency(kHz)
150
200
200 0 0.0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
Frequency(MHz)
FIGURE 14-26: MAXIMUM IDD vs. FREQUENCY (LP MODE, 85C TO -40C)
140 120 100 80 IDD(A) 60 40 20 0 0
FIGURE 14-28: MAXIMUM IDD vs. FREQUENCY (XT MODE, -40C TO 85C)
1800 1600 1400 1200 1000 IDD(A) 800 600 400 200
5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V
5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V
50
100 Frequency(kHz)
150
200 0 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0
Frequency(MHz)
(c) 1997 Microchip Technology Inc.
DS30272A-page 133
PIC16C71X
Applicable Devices 710 71 711 715 FIGURE 14-30: MAXIMUM IDD vs. FREQUENCY (HS MODE, -40C TO 85C)
7.0 6.0 6.0 5.0 5.0 IDD(mA) 4.0 3.0 2.0 1.0 0.0 12 IDD(mA)
5.5V 5.0V 4.5V 4.0V
FIGURE 14-29: TYPICAL IDD vs. FREQUENCY (HS MODE, 25C)
7.0
4.0 3.0 2.0 1.0
5.5V 5.0V 4.5V 4.0V
4
6
8
10
12
14
16
18
20
Frequency(MHz)
0.0 12
4
6
8
10
12
14
16
18
20
Frequency(MHz)
DS30272A-page 134
(c) 1997 Microchip Technology Inc.
PIC16C71X
Applicable Devices 710 71 711 715
15.0
ELECTRICAL CHARACTERISTICS FOR PIC16C71
Absolute Maximum Ratings Ambient temperature under bias................................................................................................................ .-55 to +125C Storage temperature .............................................................................................................................. -65C to +150C Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4).......................................... -0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS .......................................................................................................... -0.3 to +7.5V Voltage on MCLR with respect to VSS (Note 2)..................................................................................................0 to +14V Voltage on RA4 with respect to Vss ...................................................................................................................0 to +14V Total power dissipation (Note 1)...........................................................................................................................800 mW Maximum current out of VSS pin ...........................................................................................................................150 mA Maximum current into VDD pin ..............................................................................................................................100 mA Input clamp current, IIK (VI < 0 or VI > VDD)..................................................................................................................... 20 mA Output clamp current, IOK (VO < 0 or VO > VDD) ............................................................................................................. 20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................20 mA Maximum current sunk by PORTA ..........................................................................................................................80 mA Maximum current sourced by PORTA .....................................................................................................................50 mA Maximum current sunk by PORTB........................................................................................................................150 mA Maximum current sourced by PORTB...................................................................................................................100 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOl x IOL) Note 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a "low" level to the MCLR pin rather than pulling this pin directly to VSS. NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
TABLE 15-1:
OSC
CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)
PIC16C71-20 VDD: 4.5V to 5.5V IDD: 1.8 mA typ. at 5.5V IPD: 1.0 A typ. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 1.8 mA typ. at 5.5V IPD: 1.0 A typ. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 30 mA max. at 5.5V IPD: 1.0 A typ. at 4.5V Freq: 20 MHz max. VDD: 3.0V to 6.0V IDD: 32 A max. at 32 kHz, 3.0V IPD: 9 A max. at 3.0V Freq: 200 kHz max. Not recommended for use in HS mode PIC16LC71-04 VDD: 3.0V to 6.0V IDD: 1.4 mA typ. at 3.0V IPD: 0.6 A typ. at 3V Freq: 4 MHz max. VDD: 3.0V to 6.0V IDD: 1.4 mA typ. at 3.0V IPD: 0.6 A typ. at 3V Freq: 4 MHz max. JW Devices VDD: 4.0V to 6.0V IDD: 3.3 mA max. at 5.5V IPD: 14 A max. at 4V Freq:4 MHz max. VDD: 4.0V to 6.0V IDD: 3.3 mA max. at 5.5V IPD: 14 A max. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 30 mA max. at 5.5V IPD: 1.0 A typ. at 4.5V Freq: 20 MHz max. VDD: 3.0V to 6.0V IDD: 32 A max. at 32 kHz, 3.0V IPD: 9 A max. at 3.0V Freq: 200 kHz max.
PIC16C71-04 VDD: 4.0V to 6.0V IDD: 3.3 mA max. at 5.5V IPD: 14 A max. at 4V Freq:4 MHz max. VDD: 4.0V to 6.0V IDD: 3.3 mA max. at 5.5V IPD: 14 A max. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V
RC
XT
HS
IDD: 13.5 mA typ. at 5.5V IPD: 1.0 A typ. at 4.5V Freq: 4 MHz max. VDD: 4.0V to 6.0V IDD: 15 A typ. at 32 kHz, 4.0V IPD: 0.6 A typ. at 4.0V Freq: 200 kHz max.
LP
Not recommended for use in LP mode
The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recommended that the user select the device type that ensures the specifications required.
(c) 1997 Microchip Technology Inc.
DS30272A-page 135
PIC16C71X
Applicable Devices 15.1 710 71 711 715 PIC16C71-04 (Commercial, Industrial) PIC16C71-20 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature 0C TA +70C (commercial) -40C TA +85C (industrial) Sym VDD VDR VPOR Min 4.0 4.5 Typ Max Units 1.5 VSS 6.0 5.5 V V V V See section on Power-on Reset for details Conditions XT, RC and LP osc configuration HS osc configuration
DC Characteristics:
DC CHARACTERISTICS Param No. Characteristic
D001 Supply Voltage D001A D002* D003 RAM Data Retention Voltage (Note 1) VDD start voltage to ensure internal Power-on Reset signal VDD rise rate to ensure internal Power-on Reset signal Supply Current (Note 2)
D004*
SVDD
0.05
-
-
V/ms See section on Power-on Reset for details
D010
IDD
-
1.8
3.3
mA
XT, RC osc configuration FOSC = 4 MHz, VDD = 5.5V (Note 4) HS osc configuration FOSC = 20 MHz, VDD = 5.5V VDD = 4.0V, WDT enabled, -40C to +85C VDD = 4.0V, WDT disabled, -0C to +70C VDD = 4.0V, WDT disabled, -40C to +85C
D013 D020 Power-down Current D021 (Note 3) D021A * Note 1: 2: IPD
-
13.5 7 1.0 1.0
30 28 14 16
mA A A A
3: 4:
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. This is the limit to which VDD can be lowered without losing RAM data. The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
DS30272A-page 136
(c) 1997 Microchip Technology Inc.
PIC16C71X
Applicable Devices 15.2 DC Characteristics: PIC16LC71-04 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated) OOperating temperature 0C TA +70C (commercial) -40C TA +85C (industrial) Sym VDD VDR VPOR Min 3.0 Typ Max Units 1.5 VSS 6.0 V V V See section on Power-on Reset for details Conditions XT, RC, and LP osc configuration
710 71 711 715
DC CHARACTERISTICS Param No. D001 D002* D003 Characteristic Supply Voltage RAM Data Retention Voltage (Note 1) VDD start voltage to ensure internal Power-on Reset signal VDD rise rate to ensure internal Power-on Reset signal Supply Current (Note 2)
D004*
SVDD
0.05
-
-
V/ms See section on Power-on Reset for details
D010
IDD
-
1.4
2.5
mA A A A A
XT, RC osc configuration FOSC = 4 MHz, VDD = 3.0V (Note 4) LP osc configuration FOSC = 32 kHz, VDD = 3.0V, WDT disabled VDD = 3.0V, WDT enabled, -40C to +85C VDD = 3.0V, WDT disabled, 0C to +70C VDD = 3.0V, WDT disabled, -40C to +85C
D010A D020 D021 D021A * Note 1: 2: Power-down Current (Note 3) IPD
-
15 5 0.6 0.6
32 20 9 12
3: 4:
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. This is the limit to which VDD can be lowered without losing RAM data. The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
(c) 1997 Microchip Technology Inc.
DS30272A-page 137
PIC16C71X
Applicable Devices 15.3 710 71 711 715 PIC16C71-04 (Commercial, Industrial) PIC16C71-20 (Commercial, Industrial) PIC16LC71-04 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated) OOperating temperature 0C TA +70C (commercial) -40C TA +85C (industrial) Operating voltage VDD range as described in DC spec Section 15.1 and Section 15.2. Sym Min Typ Max Units Conditions VIL VSS VSS VSS VSS VIH 0.15V 0.8V 0.2VDD 0.3VDD V V V V For entire VDD range 4.5 VDD 5.5V Note1
DC Characteristics:
DC CHARACTERISTICS
Param No.
Characteristic Input Low Voltage I/O ports with TTL buffer with Schmitt Trigger buffer MCLR, OSC1 (in RC mode) OSC1 (in XT, HS and LP) Input High Voltage I/O ports (Note 4) with TTL buffer
D030 D031 D032 D033
D040 D040A D041 D042 D042A D043 D070 D060 D061 D063
with Schmitt Trigger buffer MCLR, RB0/INT OSC1 (XT, HS and LP) OSC1 (in RC mode) PORTB weak pull-up current Input Leakage Current (Notes 2, 3) I/O ports MCLR, RA4/T0CKI OSC1 Output Low Voltage I/O ports OSC2/CLKOUT (RC osc config) Output High Voltage I/O ports (Note 3)
2.0 VDD 0.25VDD VDD + 0.8V VDD 0.85VDD 0.85VDD VDD 0.7VDD VDD 0.9VDD VDD IPURB 50 250 400 IIL 1 5 5
V
4.5 VDD 5.5V For entire VDD range
For entire VDD range V V Note1 V A VDD = 5V, VPIN = VSS A Vss VPIN VDD, Pin at hiimpedance A Vss VPIN VDD A Vss VPIN VDD, XT, HS and LP osc configuration V V IOL = 8.5mA, VDD = 4.5V, -40C to +85C IOL = 1.6mA, VDD = 4.5V, -40C to +85C
D080 D083
VOL
-
-
0.6 0.6
D090 D092 D130* Note 1: 2: 3: 4:
IOH = -3.0mA, VDD = 4.5V, -40C to +85C OSC2/CLKOUT (RC osc config) VDD - 0.7 V IOH = -1.3mA, VDD = 4.5V, -40C to +85C Open-Drain High Voltage VOD 14 V RA4 pin Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. In RC oscillator configuration, the OSC1 pin is a Schmitt trigger input. It is not recommended that the PIC16C71 be driven with external clock in RC mode. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as current sourced by the pin. PIC16C71 Rev. "Ax" INT pin has a TTL input buffer. PIC16C71 Rev. "Bx" INT pin has a Schmitt Trigger input buffer.
VOH VDD - 0.7 -
-
V
DS30272A-page 138
(c) 1997 Microchip Technology Inc.
PIC16C71X
Applicable Devices 710 71 711 715
Standard Operating Conditions (unless otherwise stated) OOperating temperature 0C TA +70C (commercial) -40C TA +85C (industrial) Operating voltage VDD range as described in DC spec Section 15.1 and Section 15.2. Sym Min Typ Max Units Conditions
DC CHARACTERISTICS
Param No.
Characteristic Capacitive Loading Specs on Output Pins OSC2 pin
D100
COSC2
15
pF
In XT, HS and LP modes when external clock is used to drive OSC1.
D101 Note 1: 2: 3: 4:
All I/O pins and OSC2 (in RC mode) CIO 50 pF Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. In RC oscillator configuration, the OSC1 pin is a Schmitt trigger input. It is not recommended that the PIC16C71 be driven with external clock in RC mode. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as current sourced by the pin. PIC16C71 Rev. "Ax" INT pin has a TTL input buffer. PIC16C71 Rev. "Bx" INT pin has a Schmitt Trigger input buffer.
(c) 1997 Microchip Technology Inc.
DS30272A-page 139
PIC16C71X
Applicable Devices 15.4 710 71 711 715 Timing Parameter Symbology
The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKOUT cs CS di SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (Hi-impedance) L Low
T
Time
osc rd rw sc ss t0 t1 wr
OSC1 RD RD or WR SCK SS T0CKI T1CKI WR
P R V Z
Period Rise Valid Hi-impedance
FIGURE 15-1: LOAD CONDITIONS
Load condition 1 VDD/2 Load condition 2
RL
Pin VSS RL = 464 CL = 50 pF 15 pF
CL
Pin VSS
CL
for all pins except OSC2/CLKOUT for OSC2 output
DS30272A-page 140
(c) 1997 Microchip Technology Inc.
PIC16C71X
Applicable Devices 15.5 Timing Diagrams and Specifications 710 71 711 715
FIGURE 15-2: EXTERNAL CLOCK TIMING
Q4 Q1 Q2 Q3 Q4 Q1
OSC1
1 2 3 3 4 4
CLKOUT
TABLE 15-2:
Parameter No.
EXTERNAL CLOCK TIMING REQUIREMENTS
Sym Fosc Characteristic External CLKIN Frequency (Note 1) Min Typ Max Units Conditions
DC -- 4 MHz XT osc mode DC -- 4 MHz HS osc mode (-04) DC -- 20 MHz HS osc mode (-20) DC -- 200 kHz LP osc mode Oscillator Frequency DC -- 4 MHz RC osc mode (Note 1) 0.1 -- 4 MHz XT osc mode 1 -- 4 MHz HS osc mode 1 -- 20 MHz HS osc mode 1 Tosc External CLKIN Period 250 -- -- ns XT osc mode (Note 1) 250 -- -- ns HS osc mode (-04) 50 -- -- ns HS osc mode (-20) 5 -- -- s LP osc mode Oscillator Period 250 -- -- ns RC osc mode (Note 1) 250 -- 10,000 ns XT osc mode 250 -- 1,000 ns HS osc mode (-04) 50 -- 1,000 ns HS osc mode (-20) 5 -- -- s LP osc mode 1.0 TCY DC s TCY = 4/Fosc 2 TCY Instruction Cycle Time (Note 1) 3 TosL, External Clock in (OSC1) High or 50 -- -- ns XT oscillator TosH Low Time 2.5 -- -- s LP oscillator 10 -- -- ns HS oscillator 4 TosR, External Clock in (OSC1) Rise or 25 -- -- ns XT oscillator TosF Fall Time 50 -- -- ns LP oscillator 15 -- -- ns HS oscillator Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices. OSC2 is disconnected (has no loading) for the PIC16C71.
(c) 1997 Microchip Technology Inc.
DS30272A-page 141
PIC16C71X
Applicable Devices 710 71 711 715 FIGURE 15-3: CLKOUT AND I/O TIMING
Q4 OSC1 10 CLKOUT 13 14 I/O Pin (input) 17 I/O Pin (output) old value 20, 21 Note: Refer to Figure 15-1 for load conditions. 15 new value 19 12 18 16 11 Q1 Q2 Q3
TABLE 15-3:
Parameter Sym No. 10* 11* 12* 13* 14* 15* 16* 17* 18*
CLKOUT AND I/O TIMING REQUIREMENTS
Characteristic OSC1 to CLKOUT OSC1 to CLKOUT CLKOUT rise time CLKOUT fall time CLKOUT to Port out valid Port in valid before CLKOUT Port in hold after CLKOUT OSC1 (Q1 cycle) to Port out valid OSC1 (Q2 cycle) to Port input invalid (I/O in hold time) Port output rise time Port output fall time INT pin high or low time RB7:RB4 change INT high or low time PIC16C71 PIC16LC71 Min -- -- -- -- -- 0.25TCY + 25 0 -- 100 200 0 -- -- -- -- 20 20 Typ 15 15 5 5 -- -- -- -- -- -- -- 10 -- 10 -- -- -- Max 30 30 15 15 0.5TCY + 20 -- -- 80 - 100 -- -- -- 25 60 25 60 -- -- Units Conditions ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1
TosH2ckL TosH2ckH TckR TckF TckL2ioV TioV2ckH TckH2ioI TosH2ioV TosH2ioI
19* 20* 21* 22* 23*
TioV2osH TioR TioF Tinp Trbp
Port input valid to OSC1 (I/O in setup time) PIC16C71 PIC16LC71 PIC16C71 PIC16LC71
* These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. These parameters are asynchronous events not related to any internal clock edges. Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
DS30272A-page 142
(c) 1997 Microchip Technology Inc.
PIC16C71X
Applicable Devices 710 71 711 715 FIGURE 15-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING
VDD MCLR Internal POR 33 PWRT Time-out OSC Time-out Internal RESET Watchdog Timer RESET 34 I/O Pins 32 30
31 34
Note: Refer to Figure 15-1 for load conditions.
TABLE 15-4:
Parameter No. 30 31 32 33 34
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER REQUIREMENTS
Sym TmcL Twdt Tost Tpwrt TIOZ Characteristic MCLR Pulse Width (low) Watchdog Timer Time-out Period (No Prescaler) Oscillation Start-up Timer Period Power-up Timer Period I/O High Impedance from MCLR Low -- 28* -- 1024 TOSC 72 -- -- 132* 100 -- ms ns TOSC = OSC1 period Min 200 7* Typ -- 18 Max -- 33* Units ns ms Conditions
VDD = 5V, -40C to +85C VDD = 5V, -40C to +85C
VDD = 5V, -40C to +85C
*
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
(c) 1997 Microchip Technology Inc.
DS30272A-page 143
PIC16C71X
Applicable Devices 710 71 711 715 FIGURE 15-5: TIMER0 EXTERNAL CLOCK TIMINGS
RA4/T0CKI
40 42
41
TMR0
Note: Refer to Figure 15-1 for load conditions.
TABLE 15-5:
Param No. 40*
TIMER0 EXTERNAL CLOCK REQUIREMENTS
Min No Prescaler With Prescaler 0.5TCY + 20 10 0.5TCY + 20 10 TCY + 40 Greater of: 20 ns or TCY + 40 N Typ Max Units Conditions -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns Must also meet parameter 42 Must also meet parameter 42 N = prescale value (2, 4,..., 256)
Sym Characteristic Tt0H T0CKI High Pulse Width
41*
Tt0L T0CKI Low Pulse Width
No Prescaler With Prescaler
42*
Tt0P T0CKI Period
No Prescaler With Prescaler
*
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
DS30272A-page 144
(c) 1997 Microchip Technology Inc.
PIC16C71X
Applicable Devices TABLE 15-6:
Param No. A01 A02
710 71 711 715
A/D CONVERTER CHARACTERISTICS
Min -- -- -- -- -- -- -- -- -- -- -- -- 3.0V VSS - 0.3 -- -- 10 PIC16C71 -- -- PIC16LC71 -- -- 10 A -- -- 40 1 A mA Typ -- -- -- -- -- -- -- -- -- -- -- guaranteed -- -- -- 180 -- Max 8 bits < 1 < 2 < 1 < 2 < 1 < 2 < 1 < 2 < 1 < 2 -- VDD + 0.3 VREF 10.0 -- 1000 Units bits LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb -- V V k A A Average current consumption when A/D is on. (Note 1) During VAIN acquisition. Based on differential of VHOLD to VAIN. To charge CHOLD see Section 7.1. During A/D Conversion cycle During VAIN acquisition. Based on differential of VHOLD to VAIN. To charge CHOLD see Section 7.1. During A/D Conversion cycle Conditions VREF = VDD = 5.12V, VSS VAIN VREF VREF = VDD = 5.12V, VSS VAIN VREF VREF = VDD = 3.0V (Note 3) VREF = VDD = 5.12V, VSS VAIN VREF VREF = VDD = 3.0V (Note 3) VREF = VDD = 5.12V, VSS VAIN VREF VREF = VDD = 3.0V (Note 3) VREF = VDD = 5.12V, VSS VAIN VREF VREF = VDD = 3.0V (Note 3) VREF = VDD = 5.12V, VSS VAIN VREF VREF = VDD = 3.0V (Note 3) VSS VAIN VREF
Sym Characteristic NR Resolution
EABS Absolute error
PIC16C71 PIC16LC71
A03
EIL
Integral linearity error
PIC16C71 PIC16LC71
A04
EDL
Differential linearity error
PIC16C71 PIC16LC71
A05
EFS
Full scale error
PIC16C71 PIC16LC71
A06
EOFF Offset error
PIC16C71 PIC16LC71
A10 A20 A25 A30 A40 A50
--
Monotonicity
VREF Reference voltage VAIN Analog input voltage ZAIN Recommended impedance of analog voltage source IAD A/D conversion current (VDD)
IREF VREF input current (Note 2)
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes any such leakage from the A/D module. 2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input. 3: These specifications apply if VREF = 3.0V and if VDD 3.0V. VAIN must be between VSS and VREF.
*
(c) 1997 Microchip Technology Inc.
DS30272A-page 145
PIC16C71X
Applicable Devices 710 71 711 715 FIGURE 15-6: A/D CONVERSION TIMING
BSF ADCON0, GO (TOSC/2) (1) Q4 130 A/D CLK 132 131
1 Tcy
A/D DATA
7
6
5
4
3
2
1
0
ADRES
OLD_DATA
NEW_DATA
ADIF GO SAMPLING STOPPED DONE
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
TABLE 15-7:
Param No. 130 Sym TAD
A/D CONVERSION REQUIREMENTS
Characteristic A/D clock period PIC16C71 PIC16LC71 PIC16C71 PIC16LC71 Min 2.0 2.0 2.0 3.0 -- Note 2 5* Typ -- -- 4.0 6.0 9.5 20 -- Max -- -- 6.0 9.0 -- -- -- Units s s s s TAD s s The minimum time is the amplifier settling time. This may be used if the "new" input voltage has not changed by more than 1 LSb (i.e., 19.5 mV @ 5.12V) from the last sampled voltage (as stated on CHOLD). If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. Conditions TOSC based, VREF 3.0V TOSC based, VREF full range A/D RC Mode A/D RC Mode
131 132
TCNV TACQ
Conversion time (not including S/H time) (Note 1) Acquisition time
134
TGO
Q4 to A/D clock start
--
Tosc/2
--
--
135 *
TSWC
Switching from convert sample time
1.5
--
--
TAD
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. These specifications ensured by design. Note 1: ADRES register may be read on the following TCY cycle. 2: See Section 7.1 for min conditions.
DS30272A-page 146
(c) 1997 Microchip Technology Inc.
PIC16C71X
Applicable Devices 710 71 711 715
16.0
DC AND AC CHARACTERISTICS GRAPHS AND TABLES FOR PIC16C71
FIGURE 16-2: TYPICAL RC OSCILLATOR FREQUENCY VS. VDD
5.0 R = 4.7k 4.5 4.0 3.5 3.0 R = 10k 2.5 Fosc (MHz) 2.0 1.5 Cext = 20 pF, T = 25C 1.0 R = 100k 0.5 0.0 3.0
The graphs and tables provided in this section are for design guidance and are not tested or guaranteed. In some graphs or tables the data presented are outside specified operating range (e.g. outside specified VDD range). This is for information only and devices are guaranteed to operate properly only within the specified range. Note: The data presented in this section is a statistical summary of data collected on units from different lots over a period of time and matrix samples. 'Typical' represents the mean of the distribution while 'max' or 'min' represents (mean + 3) and (mean - 3) respectively where is standard deviation.
FIGURE 16-1: TYPICAL RC OSCILLATOR FREQUENCY VS. TEMPERATURE
Fosc Fosc (25C) Frequency Normalized to 25C 1.050 1.025 1.000 0.975 0.950 0.925 0.900 0.875 VDD = 3.5V VDD = 5.5V Rext = 10k Cext = 100 pF
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
FIGURE 16-3: TYPICAL RC OSCILLATOR FREQUENCY VS. VDD
2.0 1.8 1.6 1.4 R = 3.3k
0.850 0 10 20 30 T(C) 1.0 Fosc (MHz) 0.8 40 50 60 70 1.2
R = 4.7k
R = 10k 0.6 Cext = 100 pF, T = 25C 0.4 0.2 0.0 3.0 R = 100k
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
(c) 1997 Microchip Technology Inc.
DS30272A-page 147
PIC16C71X
Applicable Devices 710 71 711 715 TABLE 16-1: RC OSCILLATOR FREQUENCIES
Average Cext 20 pF
.6 R = 4.7k
FIGURE 16-4: TYPICAL RC OSCILLATOR FREQUENCY VS. VDD
.8 R = 3.3k .7
Rext FOSC @ 5V, 25C 4.7k 10k 100k 3.3k 4.7k 10k 100k 3.3k 4.7k 10k 100k 4.52 MHz 2.47 MHz 290.86 kHz 1.92 MHz 1.49 MHz 788.77 kHz 88.11 kHz 726.89 kHz 573.95 kHz 307.31 kHz 33.82 kHz 17.35% 10.10% 11.90% 9.43% 9.83% 10.92% 16.03% 10.97% 10.14% 10.43% 11.24%
100 pF
Fosc (MHz) .5
.4 R = 10k .3
300 pF
.2
Cext = 300 pF, T = 25C
Data based on matrix samples. See first page of this section for details.
.1 R = 100k 0
The percentage variation indicated here is part to part variation due to normal process distribution. The variation indicated is 3 standard deviation from average value for VDD = 5V.
3.0
3.5
4.0
4.5 VDD (Volts)
5.0
5.5
6.0
FIGURE 16-6: TYPICAL IPD VS. VDD WATCHDOG TIMER ENABLED 25C
14
FIGURE 16-5: TYPICAL IPD VS. VDD WATCHDOG TIMER DISABLED 25C
0.6
12
10 0.5 IPD (A) 8
0.4
6 IPD (A)
0.3
4
0.2
2
0.1
0 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts) 0.0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (Volts)
DS30272A-page 148
(c) 1997 Microchip Technology Inc.
PIC16C71X
Applicable Devices FIGURE 16-7: MAXIMUM IPD VS. VDD WATCHDOG DISABLED
25 40 125C 35 20 30 25 IPD (A) 15 IPD (A) 20 15 10 85C 70C 5 4.0 4.5 5.0 5.5 6.0 VDD (Volts) IPD, with Watchdog Timer enabled, has two components: The leakage current which increases with higher temperature and the operating current of the Watchdog Timer logic which increases with lower temperature. At -40C, the latter dominates explaining the apparently anomalous behavior. 0 3.0 3.5 10 5 0C 70C 85C 125C
710 71 711 715
FIGURE 16-8: MAXIMUM IPD VS. VDD WATCHDOG ENABLED
45 -55C -40C
0 3.0
3.5
4.0 4.5 5.0 VDD (Volts)
5.5
0C -40C -55C 6.0
FIGURE 16-9: VTH (INPUT THRESHOLD VOLTAGE) OF I/O PINS VS. VDD
2.00 1.80 1.60 VTH (Volts) 1.40 1.20 1.00 0.80 0.60 2.5 3.0 3.5 4.0 4.5 VDD (Volts) 5.0 5.5 6.0
25C, TYP
Max (-40C to 85C)
Min (-40C to 85C)
(c) 1997 Microchip Technology Inc.
DS30272A-page 149
Data based on matrix samples. See first page of this section for details.
PIC16C71X
Applicable Devices 710 71 711 715 FIGURE 16-10: VIH, VIL OF MCLR, T0CKI AND OSC1 (IN RC MODE) VS. VDD
4.50 4.00 3.50 VIH, VIL (Volts) 3.00 2.50 2.00 1.50 1.00 0.50 0.00 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (Volts) Data based on matrix samples. See first page of this section for details. Note: These input pins have a Schmitt Trigger input buffer.
VIL, Max (-40C to 85C) VIL, Typ (25C) VIL, Min (-40C to 85C) VIH, Max (-40C to 85C) VIH, Typ (25C) VIH, Min (-40C to 85C)
FIGURE 16-11: VTH (INPUT THRESHOLD VOLTAGE) OF OSC1 INPUT (IN XT, HS, AND LP MODES) VS. VDD
Min (-40C to 85C)
3.60 3.40 3.20 3.00 2.80 2.60 VTH (Volts) 2.40 2.20 2.00 1.80 1.60 1.40 1.20 1.00 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
Min (-40C to 85C) Max (-40C to 85C) TYP (25C)
VDD (Volts)
DS30272A-page 150
(c) 1997 Microchip Technology Inc.
PIC16C71X
Applicable Devices FIGURE 16-12: TYPICAL IDD VS. FREQ (EXT CLOCK, 25C)
10,000 6.0 5.5 5.0 4.5 4.0 3.5 3.0
710 71 711 715
1,000
IDD (A)
100
10
1 10,000 100,000 1,000,000 Frequency (Hz) 10,000,000 100,000,000
FIGURE 16-13: MAXIMUM, IDD VS. FREQ (EXT CLOCK, -40 TO +85C)
10,000 6.0 5.5 5.0 4.5 4.0 3.5 3.0 1,000 IDD (A)
100
10 10,000
100,000
1,000,000 Frequency (Hz)
10,000,000
100,000,000
(c) 1997 Microchip Technology Inc.
DS30272A-page 151
Data based on matrix samples. See first page of this section for details.
PIC16C71X
Applicable Devices 710 71 711 715 FIGURE 16-14: MAXIMUM IDD VS. FREQ WITH A/D OFF (EXT CLOCK, -55 TO +125C)
10,000 6.0 5.5 5.0 4.5 4.0 3.5 3.0 1,000 IDD (A) 100
Data based on matrix samples. See first page of this section for details.
10 10,000 100,000 1,000,000 10,000,000 100,000,000 Frequency (Hz)
FIGURE 16-15: WDT TIMER TIME-OUT PERIOD VS. VDD
FIGURE 16-16: TRANSCONDUCTANCE (gm) OF HS OSCILLATOR VS. VDD
9000
50 8000 45 7000 40 6000 Max, 85C Max, 70C gm (A/V) 35 WDT Period (ms) 5000 4000 Typ, 25C 3000 2000 1000 0 Min, -40C 2 3 4 5 VDD (Volts) 5 2 3 4 5 6 7 VDD (Volts) 6 7 Min, 85C Max, -40C
30 25 20
Typ, 25C Min, 0C
15
10
DS30272A-page 152
(c) 1997 Microchip Technology Inc.
PIC16C71X
Applicable Devices FIGURE 16-17: TRANSCONDUCTANCE (gm) OF LP OSCILLATOR VS. VDD
225 200 Max, -40C 175 150 gm (A/V) 125 100 75 50 -20 25 0 3.0 Max, -40C IOH (mA) Typ, 25C -10 -5 Min, 85C
710 71 711 715
FIGURE 16-19: IOH VS. VOH, VDD = 3V
0
Typ, 25C -15
Min, 85C
3.5
4.0 4.5 VDD (Volts)
5.0
5.5
6.0
-25 0.0
0.5
1.0
1.5 2.0 VOH (Volts)
2.5
3.0
FIGURE 16-18: TRANSCONDUCTANCE (gm) OF XT OSCILLATOR VS. VDD
2500 Max, -40C 2000
FIGURE 16-20: IOH VS. VOH, VDD = 5V
0 -5 -10 -15
Typ, 25C gm (A/V) 1500
-20 -25
Min @ 85C
Typ @ 25C -30 1000 -35 -40 Min, 85C 500 -45 -50 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 2 3 4 5 VDD (Volts) 6 7 Max @ -40C
0
VOH (Volts)
(c) 1997 Microchip Technology Inc.
DS30272A-page 153
Data based on matrix samples. See first page of this section for details.
IOH (mA)
PIC16C71X
Applicable Devices 710 71 711 715 FIGURE 16-22: IOL VS. VOL, VDD = 5V
90 Max @ -40C 80 70 25 Typ @ 25C 20 IOL (mA) IOL (mA) 50 Min @ +85C 40 60 Typ @ 25C
FIGURE 16-21: IOL VS. VOL, VDD = 3V
35
30
Max @ -40C
15
Min @ +85C
10
30
20 5
Data based on matrix samples. See first page of this section for details.
10 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VOL (Volts) VOL (Volts)
DS30272A-page 154
(c) 1997 Microchip Technology Inc.
PIC16C71X
17.0
17.1
PACKAGING INFORMATION
18-Lead Ceramic CERDIP Dual In-line with Window (300 mil) (JW)
N E1 E Pin No. 1 Indicator Area eA eB C
D S Base Plane Seating Plane B1 B D1 e1 L A1 A3 A A2 S1
Package Group: Ceramic CERDIP Dual In-Line (CDP) Millimeters Symbol A A1 A2 A3 B B1 C D D1 E E1 e1 eA eB L N S S1 Min 0 -- 0.381 3.810 3.810 0.355 1.270 0.203 22.352 20.320 7.620 5.588 2.540 7.366 7.620 3.175 18 0.508 0.381 Max 10 5.080 1.7780 4.699 4.445 0.585 1.651 0.381 23.622 20.320 8.382 7.874 2.540 8.128 10.160 3.810 18 1.397 1.270 Notes Min 0 -- 0.015 0.150 0.150 0.014 0.050 0.008 0.880 0.800 0.300 0.220 0.100 0.290 0.300 0.125 18 0.020 0.015 Inches Max 10 0.200 0.070 0.185 0.175 0.023 0.065 0.015 0.930 0.800 0.330 0.310 0.100 0.320 0.400 0.150 18 0.055 0.050 Notes
Typical Typical Reference
Typical Typical Reference
Reference Typical
Reference Typical
(c) 1997 Microchip Technology Inc.
DS30272A-page 155
PIC16C71X
17.2 18-Lead Plastic Dual In-line (300 mil) (P)
N E1 E Pin No. 1 Indicator Area eA eB C
D S Base Plane Seating Plane B1 B D1 e1 L A1 A2 A S1
Package Group: Plastic Dual In-Line (PLA) Millimeters Symbol A A1 A2 B B1 C D D1 E E1 e1 eA eB L N S S1 Min 0 - 0.381 3.048 0.355 1.524 0.203 22.479 20.320 7.620 6.096 2.489 7.620 7.874 3.048 18 0.889 0.127 Max 10 4.064 - 3.810 0.559 1.524 0.381 23.495 20.320 8.255 7.112 2.591 7.620 9.906 3.556 18 - - Notes Min 0 - 0.015 0.120 0.014 0.060 0.008 0.885 0.800 0.300 0.240 0.098 0.300 0.310 0.120 18 0.035 0.005 Inches Max 10 0.160 - 0.150 0.022 0.060 0.015 0.925 0.800 0.325 0.280 0.102 0.300 0.390 0.140 18 - - Notes
Reference Typical Reference
Reference Typical Reference
Typical Reference
Typical Reference
DS30272A-page 156
(c) 1997 Microchip Technology Inc.
PIC16C71X
17.3 18-Lead Plastic Surface Mount (SOIC - Wide, 300 mil Body)(SO)
e B N Index Area E Chamfer h x 45 1 2 3 H L C h x 45
D
Seating Plane
CP
Base Plane
A1
A
Package Group: Plastic SOIC (SO) Millimeters Symbol A A1 B C D E e H h L N CP Min 0 2.362 0.101 0.355 0.241 11.353 7.416 1.270 10.007 0.381 0.406 18 - Max 8 2.642 0.300 0.483 0.318 11.735 7.595 1.270 10.643 0.762 1.143 18 0.102 Notes Min 0 0.093 0.004 0.014 0.009 0.447 0.292 0.050 0.394 0.015 0.016 18 - Inches Max 8 0.104 0.012 0.019 0.013 0.462 0.299 0.050 0.419 0.030 0.045 18 0.004 Notes
Reference
Reference
(c) 1997 Microchip Technology Inc.
DS30272A-page 157
PIC16C71X
17.4 20-Lead Plastic Surface Mount (SSOP - 209 mil Body 5.30 mm) (SS)
N Index area
E
H L C
123 e B
A CP
Base plane
Seating plane D A1
Package Group: Plastic SSOP Millimeters Symbol A A1 B C D E e H L N CP Min 0 1.730 0.050 0.250 0.130 7.070 5.200 0.650 7.650 0.550 20 Max 8 1.990 0.210 0.380 0.220 7.330 5.380 0.650 7.900 0.950 20 0.102 Notes Min 0 0.068 0.002 0.010 0.005 0.278 0.205 0.026 0.301 0.022 20 Inches Max 8 0.078 0.008 0.015 0.009 0.289 0.212 0.026 0.311 0.037 20 0.004 Notes
Reference
Reference
Note 1: Dimensions D1 and E1 do not include mold protrusion. Allowable mold protrusion is 0.25m/m (0.010") per side. D1 and E1 dimensions including mold mismatch. 2: Dimension "b" does not include Dambar protrusion, allowable Dambar protrusion shall be 0.08m/m (0.003")max. 3: This outline conforms to JEDEC MS-026.
DS30272A-page 158
(c) 1997 Microchip Technology Inc.
PIC16C71X
17.5 Package Marking Information Example PIC16C711-04/P 9452CBA Example PIC16C715 -20/50 9447CBA 18-Lead PDIP MMMMMMMMMMMMM XXXXXXXXXXXXXXXX AABBCDE 18-Lead SOIC MMMMMMMMMM XXXXXXXXXXXX XXXXXXXXXXXX AABBCDE
18-Lead CERDIP Windowed MMMMMM XXXXXXXX AABBCDE 20-Lead SSOP
XXXXXXXX XXXXXXXX
Example PIC16C71 /JW 945/CBT Example
PIC16C710 20I/SS025
AABBCAE
9517SBP
Legend:
MM...M XX...X AA BB C D1 E
Microchip part number information Customer specific information* Year code (last 2 digits of calender year) Week code (week of January 1 is week '01') Facility code of the plant at which wafer is manufactured. C = Chandler, Arizona, U.S.A. S = Tempe, Arizona, U.S.A. Mask revision number for microcontroller Assembly code of the plant or country of origin in which part was assembled.
Note:
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information.
* Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask revision number, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
(c) 1997 Microchip Technology Inc.
DS30272A-page 159
PIC16C71X
NOTES:
DS30272A-page 160
(c) 1997 Microchip Technology Inc.
PIC16C71X
APPENDIX A:
The following are the list of modifications over the PIC16C5X microcontroller family: 1. Instruction word length is increased to 14-bits. This allows larger page sizes both in program memory (1K now as opposed to 512 before) and register file (68 bytes now versus 32 bytes before). A PC high latch register (PCLATH) is added to handle program memory paging. Bits PA2, PA1, PA0 are removed from STATUS register. Data memory paging is redefined slightly. STATUS register is modified. Four new instructions have been added: RETURN, RETFIE, ADDLW, and SUBLW. Two instructions TRIS and OPTION are being phased out although they are kept for compatibility with PIC16C5X. OPTION and TRIS registers are made addressable. Interrupt capability is added. Interrupt vector is at 0004h. Stack size is increased to 8 deep. Reset vector is changed to 0000h. Reset of all registers is revisited. Five different reset (and wake-up) types are recognized. Registers are reset differently. Wake up from SLEEP through interrupt is added. Two separate timers, Oscillator Start-up Timer (OST) and Power-up Timer (PWRT) are included for more reliable power-up. These timers are invoked selectively to avoid unnecessary delays on power-up and wake-up. PORTB has weak pull-ups and interrupt on change feature. T0CKI pin is also a port pin (RA4) now. FSR is made a full eight bit register. "In-circuit serial programming" is made possible. The user can program PIC16CXX devices using only five pins: VDD, VSS, MCLR/VPP, RB6 (clock) and RB7 (data in/out). PCON status register is added with a Power-on Reset status bit (POR). Code protection scheme is enhanced such that portions of the program memory can be protected, while the remainder is unprotected. Brown-out protection circuitry has been added. Controlled by configuration word bit BODEN. Brown-out reset ensures the device is placed in a reset condition if VDD dips below a fixed setpoint.
APPENDIX B: COMPATIBILITY
To convert code written for PIC16C5X to PIC16CXX, the user should take the following steps: 1. 2. Remove any program memory page select operations (PA2, PA1, PA0 bits) for CALL, GOTO. Revisit any computed jump operations (write to PC or add to PC, etc.) to make sure page bits are set properly under the new scheme. Eliminate any data memory page switching. Redefine data variables to reallocate them. Verify all writes to STATUS, OPTION, and FSR registers since these have changed. Change reset vector to 0000h.
2.
3. 4. 5.
3. 4.
5. 6. 7. 8. 9.
10. 11.
12. 13. 14. 15.
16. 17.
18.
(c) 1997 Microchip Technology Inc.
DS30272A-page 161
PIC16C71X
APPENDIX C: WHAT'S NEW
1. Consolidated all pin compatible 18-pin A/D based devices into one data sheet.
APPENDIX D: WHAT'S CHANGED
1. 2. 3. Minor changes, spelling and grammatical changes. Low voltage operation on the PIC16LC710/711/ 715 has been reduced from 3.0V to 2.5V. Part numbers of the PIC16C70 and PIC16C71A have changed to PIC16C710 and PIC16C711, respectively.
DS30272A-page 162
(c) 1997 Microchip Technology Inc.
PIC16C71X
INDEX
A
A/D Accuracy/Error ........................................................... 44 ADIF bit ...................................................................... 39 Analog Input Model Block Diagram ............................ 40 Analog-to-Digital Converter ........................................ 37 Configuring Analog Port Pins ..................................... 41 Configuring the Interrupt ............................................ 39 Configuring the Module .............................................. 39 Connection Considerations ........................................ 44 Conversion Clock ....................................................... 41 Conversion Time ........................................................ 43 Conversions ............................................................... 42 Converter Characteristics .......................... 99, 122, 145 Delays ........................................................................ 40 Effects of a Reset ....................................................... 44 Equations ................................................................... 40 Faster Conversion - Lower Resolution Trade-off ....... 43 Flowchart of A/D Operation ........................................ 45 GO/DONE bit ............................................................. 39 Internal Sampling Switch (Rss) Impedence ............... 40 Minimum Charging Time ............................................ 40 Operation During Sleep ............................................. 44 Sampling Requirements ............................................. 40 Source Impedence ..................................................... 40 Time Delays ............................................................... 40 Transfer Function ....................................................... 45 Absolute Maximum Ratings ............................... 89, 111, 135 AC Characteristics PIC16C710 .............................................................. 101 PIC16C711 .............................................................. 101 PIC16C715 .............................................................. 125 ADCON0 Register .............................................................. 37 ADCON1 ............................................................................ 37 ADCON1 Register ........................................................ 14, 37 ADCS0 bit .......................................................................... 37 ADCS1 bit .......................................................................... 37 ADIE bit ........................................................................ 19, 20 ADIF bit ........................................................................ 21, 37 ADON bit ............................................................................ 37 ADRES Register .................................................... 15, 37, 39 ALU ...................................................................................... 7 Application Notes AN546 ........................................................................ 37 AN552 ........................................................................ 27 AN556 ........................................................................ 23 AN607, Power-up Trouble Shooting .......................... 53 Architecture Harvard ........................................................................ 7 Overview ...................................................................... 7 von Neumann ............................................................... 7 Assembler MPASM Assembler .................................................... 86 RB7:RB4 Port Pins .....................................................28 Timer0 ........................................................................31 Timer0/WDT Prescaler ...............................................34 Watchdog Timer .........................................................65 BODEN bit ..........................................................................48 BOR bit ........................................................................ 22, 54 Brown-out Reset (BOR) ......................................................53
C
C bit ....................................................................................17 C16C71 ..............................................................................47 Carry bit ................................................................................7 CHS0 bit .............................................................................37 CHS1 bit .............................................................................37 Clocking Scheme ................................................................10 Code Examples Call of a Subroutine in Page 1 from Page 0 ...............24 Changing Prescaler (Timer0 to WDT) ........................35 Changing Prescaler (WDT to Timer0) ........................35 Doing an A/D Conversion ...........................................42 I/O Programming ........................................................30 Indirect Addressing .....................................................24 Initializing PORTA ......................................................25 Initializing PORTB ......................................................27 Saving STATUS and W Registers in RAM .................64 Code Protection ........................................................... 47, 67 Computed GOTO ...............................................................23 Configuration Bits ...............................................................47 CP0 bit ......................................................................... 47, 48 CP1 bit ................................................................................48
D
DC bit ..................................................................................17 DC Characteristics ........................................................... 147 PIC16C71 ................................................................ 136 PIC16C710 ........................................................ 90, 101 PIC16C711 ........................................................ 90, 101 PIC16C715 ...................................................... 113, 125 Development Support .................................................... 3, 85 Development Tools .............................................................85 Diagrams - See Block Diagrams Digit Carry bit ........................................................................7 Direct Addressing ...............................................................24
E
Electrical Characteristics PIC16C71 ................................................................ 135 PIC16C710 .................................................................89 PIC16C711 .................................................................89 PIC16C715 .............................................................. 111 External Brown-out Protection Circuit .................................60 External Power-on Reset Circuit ........................................60
F
Family of Devices PIC16C71X ...................................................................4 FOSC0 bit .................................................................... 47, 48 FOSC1 bit .................................................................... 47, 48 FSR Register ......................................................... 15, 16, 24 Fuzzy Logic Dev. System (fuzzyTECH(R)-MP) .....................87
B
Block Diagrams Analog Input Model .................................................... 40 On-Chip Reset Circuit ................................................ 52 PIC16C71X .................................................................. 8 RA3/RA0 Port Pins .................................................... 25 RA4/T0CKI Pin ........................................................... 25 RB3:RB0 Port Pins .................................................... 27 RB7:RB4 Pins ............................................................ 28
G
General Description ..............................................................3 GIE bit .......................................................................... 19, 61 GO/DONE bit ......................................................................37
(c) 1997 Microchip Technology Inc.
DS30390D-page 163
PIC16C71X
I
I/O Ports PORTA ....................................................................... 25 PORTB ....................................................................... 27 Section ....................................................................... 25 I/O Programming Considerations ....................................... 30 ICEPIC Low-Cost PIC16CXXX In-Circuit Emulator ........... 85 In-Circuit Serial Programming ...................................... 47, 67 INDF Register ........................................................ 14, 16, 24 Indirect Addressing ............................................................ 24 Instruction Cycle ................................................................. 10 Instruction Flow/Pipelining ................................................. 10 Instruction Format .............................................................. 69 Instruction Set ADDLW ...................................................................... 71 ADDWF ...................................................................... 71 ANDLW ...................................................................... 71 ANDWF ...................................................................... 71 BCF ............................................................................ 72 BSF ............................................................................ 72 BTFSC ....................................................................... 72 BTFSS ....................................................................... 73 CALL .......................................................................... 73 CLRF .......................................................................... 74 CLRW ........................................................................ 74 CLRWDT .................................................................... 74 COMF ........................................................................ 75 DECF ......................................................................... 75 DECFSZ ..................................................................... 75 GOTO ........................................................................ 76 INCF ........................................................................... 76 INCFSZ ...................................................................... 77 IORLW ....................................................................... 77 IORWF ....................................................................... 78 MOVF ......................................................................... 78 MOVLW ..................................................................... 78 MOVWF ..................................................................... 78 NOP ........................................................................... 79 OPTION ..................................................................... 79 RETFIE ...................................................................... 79 RETLW ...................................................................... 80 RETURN .................................................................... 80 RLF ............................................................................ 81 RRF ............................................................................ 81 SLEEP ....................................................................... 82 SUBLW ...................................................................... 82 SUBWF ...................................................................... 83 SWAPF ...................................................................... 83 TRIS ........................................................................... 83 XORLW ...................................................................... 84 XORWF ...................................................................... 84 Section ....................................................................... 69 Summary Table .......................................................... 70 INT Interrupt ....................................................................... 63 INTCON Register ............................................................... 19 INTE bit .............................................................................. 19 INTEDG bit ................................................................... 18, 63 Internal Sampling Switch (Rss) Impedence ....................... 40 Interrupts ............................................................................ 47 A/D ............................................................................. 61 External ...................................................................... 61 PORTB Change ......................................................... 61 PortB Change ............................................................ 63 RB7:RB4 Port Change ............................................... 27 Section ....................................................................... 61 TMR0 ......................................................................... 63 TMR0 Overflow .......................................................... 61 INTF bit .............................................................................. 19 IRP bit ................................................................................ 17
K
KeeLoq(R) Evaluation and Programming Tools ................... 87
L
Loading of PC .................................................................... 23 LP ...................................................................................... 54
M
MCLR ........................................................................... 52, 56 Memory Data Memory ............................................................. 12 Program Memory ....................................................... 11 Register File Maps PIC16C71 .......................................................... 12 PIC16C710 ........................................................ 12 PIC16C711 ........................................................ 13 PIC16C715 ........................................................ 13 MP-DriveWayTM - Application Code Generator .................. 87 MPEEN bit ................................................................... 22, 48 MPLABTM C ........................................................................ 87 MPLABTM Integrated Development Environment Software ............................................................................. 86
O
OPCODE ........................................................................... 69 OPTION Register ............................................................... 18 Orthogonal ........................................................................... 7 OSC selection .................................................................... 47 Oscillator HS ........................................................................ 49, 54 LP ........................................................................ 49, 54 RC ............................................................................. 49 XT ........................................................................ 49, 54 Oscillator Configurations .................................................... 49 Oscillator Start-up Timer (OST) ......................................... 53
P
Packaging 18-Lead CERDIP w/Window ................................... 155 18-Lead PDIP .......................................................... 156 18-Lead SOIC .......................................................... 157 20-Lead SSOP ........................................................ 158 Paging, Program Memory .................................................. 23 PCL Register ................................................... 14, 15, 16, 23 PCLATH ....................................................................... 57, 58 PCLATH Register ............................................ 14, 15, 16, 23 PCON Register ............................................................ 22, 54 PD bit ..................................................................... 17, 52, 55 PER bit ............................................................................... 22 PIC16C71 ........................................................................ 147 AC Characteristics ................................................... 147 PICDEM-1 Low-Cost PIC16/17 Demo Board .................... 86 PICDEM-2 Low-Cost PIC16CXX Demo Board .................. 86 PICDEM-3 Low-Cost PIC16CXXX Demo Board ............... 86 PICMASTER(R) In-Circuit Emulator ..................................... 85 PICSTART(R) Plus Entry Level Development System ......... 85 PIE1 Register ..................................................................... 20 Pin Functions MCLR/VPP ................................................................... 9 OSC1/CLKIN ............................................................... 9 OSC2/CLKOUT ........................................................... 9 RA0/AN0 ...................................................................... 9 RA1/AN1 ...................................................................... 9
DS30390D-page 164
(c) 1997 Microchip Technology Inc.
PIC16C71X
RA2/AN2 ...................................................................... 9 RA3/AN3/VREF ............................................................. 9 RA4/T0CKI ................................................................... 9 RB0/INT ....................................................................... 9 RB1 .............................................................................. 9 RB2 .............................................................................. 9 RB3 .............................................................................. 9 RB4 .............................................................................. 9 RB5 .............................................................................. 9 RB6 .............................................................................. 9 RB7 .............................................................................. 9 VDD .............................................................................. 9 VSS ............................................................................... 9 Pinout Descriptions PIC16C71 .................................................................... 9 PIC16C710 .................................................................. 9 PIC16C711 .................................................................. 9 PIC16C715 .................................................................. 9 PIR1 Register ..................................................................... 21 POP ................................................................................... 23 POR ............................................................................. 53, 54 Oscillator Start-up Timer (OST) ........................... 47, 53 Power Control Register (PCON) ................................ 54 Power-on Reset (POR) ............................ 47, 53, 57, 58 Power-up Timer (PWRT) ..................................... 47, 53 Time-out Sequence .................................................... 54 Time-out Sequence on Power-up .............................. 59 TO ........................................................................ 52, 55 POR bit ........................................................................ 22, 54 Port RB Interrupt ................................................................ 63 PORTA ......................................................................... 57, 58 PORTA Register .................................................... 14, 15, 25 PORTB ......................................................................... 57, 58 PORTB Register .................................................... 14, 15, 27 Power-down Mode (SLEEP) .............................................. 66 Prescaler, Switching Between Timer0 and WDT ............... 35 PRO MATE(R) II Universal Programmer .............................. 85 Program Branches ............................................................... 7 Program Memory Paging ........................................................................ 23 Program Memory Maps PIC16C71 .................................................................. 11 PIC16C710 ................................................................ 11 PIC16C711 ................................................................ 11 PIC16C715 ................................................................ 11 Program Verification .......................................................... 67 PS0 bit ............................................................................... 18 PS1 bit ............................................................................... 18 PS2 bit ............................................................................... 18 PSA bit ............................................................................... 18 PUSH ................................................................................. 23 PWRT Power-up Timer (PWRT) ........................................... 53 PWRTE bit ................................................................... 47, 48 PIC16C711 .........................................................13 PIC16C715 .........................................................13 Reset Conditions ........................................................56 Summary ............................................................. 14-?? Reset ........................................................................... 47, 52 Reset Conditions for Special Registers ..............................56 RP0 bit ......................................................................... 12, 17 RP1 bit ................................................................................17
S
SEEVAL(R) Evaluation and Programming System ...............87 Services One-Time-Programmable (OTP) Devices ....................5 Quick-Turnaround-Production (QTP) Devices ..............5 Serialized Quick-Turnaround Production (SQTP) Devices .........................................................................5 SLEEP ......................................................................... 47, 52 Software Simulator (MPLABTM SIM) ...................................87 Special Features of the CPU ..............................................47 Special Function Registers PIC16C71 ...................................................................14 PIC16C710 .................................................................14 PIC16C711 .................................................................14 Special Function Registers, Section ...................................14 Stack ...................................................................................23 Overflows ....................................................................23 Underflow ...................................................................23 STATUS Register ...............................................................17
T
T0CS bit ..............................................................................18 T0IE bit ...............................................................................19 T0IF bit ...............................................................................19 TAD .....................................................................................41 Timer0 RTCC ................................................................... 57, 58 Timers Timer0 Block Diagram ....................................................31 External Clock ....................................................33 External Clock Timing ........................................33 Increment Delay .................................................33 Interrupt ..............................................................31 Interrupt Timing ..................................................32 Prescaler ............................................................34 Prescaler Block Diagram ....................................34 Section ...............................................................31 Switching Prescaler Assignment ........................35 Synchronization ..................................................33 T0CKI .................................................................33 T0IF ....................................................................63 Timing .................................................................31 TMR0 Interrupt ...................................................63 Timing Diagrams A/D Conversion ....................................... 100, 124, 146 Brown-out Reset .................................................. 53, 97 CLKOUT and I/O ....................................... 96, 119, 142 External Clock Timing ................................ 95, 118, 141 Power-up Timer ................................................. 97, 143 Reset ................................................................. 97, 143 Start-up Timer .................................................... 97, 143 Time-out Sequence ....................................................59 Timer0 ................................................. 31, 98, 121, 144 Timer0 Interrupt Timing ..............................................32 Timer0 with External Clock .........................................33 Wake-up from SLEEP through Interrupt .....................67 Watchdog Timer ................................................ 97, 143
R
RBIE bit .............................................................................. 19 RBIF bit .................................................................. 19, 27, 63 RBPU bit ............................................................................ 18 RC ...................................................................................... 54 RC Oscillator ................................................................ 51, 54 Read-Modify-Write ............................................................. 30 Register File ....................................................................... 12 Registers Maps PIC16C71 .......................................................... 12 PIC16C710 ........................................................ 12
(c) 1997 Microchip Technology Inc.
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TO bit ................................................................................. 17 TOSE bit ............................................................................. 18 TRISA Register ...................................................... 14, 16, 25 TRISB Register ...................................................... 14, 16, 27 Two's Complement .............................................................. 7
LIST OF EXAMPLES
Example 3-1: Example 4-1: Example 4-2: Example 5-1: Example 5-2: Example 5-3: Example 6-1: Example 6-2: Equation 7-1: Example 7-1: Example 7-2: Example 7-3: Example 8-1: Instruction Pipeline Flow ........................... 10 Call of a Subroutine in Page 1 from Page 0 ...................................................... 24 Indirect Addressing ................................... 24 Initializing PORTA..................................... 25 Initializing PORTB..................................... 27 Read-Modify-Write Instructions on an I/O Port ........................................... 30 Changing Prescaler (Timer0WDT) ........ 35 Changing Prescaler (WDTTimer0) ........ 35 A/D Minimum Charging Time.................... 40 Calculating the Minimum Required Aquisition Time ......................................... 40 A/D Conversion......................................... 42 4-bit vs. 8-bit Conversion Times ............... 43 Saving STATUS and W Registers in RAM ...................................................... 64
U
Upward Compatibility ........................................................... 3 UV Erasable Devices ........................................................... 5
W
W Register ALU .............................................................................. 7 Wake-up from SLEEP ........................................................ 66 Watchdog Timer (WDT) ................................... 47, 52, 56, 65 WDT ................................................................................... 56 Block Diagram ............................................................ 65 Programming Considerations .................................... 65 Timeout ................................................................ 57, 58 WDT Period ........................................................................ 65 WDTE bit ...................................................................... 47, 48
LIST OF FIGURES
Figure 3-1: Figure 3-2: Figure 4-1: Figure 4-2: Figure 4-3: Figure 4-4: Figure 4-5: Figure 4-6: Figure 4-7: Figure 4-8: Figure 4-9: Figure 4-10: Figure 4-11: Figure 4-12: Figure 4-13: Figure 4-14: Figure 4-15: Figure 5-1: Figure 5-2: Figure 5-3: Figure 5-4: Figure 5-5: Figure 5-6: Figure 6-1: Figure 6-2: Figure 6-3: Figure 6-4: Figure 6-5: Figure 6-6: Figure 7-1: Figure 7-2: PIC16C71X Block Diagram ........................ 8 Clock/Instruction Cycle ............................. 10 PIC16C710 Program Memory Map and Stack .................................................. 11 PIC16C71/711 Program Memory Map and Stack .................................................. 11 PIC16C715 Program Memory Map and Stack .................................................. 11 PIC16C710/71 Register File Map ............. 12 PIC16C711 Register File Map .................. 13 PIC16C715 Register File Map .................. 13 Status Register (Address 03h, 83h).......... 17 OPTION Register (Address 81h, 181h) .... 18 INTCON Register (Address 0Bh, 8Bh) ..... 19 PIE1 Register (Address 8Ch) ................... 20 PIR1 Register (Address 0Ch) ................... 21 PCON Register (Address 8Eh), PIC16C710/711 ........................................ 22 PCON Register (Address 8Eh), PIC16C715 ............................................... 22 Loading of PC In Different Situations........ 23 Direct/Indirect Addressing......................... 24 Block Diagram of RA3:RA0 Pins .............. 25 Block Diagram of RA4/T0CKI Pin ............. 25 Block Diagram of RB3:RB0 Pins .............. 27 Block Diagram of RB7:RB4 Pins (PIC16C71) ............................................... 28 Block Diagram of RB7:RB4 Pins (PIC16C710/711/715) ............................... 28 Successive I/O Operation ......................... 30 Timer0 Block Diagram .............................. 31 Timer0 Timing: Internal Clock/ No Prescale .............................................. 31 Timer0 Timing: Internal Clock/ Prescale 1:2 .............................................. 32 Timer0 Interrupt Timing ............................ 32 Timer0 Timing with External Clock ........... 33 Block Diagram of the Timer0/ WDT Prescaler ......................................... 34 ADCON0 Register (Address 08h), PIC16C710/71/711 ................................... 37 ADCON0 Register (Address 1Fh), PIC16C715 ............................................... 38
Z
Z bit .................................................................................... 17 Zero bit ................................................................................. 7
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PIC16C71X
Figure 7-3: ADCON1 Register, PIC16C710/71/711 (Address 88h), PIC16C715 (Address 9Fh)........................ 38 A/D Block Diagram.................................... 39 Analog Input Model ................................... 40 A/D Transfer Function ............................... 45 Flowchart of A/D Operation....................... 45 Configuration Word for PIC16C71 ............ 47 Configuration Word, PIC16C710/711........ 48 Configuration Word, PIC16C715............... 48 Crystal/Ceramic Resonator Operation (HS, XT or LP OSC Configuration) ........... 49 External Clock Input Operation (HS, XT or LP OSC Configuration) ........... 49 External Parallel Resonant Crystal Oscillator Circuit ........................................ 51 External Series Resonant Crystal Oscillator Circuit ........................................ 51 RC Oscillator Mode ................................... 51 Simplified Block Diagram of On-chip Reset Circuit.............................................. 52 Brown-out Situations ................................. 53 Time-out Sequence on Power-up (MCLR not Tied to VDD): Case 1............... 59 Time-out Sequence on Power-up (MCLR Not Tied To VDD): Case 2............. 59 Time-out Sequence on Power-up (MCLR Tied to VDD) .................................. 59 External Power-on Reset Circuit (for Slow VDD Power-up)........................... 60 External Brown-out Protection Circuit 1 .... 60 External Brown-out Protection Circuit 2 .... 60 Interrupt Logic, PIC16C710, 71, 711......... 62 Interrupt Logic, PIC16C715....................... 62 INT Pin Interrupt Timing ............................ 63 Watchdog Timer Block Diagram ............... 65 Summary of Watchdog Timer Registers ... 65 Wake-up from Sleep Through Interrupt..... 67 Typical In-Circuit Serial Programming Connection ................................................ 67 General Format for Instructions ................ 69 Load Conditions ........................................ 94 External Clock Timing ............................... 95 CLKOUT and I/O Timing ........................... 96 Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing ....................................................... 97 Brown-out Reset Timing............................ 97 Timer0 External Clock Timings ................. 98 A/D Conversion Timing ........................... 100 Typical IPD vs. VDD (WDT Disabled, RC Mode) ..................... 101 Maximum IPD vs. VDD (WDT Disabled, RC Mode) ..................... 101 Typical IPD vs. VDD @ 25C (WDT Enabled, RC Mode) ...................... 102 Maximum IPD vs. VDD (WDT Enabled, RC Mode) ...................... 102 Typical RC Oscillator Frequency vs. VDD .................................................... 102 Typical RC Oscillator Frequency vs. VDD .................................................... 102 Typical RC Oscillator Frequency vs. VDD .................................................... 102 Typical IPD vs. VDD Brown-out Detect Enabled (RC Mode) ................................ 103 Figure 12-9: Figure 12-10: Maximum IPD vs. VDD Brown-out Detect Enabled (85C to -40C, RC Mode)........ 103 Typical IPD vs. Timer1 Enabled (32 kHz, RC0/RC1 = 33 pF/33 pF, RC Mode) ............................................... 103 Maximum IPD vs. Timer1 Enabled (32 kHz, RC0/RC1 = 33 pF/33 pF, 85C to -40C, RC Mode) ....................... 103 Typical IDD vs. Frequency (RC Mode @ 22 pF, 25C) ..................... 104 Maximum IDD vs. Frequency (RC Mode @ 22 pF, -40C to 85C) ....... 104 Typical IDD vs. Frequency (RC Mode @ 100 pF, 25C) ................... 105 Maximum IDD vs. Frequency (RC Mode @ 100 pF, -40C to 85C) ..... 105 Typical IDD vs. Frequency (RC Mode @ 300 pF, 25C) ................... 106 Maximum IDD vs. Frequency (RC Mode @ 300 pF, -40C to 85C) ..... 106 Typical IDD vs. Capacitance @ 500 kHz (RC Mode) ........................... 107 Transconductance(gm) of HS Oscillator vs. VDD.............................. 107 Transconductance(gm) of LP Oscillator vs. VDD .............................. 107 Transconductance(gm) of XT Oscillator vs. VDD .............................. 107 Typical XTAL Startup Time vs. VDD (LP Mode, 25C) ............................. 108 Typical XTAL Startup Time vs. VDD (HS Mode, 25C)............................. 108 Typical XTAL Startup Time vs. VDD (XT Mode, 25C) ............................. 108 Typical IDD vs. Frequency (LP Mode, 25C) ..................................... 109 Maximum IDD vs. Frequency (LP Mode, 85C to -40C)....................... 109 Typical IDD vs. Frequency (XT Mode, 25C)..................................... 109 Maximum IDD vs. Frequency (XT Mode, -40C to 85C) ...................... 109 Typical IDD vs. Frequency (HS Mode, 25C) .................................... 110 Maximum IDD vs. Frequency (HS Mode, -40C to 85C) ...................... 110 Load Conditions...................................... 117 External Clock Timing............................. 118 CLKOUT and I/O Timing......................... 119 Reset, Watchdog Timer, Oscillator Start-Up Timer, and Power-Up Timer Timing ..................................................... 120 Brown-out Reset Timing ......................... 120 Timer0 Clock Timings ............................. 121 A/D Conversion Timing........................... 124 Typical IPD vs. VDD (WDT Disabled, RC Mode) ..................... 125 Maximum IPD vs. VDD (WDT Disabled, RC Mode) ..................... 125 Typical IPD vs. VDD @ 25C (WDT Enabled, RC Mode)...................... 126 Maximum IPD vs. VDD (WDT Enabled, RC Mode)...................... 126 Typical RC Oscillator Frequency vs. VDD ......................................................... 126
Figure 7-4: Figure 7-5: Figure 7-6: Figure 7-7: Figure 8-1: Figure 8-2: Figure 8-3: Figure 8-4: Figure 8-5: Figure 8-6: Figure 8-7: Figure 8-8: Figure 8-9: Figure 8-10: Figure 8-11: Figure 8-12: Figure 8-13: Figure 8-14: Figure 8-15: Figure 8-16: Figure 8-17: Figure 8-18: Figure 8-19: Figure 8-20: Figure 8-21: Figure 8-22: Figure 8-23: Figure 9-1: Figure 11-1: Figure 11-2: Figure 11-3: Figure 11-4:
Figure 12-11:
Figure 12-12: Figure 12-13: Figure 12-14: Figure 12-15: Figure 12-16: Figure 12-17: Figure 12-18: Figure 12-19: Figure 12-20: Figure 12-21: Figure 12-22: Figure 12-23: Figure 12-24: Figure 12-25: Figure 12-26: Figure 12-27: Figure 12-28: Figure 12-29: Figure 12-30: Figure 13-1: Figure 13-2: Figure 13-3: Figure 13-4:
Figure 11-5: Figure 11-6: Figure 11-7: Figure 12-1: Figure 12-2: Figure 12-3: Figure 12-4: Figure 12-5: Figure 12-6: Figure 12-7: Figure 12-8:
Figure 13-5: Figure 13-6: Figure 13-7: Figure 14-1: Figure 14-2: Figure 14-3: Figure 14-4: Figure 14-5:
(c) 1997 Microchip Technology Inc.
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Figure 14-6: Figure 14-7: Figure 14-8: Figure 14-9: Typical RC Oscillator Frequency vs. VDD.......................................................... 126 Typical RC Oscillator Frequency vs. VDD.......................................................... 126 Typical IPD vs. VDD Brown-out Detect Enabled (RC Mode) ................................ 127 Maximum IPD vs. VDD Brown-out Detect Enabled (85C to -40C, RC Mode) ...................... 127 Typical IPD vs. Timer1 Enabled (32 kHz, RC0/RC1 = 33 pF/33 pF, RC Mode) ....... 127 Maximum IPD vs. Timer1 Enabled (32 kHz, RC0/RC1 = 33 pF/33 pF, 85C to -40C, RC Mode)........................ 127 Typical IDD vs. Frequency (RC Mode @ 22 pF, 25C)...................... 128 Maximum IDD vs. Frequency (RC Mode @ 22 pF, -40C to 85C)........ 128 Typical IDD vs. Frequency (RC Mode @ 100 pF, 25C).................... 129 Maximum IDD vs. Frequency (RC Mode @ 100 pF, -40C to 85C)...... 129 Typical IDD vs. Frequency (RC Mode @ 300 pF, 25C).................... 130 Maximum IDD vs. Frequency (RC Mode @ 300 pF, -40C to 85C)...... 130 Typical IDD vs. Capacitance @ 500 kHz (RC Mode)............................................... 131 Transconductance(gm) of HS Oscillator vs. VDD .............................. 131 Transconductance(gm) of LP Oscillator vs. VDD............................... 131 Transconductance(gm) of XT Oscillator vs. VDD .............................. 131 Typical XTAL Startup Time vs. VDD (LP Mode, 25C).............................. 132 Typical XTAL Startup Time vs. VDD (HS Mode, 25C) ............................. 132 Typical XTAL Startup Time vs. VDD (XT Mode, 25C).............................. 132 Typical IDD vs. Frequency (LP Mode, 25C) ..................................... 133 Maximum IDD vs. Frequency (LP Mode, 85C to -40C) ....................... 133 Typical IDD vs. Frequency (XT Mode, 25C) ..................................... 133 Maximum IDD vs. Frequency (XT Mode, -40C to 85C) ....................... 133 Typical IDD vs. Frequency (HS Mode, 25C)..................................... 134 Maximum IDD vs. Frequency (HS Mode, -40C to 85C)....................... 134 Load Conditions ...................................... 140 External Clock Timing ............................. 141 CLKOUT and I/O Timing ......................... 142 Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing ..................................................... 143 Timer0 External Clock Timings ............... 144 A/D Conversion Timing ........................... 146 Typical RC Oscillator Frequency vs. Temperature............................................ 147 Typical RC Oscillator Frequency vs. VDD.......................................................... 147 Typical RC Oscillator Frequency vs. VDD.......................................................... 147 Figure 16-4: Figure 16-5: Figure 16-6: Figure 16-7: Figure 16-8: Figure 16-9: Figure 16-10: Figure 16-11: Typical RC Oscillator Frequency vs. VDD ......................................................... 148 Typical Ipd vs. VDD Watchdog Timer Disabled 25C......................................... 148 Typical Ipd vs. VDD Watchdog Timer Enabled 25C.......................................... 148 Maximum Ipd vs. VDD Watchdog Disabled .................................................. 149 Maximum Ipd vs. VDD Watchdog Enabled................................................... 149 Vth (Input Threshold Voltage) of I/O Pins vs. VDD ...................................... 149 VIH, VIL of MCLR, T0CKI and OSC1 (in RC Mode) vs. VDD ............................. 150 VTH (Input Threshold Voltage) of OSC1 Input (in XT, HS, and LP Modes) vs. VDD ................................. 150 Typical IDD vs. Freq (Ext Clock, 25C).... 151 Maximum, IDD vs. Freq (Ext Clock, -40 to +85C) ......................................... 151 Maximum IDD vs. Freq with A/D Off (Ext Clock, -55 to +125C) .................... 152 WDT Timer Time-out Period vs. VDD...... 152 Transconductance (gm) of HS Oscillator vs. VDD.............................. 152 Transconductance (gm) of LP Oscillator vs. VDD .............................. 153 Transconductance (gm) of XT Oscillator vs. VDD .............................. 153 IOH vs. VOH, VDD = 3V .......................... 153 IOH vs. VOH, VDD = 5V .......................... 153 IOL vs. VOL, VDD = 3V ........................... 154 IOL vs. VOL, VDD = 5V ........................... 154
Figure 14-10: Figure 14-11:
Figure 14-12: Figure 14-13: Figure 14-14: Figure 14-15: Figure 14-16: Figure 14-17: Figure 14-18: Figure 14-19: Figure 14-20: Figure 14-21: Figure 14-22: Figure 14-23: Figure 14-24: Figure 14-25: Figure 14-26: Figure 14-27: Figure 14-28: Figure 14-29: Figure 14-30: Figure 15-1: Figure 15-2: Figure 15-3: Figure 15-4:
Figure 16-12: Figure 16-13: Figure 16-14: Figure 16-15: Figure 16-16: Figure 16-17: Figure 16-18: Figure 16-19: Figure 16-20: Figure 16-21: Figure 16-22:
Figure 15-5: Figure 15-6: Figure 16-1: Figure 16-2: Figure 16-3:
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LIST OF TABLES
Table 1-1: Table 3-1: Table 4-1: Table 4-2: Table 5-1: Table 5-2: Table 5-3: Table 5-4: Table 6-1: Table 7-1: Table 7-2: Table 7-3: Table 7-4: Table 8-1: Table 8-2: Table 8-3: Table 8-4: Table 8-5: Table 8-6: Table 8-7: Table 8-8: Table 8-9: Table 8-10: Table 8-11: Table 8-12: Table 8-13: Table 9-1: Table 9-2: Table 10-1: Table 11-1: PIC16C71X Family of Devices.................... 4 PIC16C710/71/711/715 Pinout Description .................................................. 9 PIC16C710/71/711 Special Function Register Summary .................................... 14 PIC16C715 Special Function Register Summary................................................... 15 PORTA Functions ..................................... 26 Summary of Registers Associated with PORTA...................................................... 26 PORTB Functions ..................................... 28 Summary of Registers Associated with PORTB...................................................... 29 Registers Associated with Timer0............. 35 TAD vs. Device Operating Frequencies, PIC16C71.................................................. 41 TAD vs. Device Operating Frequencies, PIC16C710/711, PIC16C715 .................... 41 Registers/Bits Associated with A/D, PIC16C710/71/711.................................... 46 Registers/Bits Associated with A/D, PIC16C715................................................ 46 Ceramic Resonators, PIC16C71............... 49 Capacitor Selection For Crystal Oscillator, PIC16C71................................. 49 Ceramic Resonators, PIC16C710/711/715.................................. 50 Capacitor Selection for Crystal Oscillator, PIC16C710/711/715................. 50 Time-out in Various Situations, PIC16C71.................................................. 54 Time-out in Various Situations, PIC16C710/711/715.................................. 54 Status Bits and Their Significance, PIC16C71.................................................. 55 Status Bits and Their Significance, PIC16C710/711......................................... 55 Status Bits and Their Significance, PIC16C715................................................ 55 Reset Condition for Special Registers, PIC16C710/71/711.................................... 56 Reset Condition for Special Registers, PIC16C715................................................ 56 Initialization Conditions For All Registers, PIC16C710/71/711.................................... 57 Initialization Conditions for All Registers, PIC16C715................................................ 58 Opcode Field Descriptions ........................ 69 PIC16CXX Instruction Set......................... 70 Development Tools From Microchip ......... 88 Cross Reference of Device Specs for Oscillator Configurations and Frequencies of Operation (Commercial Devices)............................... 89 External Clock Timing Requirements........ 95 CLKOUT and I/O Timing Requirements.... 96 Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer, and Brown-out Reset Requirements ......... 97 Timer0 External Clock Requirements ....... 98 Table 11-6: A/D Converter Characteristics: PIC16C710/711-04 (Commercial, Industrial, Extended) PIC16C710/711-10 (Commercial, Industrial, Extended) PIC16C710/711-20 (Commercial, Industrial, Extended) PIC16LC710/711-04 (Commercial, Industrial, Extended) ...........99 A/D Conversion Requirements ............... 100 RC Oscillator Frequencies...................... 107 Capacitor Selection for Crystal Oscillators ............................................... 108 Cross Reference of Device Specs for Oscillator Configurations and Frequencies of Operation (Commercial Devices) ............................ 112 Clock Timing Requirements.................... 118 CLKOUT and I/O Timing Requirements . 119 Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer, and Brown-out Reset Requirements....... 120 Timer0 Clock Requirements ................... 121 A/D Converter Characteristics: PIC16C715-04 (Commercial, Industrial, Extended) PIC16C715-10 (Commercial, Industrial, Extended) PIC16C715-20 (Commercial, Industrial, Extended) ........ 122 A/D Converter Characteristics: PIC16LC715-04 (Commercial, Industrial) ................................................ 123 A/D Conversion Requirements ............... 124 RC Oscillator Frequencies...................... 131 Capacitor Selection for Crystal Oscillators ............................................... 132 Cross Reference of Device Specs for Oscillator Configurations and Frequencies of Operation (Commercial Devices) ............................ 135 External Clock Timing Requirements ..... 141 CLKOUT and I/O Timing Requirements . 142 Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Requirements ......................................... 143 Timer0 External Clock Requirements ..... 144 A/D Converter Characteristics ................ 145 A/D Conversion Requirements ............... 146 RC Oscillator Frequencies...................... 148
Table 11-7: Table 12-1: Table 12-2: Table 13-1:
Table 13-2: Table 13-3: Table 13-4:
Table 13-5: Table 13-6:
Table 13-7:
Table 13-8: Table 14-1: Table 14-2: Table 15-1:
Table 15-2: Table 15-3: Table 15-4:
Table 15-5: Table 15-6: Table 15-7: Table 16-1:
Table 11-2: Table 11-3: Table 11-4:
Table 11-5:
(c) 1997 Microchip Technology Inc.
DS30390D-page 169
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NOTES:
DS30390D-page 170
(c) 1997 Microchip Technology Inc.
PIC16C71X
ON-LINE SUPPORT
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PIC16C71X
READER RESPONSE
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From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Device: PIC16C71X Questions: 1. What are the best features of this document? Y N Literature Number: DS30272A FAX: (______) _________ - _________
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DS30272A-page 172
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PIC16C71X
PIC16C71X PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery refer to the factory or the listed sales office. PART NO. -XX X /XX XXX Pattern: Package: Examples QTP, SQTP, Code or Special Requirements a) JW = Windowed CERDIP SO = SOIC SP = Skinny plastic dip P = PDIP SS = SSOP b) = 0C to +70C I = -40C to +85C E = -40C to +125C 04 = 200 kHz (PIC16C7X-04) 04 = 4 MHz 10 = 10 MHz 20 = 20 MHz PIC16C7X :VDD range 4.0V to 6.0V PIC16C7XT :VDD range 4.0V to 6.0V (Tape/Reel) PIC16LC7X :VDD range 2.5V to 6.0V PIC16LC7XT :VDD range 2.5V to 6.0V (Tape/Reel)
PIC16C71 - 04/P 301 Commercial Temp., PDIP Package, 4 MHz, normal VDD limits, QTP pattern #301
Temperature Range: Frequency Range: Device
* JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of each oscillator type (including LC devices).
Sales and Support
Products supported by a preliminary Data Sheet may possibly have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office (see below) 2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277 3. The Microchip's Bulletin Board, via your local CompuServe number (CompuServe membership NOT required). Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. For latest version information and upgrade kits for Microchip Development Tools, please call 1-800-755-2345 or 1-602-786-7302.
(c) 1997 Microchip Technology Inc.
DS30272A-page 173
PIC16C71X
NOTES:
DS30272A-page 174
(c) 1997 Microchip Technology Inc.
PIC16C71X
NOTES:
(c) 1997 Microchip Technology Inc.
DS30272A-page 175
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office
Microchip Technology Inc. 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-786-7200 Fax: 480-786-7277 Technical Support: 480-786-7627 Web Address: http://www.microchip.com
AMERICAS (continued)
Toronto
Microchip Technology Inc. 5925 Airport Road, Suite 200 Mississauga, Ontario L4V 1W1, Canada Tel: 905-405-6279 Fax: 905-405-6253
ASIA/PACIFIC (continued)
Singapore
Microchip Technology Singapore Pte Ltd. 200 Middle Road #07-02 Prime Centre Singapore 188980 Tel: 65-334-8870 Fax: 65-334-8850
ASIA/PACIFIC
Hong Kong
Microchip Asia Pacific Unit 2101, Tower 2 Metroplaza 223 Hing Fong Road Kwai Fong, N.T., Hong Kong Tel: 852-2-401-1200 Fax: 852-2-401-3431
Taiwan, R.O.C
Microchip Technology Taiwan 10F-1C 207 Tung Hua North Road Taipei, Taiwan, ROC Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
Atlanta
Microchip Technology Inc. 500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 Tel: 770-640-0034 Fax: 770-640-0307
Boston
Microchip Technology Inc. 5 Mount Royal Avenue Marlborough, MA 01752 Tel: 508-480-9990 Fax: 508-480-8575
EUROPE
United Kingdom
Arizona Microchip Technology Ltd. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44 118 921 5858 Fax: 44-118 921-5835
Beijing
Microchip Technology, Beijing Unit 915, 6 Chaoyangmen Bei Dajie Dong Erhuan Road, Dongcheng District New China Hong Kong Manhattan Building Beijing 100027 PRC Tel: 86-10-85282100 Fax: 86-10-85282104
Chicago
Microchip Technology Inc. 333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 630-285-0071 Fax: 630-285-0075
India
Microchip Technology Inc. India Liaison Office No. 6, Legacy, Convent Road Bangalore 560 025, India Tel: 91-80-229-0061 Fax: 91-80-229-0062
Denmark
Microchip Technology Denmark ApS Regus Business Centre Lautrup hoj 1-3 Ballerup DK-2750 Denmark Tel: 45 4420 9895 Fax: 45 4420 9910
Dallas
Microchip Technology Inc. 4570 Westgrove Drive, Suite 160 Addison, TX 75248 Tel: 972-818-7423 Fax: 972-818-2924
Japan
Microchip Technology Intl. Inc. Benex S-1 6F 3-18-20, Shinyokohama Kohoku-Ku, Yokohama-shi Kanagawa 222-0033 Japan Tel: 81-45-471- 6166 Fax: 81-45-471-6122
France
Arizona Microchip Technology SARL Parc d'Activite du Moulin de Massy 43 Rue du Saule Trapu Batiment A - ler Etage 91300 Massy, France Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Dayton
Microchip Technology Inc. Two Prestige Place, Suite 150 Miamisburg, OH 45342 Tel: 937-291-1654 Fax: 937-291-9175
Detroit
Microchip Technology Inc. Tri-Atria Office Building 32255 Northwestern Highway, Suite 190 Farmington Hills, MI 48334 Tel: 248-538-2250 Fax: 248-538-2260
Korea
Microchip Technology Korea 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea Tel: 82-2-554-7200 Fax: 82-2-558-5934
Germany
Arizona Microchip Technology GmbH Gustav-Heinemann-Ring 125 D-81739 Munchen, Germany Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
Los Angeles
Microchip Technology Inc. 18201 Von Karman, Suite 1090 Irvine, CA 92612 Tel: 949-263-1888 Fax: 949-263-1338
Italy
Arizona Microchip Technology SRL Centro Direzionale Colleoni Palazzo Taurus 1 V. Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-039-65791-1 Fax: 39-039-6899883
11/15/99
Shanghai
Microchip Technology RM 406 Shanghai Golden Bridge Bldg. 2077 Yan'an Road West, Hong Qiao District Shanghai, PRC 200335 Tel: 86-21-6275-5700 Fax: 86 21-6275-5060
New York
Microchip Technology Inc. 150 Motor Parkway, Suite 202 Hauppauge, NY 11788 Tel: 631-273-5305 Fax: 631-273-5335
San Jose
Microchip Technology Inc. 2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408-436-7950 Fax: 408-436-7955
Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999. The Company's quality system processes and procedures are QS-9000 compliant for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs and microperipheral products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified.
All rights reserved. (c) 1999 Microchip Technology Incorporated. Printed in the USA. 11/99
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
1999 Microchip Technology Inc.

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