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DATA SHEET
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SEN6A39 80-COLUMN driver for dot-matrix STN LCD
To improve design and/or performance, Avant Electronics may make changes to its products. Please contact Avant Electronics for the latest versions of its products
data sheet (v3)
2005 Oct 20
Avant Electronics
SEN6A39 80-COLUMN driver for dot-matrix STN
1 1.1
GENERAL Description
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The SEN6A39 is an 80-COLUMN (SEGMENT) driver for dot-matrix STN LCD. It is desinged to be paired with the SEN6A40 68-ROW (COMMON) driver. 1.2 Features
* 80-output COLUMN driver for dot-matrix STN LCD module. * Display duty : up to 1/240. * Data transfer with a controller: 1, 2, 4-bits, bi-directional. * Data transfer clock: 6.0 MHz, when VDD= 5 volts. * Can be cascaded to expand column number. * External LCD bias voltage. * Operating voltage range (control logic): 2.7 ~ 5.5 volts. * Operating voltage range (LCD bias, VDD-V5): 8 ~ 30 volts. * Operating temperature range: -20 to +75 C. * Storage temperature range: -55 to +125 C. 1.3 Ordering information Ordering information DESCRIPTION LQFP100 Green package. QFP100 Green package. LQFP100 package. QFP100 package.
Table 1
TYPE NUMBER SEN6A39-LQFPG SEN6A39-QFPG SEN6A39-LQFP SEN6A39-QFP
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data sheet (v3)
Avant Electronics
SEN6A39 80-COLUMN driver for dot-matrix STN
2 2.1
FUNCTIONAL BLOCK DIAGRAM AND DESCRIPTION Funtional block diagram
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O1 O2 O3 V2 V3 V5
O79 O80
4-level LCD Driver Circuit (80 bits)
VDD VSS
High voltage area
80
Level shifter (80 bits) FR
80 2nd Latch (80 bits) 80 1st latch ( shift register, 80 bits )
LP 4 DI4 DI3 DI2 DI1 DF1 DF2 DIR SCP 4 bits Data Bus Interface
20
Address Decoder
5
Address Counter (5 bits)
Shift direction Control
Chip Disable & Latch Control
EIO1 EIO2 DUAL
Fig.1 Functional Block Diagram
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data sheet (v3)
Avant Electronics
SEN6A39 80-COLUMN driver for dot-matrix STN
3 3.1
PINNING INFORMATION Pinning diagram
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O53 O54 O55 O56 O57 O58 O59 O60 O61 O62 O63 O64 O65 O66 O67 O68 O69 O70 O71 O72 O73 O74 O75 O76 O77
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 76 49 77 48 78 47 79 46 80 45 81 44 82 43 83 42 84 41 85 40 86 39 87 38 88 37 89 36 90 35 91 34 92 33 93 32 94 31 95 30 96 29 97 28 98 27 99 26 100
O52 O51 O50 O49 O48 O47 O46 O45 O44 O43 O42 O41 O40 O39 O38 O37 O36 O35 O34 O33 O32 O31 O30 O29 O28
SEN6A39
O27 O26 O25 O24 O23 O22 O21 O20 O19 O18 O17 O16 O15 O14 O13 O12 O11 O10 O9 O8 O7 O6 O5 O4 O3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
O78 O79 O80 EIO2 SCP FR LP DF1 DF2 VSS DUAL DIR VDD DI4 DI3 DI2 DI1 V2 V3 V5 EIO1 NC NC O1 O2
Fig.2 Pin diagram of LQFP100/QFP100 package
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data sheet (v3)
Avant Electronics
SEN6A39 80-COLUMN driver for dot-matrix STN
3.2
www..com Table 2 Pin signal description. To avoid a latch-up effect at power-on: VSS - 0.5 V < voltage at any pin at any time < VDD + 0.5 V .
Pin number 1~3, 24~100 SYMBOL O78~O80, O1~O77 I/O Column (segment) driver output. Output Please refer to Table 4 for output voltage level. ENABLE input/output for cascading application. The functionality of these two inputs are decided by DUAL and DIR, as shown in the following table. 4, 21 EIO1, EIO2 I/O DUAL L L H 5 6 7 SCP FR LP Input Input Input DIR L H EIO1 input output EIO2 output input output DESCRIPTION
Signal description
don't care input
Input data shift clock, for shifting bit data. Frame signal, indicating a display frame. This signal is used to generate alternating LCD bias voltage. Line pulse, used as latch clock for internal 80-bit shift register. Data Format selection. These two inputs are used to select bit number of data transfer between a controller (such as the SAP1024B, for example) and the SEN6A39. The data transfer can be 1-bit, 2-bit, or 4-bit, as shown in the following table.
8, 9
DF1, DF2
Input
DF1 L H
DF2 L L
BITS 1-bit 2-bit 4-bit
don't care H 10 11 12 13 14~17 18,19, 20 22, 23 VSS DUAL DIR VDD DI4 ~ DI1 V2, V3, V5 NC Input Input Input input Input Input Ground terminal.
Selection of dual-input mode or single-input mode. Selecting shift direction of input data. Positive power supply for control logic. 4-bit parallel data bus for display data. External LCD bias voltage. No Connection. Leave these two pins unconnected in application.
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data sheet (v3)
Avant Electronics
SEN6A39 80-COLUMN driver for dot-matrix STN
4 4.1
PAD DIAGRAM AND COORDINATES Pad diagram O51 O50 O49 O48 O47 O46 O45 O44 O43 O42 O41 O40 O39 O38 O37 O36 O35 O34 O33 O32 O31
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O30
O52 O53 O54 O55 O56 O57 O58 O59 O50 O61 O62 O63 O64 O65 O66 O67 O68 O69 O70 O71 O72 O73 O74 O75 O76 O77 O78 O79 O80 SCP VSS FR LP EIO2 DIR VDD DF1 DF2 DI4 DI3 DI2 DUAL DI1 First pad EIO1 V2 V3 V5
O29 O28 O27 O26 O25 O24 O23 O22 O21 O20 O19 O18 O17 O16 O15 O14 O13 O12 O11 O10 O9 O8 O7 O6 O5 O4 O3 O2 O1
Note: 1. For chip_on_board (COB) bonding, chip carrier should be connected to VDD or left open. Chip carrier is the metal pad to which die is attached. 2. The chip size is : (X-axis, Y-axis)= 2786 m x 3184 m. 3. The Chip ID is: 3006. Fig.3 Pad locations.
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data sheet (v3)
Avant Electronics
SEN6A39 80-COLUMN driver for dot-matrix STN
4.2
Pad description
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Table 3 Pad signal names and coordinates The unit for coordinates is m. PAD NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 PAD NAME O80 O79 O78 O77 O76 O75 O74 O73 O72 O71 O70 O69 O68 O67 O66 O65 O64 O63 O62 O61 O60 O59 O58 O57 O56 O55 O54 O53 O52 O51 O50 O49 O48 O47 COORDINATES X 98.70 98.70 98.70 98.70 98.70 98.70 98.70 98.70 98.70 98.70 98.70 98.70 98.70 98.70 98.70 98.70 98.70 98.70 98.70 98.70 98.70 98.70 98.70 98.70 98.70 98.70 98.70 98.70 98.70 Y 108.60 213.60 318.60 423.60 528.60 633.60 738.60 843.60 948.60 1053.60 1158.60 1263.60 1368.60 1473.60 1578.60 1683.60 1788.60 1893.60 1998.60 2103.60 2208.60 2313.60 2418.60 2523.60 2628.60 2733.60 2838.60 2943.60 3048.60 PAD NO. 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 PAD NAME O46 O45 O44 O43 O42 O41 O40 O39 O38 O37 O36 O35 O34 O33 O32 O31 O30 O29 O28 O27 O26 O25 O24 O23 O22 O21 O20 O19 O18 O17 O16 O15 O14 O13 COORDINATES X 800.10 905.10 1010.10 1115.10 1220.10 1325.10 1430.10 1535.10 1640.10 1745.10 1850.10 1955.10 2060.10 2165.10 2270.10 2375.10 2480.10 2657.5 2657.5 2657.5 2657.5 2657.5 2657.5 2657.5 2657.5 2657.5 2657.5 2657.5 2657.5 2657.5 2657.5 2657.5 2657.5 2657.5 Y 3055.90 3055.90 3055.90 3055.90 3055.90 3055.90 3055.90 3055.90 3055.90 3055.90 3055.90 3055.90 3055.90 3055.90 3055.90 3055.90 3055.90 3048.60 2943.60 2838.60 2733.60 2628.60 2523.60 2418.60 2313.60 2208.60 2103.60 1998.60 1893.60 1788.60 1683.60 1578.60 1473.60 1368.60 PAD NO. 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 PAD NAME O12 O11 O10 O9 O8 O7 O6 O5 O4 O3 O2 O1 EIO1 V5 V3 V2 DI1 DI2 DI3 DI4 VDD DIR DUAL VSS DF2 DF1 LP FR SCP EIO2 COORDINATES X 2657.5 2657.5 2657.5 2657.5 2657.5 2657.5 2657.5 2657.5 2657.5 2657.5 2657.5 2657.5 2436.0 2293.0 2183.6 2071.0 1827.3 1721.0 1614.7 1058.4 1402.0 1295.8 1182.5 1071.5 965.2 858.80 752.6 646.3 540.0 433.7 Y 1263.60 1158.60 1053.60 948.60 843.60 738.60 633.60 528.60 423.60 318.6 213.60 107.50 117.10 117.10 117.10 117.10 117.10 117.10 117.10 117.10 117.10 117.10 117.10 117.10 117.10 117.10 117.10 117.10 117.10 117.10
275.10 3055.90 380.10 3055.90 485.10 3055.90 590.10 3055.90 695.10 3055.90
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data sheet (v3)
Avant Electronics
SEN6A39 80-COLUMN driver for dot-matrix STN
5 5.1
FUNCTIONAL DESCRIPTION Segment output drive (O1~O80)
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The voltage level of the outputs O1~O80 is determined by Input data (display data) and FR (frame signal), as given in the following table. Table 4 output voltage level of O1~O80 FR L L H H 5.2 Data L H L H SEN6A39 O1~O80 outputs V2 VDD V3 V5 SEN6A40 O1~O68 outputs V1 V5 V4 VDD
Display Data Inputs (DI1~DI4)
The SEN6A39 has a 4-bit parallel data bus (DI1~DI4) to interface with a controller. A logic HIGH bit represents an ON cell (black pixel on the LCD screen). Table 5 Data bits LCD drive output Selected level (VDD, V5) Unselected level (V2, V3) LCD display ON OFF
Display data H L
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data sheet (v3)
5.3
Data input format Avant Electronics Data input DI1 IN IN IN IN 2-bits IN IN IN 4-bits IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN
O1,O3,...O37,O39 O77,O73,...O5,O1 O1,O5,...O73,O77 O77,O73,...O45,O41 O2,O4,...O38,O40 O78,O74,...O6,O2 O2,O6,...O74,O78 O78,O74,...O46,O42
2005 Oct 20 9 of 20 data sheet (v3)
Data input format is given in the following table. DF1 L L L L H H H H * * * * Note: 1. When DF1=DF2=DUAL=DIR="L", 1-bit data transfer between the SEN6A39 and controller is selected, DI4 is used as input, and the first bit sent by the controller goes to O1; the last bit goes to O80. 2. When DF1=DF2=DUAL="L" and DIR="H", 1-bit data transfer between the SEN6A39 and controller is selected, DI1 is used as input, and the first bit sent by the controller goes to O80; the last bit goes to O1. DF2 L L L L L L L L H H H H DUAL L L H H L L H H L L H H DIR L H L H L H L H L H L H 1-bit bits Data format DI4 IN
O1,O2,...O79,O80 O80,O79...O42,O41 O1,O2,...O39,O40 O79,O77,...O3,O1 O1,O3,...O77,O79 O2,O4,...O78,O80 O79,O77,...O43,O41 O79,O77,...O43,O41 O79,O75,...O7,O3 O3,O7,...O75,O79 O79,O75...O47,O43 O80,O78,...O44,O42 O80,O78,...O44,O42 O80,O76,...O8,O4 O4,O8,...O76,O80 O80,O76...O48,O44 O80,O79,...O42,O41 O80,O78,...O4,O2
DI2
DI3
DI1
DI2
DI3
DI4
O80,O79,...O2,O1
IN IN
don't use
80-COLUMN driver for dot-matrix STN
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SEN6A39
Avant Electronics
SEN6A39 80-COLUMN driver for dot-matrix STN
6
ABSOLUTE MAXIMUM RATING Absolute maximum rating
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Table 6
VDD = 5 V 10%; VSS = 0 V; all voltages with respect to VSS unless otherwise specified; Tamb = 252C. SYMBOL VDD VDD-V5 Vi(max) Tamb Tstg Note: 1. The condition VDD V2 > V3 > V5 must always be met. PARAMETER Voltage on the VDD input LCD bias voltage, note 1 Maximum input voltage to input pins Operating ambient temperature range Storage temperature range 0 -0.3 -20 -55 MIN. -0.3 30 VDD + 0.3 + 75 +125 MAX. +7.0 V V V C C UNIT
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data sheet (v3)
Avant Electronics
SEN6A39 80-COLUMN driver for dot-matrix STN
7
DC CHARACTERISTICS DC Characteristics
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Table 7
VDD = 5 V 10%; VSS = 0 V; all voltages with respect to VSS unless otherwise specified; Tamb = 252 C. SYMBOL VDD VDD-V5 VIL PARAMETER Supply voltage for control logic LCD bias voltage Input LOW voltage of input pins CONDITIONS Please refer to Fig. 8 for DC power-up sequence. Note 1. DI1~DI4, SCP, DIR, EIO1, EIO2, LP, FR, DUAL, DF1, DF2 DI1~DI4, SCP, DIR, EIO1, EIO2, LP, FR, DUAL, DF1, DF2 VIN=VSS, DI1~DI4, SCP, DIR, EIO1, EIO2, LP, FR, DUAL, DF1, DF2 VIN=VDD, DI1~DI4, SCP, DIR, EIO1, EIO2, LP, FR, DUAL, DF1, DF2 IOL=400A IOH=-400A Note 2. Note 3. Note 4. The SCP clock frequency is 6.0 MHz. Note 5. Note 5. 5.0 1.5 2.0 3.0 3.5 0.0 VDD - 0.4 1 A 1 A MIN. 2.7 12 0 TYP. 5.0 MAX. 5.5 30 0.2VDD V UNIT V
VIH
Inout HIGH voltage of input pins Input LOW leakage current of input pins (i. e. Reverse leakage current of input ESD protection diode) Input HIGH leakage current of input pins (i. e. Reverse leakage current of input protection diode) Output LOW voltage level of the EIO1 and EIO2 pins Output HIGH voltage level of the EIO1 and EIO2 pins Standby current Operating current Operating current Input capacitance of the SCP pin Driver ON resistance at VLCD= 30 V Driver ON resistance at VLCD= 20 V
0.8VDD
VDD
V
IIL
IIH
VOL VOH ISTBY ISS IEE Ci RON1 RON2 Notes:
0.4 VDD 200 4.0 0.5
V V A mA mA pF
1. The condition VDD V2 > V3 > V5 must always be met. 2. EIO1=EIO2=VDD, VDD-V5=30 V, SCP=6.0MHz, Output unloaded; measured at the VSS pin. 3. Condition for the measurement: VLCD=VDD-V5=30 V, SCP=6.0 MHz, LP=14 KHz, FR=35 Hz. This is the current flowing from VDD to VSS, measured at the VSS pin. 4. Condition for the measurement: VLCD=VDD-V5=30 V, SCP=6.0 MHz, LP=14 KHz, FR=35 Hz. This is the current flowing from VDD to V5, measured at the V5 pin. 5. Condition for the measurment: VDD-V5=30 V, |VDE-VO|=0.5 V, where VDE= one of VDD, V2, V3, or V5. V2=VDD - (2/9) x (VDD-V5), V3=VDD - (7/9) x (VDD-V5). For the driver circuits (O1~O80), please refer to Section 11 Pin Circuits.
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data sheet (v3)
Avant Electronics
SEN6A39 80-COLUMN driver for dot-matrix STN
8
AC CHARACTERISTICS
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tLW tSL
LP
tLRP tLFP
tLS
tR SCP
0.2VDD
tWCH
0.8VDD
tF
0.2VDD
tWCL
0.2VDD
tDSU DI1~DI4
0.8VDD 0.2VDD
tDHD
tEOD
EIO OUT
tEOH
0.8VDD 0.2VDD
SCP
0.2VDD
tEIFP tSE
EIO IN
0.2VDD
tEIRP tEIW
tES
Fig.4 AC characteristics Table 8 AC Characteristics
VDD = 5 V 10%; VSS = 0 V; all voltages with respect to VSS unless otherwise specified; Tamb = 25 2 C. SYMBOL fSCP TWCL TWCH Tr, Tf tDSU tDHD tSL tLW tLS tLRP 2005 Oct 20 PARAMETER SCP clock frequency SCP clock LOW pulse width SCP clock HIGH pulse width SCP clock rising/falling time Input data setup time Input data hold time. SCP-rising-edge-to-LP-rising-edge LP pulse width LP-falling-edge-to-SCP-falling-edge LP set-up time 12 of 20 DI1~DI4 data to the falling edge of the CP clock. Falling edge of the CP clock to DI1~DI4 data change. 20 30 10 40 10 20 50 50 30 CONDITIONS MIN. MAX. 6.0 UNIT MHz ns ns 30 ns ns ns ns ns ns data sheet (v3)
Avant Electronics
SEN6A39 80-COLUMN driver for dot-matrix STN
SYMBOL tLFP tEIRP tEIFP tEIW tSE tES tEOD tEOH
PARAMETER LP hold time EIO IN set-up time EIO IN hold time EIO IN pulse width SCP-rising-edge-to-EIO-rising-edge Output delay time EIO OUT data delay time EIO OUT hols time
CONDITIONS
MIN. 40 20 40 40
MAX. UNIT www..com ns ns ns ns ns ns 100 95 ns ns
the EIO pin, load= 10 pF. the EIO pin, load= 10 pF.
10 10
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data sheet (v3)
Avant Electronics
SEN6A39 80-COLUMN driver for dot-matrix STN
9 9.1
TIMING CHART ( 1/240 DUTY) AND BIAS CIRCUIT 1/240 duty timing chart
240 1 2 240 1 2 240 1 2
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LP 01~O80 FR
FR LP DI1~DI4 SCP D1~D80
Fig.5 1/240 duty timing chart 9.2 Bias circuit VDD
VDD VDD R V1 R V2 V2 V1
VDD
VLCD=VDD-V5 V1 = VDD - (1/9) VLCD V2 = VDD - (2/9) VLCD V3 = VDD - (7/9) VLCD
SEN6A39
SEN6A40
5R
VLCD
V3 V3
V4 = VDD - (8/9) VLCD V5 = VDD - (9/9) VLCD
R V4 R V5 V5 VR V5 V4
VSS
VEE
Fig.6 LCD bias voltage
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data sheet (v3)
Avant Electronics
SEN6A39 80-COLUMN driver for dot-matrix STN
10 APPLICATION CIRCUIT (64 X 160 DOTS)
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D0~D7
8
D0~D7 MDS MD0 ad0~ad12 MD1 MD2 MD3
Display Memory 13
A0~12
R/W I/O1~8 CE1 6264
r/w d0~d7 ce
Z80
FS0 FS1 SDSEL
SAP1024B
HALT
IORQ WR RD A0 Address decoding circuit
DUAL WR RD C/D CDATA DIO1
LP FR
SCP FR
SEN6A40
DUAL
O1 O64
ED CE HSCP
A1~A7
TSW
64 x 160 dots LCD
O1....O80 SEN6A39
EIO2 EIO1 EIO2
DI1 DI2 DI3 DI4 SCP FR LP DUAL DIR DF1 DF2
....
DIR
O1....O80 SEN6A39
DI1 DI2 DI3 DI4 SCP FR LP DUAL DIR DF1 DF2
RESET XI XO
EIO1
RESET
VDD
VSS
Fig.7 64 X 160 dots application
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data sheet (v3)
Avant Electronics
SEN6A39 80-COLUMN driver for dot-matrix STN
11 PIN CIRCUITS Table 9 MOS-level schematics of all input, output, and I/O pins.
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SYMBOL
Input/ output
Output Enable
CIRCUIT
VDD VDD
NOTES
Data out
EIO1, EIO2
I/O
VSS VSS
Data in
VDD
VDD
SCP, DIR, LP, DI1~DI4, FR
Inputs
VSS
VSS
VDD VDD
EN1
VDD
V5
On n= 1 ~ 80
O1~O80,
Driver outputs,
VDD
EN2
V5
V2
V5 VDD
VDD, V2, V3, High voltage V5 inputs
EN3
V3
V5 VDD
EN4
V5
V5
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data sheet (v3)
Avant Electronics
SEN6A39 80-COLUMN driver for dot-matrix STN
www..com 1. It is recommended that the following power-up sequence be followed to ensure reliable operation of your display system. As the ICs are fabricated in CMOS and there is intrinsic latch-up problem associated with any CMOS devices, proper power-up sequence can reduce the danger of triggering latch-up. When powering up the system, control logic power must be powered on first. When powering down the system, control logic must be shut off later than or at the same time with the LCD bias (V5).
12 APPLICATION NOTES
1 second (minimum) 5V
1 second (minimum)
VDD
0V 0~50 ms 0~50 ms
Signal
0 second (minimum) 0 second (minimum)
V5
-30V
Fig.8 Recommended power up/down sequence
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data sheet (v3)
Avant Electronics
SEN6A39 80-COLUMN driver for dot-matrix STN
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13 PACKAGE INFORMATION
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SEN6A39 LQFP100 Package Outline Drawing
data sheet (v3)
Avant Electronics
SEN6A39 80-COLUMN driver for dot-matrix STN
14 SOLDERING 14.1 Introduction
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There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. For more in-depth account of soldering ICs, please refer to dedicated reference materials. 14.2 Reflow soldering
Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, please contact Avant for drypack information. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. 14.3 Wave soldering
Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 14.4 Repairing soldered joints
Fix the component by first soldering two diagonally- opposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
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data sheet (v3)
STN LCD Driver
data sheet (v3)
80-COLUMN driver for dot-matrix STN LCD
15 LIFE SUPPORT APPLICATIONS
SEN6A39
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This product is not designed for use in life support appliances, devices, or systems, where malfunction of this product can reasonably be expected to result in personal injury. Avant customers using or selling this product for use in such applications do so at their own risk and agree to fully indemnify Avant for any damages resulting from such improper use or sale.
2005 Oct 20
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