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YDA146
D-530
STEREO 5W-30W DIGITAL AUDIO POWER AMPLIFIER Overview
YDA146 (D-530) is a high-efficiency digital audio power amplifier IC with the maximum output of 30W x 2ch. YDA146 has a "Pure Pulse Direct Speaker Drive Circuit" that directly drives speakers while reducing distortion of pulse output signal and reducing noise on the signal, which realizes the highest standard low distortion rate characteristics and low noise characteristics among digital amplifier ICs in the same class. In addition, supporting filterless design allows circuit design with fewer external parts to be realized depending on use conditions. YDA146 features Power Limit Function, Non-clip Function, and DRC (Dynamic Range Control) Function that were developed by Yamaha original digital amplifier technology. YDA146 has overcurrent protection function for speaker output terminals, high temperature protection function, and lowsupply voltage malfunction prevention function.
Features
Operating supply voltage range PVDD: 8.0V to 16.5V Maximum momentary output 30 Wx2ch (VDDP=15V, RL=4, THD+N=10%) 20 Wx2ch (VDDP=14V, RL=4, THD+N=10%) Maximum continuous output 15 W*1x2ch (VDDP=15V, RL=8, THD+N=10%, Ta=70C) 13.5W*1x2ch (VDDP=15V, RL=4, THD+N=10%, Ta=25C) Distortion Rate (THD+N) 0.02 % (VDDP=12V, RL=8, Po=0.2W, 1kHz) Residual Noise 48Vrms (VDDP=12V, GAIN[1:0]=L,L, NCDRC[1:0]=L,L) Efficiency 92 % (VDDP=12V, RL=8) S/N Ratio 105 dB (VDDP=12V, GAIN[1:0]=L,L, NCDRC[1:0]=L,L) Channel separation -80 dB (VDDP=12V, GAIN[1:0]=L,L, NCDRC[1:0]=L,L) PSRR 60dB (VDDP=12V,Vripple=100mV, 1kHz, GAIN[1:0]=L,L, NCDRC[1:0]=L,L) Non-clip function/DRC function (switchable) Power limit function Clock External Synchronization Function Master/Slave Synchronization Function using clock outputs Over-current Protection Function, High Temperature Protection Function, Low Voltage Malfunction Prevention Function, and DC Detection Function Sleep Function using SLEEPN terminal and Output Mute Function using MUTEN terminal Spread Clock Function Pop Noise Reduction Function Package Lead-free 48-pin Plastic SQFP (Exposed stage) Note) *1: A value based on Yamaha's board implementation conditions (See Note *2 of page 26)
YDA146 CATALOG CATALOG No.:LSI-4DA146A51 2009.1
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YDA146
Terminal Configuration
< 48-pin SQFP Top View >
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YDA146
Terminal Function
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Name *4) NC NC PVDDREG AVDD INLP INLM VREF INRM INRP AVSS PLIMIT NC PVDDPR PVDDPR OUTPR OUTPR OUTPR PVSSR PVSSR OUTMR OUTMR OUTMR PVDDMR PVDDMR NC SLEEPN PROTN MUTEN CKOUT CKIN NCDRC0 NCDRC1 GAIN0 GAIN1 NC NC PVDDML PVDDML OUTML OUTML OUTML PVSSL PVSSL OUTPL OUTPL OUTPL PVDDPL PVDDPL I/O *1), *2), *3) PVDD OA IA IA OA IA IA GND IA PVDD PVDD O O O GND GND O O O PVDD PVDD I O/D I O I I I I I PVDD PVDD O O O GND GND O O O PVDD PVDD
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Function Normally, use this terminal in no-connection Normally, use this terminal in no-connection Power supply terminal for regulators 3.3V regulator output terminal Analog input terminal (Lch+) Analog input terminal (Lch-) Reference voltage output terminal Analog input terminal (Rch-) Analog input terminal (Rch+) Analog ground terminal Power limit setting terminal Normally, use this terminal in no-connection Power supply terminal for digital amplifier output (Rch+) Power supply terminal for digital amplifier output (Rch+) Digital amplifier output terminal (Rch+) Digital amplifier output terminal (Rch+) Digital amplifier output terminal (Rch+) Ground terminal for digital amplifier output (Rch) Ground terminal for digital amplifier output (Rch) Digital amplifier output terminal (Rch-) Digital amplifier output terminal (Rch-) Digital amplifier output terminal (Rch-) Power supply terminal for digital amplifier output (Rch-) Power supply terminal for digital amplifier output (Rch-) Normally, use this terminal in no-connection Sleep control terminal *5) Error flag output terminal MUTE control terminal Clock output terminal for synchronization External clock input terminal Non-clip/DRC1/DRC2 mode selection terminal 0 Non-clip/DRC1/DRC2 mode selection terminal 1 GAIN setting terminal 0 GAIN setting terminal 1 Normally, use this terminal in no-connection Normally, use this terminal in no-connection Power supply terminal for digital amplifier output (Lch-) Power supply terminal for digital amplifier output (Lch-) Digital amplifier output terminal (Lch-) Digital amplifier output terminal (Lch-) Digital amplifier output terminal (Lch-) Ground terminal for digital amplifier output (Lch) Ground terminal for digital amplifier output (Lch) Digital amplifier output terminal (Lch+) Digital amplifier output terminal (Lch+) Digital amplifier output terminal (Lch+) Power supply terminal for digital amplifier output (Lch+) Power supply terminal for digital amplifier output (Lch+)
(Note) *1 *2 *3 *4
I: Input terminal, O: Output terminal, A: Analog terminal, O/D: Open/Drain output terminal PVDD should be connected each other on a board. GND should be connected each other on a board. Each output terminal with the same name (OUTPR, OUTMR, OUTPL, and OUTML) should be connected on a board. *5 Do not use AVDD pin to apply "H" level to SLEEPN pin. The device will not start when using AVDD pin as "H" level signal because AVDD goes up at the time SLEEPN pin becomes "H". 3
CATALOG No.:LSI-4DA146A51
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YDA146
Block Diagram
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YDA146
Functional Description
Digital Amplifier Function
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YDA146 has digital amplifiers with analog input, PWM pulse output, the maximum output of 30W x 2ch. Adopting "Pure Pulse Direct Speaker Drive Circuit" reduces distortion and noise on PWM pulse output signal. Digital Amplifier Gain The total gain of the digital amplifier varies depending on operation modes, as shown below. NCDRC1 L NCDRC0 L GAIN1 L L H H L L H H L L H H L L H H GAIN0 L H L H L H L H L H L H L H L H Total Gain +22dB +28dB +34dB +16dB +34dB +40dB +46dB +28dB +34dB +40dB +46dB +28dB +34dB +40dB +46dB +28dB Operation Mode Normal mode Non-clip: OFF DRC: OFF
L
H
Non-clip mode
H
L
DRC1 mode
H
H
DRC2 mode
Audio Signal Input For a differential input, the signal should be input to INLP and INLM terminals (Lch) and to INRP and INRM terminals (Rch) through a DC-cut capacitor (CIN). On the contrary, for a single-ended input, the signal should be input to INLP terminal (Lch) and to INRP terminal (Rch) through a DC-cut capacitor (CIN). At this time, INLM and INRM terminals should be connected to AVSS through DC-cut capacitors (CIN) with the same value.
In the differential input mode, use signal sources with the same impedance to reduce pop-noise. Its value should be 10k or less. Use a DC-cut capacitor (CIN) of 1F. (The capacitance value should be less than 1.5F throughout the operating temperature range.) (Cautions) When inputting audio signals in Power-off state ( PVDD < VHUVLL ) or Sleep state, current may flow toward the former device from YDA146's ground, through each protection circuit of analog pins (INLP, INLM, INRP, and INRM). For this reason, audio signals should not be input in Power-off state ( PVDD < VHUVLL ) or Sleep state. CATALOG No.:LSI-4DA146A51 5
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YDA146
Input Impedance The input impedance (ZIN) is 18.8k regardless of a Gain setting. Reference Voltage Output Function Half a voltage of AVDD terminal is output to the reference voltage terminal (VREF). Connect a capacitor of 0.1F for voltage stabilization. Maximum Output The output varies depending on load impedance and a supply voltage, as shown below. Maximum momentary Output Maximum Continuous Output 30Wx2ch 20Wx2ch 15Wx2ch 13.5Wx2ch (PVDD=15V, RL=4, THD+N=10%) (PVDD=14V, RL=4, THD+N=10%) (PVDD=15V, RL=8, THD+N=10%, Ta=70) (PVDD=15V, RL=4, THD+N=10%, Ta=25)
The maximum momentary output means a possible maximum output by considering heat problems due to power loss separately. The maximum continuous output means a maximum output with Tjmax not exceeding 150C at a given temperature while outputting a sine wave continuously. In addition, this value is based on Yamaha's board implementation conditions. (See Note *2 of Page 26) A possible maximum continuous output in other settings can be converted by the following data: 1. Graph of Power Dissipation vs Output Power of Example of typical characteristics. (See Page 30) 2. Power Dissipation of Electrical Characteristics. (See Page 26)
Control Function
Output Power limit Function This is the function to set a voltage at which the output is clipped. At this time, a value at which the output is clipped is defined as a power limit value (VPL). Using this function prevents increase of temperature in a device as well as allowing the maximum output power to be limited. The output power limit value is determined by a voltage (voltage dividing resistor 1, 2) applied to PLIMIT terminal. In addition, changing the voltage at PLIMIT terminal during power-on is prohibited. The relation between a resistor ratio (R2/(R1+R2)(between voltage dividing resistor 1 and 2) and an output power with a 10% distortion is shown below. Since it may vary between MIN and MAX due to variation of internal AVDD, select resistors in consideration of the variation. PLIMIT resistor R1 and R2 should be set as follows. R1+R2=500k or less R1//R2=50k to 70k (R1//R2 means a parallel resistance between R1 and R2) Example 1: 4 max30W (8 max15W) R1=220k+4.7k, R2=75k Example 2: 8 min10W R1=200k, R2=75k+1.5k 6 CATALOG No.:LSI-4DA146A51
AVDD Voltage Dividing Resistor R1 PLIMIT Voltage Dividing Resistor R2 AVSS
PLIMIT terminal setting circuit
YDA146
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* Minimum value restriction on the output power limit. The minimum value of the output-power limit values is restricted by the value determined with the resistance voltage division ratio of "0.45." Even though the resistance voltage division ratio is set beyond "0.45," the output-power limit value wouldn't be set lower. * Cancellation of the output power limit function. It is possible to disable the power limit by setting "0"V (voltage division ratio "0") to the PLIMIT pin. However, it is necessary to set the power limit value when the following function is used. Non-clip function (Non-clip/DRC Function : P.9). DRC function (Non-clip/DRC Function : P.9). High Temperature Power Limiter State of High Temperature Protection (High Temperature Protection Function : P.18). For the relation between each function and the power limit value, see the item of each function.
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Enlarged Figures
PLIMIT Voltage Dividing Ratio vs Output Power at 10 distortion 4
35 Typ MIN MAX
10 9 8 7 6 5 4 3 2 1 Typ MIN MAX
PLIMIT Voltage Dividing Ratio vs Output Power at 10 distortion 4
30
Output Power at 10 distortion [W]
25
20
15
10
5
Output Power at 10 distortion [W]
0.300
0.350
0.400
0.450
0.200
0.250
0.300
0.350
0.400
0.450
0.500
PLIMIT Voltage Dividing Ratio
PLIMIT Voltage Dividing Ratio
PLIMIT Voltage Dividing Ratio vs Output Power at 10 distortion 8
18 16 Typ MIN MAX
10 9
PLIMIT Voltage Dividing Ratio vs Output Power at 10 distortion 8
Typ MIN MAX
Output Power at 10 distortion [W]
Output Power at 10 distortion [W]
14 12 10 8 6 4 2 0
8 7 6 5 4 3 2 1 0
0.200
0.250
0.300
0.350
0.400
0.450
0.250
0.300
0.350
0.400
PLIMIT Voltage Dividing Ratio
PLIMIT Voltage Dividing Ratio
PLIMIT Voltage Dividing Ratio vs Output Power at 10 distortion 16
9 8 Typ MIN MAX
5 4.5 4
PLIMIT Voltage Dividing Ratio vs Output Power at 10 distortion 16
Output Power at 10 distortion [W]
Typ MIN MAX
Output Power at 10 distortion [W]
7 6 5 4 3 2 1 0
3.5 3 2.5 2 1.5 1 0.5 0 0.250 0.300 0.350 0.400 0.450
0.200
0.250
0.300
0.350
0.400
PLIMIT Voltage Dividing Ratio
0.450
PLIMIT Voltage Dividing Ratio
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CATALOG No.:LSI-4DA146A51
0.450
0.500
0
0
YDA146
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Non-clip/DRC Function This is the function to change the gain by detecting an input level to the PWM amplifier and to raise an average output level while suppressing clipping. A mode is determined by the combination of NCDRC[1:0] terminals, as shown below. NCDRC1 L L H H NCDRC0 L H L H Mode Non-clip & DRC mode OFF Non-clip mode DRC1 mode DRC2 mode
In Non-clip mode, the gain increases by 12dB. The gain is automatically adjusted so that an output peak voltage becomes a power limit value. The maximum attenuation is -12dB. Attack Time is 0 second. The release time from -12dB to 0dB is 7.7 s (typ.). In DRC1 mode, the gain increases by 12dB. Dynamic Range Compression (a half of gain in dB) is performed within an output range of -12dB (-24dB for input range) from the power limit value. Attack Time is 0 s. The release time from -12dB to 0dB is 3.9 s (typ.). In DRC2 mode, the gain increases by 12dB. As with DRC1, similar compression is performed, but power-limit operation is not performed. PLIMIT terminal can be used to set a DRC operating point. Therefore, the setting of a gain curve is possible regardless of the maximum output power, and this allows for DRC operation from a low output power. NCDRC [1:0] terminal should be switched under either of the following conditions. Before PVDD power-on (lower than the PVDD start-up threshold voltage (VHUVLH)) SLEEPN=L Pop noise may occur when switching it under an operating condition other than the above.
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YDA146
A condition in which the power limit is being applied.
Power Limit Value VPL
Output Voltage [dB]
Output Voltage [dB]
OFF NCDRC[1:0]=00
Input Voltage [dB]
0
Non-clip/DRC Gain Curve (OFF)
A condition in which the power limit is being applied.
Power Limit Value VPL
Non-clip NCDRC[1:0]=01
Output Voltage [dB]
Output Voltage [dB]
OFF NCDRC[1:0]=00
Input Voltage [dB]
-12
0
Non-clip/DRC Gain Curve (Non-clip)
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YDA146
A Condition in which the power limit is being applied.
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V Power Limit Value (VPL) PL
DRC1 NCDRC[1:0]=10
VPL - 12dB [dB]
OFF NCDRC[1:0]=00
Output Voltage [dB]
-24
[dB] Input Voltage [dB]
0
Non-clip/DRC Gain Curve (DRC1)
A condition in which it is not applied even if exceeding the power limit.
Power Limit Value VPL
DRC2 NCDRC[1:0]=11
VPL - 12dB Output Voltage [dB]
OFF NCDRC[1:0]=00
Output Voltage [dB]
-24
Input Voltage [dB]
0
Non-clip/DRC Gain Curve (DRC2)
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YDA146
Sleep Function YDA146 shifts into sleep mode when SLEEPN terminal goes to "L" level. In the sleep mode, all functions stop and consumption current is minimized (SLEEP). When shifting into sleep mode during any protection mode, the protection mode is cancelled and PROTN terminal output becomes Hi-Z state. The digital amplifier output becomes Weak Low (a state grounded through a high resistance). AVDD and VREF outputs are pulled down. When the level at SLEEPN terminal is changed from "L" to "H" under the condition that the voltage at PVDDREG terminal is higher than the threshold voltage (VHUVLH) for low voltage malfunction prevention cancellation, the sleep mode is cancelled and the state shifts into the normal operation state after the period of sleep recovery time (tWU). Mute Function YDA146 shifts into mute mode when MUTEN terminal goes to "L" level. In the mute mode, the digital amplifier output becomes Weak Low (a state grounded through a high resistance). When the level at MUTEN terminal is changed from "L" to "H" under the condition that the voltage at PVDDREG terminal is higher than the threshold voltage (VHUVLH) for low voltage malfunction prevention cancellation and state of SLEEPN terminal=H, the mute mode is cancelled and the state shifts into the normal operation state after the period of mute recovery time (tMRCV). Clock Control Function The setting of CKIN terminal controls the clock mode as shown below. CKIN terminal Setting L fixed H fixed Clock input Mode Internal Clock mode Internal Clock (Spread clock) mode External Clock mode CKOUT Internal Clock (frequency: fCK) output Internal Clock (Spread Clock) frequency: (fCK) output CKIN input buffer output (frequency: fCKIN)
When CKIN terminal is held L or H level, internal clock mode is selected to generate a clock internally. And, when CKIN terminal is held H level, Spread Clock function operates to reduce EMI. When an external clock is input to CKIN terminal, its frequency should be fCKIN. Do not use with CKIN terminal left open. Digital Amplifier Pop Noise Reduction Function Pop noise that may occur at the power-on, power-off, power-down, and power-down cancel operations, etc. is reduced by minimizing an output offset voltage. Multi-chip Synchronization Function The external clock synchronization function and clock output function are prepared and the use of master/slave configuration realizes carrier clock synchronization. When using it with multi chips synchronized, one is used as a master chip and the other is used as a slave chip. At this time, connect CKOUT terminal of a master chip to CKIN terminal of a slave chip. When using 3 chips (master/slave1/slave2), connect CKOUT terminal of a slave1 chip to CKIN terminal of a slave2 chip. For details of connections, see "MASTER-SLAVE operation" (See page 24-25) in the "Examples of Application Circuits." PVDD pins should be connected each other on a board.
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YDA146
Startup Sequence, Shutdown Sequence
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VDDP PVDD
VHUVLH
AVDD
VDDA
tWU
OUTPL/OUTPR
OUTML/OUTMR
Digital Amplifier Output
Power Supply Startup Sequence
VDDP PVDD
VHUVLH
VDDA AVDD
OUTPL /OUTPR
OUTML /OUTMR
Digital Amplifier Output
Stopping Digital Amplifier Output
Power Supply Shutdown Sequence
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YDA146
SLEEPN
VIH_SLPN
AVDD tWU
OUTPL /OUTPR
OUTML /OUTMR
Digital Amplifier Output
Startup Sequence from Sleep State
SLEEPN
VIL_SLPN
AVDD
OUTPL /OUTPR
OUTML /OUTMR
Digital Amplifier Output
Stopping Digital Amplifier Output
Transient Sequence to Sleep State
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YDA146
Regulator Output
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When SLEEPN terminal is at H, YDA146 outputs VDDA to AVDD terminal. Connect a capacitor of 1F to 4.7F to AVDD terminal for stabilization. (0.8F or more should be secured including its variation and temperature change.) AVDD output must be used only for YDA146. If this output is used in a peripheral circuit of YDA146, the maximum current that can be driven will be IDDA.
LC Filter
YDA146 adopts the modulation method that reduces speaker loss sufficiently at mute state by the use of only an inductance the speaker has, and this allows for direct connection to a speaker without an LC filter. When an LC filter is used, use the LC filter circuits shown below. At this time, the following constant should be used according to an impedance of a speaker. Using these constants makes a low-pass filter with a cut-off frequency of 50kHz or so, Q=0.7 or so. LC filter constants: RL L1 4 10H 8 22H
C1 0.33F 0.22F
C2 0.22F 0.1F
L1 RL L1 C2 C1
C2
LC Filter circuit
* With use of LC filters, if there is a possibility of not using a speaker, audio signals within 20kHz should be input. And, if its band limitation is not possible, remove the speaker under the following conditions: SLEEPN terminal = L or MUTEN terminal = L, or PVDD = Power Off.
Speaker Inductance
In the following cases, use a speaker with an inductance of 20H or more (at around the switching frequency (fCKIN or fCK)). 1. Direct connection of a speaker to an output pin of the digital amplifier without an LC filter. 2. Connection of a speaker to a position after components for EMI measures such as ferrite beads etc. (filterless). With an inductance of less than 20H, power loss in the speaker and this device may increase.
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YDA146
Protection Function
YDA146 has the following four digital amplifier protection functions: overcurrent protection function, high temperature protection function, low voltage malfunction prevention function, and DC detection function.
Protection Functions PROTN terminal Output Low PROTN terminal Latch Latched Not latched Digital Amplifier Output State WL*1) Power Limit (-6dB) WL*1) WL*1) WL*1) Protection Mode Cancel
Over current Protection Function High Temperature Protection Function (High Temp. power limiter state) High Temperature Protection Function (High Temp. shutdown state) Low Voltage Malfunction Prevention Function DC Detection Function
Low (HighZ) Low
Not latched Latched
SLEEPN terminal=L or PVDD shutdown SLEEPN terminal=L or PVDD shutdown or lower temperature SLEEPN terminal=L or PVDD shutdown or lower temperature SLEEPN terminal=L or PVDD shutdown
*1: WL=Weak Low (a state when grounded with a high resistance) Use a circuit as shown below when pulling up PROTN terminal output externally. 1) Pull up the terminal to a voltage obtained by dividing the voltage between PVDD and GND with voltage-dividing resistors. Find values with reference to the following formula so that a voltage at the terminal becomes 3.3V or less when PROTN terminal is in "H" output (Hi-Z). 2.0V (R2 / (R1 + R2)) x VDDP 3.3V ;however, R1 > 100k, 10k < R2 < 100k 2) The pull-up should be performed to an external supply voltage lower than 3.3V. The pull-up resistor R3 should be a value as follows. 40k < R3 < 200k (47k is recommended.) In each case, select these values so that 0.4mA or more current will not flow into the terminal while PROTN terminal is in L state.
PROTN terminal Pull-Up Connection 1 (A pull-up to PVDD)
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YDA146
VCC(3.3V)
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R3 PROTN Error Flag
PROTN terminal Pull-Up Connection 2 (A pull-up to 3.3V) * If automatic return setting is given by connecting PROTN terminal to SLEEPN terminal, use a separate power supply as VCC, not the same power supply as AVDD. * When VCC is used as AVDD, see Startup Sequence (page 13 and 14).
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YDA146
Digital Amplifier Over current Protection Function This is the function to protect the device by detecting short-circuiting (to the supply voltage, to the ground, and between terminals) at digital amplifier output terminals. In the protection mode, PROTN terminal becomes L level and output terminals become Weak Low state (a state grounded through a high resistance). The protection mode can be cancelled by turning off the power supply or inputting an L level signal to SLEEPN terminal momentarily. And, when PROTN terminal is externally connected to SLEEPN terminal, automatic return mode is selected. At this time, the protection mode is cancelled even if the protection mode is established by detecting an overcurrent state, and PROTN terminal output is turned from L level into Hi-Z state and a normal operation state is given after a given standby time (tWU). (Automatic Return Function) The current value to detect a short-circuiting between terminals is 8A (typ,VDDP=12V), 10A (typ,VDDP=15V). High Temperature Protection Function This is the function to protect the device by detecting an unusual temperature in YDA146. The protection mode operates in the following two modes according to the temperature. 1) High Temperature Power Limiter State If the temperature rises and reaches 155C (typ.), the high temperature power limiter state is given. This state decreases the power limit level by 6dB in order to limit the digital amplifier output power, and attempts to lower the temperature. In this way, when the temperature falls and lowers than 130C (typ.), the high temperature power limiter state is automatically cancelled and the gain is restored to the original setting value. In the power limiter state, this does not affect on PROTN terminal. 2) High Temperature Shutdown State If the temperature rises and reaches 165C (typ.) during the high temperature power limiter state, the high temperature shutdown state is given. This state outputs an L level signal from PROTN terminal and digital amplifier output terminals become Weak Low state (a state grounded through a high resistance). In this way, when the temperature goes down and lowers than 130C (typ.), the high temperature shutdown state is automatically cancelled. And, even if the shutdown state is established by detecting an unusual temperature, when PROTN terminal is externally connected to SLEEPN terminal, the shutdown state is cancelled and PROTN terminal output is turned from L into Hi-Z state and a normal operation state is given if the temperature is sufficiently lowered after a given standby time (tWU). (Automatic Return Function) If the temperature is not sufficiently lowered, the high temperature protection mode will be established. Low Voltage Malfunction Prevention Function This is the function to protect the device when the supply voltage at PVDDREG terminal is unusually lowered. In this protection mode, the digital amplifier output terminals become Weak Low state (a state grounded through a high resistance). This protection mode is given if the supply voltage at PVDDREG terminal becomes a voltage lower than PVDD shutdown threshold voltage (VHUVLL). When the supply voltage at PVDDREG terminal exceeds PVDD startup threshold voltage (VHUVLH), the protection mode is cancelled and a normal operation mode is given after a given standby time (tWU). (Automatic Return Function)
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YDA146
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DC Detection Function This is the function to protect the speaker connected to the digital amplifier output when a DC signal is continuously output from the digital amplifier. When MUTEN terminal=L, the DC detection function is disabled. When a voltage in excess of a given time (tDCDET) and a given level (VDCDET) is output to the digital amplifier output, the DC detection mode is given. This state outputs an L level signal from PROTN terminal and digital amplifier output terminals become Weak Low state (a state grounded through a high resistance). Once the DC detection mode is given, an L level signal keeps outputting from PROTN terminal even if the DC output state is cancelled. The protection mode is cancelled by turning off the power supply or inputting an L level signal to SLEEPN terminal momentarily. And, even if DC protection mode is established by detecting a DC signal, when PROTN terminal is externally connected to SLEEPN terminal, the protection mode is cancelled and PROTN terminal output is turned from L into Hi-Z state and a normal operation state is given after a given standby time (tWU).
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YDA146
Examples of Application Circuits
(Caution)
A ceramic capacitor of 1F should be used as a bypass capacitor between the following terminals: PVDDPL-PVSSL, PVDDML-PVSSL, PVDDPR-PVSSR, and PVDDMR-PVSSR. Please mount the capacitor as close as possible to each terminal. A former-stage impedance of input terminals should be 10k or less. Select resistor values so that a voltage becomes 2.0V to 3.3V when PROTN terminal is at H level and current becomes 0.4mA or less when PROTN terminal is at L. For PLIMIT terminal setting, see page 6 and 7. For a pull-up resistor for PROTN terminal, see page 16 and 17.
Single operation in stereo mode (differential-input, external clock operation)
VDDP
VDDP 1uF
VSSP
VDDP 1uF
220uF
OUTPL
PVSSL
PVDDPL
OUTML
OUTML
OUTML
OUTPL
OUTPL
PVSSL
VDDP
NC NC
PVDDML
PVDDML
PVDDPL
NC NC GAIN1 GAIN0 Gain Select
PVDDREG 0.1uF 1uF Lch Input+ 1uF Lch Input0.1uF Rch Input1uF Rch Input+ 1uF AVSS PLIMIT PVDDPR PVDDPR PVDDMR VSSA NC INRP INLM VREF INRM 1uF AVDD INLP
NCDRC1 NCDRC0 CKIN CKOUT MUTEN PROTN SLEEPN PVDDMR NC
Non-Clip/DRC1/DRC2 mode select
External Clock (open) Mute Control VCC Error Flag Sleep Control
OUTMR
OUTPR
OUTPR
1uF VDDP VSSP
OUTMR 1uF
PVSSR
OUTMR
OUTPR
PVSSR
VDDP
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YDA146
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Single operation in stereo mode (single-ended input, external clock operation)
VDDP
VDDP 1uF
VSSP
VDDP 1uF
220uF
OUTPL
PVSSL
PVSSL
PVDDPL
OUTML
OUTML
OUTML
OUTPL
OUTPL
VDDP
NC NC
PVDDML
PVDDML
PVDDPL
NC NC GAIN1 GAIN0 Gain Select
PVDDREG 0.1uF 1uF Lch Input+ 1uF INLM 0.1uF VREF INRM 1uF Rch Input+ 1uF AVSS PLIMIT PVDDPR PVDDPR PVDDMR VSSA NC INRP 1uF AVDD INLP
NCDRC1 NCDRC0 CKIN CKOUT MUTEN PROTN SLEEPN PVDDMR NC
Non-Clip/DRC1/DRC2 mode select
External Clock (open) Mute Control VCC Error Flag Sleep Control
OUTMR
OUTPR
OUTPR
1uF VDDP VSSP
OUTMR 1uF
PVSSR
OUTMR
OUTPR
PVSSR
VDDP
Single operation in stereo mode (differential-input, input signal level (externally set), external clock operation)
VDDP
VDDP 1uF
VSSP
VDDP 1uF
220uF
OUTPL
PVDDPL
OUTML
PVSSL
PVSSL
OUTML
OUTML
OUTPL
OUTPL
VDDP NC NC
PVDDML
PVDDML
PVDDPL
NC NC GAIN1 GAIN0 Gain Select
PVDDREG 0.1uF 1uF Lch Input+ 1uF Lch Input0.1uF Rch Input1uF Rch Input+ 1uF AVSS PLIMIT PVDDMR PVDDPR PVDDPR NC VSSA INLM VREF INRM INRP 1uF AVDD INLP
NCDRC1 NCDRC0 CKIN CKOUT MUTEN PROTN SLEEPN PVDDMR NC
Non-Clip/DRC1/DRC2 mode select
External Clock (open) Mute Control VCC Error Flag Sleep Control
OUTMR
OUTMR 1uF
OUTPR
OUTPR
1uF VDDP VSSP
OUTMR
OUTPR
PVSSR
PVSSR
VDDP
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YDA146
Single operation in stereo mode (single-ended input, input signal level (externally set), external clock operation)
VDDP
VDDP 1uF
VSSP
VDDP 1uF
220uF
OUTPL
PVDDPL
PVSSL
PVSSL
OUTML
OUTML
OUTPL
OUTPL
PVDDPL
OUTML
PVDDML
VDDP NC NC
PVDDML
NC NC GAIN1 GAIN0 Gain Select
PVDDREG 0.1uF 1uF Lch Input+ 1uF INLM 0.1uF VREF INRM 1uF Rch Input+ 1uF AVSS PLIMIT PVDDPR PVDDPR PVDDMR NC INRP 1uF AVDD INLP
NCDRC1 NCDRC0 CKIN CKOUT MUTEN PROTN SLEEPN PVDDMR NC
Non-Clip/DRC1/DRC2 mode select
External Clock (open) Mute Control VCC Error Flag Sleep Control
OUTMR
OUTMR 1uF
OUTPR
OUTPR
1uF VDDP VSSP
OUTMR
OUTPR
PVSSR
PVSSR
VDDP
Single operation in stereo mode (differential-input, internal clock operation)
VDDP
VDDP 1uF
VSSP
VDDP 1uF
220uF
PVDDPL
OUTML
OUTML
OUTML
OUTPL
OUTPL
OUTPL
PVSSL
PVSSL
VDDP
NC NC
PVDDML
PVDDML
PVDDPL
NC NC GAIN1 GAIN0 Gain Select
PVDDREG 0.1uF 1uF Lch Input+ 1uF Lch Input0.1uF Rch Input1uF Rch Input+ 1uF AVSS PLIMIT PVDDMR PVDDPR PVDDPR NC INRP INLM VREF INRM 1uF AVDD INLP
NCDRC1 NCDRC0 CKIN CKOUT MUTEN PROTN SLEEPN PVDDMR NC AVSS
Non-Clip/DRC1/DRC2 mode select
(open) Mute Control VCC Error Flag Sleep Control
OUTMR
OUTMR 1uF
OUTPR
OUTPR
OUTPR
PVSSR
1uF VDDP VSSP
PVSSR
VSSA
OUTMR
VDDP
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YDA146
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Single operation in stereo mode (differential-input, external clock operation, automatic return setting)
VDDP
VDDP 1uF
VSSP
VDDP 1uF
220uF
PVDDPL
OUTML
OUTML
OUTML
OUTPL
OUTPL
OUTPL
PVSSL
PVSSL
VDDP
NC NC
PVDDML
PVDDML
PVDDPL
NC NC GAIN1 GAIN0 Gain Select
PVDDREG 0.1uF 1uF Lch Input+ 1uF Lch Input0.1uF Rch Input1uF Rch Input+ 1uF AVSS PLIMIT PVDDPR PVDDPR PVDDMR NC INRP INLM VREF INRM 1uF AVDD INLP
NCDRC1 NCDRC0 CKIN CKOUT MUTEN PROTN SLEEPN PVDDMR NC
Non-Clip/DRC1/DRC2 mode select
External Clock (open) Mute Control VDDP
OUTMR
OUTPR
OUTPR
OUTPR
PVSSR
PVSSR
VSSA
OUTMR
OUTMR
VSSP
1uF VDDP VSSP
1uF VDDP
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YDA146
M ASTER-SLAVE operation (differential-input, external clock operation)
VDDP
VDDP 1uF
VSSP
VDDP 1uF
220uF
M aster
OUTPL PVDDPL OUTML PVSSL PVSSL OUTML PVDDML PVDDPL VDDP NC NC PVDDREG 0.1uF 1uF Lch Input+ 1uF Lch Input0.1uF Rch Input1uF Rch Input+ 1uF AVSS PLIM IT PVDDMR PVDDPR PVDDPR NC PROTN SLEEPN PVDDMR NC Sleep Control VCC Error Flag INRP M UTEN Mute Control INLM VREF INRM NCDRC0 CKIN CKOUT 1uF AVDD INLP PVDDML OUTML OUTPL OUTPL NC NC GAIN1 GAIN0 NCDRC1
Gain Select
Non-Clip/DRC1/DRC2 mode select
External Clock
OUTMR
OUTMR 1uF
OUTPR
OUTPR
VSSA
1uF VDDP VSSP
OUTMR
OUTPR
PVSSR
PVSSR
VDDP
VDDP
VDDP 1uF
VSSP
VDDP 1uF
220uF
Slave1
PVDDPL OUTML OUTPL PVSSL PVSSL PVDDPL OUTML PVDDML VDDP NC NC PVDDREG 0.1uF 1uF Lch Input+ 1uF Lch Input0.1uF Rch Input1uF Rch Input+ 1uF AVSS PLIM IT PVDDMR PVDDPR PVDDPR NC PROTN SLEEPN PVDDMR NC Sleep Control VCC Error Flag INRP M UTEN Mute Control INLM VREF INRM NCDRC0 CKIN CKOUT 1uF AVDD INLP PVDDML OUTML OUTPL OUTPL NC NC GAIN1 GAIN0 NCDRC1
Gain Select
Non-Clip/DRC1/DRC2 mode select
OUTMR 1uF
OUTPR
OUTPR
OUTPR
PVSSR
1uF VDDP VSSP
PVSSR
VSSA
OUTMR
OUTMR
VDDP
VDDP
VDDP 1uF
VSSP
VDDP 1uF
220uF
Slave2
OUTPL PVDDPL OUTML PVSSL PVSSL OUTML OUTPL OUTPL VDDP NC NC PVDDREG 0.1uF 1uF Lch Input+ 1uF Lch Input0.1uF Rch Input1uF Rch Input+ 1uF AVSS PLIM IT PVDDMR PVDDPR PVDDPR NC VSSA PROTN SLEEPN PVDDMR NC Sleep Control VCC Error Flag INRP M UTEN Mute Control INLM VREF INRM NCDRC0 CKIN CKOUT (open) 1uF AVDD INLP PVDDML PVDDML PVDDPL OUTML NC NC GAIN1 GAIN0 NCDRC1
Gain Select
Non-Clip/DRC1/DRC2 mode select
OUTPR
OUTPR
1uF VDDP VSSP
1uF VDDP
OUTMR
OUTMR
OUTMR
OUTPR
PVSSR
PVSSR
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CATALOG No.:LSI-4DA146A51
YDA146
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MASTER-SLAVE operation (differential-input, external clock operation, automatic return setting)
VDDP
VDDP 1uF
VSSP
VDDP 1uF
220uF
Master
OUTPL OUTML OUTML OUTPL PVDDPL OUTML OUTPL PVSSL PVSSL PVDDML VDDP NC NC PVDDREG 0.1uF 1uF Lch Input+ 1uF Lch Input0.1uF Rch Input1uF Rch Input+ 1uF AVSS PLIMIT PVDDMR PVDDPR PVDDPR NC PROTN SLEEPN PVDDMR NC INRP MUTEN Mute Control INLM VREF INRM NCDRC0 CKIN CKOUT External Clock 1uF AVDD INLP GAIN0 NCDRC1 PVDDML PVDDPL NC NC GAIN1 Gain Select
Non-Clip/DRC1/DRC2 mode select
OUTMR
OUTMR
OUTPR
OUTPR
OUTPR
PVSSR
1uF VDDP VSSP
PVSSR
VSSA
1uF VDDP
VDDP
VDDP 1uF
VSSP
OUTMR
VDDP 1uF
220uF
Slave1
OUTPL OUTML OUTPL OUTML OUTPL PVSSL PVDDPL OUTML PVSSL PVDDML PVDDPL VDDP PVDDML NC NC PVDDREG 0.1uF 1uF Lch Input+ 1uF Lch Input0.1uF Rch Input1uF Rch Input+ 1uF AVSS PLIMIT PVDDMR PVDDPR PVDDPR NC PROTN SLEEPN PVDDMR NC INRP MUTEN Mute Control INLM VREF INRM NCDRC0 CKIN CKOUT 1uF AVDD INLP GAIN0 NCDRC1 NC NC GAIN1 Gain Select
Non-Clip/DRC1/DRC2 mode select
OUTMR
OUTMR
OUTPR
OUTPR
OUTPR
PVSSR
1uF VDDP VSSP
PVSSR
VSSA
1uF VDDP
VDDP
VDDP 1uF
VSSP
OUTMR
VDDP 1uF
Slave2
VDDP
220uF
PVDDPL
OUTML
OUTPL
PVSSL
OUTPL
PVSSL
OUTML
OUTPL
OUTML
PVDDML
PVDDPL
NC NC
PVDDML
NC NC GAIN1 GAIN0 Gain Select
PVDDREG 0.1uF 1uF Lch Input+ 1uF Lch Input0.1uF Rch Input1uF Rch Input+ 1uF AVSS PLIMIT PVDDMR PVDDPR PVDDPR NC INRP INLM VREF INRM 1uF AVDD INLP
NCDRC1 NCDRC0 CKIN CKOUT MUTEN PROTN SLEEPN PVDDMR NC
Non-Clip/DRC1/DRC2 mode select
(open) Mute Control
VDDP
OUTMR
OUTMR
OUTPR
OUTPR
OUTPR
PVSSR
PVSSR
VSSA
OUTMR
VSSP
1uF VDDP VSSP
1uF VDDP
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YDA146
Electrical Characteristics
Absolute Maximum Ratings *1) Parameter Symbol Min. Max. Unit Power Supply terminal (PVDD) Voltage Range VDDP -0.3 20 V Input Terminal Voltage Range VIN -0.3 4 V PROTN Terminal Voltage Range VPROTN -0.3 4 V Power Dissipation (Ta=25C) PD25 6.5*2) W 4 layers Power Dissipation (Ta=70C) PD70 4.21*2) W 3.4*2) W Power Dissipation (Ta=85C) PD85 SQFP48 Power Dissipation (Ta=25C) PD25 3.72*3) W 2 layers Power Dissipation (Ta=70C) PD70 2.38*3) W Power Dissipation (Ta=85C) PD85 1.93*3) W Junction Temperature TJMAX 150 C Storage Temperature TSTG -40 150 C Note) *1: Absolute Maximum Ratings is values which must not be exceeded to guarantee device reliability and life, and when using a device in excess even a moment, it may immediately cause damage to device or may significantly deteriorate its reliability. *2: A value based on the following implementation conditions: LC FilterL=22 [H]/C=0.47[H], Board Layer4 layers(FR-4), Board Size136 [mm] x 85 [mm], Board Copper Foil Thickness35 [m], Wiring Density379%, Device Heat Padsoldering on the board Through Hole for heat dissipation25 (5x5) holes from a point just below the exposed stage to the inner layer (VSS) and B layer. *3: A value based on the following implementation conditions: Board Layer: 2 layers (FR-4), Board Size: 136 [mm] x 85 [mm], Board Copper Foil Thickness: 35 [m], Wiring Density: 187%, Exposed stage: soldering on the board Through Hole for heat radiation: 25 (5x5) holes from a point just below the exposed stage to B layer. Recommended Operating Condition Parameter Symbol Min. Typ. Power Supply Voltage (PVDD) VDDP 8 Digital terminals*4) H level input voltage VIN 2.52 3.3 SLEEPN terminal H level input voltage VIN 2.0 3.3 Operating Ambient Temperature Ta -40 25 Speaker Impedance RL 3.6 4 Note) *4:MUTEN, CKIN, NCDRC0, NCDRC1, GAIN0, GAIN1(CMOS I/F) terminals
Max. 16.5 3.6 3.6 85 -
Unit V V V C
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CATALOG No.:LSI-4DA146A51
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DC Characteristics (VSS=0V, VDDP=8V to 16.5V, Ta=-40C to 85C, CKIN=1MHz, unless otherwise specified.) Parameter Symbol Conditions Min. Typ. Max. Unit PVDD Startup threshold voltage VHUVLH 6.5 V PVDD Shutdown threshold voltage VHUVLL 6.0 V DC Detection Voltage VDCDET PVDD=15V 4 V DC Detection Time tDCDET 0.5 s Digital terminal*5) H level input voltage VIH 2.52 V Digital terminal*5) L level input voltage VIL 0.9 V Digital terminal *5 Input Impedance RIN_D 3.3 M SLEEPN terminal H level input voltage VIH_SLPN 2.0 V SLEEPN terminal L level input voltage VIL_SLPN 0.8 V SLEEPN terminal Input Impedance RIN_ SLPN 3.3 M CKOUT Output Voltage VOL IOL=4mA 0.4 V CKOUT Output Voltage VOH IOH=-4mA 2.4 V PROTN Output Voltage VOL IOL=0.4mA 0.4 V INLP, INLM, INRP, INRM terminals RIN 18.8 k Input impedance AVDD Output Voltage VDDA 3.0 3.3 3.6 V AVDD Output Current IDDA 1 mA VREF Output Voltage VREF VDDA /2 V PVDD Consumption Current IDDP VDDP=12V, no-load 32 mA PVDD consumption current ISLEEP VDDP=15V, Ta=25C 30 A during power-down mode (SLEEPN=L) PVDD consumption current IMUTE VDDP=15V, Ta=25C 16 mA during Mute state (MUTEN=L) PVDD consumption current INOSIG VDDP=15V, Ta=25C 38 mA during no signal input
Note) *5: This value is applicable to MUTEN, CKIN, NCDRC0, NCDRC1, GAIN0, and GAIN1 (CMOS I/F) terminals.
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YDA146
AC characteristics (VSS=0V, VDDP=8V to 16.5V, Ta=-40C to 85C, CKIN=1MHz, unless otherwise specified.) Parameter Symbol Min. Typ. Max. Unit CKIN Input Frequency fCKIN 0.9 1,0 1.1 MHz CKIN Input Duty DTCKEXT 40 60 % Self-excited Clock Frequency fCK 1.0 MHz Sleep Recovery Time tWU 1 1.5 s Mute Recovery Time tMRCV 1 ms Analog Characteristics (VSS=0V, VDDP=12V, Ta=25C, GAIN[1:0]=L,L, NCDRC[1:0]=L,L, CKIN= L*7), unless otherwise specified.) Parameter Symbol Conditions Min. Typ. Max. Unit RL=4, VDDP=12V, THD+N=10% 19.4 W Maximum momentary Output Po RL=8, VDDP=15V, THD+N=10% 15 W RL=4, VDDP=15V, THD+N=10% 30 W GAIN[1:0]=L,L 22 dB GAIN[1:0]=L,H 28 dB Voltage Gain AV GAIN[1:0]=H,L 34 dB GAIN[1:0]=H,H 16 dB VDDP=15V, RL=4, PO=0.2W 0.02 % Total Harmonic Distortion Rate THD+N (BW::20kHz) VDDP=12V, RL=8, PO=0.2W 0.02 % Signal /Noise Ratio SNR RL=4,GAIN[1:0]=H,H 105 dB (BW::20kHz A-Filter) Residual Noise Vn RL=4,GAIN[1:0]=H,H 48 Vrms (BW::20kHz A-Filter) Channel Separation Ratio CS 1kHz 80 dB Power Supply Rejection Ratio PSRR Vripple=100mV, f=1kHz 60 dB (PVDD applied) Common Mode Rejection Ratio CMRR f=1kHz 41 dB VDDP=15V, RL=4 90 % Maximum Efficiency VDDP=15V, RL=8 92 % *6) Output Offset Voltage |Vo| 5 15 mV f=20Hz -1 0 1 dB Frequency characteristics fRES f=20kHz -1 0 1 dB Note) *6: The offset voltage is denoted by considering a typical value and the maximum value as and 3, respectively. *7: The same specification is applied to the external clock mode and internal clock (spread clock mode). All the values of analog characteristics were obtained in our evaluation circumstance. Depending upon pattern layout etc., characteristics may vary. The measurement is performed with an 8 or 4 resistor connected in series with a 30H coil as an output load.
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Example of typical characteristics
POWER vs THD+N(YDA146, RL=4) (Freq=1kHz, with 20kHz filter)
100.00%
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(VSS=0V, VDDP=12V, Ta=25C, GAIN[1:0]=L,L, NCDRC[1:0]=L,L, CKIN=1MHz, unless otherwise specified)
POWER vs THD+N(YDA146, RL=8) (Freq=1kHz, with 20kHz filter) Lch Rch
100.00% 10.00% THD+N 1.00% 0.10%
Lch Rch
10.00% THD+N 1.00% 0.10% 0.01% 0.0001 0.001
0.01% 0.0001 0.001
0.01
0.1 1 Power [W]
10
100
0.01
0.1 1 Power [W]
10
100
100.00% 10.00% THD+N 1.00% 0.10% 0.01% 100
FREQ vs THD+N (YDA146) (Po=0.2W with 20kHz filter)
Noise FFT (YDA146) 0 -20 Noise Level [dBV] -40 -60 -80 -100 -120 -140 -160 Lch Rch
Lch Rch
1000 10000 FREQ [Hz
Frequency Response (YDA146)
100000
10
100
1000 Freq [Hz]
10000
100000
Power vs Efficiency(YDA146,PVDD=15V) 100 95 90 85 80 75 70 65 60 55 50 0 5 10 15 20 Power [W] 25
30
Gain [dBV]
20 Lch Rch
10
Efficiency [%]
4 8 30
0 10 100 1000 FREQ [Hz] 10000 100000
Power vs Efficiency(YDA146,PVDD=12V) 100 95 90 85 80 75 70 65 60 55 50 0 5 10 Power [W] 15
40 35 Max Power [W] 30 25 20 15 10 5 0 5
PVDD VS Max-Power (YDA146) 4 THD+N=1% 4 THD+N=10% 8 THD+N=1% 8 THD+N=10%
Efficiency [%]
4 8 20
10
PVDD [V]
15
20
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Power Dissipation vs Output Power (YDA146 stereo)
6 Power Dissipation [W] 5 4 3 2 1 0 0 2 4 6 8 Output Power [W] 10 12
Power Dissipation vs Output Power (YDA146 stereo) 6 Power Dissipation [W] 5 4 3 2 1 0 0 2 4 6 8 10 12 14 Output Power [W] 16 18 20
12V_8_25 12V_8_70
15V_8_25 15V_8_70
Power Dissipation vs Output Power (YDA146 stereo) 8
Power Dissipation vs Output Power (YDA146 stereo) 8 Power Dissipation [W]
Power Dissipation [W]
6 4 2 0 0
12V_4_25 12V_4_70
6 4 2 0
15V_4_25 15V_4_70
2
4
6
8 10 12 14 Output Power [W]
16
18
20
0
2
4
6
8 10 12 14 Output Power [W]
16
18
20
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CATALOG No.:LSI-4DA146A51
YDA146
Package Outline
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YDA146
Notice
The specifications of this product are subject to improvement changes without prior notice.

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