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HN27C101AG Series HN27C301AG Series
131072-word x 8-bit CMOS UV Erasable and Programmable ROM
ADE-203Rev. 0.0 Dec. 1, 1995
Description
The Hitachi HN27C101AG/HN27C301AG is a 1-Mbit ultraviolet erasable and electrically programmable ROM. This device is packaged in a 32-pin dual-in-line package with transparent lid. The transparent lid allows the memory content to be erased with ultraviolet light, whereby a new pattern can then be written into the device.
Features
* Single power supply: +5 V 5% (HN27C101AG-10/HN27C301AG-10) +5 V 10% (HN27C101AG/HN27C301AG-12/15/17/20/ 25) Fast high-reliability programming mode and fast high-reliability page programming mode - Programming voltage: +12.5 V DC - Fast high-reliability page programming: 14 sec typ High speed inputs and outputs TTL compatible during both read and program modes Low power dissipation: 50 mW/MHz typ (active) 5 W typ (standby) Pin arrangement : 32-pin JEDEC standard (HN27C101AG) : replaceable 32 pin MASK ROM (HN27C301AG) Device identifier mode: manufacturer code and device code Fully compatible with HN27C101G/ HN27C301G series
*
* * * * *
HN27C101AG/HN27C301AG Series
Ordering Information
Type No. HN27C101AG-10 HN27C101AG-12 HN27C101AG-15 HN27C101AG-17 HN27C101AG-20 HN27C101AG-25 HN27C301AG-10 HN27C301AG-12 HN27C301AG-15 HN27C301AG-17 HN27C301AG-20 HN27C301AG-25 Access Time 100 ns 120 ns 150 ns 170 ns 200 ns 250 ns 100 ns 120 ns 150 ns 170 ns 200 ns 250 ns Package 600-mil 32-pin cerdip (DG-32)
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HN27C101AG/HN27C301AG Series
Pin Arrangement
HN27C101AG Series HN27C301AG Series
VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (Top view)
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VCC PGM NC A14 A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3
VPP OE A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (Top view)
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VCC PGM NC A14 A13 A8 A9 A11 A16 A10 CE I/O7 I/O6 I/O5 I/O4 I/O3
Pin Description
Pin Name A0 - A16 I/O0 - I/O7 CE OE VCC VPP VSS PGM NC Function Address Input/output Chip enable Output enable Power supply Programming power supply Ground Programming enable No connection
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HN27C101AG/HN27C301AG Series
Block Diagram
A5 A9 A12 A16 X-Decoder 1024 x 1024 Memory Matrix
I/O0 I/O7
Input Data Control
Y-Gating Y-Decoder
CE OE PGM VCC VPP VSS H H : High Threshold Inverter A0 - A4 A10, A11
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HN27C101AG/HN27C301AG Series
Mode Selection
Mode HN27C101AG HN27C301AG Read Output disable Standby Program Program verify Page data latch Page program Program inhibit CE (22) (22) VIL VIL VIH VIL VIL VIH VIH VIL VIL VIH VIH Identifier VIL Notes: 1. X: Don't care 2. VH : 12.0 V 0.5 V OE (24) (2) VIL VIH X VIH VIL VIL VIH VIL VIH VIL VIH VIL PGM (31) (31) VIH VIH X VIL VIH VIH VIL VIL VIH VIL VIH VIH VH VCC VCC Code A9 (26) (26) X X X X X X X X VPP (1) (1) VCC VCC VCC VPP VPP VPP VPP VPP VCC (32) (32) VCC VCC VCC VCC VCC VCC VCC VCC I/O (13 - 15, 17 - 21) (13 - 15, 17 - 21) Dout High-Z High-Z Din Dout Din High-Z High-Z
Absolute Maximum Ratings
Parameter All input and output voltages* A9 input voltage* VPP voltage*
1 1 1 1
Symbol Vin, Vout VID VPP VCC Topr Tstg Tbias
Value -0.6* to +7.0 -0.6* to +13.5 -0.6 to +13.5 -0.6 to +7.0 0 to +70 -65 to +125 -10 to +80
2 2
Unit V V V V C C C
VCC voltage*
Operating temperature range Storage temperature range Storage temperature range under bias
Notes: 1. Relative to VSS 2. Vin, Vout and VID min = -1.0 V for pulse width 50 ns
Capacitance (Ta = 25C, f = 1 MHz)
Parameter Input capacitance Output capacitance Symbol Cin Cout Min -- -- Typ -- -- Max 10 15 Unit pF pF Test Conditions Vin = 0 V Vout = 0 V
5
HN27C101AG/HN27C301AG Series
Read Operation
DC Characteristics (V CC = 5 V 5%, VPP = VCC, Ta = 0 to +70C) (HN27C101AG/HN27C301AG-10) (V CC = 5 V 10%, VPP = VCC, Ta = 0 to +70C) (HN27C101AG/HN27C301AG-12/15/17/20/25)
Parameter Input leakage current Output leakage current VPP current Standby V CC current Symbol I LI I LO I PP1 I SB1 I SB2 Operating VCC current I CC1 I CC2 Min -- -- -- -- -- -- -- -- Input low voltage Input high voltage Output low voltage Output high voltage VIL VIH VOL VOH -0.3* 2.2 -- 2.4
1
Typ -- -- 1 -- 1 -- -- -- -- -- -- --
Max 2 2 20 1 20 30 30 50 0.8 VCC + 1.0*2 0.45 -- --
Unit A A A mA A mA mA mA V V V V V
Test Conditions Vin = 0 V to VCC Vout = 0 V to VCC VPP = 5.5 V CE = VIH CE = VCC 0.3 V CE = VIL, Iout = 0 mA f = 5 MHz, Iout = 0 mA f = 10 MHz, Iout = 0 mA
I OL = 2.1 mA I OH = -1 mA I OH = -0.1 mA
VCC - 0.7 --
Notes: 1. VIL min = -1.0 V for pulse width 50 ns 2. VIH max = VCC +1.5 V for pulse width 20 ns If V IH is over the specified maximum value, read operation cannot be guaranteed.
6
HN27C101AG/HN27C301AG Series
AC Characteristics (V CC = 5 V 5%, VPP = VCC, Ta = 0 to +70C) (HN27C101AG/HN27C301AG-10) (V CC = 5 V 10%, VPP = VCC, Ta = 0 to +70C) (HN27C101AG/HN27C301AG-12/15/17/20/25) Test Conditions * * * * Input pulse levels: 0.45 V to 2.4 V Input rise and fall time: 20 ns Output load: 1 TTL gate +100 pF Reference levels for measuring timing: Inputs; 0.8 V and 2.0 V Outputs; 0.8 V and 2.0 V
HN27C101AG/HN27C301AG -10 Parameter -12 -15 -17 -20 -25 Test CE = OE = VIL OE = VIL CE = VIL CE = VIL CE = OE = VIL
Symbol Min Max Min Max Min Max Min Max Min Max Min Max Unit Conditions -- -- -- 0 0 100 -- 100 -- 60 50 -- -- 0 0 120 -- 120 -- 60 50 -- -- 0 0 150 -- 150 -- 70 50 -- -- 0 0 170 -- 170 -- 70 50 -- -- 0 0 200 -- 200 -- 70 50 -- -- 0 0 250 ns 250 ns 100 ns 60 -- ns ns
Address to t ACC output delay CE to output t CE delay OE to output t OE delay OE high to output float Address to output hold t DF t OH
Note: t DF is defined as the time at which the output achieves the open circuit condition and data is no longer driven.
7
HN27C101AG/HN27C301AG Series
Read Timing Waveform
Address
CE
Standby Mode tCE
Active Mode
Standby Mode
OE tOE tACC Data Out Data Out Valid tOH tDF
8
HN27C101AG/HN27C301AG Series
Fast High-Reliability Programming
This device can be applied the programming algorithm shown in following flowchart. This algorithm allows to obtain faster programming time without any voltage stress to the device nor deterioration in reliability of programmed data.
START SET PROG./VERIFY MODE VPP = 12.5 0.3 V, VCC = 6.0 0.25 V Address = 0 n=0 n+1 n
Program tOPW = 0.2 ms 5% Address + 1 Address VERIFY NOGO NO
GO Program tOPW = 0.2n ms NO LAST Address?
n = 25 YES
YES SET READ MODE VCC = 5.0 0.25 V, VPP = VCC READ All Address GO END FAIL NOGO
Fast High-Reliability Programming Flowchart
9
HN27C101AG/HN27C301AG Series
DC Characteristics (Ta = 25 C 5C, VCC = 6 V 0.25 V, VPP = 12.5 V 0.3 V)
Parameter Input leakage current VPP supply current Operating VCC current Input low level Input high level Output low voltage during verify Output high voltage during verify Symbol I LI I PP I CC VIL VIH VOL VOH Min -- -- -- -0.1* 2.2 -- 2.4
5
Typ -- -- -- -- -- -- --
Max 2 40 30 0.8
6
Unit A mA mA V
Test Conditions Vin = 0 V to VCC CE = PGM = VIL
VCC + 0.5* V 0.45 -- V V I OL = 2.1 mA I OH = -400 A
Notes: 1. VCC must be applied simultaneously or before VPP and removed simultaneously or after V PP . 2. VPP must not exceed 13.5 V including overshoot. 3. An influence may be had upon device reliability if the device is installed or removed while VPP = 12.5 V. 4. Do not alter VPP either V IL to 12.5 V or 12.5 V to VIL when CE = Low. 5. VIL min = -0.6 V for pulse width 20 ns 6. If V IH is over the specified maximum value, programming operation cannot be guaranteed.
10
HN27C101AG/HN27C301AG Series
AC Characteristics (Ta = 25C 5C, VCC = 6 V 0.25 V, VPP = 12.5 V 0.3 V) Test Conditions * * * Input pulse levels: 0.45 V to 2.4 V Input rise and fall time: 20 ns Reference levels for measuring timing: Inputs; 0.8 V and 2.0 V Outputs; 0.8 V and 2.0 V
Symbol t AS t OES t DS t AH t DH t DF * t VPS t VCS t PW
1
Parameter Address setup time OE setup time Data setup time Address hold time Data hold time OE to output float delay VPP setup time VCC setup time PGM initial programming pulse width CE setup time Data valid from OE
Min 2 2 2 0 2 0 2 2 0.19 0.19 2 0
Typ -- -- -- -- -- -- -- -- 0.2 -- -- --
Max -- -- -- -- -- 130 -- -- 0.21 5.25 -- 150
Unit s s s s s ns s s ms ms s ns
Test Conditions
PGM overprogramming pulse width t OPW* 2 t CES t OE
Notes: 1. t DF is defined as the time at which the output achieves the open circuit condition and data is no longer driven. 2. Refer to the programming flowchart for tOPW.
11
HN27C101AG/HN27C301AG Series
Fast High-Reliability Programming Timing Waveform
Program Address tAS
Program Verify
tAH
Data tDS VPP VCC tVPS VCC+1 VCC tVCS
Data In Stable tDH
Data Out Valid tDF
VPP
VCC
CE
tCES
PGM tPW OE tOES tOE
12
HN27C101AG/HN27C301AG Series
Fast High-Reliability Page Programming
This device can be applied the high performance page programming algorithm shown in following flowchart. This algorithm allows to obtain faster programming time without any voltage stress to the device nor deterioration in reliability of programmed data.
START SET PAGE PROG. LATCH MODE VPP = 12.5 0.3 V, VCC = 6.0 0.25 V Address = 0 A n=0 Latch Address + 1 Address Address + 1 Address Latch Address + 1 Address B Latch Address + 1 Address Latch A NO B n+1 n NO n = 25 YES
SET PAGE PROG./ VERIFY MODE VPP = 12.5 0.3 V, VCC = 6.0 0.25 V Program tPW = 0.2 ms 5% VERIFY NOGO
GO Program tOPW = 0.2n ms LAST Address?
YES SET READ MODE VCC = 5.0 0.25 V, VPP = VCC READ All Address GO END FAIL NOGO
Fast High-Reliability Page Programming Flowchart
13
HN27C101AG/HN27C301AG Series
DC Characteristics (Ta = 25 C 5C, VCC = 6 V 0.25 V, VPP = 12.5 V 0.3 V)
Parameter Input leakage current VPP supply current Operating VCC current Input low level Input high level Output low voltage during verify Symbol Min I LI I PP I CC VIL VIH VOL -- -- -- -0.1* 2.2 -- 2.4
5
Typ -- -- -- -- -- -- --
Max 2 50 30 0.8
6
Unit A mA mA V
Test Conditions Vin = 0 V to VCC CE = OE= VIH, PGM = VIL
VCC + 0.5* V 0.45 -- V V I OL = 2.1 mA I OH = -400 A
Output high voltage during verify VOH
Notes: 1. VCC must be applied simultaneously or before VPP and removed simultaneously or after V PP . 2. VPP must not exceed 13.5 V including overshoot. 3. An influence may be had upon device reliability if the device is installed or removed while VPP = 12.5 V. 4. Do not alter VPP either V IL to 12.5 V or 12.5 V to VIL when CE = Low. 5. VIL min = -0.6 V for pulse width 20 ns 6. If V IH is over the specified maximum value, programming operation cannot be guaranteed.
14
HN27C101AG/HN27C301AG Series
AC Characteristics (Ta = 25C 5C, VCC = 6 V 0.25 V, VPP = 12.5 V 0.3 V) Test conditions * * * Input pulse levels: 0.45 V to 2.4 V Input rise and fall time: 20 ns Reference levels for measuring timing: Inputs; 0.8 V and 2.0 V Outputs; 0.8 V and 2.0 V
Symbol t AS t OES t DS t AH t AHL Data hold time OE to output float delay VPP setup time VCC setup time PGM initial programming pulse width PGM overprogramming pulse width CE setup time Data valid from OE OE pulse width during data latch PGM setup time CE hold time OE hold time t DH t DF * t VPS t VCS t PW t OPW* t CES t OE t LW t PGMS t CEH t OEH
2 1
Parameter Address setup time OE setup time Data setup time Address hold time
Min 2 2 2 0 2 2 0 2 2 0.19 0.19 2 0 1 2 2 2
Typ -- -- -- -- -- -- -- -- -- 0.2 -- -- -- -- -- -- --
Max -- -- -- -- -- -- 130 -- -- 0.21 5.25 -- 150 -- -- -- --
Unit s s s s s s ns s s ms ms s ns s s s s
Notes: 1. t DF is defined as the time at which the output achieves the open circuit condition and data is no longer driven. 2. Refer to the programming flowchart for tOPW.
15
HN27C101AG/HN27C301AG Series
Fast High-Reliability Page Programming Timing Waveform
Page data latch A2 to A16 tAS A0, A1 tDS Data Data in stable VPP VCC VPP VCC VCC+1 VCC tVPS tVCS tDH tAHL
Page program
program verify
tAH
tPGMS
tOE
tDF
Data out valid
tCES
tOEH
CE tCEH tPW PGM tOES OE tLW
Erase
Erasure of this device is performed by exposure to ultraviolet light of 2537 A and all the output data are changed to 1" after this erasure procedure. The minimum integrated dose (i.e. UV intensity x exposure time) for erasure is 15 W. sec/cm2.
16
HN27C101AG/HN27C301AG Series
Mode Description
Device Identifier Mode The device identifier mode allows the reading out of binary codes that identify manufacturer and type of device, from outputs of EPROM. By this mode, the device will be automatically matched its own corresponding programming algorithm, using programming equipment. HN27C101AG Identifier Code
A0 (12) VIL VIH A9 (26) VH VH I/O7 (21) 0 0 I/O6 (20) 0 0 I/O5 (19) 0 1 I/O4 (18) 0 1 I/O3 (17) 0 1 I/O2 (15) 1 0 I/O1 (14) 1 0 I/O0 (13) 1 0
Identifier Manufacturer code Device code
Hex Data 07 38
HN27C301AG Identifier Code
A0 (12) VIL VIH A9 (26) VH VH I/O7 (21) 0 1 I/O6 (20) 0 0 I/O5 (19) 0 1 I/O4 (18) 0 1 I/O3 (17) 0 1 I/O2 (15) 1 0 I/O1 (14) 1 0 I/O0 (13) 1 1
Identifier Manufacturer code Device code
Hex Data 07 B9
Notes: 1. VH = 12.0 V 0.5 V 2. A1-A8, A10-A16, CE, OE = VIL, PGM = VIH
17
HN27C101AG/HN27C301AG Series
Package Dimensions
HN27C101AG/HN27C301AG Series (DG-32)
41.91 43.18 Max
Unit: mm
32
17
8
.89
1
1.32 2.54 Max
16 15.24 0.38 Min 2.54 Min 5.89 Max
14.66 15.51 Max
2.54 0.25
0.48 0.10
0.11 0.25 + 0.05 -
0 - 10
18

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