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| www..com SH67K93 24K 4-bit Micro-Controller with LCD Driver Feature - 50 Seg X 8 Com (1/8 duty 1/4 bias or 1/5 bias) SH6610D-Based Single-Chip 4-bit Micro-Controller Oscillator (Code Option) ROM: 24K X 16 bits OSC RAM: 5784 X 4 bits - Crystal Oscillator 32.768kHz - 48 bytes System Control Register - RC Oscillator: 262kHz - 5536 bytes Data Memory OSCX - 200 bytes LCD RAM - Ceramic Resonator 3.58MHz/Crystal Oscillator 3.579545MHz Operation Voltage: 2.4V - 3.6V - RC oscillator 1.8MHz 23 CMOS Bi-directional I/O pads (15 shared with LCD Instruction Cycle Time Segments) - 122.07s for 32.768kHz crystal 12 Segments of LCD Shared with Scan Output port - 15.27s for 262 kHz RC 8-Level Stack (including interrupts) - 2.22s for 1.8 MHz RC Two 8-bit Timer/Counter - 1.1s for 3.58MHz ceramic Powerful Interrupt Sources Two Low Power Operation Modes: HALT and STOP - External Interrupt (PORTA.0 Rising/Falling edge) .com Warm-up Timer for Power-On Reset (POR) - Timer0 Interrupt Watchdog Timer - Timer1 Interrupt - External Interrupts: PORTB, PORTC and PORTD DTMF/FSK Generator (Falling edge) Available In CHIP FORM LCD Driver - 50 Seg X 16 Com (1/16 duty 1/4 bias or 1/5 bias) DataShee General Description SH67K93 is a single-chip 4-bit micro-controller. The device integrates a SH6610D CPU core, RAM, ROM, Timer, LCD driver, I/O port, DTMF/FSK Generator and FSK/DTMF/CAS decoder. This chip builds in a dual-oscillator to enhance the total chip performance. The device is suitable for TypeI/II CID cord phone. .com 1 DataSheet 4 U .com V1.0 www..com SH67K93 Pad Configuration SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 COM16 COM15 COM14 COM13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 COM8 COM7 COM6 COM5 COM4 COM3 SH67K93 60 59 58 57 56 55 t4U.com COM12 COM11 COM10 COM9 C1+ C1VP2 VP1 VDD TIP DataShee .com 54 53 52 51 50 AVDD 32 33 34 35 36 OSCXI OSCXO OSCI OSCO GND 37 49 48 38 39 40 41 42 43 44 45 46 47 PORTA2 PORTA1 PORTA0 PORTB3 PORTB2 PORTB1 PORTA3 PORTB0 COM1 COM2 25 26 27 28 29 30 31 CASTIP OPOUT DTMF RING RESET TEST .com B1 2 DataSheet 4 U .com B0 www..com SH67K93 Pin Configuration SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 COM5 COM7 COM6 COM8 COM4 COM3 COM2 NC NC NC 80 79 78 77 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 COM1 PORTB0 PORTB1 PORTB2 PORTB3 PORTA0 PORTA1 PORTA2 PORTA3 GND OSCO OSCI OSCXO OSCXI AV DD TEST RESET DTMF OPOUT CASTIP 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 NC SH67K93 42 41 40 39 38 37 36 35 34 33 32 31 t4U.com SEG13 SEG12 DataShee .com SEG2 SEG1 COM16 COM15 COM14 COM13 COM12 COM11 SEG11 SEG10 SEG3 COM10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 COM9 VP2 VP1 C1+ VDD .com 3 DataSheet 4 U .com RING NC NC NC C1- NC TIP www..com SH67K93 Block Diagram ROM (24K X 16) RAM (5.6K X 4) 8-BIT TIMER0 8-BIT TIMER1 PORTB PORTA & EXTERNAL INT CPU ROM (6K X 8) TEST RESET VDD AVDD OSCI OSC OSCX OSCO OSCXI OSCXO PORTB[0:3] PORTA.0/INT0 PORTA.1 PORTA.2 PORTA.3 Common Driver COM[1:16] SEG[1:23] SEG[24:35]/Scan Output Port SEG[36:38]/PORTF SEG[39:42]/PORTE SEG[43:46]/PORTD SEG[47:50]/PORTC DTMF LCD RAM DTMF/FSK Generator Segment Driver t4U.com GND LCD Voltage FSK/DTMF/CAS Generaor & Bias decoder .com DataShee AGCIN (PORTB.0) FILIN (PORTB.2) FILOUT (PORTB.1) OPOUT CASTIP TIP RING VP1 .com 4 DataSheet 4 U .com C1- C1+ VP2 www..com SH67K93 Pad Description (Total 92 pads) Pad No. 24 32 37 30 31 36 35 34 33 38 - 41 Pin No. (QFP100) 26 36 41 34 35 40 39 38 37 42 - 45 Designation VDD AVDD GND RESET TEST OSCO OSCI OSCXO OSCXI PORTA3 - 0 I/O P P P I I O I O I I/O Digital Power supply Analog Power supply Ground pad Reset pad (internal floating, connection for user) Test Pad, internal pull-low (no connection for user) Low Oscillator output pad (32.768kHz crystal or 262kHz RC) Low Oscillator input pad (32.768kHz crystal or 262kHz RC) High Oscillator output pad (3.58MHz ceramic/3.579545MHz crystal or 1.8MHz RC) High Oscillator input pad (3.58MHz ceramic/3.579545MHz crystal or 1.8MHz RC) Bit programmable I/O PORTA.0 shared with INT0 PORTA.3 had powerful sink capacity to driver LED directly Bit programmable I/O, Vector interrupt ( INT1 ) For the caller ID application: PORTB.2 is shared with FILIN input pad PORTB.1 is shared with FILOUT output pad PORTB.0 is shared with AGCIN input pad .com When PORTB0 - 2 are shared, the interrupt function for PORTB0 - 3 are disable and the pull-high resistor setting for PORTB0 - 2 are disable Bit programmable I/O, Vector interrupt ( INT1 ) Segment50 - 47 shared with PORTC Bit programmable I/O, Vector interrupt ( INT1 ) Segment46 - 43 shared with PORTD Bit programmable I/O Segment42 - 39 shared with PORTE Bit programmable I/O Segment38 - 36 shared with PORTF Segment signal for LCD display/scan output port Segment signal output for LCD display Common signal output for LCD display Connect with external components of LCD power Connected with TIP side & Ring side for twisted pair The output pad of DTMF/FSK Generator CAS tone input pad Pre-amplifier output Description t4U.com 42 - 45 46 - 49 PORTB.3 PORTB.2/ FILIN PORTB.1/ FILOUT PORTB.0/ AGCIN PORTC3 - 0 /Segment50 - 47 PORTD3 - 0 /Segment46 - 43 PORTE3 - 0 /Segment42 - 39 PORTF2 - 0 /Segment38 - 36 Segment35 - 24 Segment23 - 1 COM1 - COM16 C1+, C1-, VP1, VP2 TIP, RING DTMF/FSK CASTIP OPOUT I/O DataShee 54 - 57 58 - 61 62 - 65 66 - 68 69 - 80 81 - 11 46 - 53 19 - 12 20, 21, 23, 22 25, 26 29 27 28 60 - 63 64 - 67 68 - 71 72 - 74 75 - 76 79 - 88 89 - 1 3 - 13 50 - 51, 54 - 59, 21 - 14 22, 23, 25, 24 29, 30 33 31 32 I/O I/O I/O I/O O O O I I O I O .com 5 DataSheet 4 U .com www..com SH67K93 Functional Descriptions 1. CPU 1.4. Table Branch Register (TBR) The CPU contains the following functional blocks: Program Counter (PC), Arithmetic Logic Unit (ALU), Carry Flag (CY), Table Data can be stored in program memory and Accumulator, Table Branch Register, Data Pointer (INX, referenced by using Table Branch (TJMP) and Return DPH, DPM, and DPL) and Stacks. Constant (RTNW) instructions. The TBR and AC are placed 1.1. PC by an offset address in program ROM. TJMP instruction branch into address ((PC11 - PC8) X (28) + (TBR, AC)). The The PC is used for ROM addressing consisting of 12-bit: address is determined by RTNW to return look-up value into Page Register (PC11), and Ripple Carry Counter (PC10, (TBR, AC). ROM code bit7-bit4 is placed into TBR and PC9, PC8, PC7, PC6, PC5, PC4, PC3, PC2, PC1, PC0). bit3-bit0 into AC. The program counter is loaded with data corresponding to 1.5. Data Pointer each instruction. The unconditional jump instruction (JMP) can be set at 1-bit page register for higher than 2K. The Data Pointer can indirectly address data memory. The program counter can only address 4K program ROM. Pointer address is located in register DPH (3-bit), DPM (Refer to the ROM description). (3-bit) and DPL (4-bit). The addressing range can have 3FFH locations. Pseudo index address (INX) is used to read 1.2. ALU and CY or write Data memory, then RAM address bit9 - bit0 which The ALU performs arithmetic and logic operations, provides comes from DPH, DPM and DPL. the following functions: 1.6. Stack Binary addition/subtraction (ADC, SBC, ADD, SUB, ADI, SBI) Decimal adjustments for addition/subtraction (DAA, DAS) The stack is a group of registers used to save the contents of Logic operations (AND, EOR, OR, ANDIM, EORIM, ORIM) CY & PC (11-0) sequentially with each subroutine call or Decisions (BA0, BA1, BA2, BA3, BAZ, BNZ, BC, BNC) interrupt. The MSB is saved for CY and it is organized into 13 Logic Shift (SHR) bits X 8 levels. The stack is operated on a first-in, last-out basis and returned sequentially to the PC with the return The Carry Flag (CY) holds the ALU overflow that generates instructions (RTNI/RTNW). the arithmetic operation. During an interrupt service or CALL instruction, the carry flag is pushed into the stack and Note: .com recovered from the stack by the RTNI instruction. It is The stack nesting includes both subroutine calls and unaffected by the RTNW instruction. interrupts requests. The maximum allowed for subroutine 1.3. Accumulator (AC) calls and interrupts are 8 levels. If the number of calls and interrupt requests exceed 8, then the bottom of stack will be The accumulator is a 4-bit register holding the results of the shifted out, that program execution may enter an abnormal arithmetic logic unit. In conjunction with the ALU, data is state. transferred between the accumulator and system register, or data memory can be performed. t4U.com DataShee .com 6 DataSheet 4 U .com www..com SH67K93 2. RAM Built-in RAM contains general-purpose data memory and system register. Because of its static nature, the RAM can keep data after the CPU enters STOP or HALT status. 2.1. RAM Addressing Data memory and system register can be accessed in one instruction by direct addressing. The following is the memory allocation map: System register and I/O: $000 - $02F Data memory: $030 - $2FF $3C8 - $3FF $430 - $7FF $830 - $BFF $C30 - $FFF $1030 - $13FF $1430 - $1787 (Total 5536 X 4 bits) Reserved: $5D0- $5FF LCD RAM space: $300 - $3C7(200 X 4 bits) RAM Mapping $000 - $02F $400 - $42F $800 - $82F System Register t4U.com $C00 - $C2F $1000 - $102F $1400 - $142F $030 - $2FF $300 - $3C7 $3C8 - $3FF $430 - $7FF $830 - $BFF $C30 - $FFF $1030 - $13FF $1430 - $1787 Note: $400 - $42F, $800 - $82F, $C00 - $C2F, $1000 - $102F, $1400 - $142F, $1800 - $182F and $000 - $02F refer to the same System Register. Data Memory Data Memory LCD Display memory DataShee .com .com 7 DataSheet 4 U .com www..com SH67K93 RAM bank table: (RAMBNK: System Register RAMBNK2 - 0) RAMBNK = 000 RAMBNK = 001 RAMBNK = 010 RAMBNK = 011 RAMBNK = 100 RAMBNK = 101 Bank 0 B = 000 Bank 8 B = 000 Bank 16 B = 000 Bank 24 B = 000 Bank 32 B = 000 Bank 40 B = 000 Bank 1 B = 001 Bank 9 B = 001 Bank 17 B = 001 Bank 25 B = 001 Bank 33 B = 001 Bank 41 B = 001 Bank 2 B = 010 Bank 10 B = 010 Bank 18 B = 010 Bank 26 B = 010 Bank 34 B = 010 Bank 42 B = 010 Bank 3 B = 011 Bank 11 B = 011 Bank 19 B = 011 Bank 27 B = 011 Bank 35 B = 011 Bank 43 B = 011 Bank 4 B = 100 Bank 12 B = 100 Bank 20 B = 100 Bank 28 B = 100 Bank 36 B = 100 Bank 44 B = 100 Bank 5 B = 101 Bank 13 B = 101 Bank 21 B = 101 Bank 29 B = 101 Bank 37 B = 101 Bank 45 B = 101 Bank 6 B = 110 Bank 14 B = 110 Bank 22 B = 110 Bank 30 B = 110 Bank 38 B = 110 Bank 46 B = 110 Bank 7 B = 111 Bank 15 B = 111 Bank 23 B = 111 Bank 31 B = 111 Bank 39 B = 111 Bank 47 B = 111 $030 - $07F $080 - $0FF $100 - $17F $180 - $1FF $200 - $27F $280 - $2FF $300 - $37F $380 - $3FF $430 - $47F $480 - $4FF $500 - $57F $580 - $5FF $600 - $67F $680 - $6FF $700 - $77F $780 - $7FF $830 - $87F $880 - $8FF $900 - $97F $980 - $9FF $A00 - $A7F $A80 - $AFF $B00 - $B7F $B80 - $BFF $C30 - $C7F $C80 - $CFF $D00 - $D7F $D80 - $DFF $E00 - $E7F $E80 - $EFF $F00 - $F7F $F80 - $FFF $1030 - $107F $1080 - $10FF $1100 - $117F $1180 - $11FF $1200 - $127F $1280 - $12FF $1300 - $137F $1380 - $13FF $1430 - $147F $1480 - $14FF $1500 - $157F $1580 - $15FF $1600 - $167F $1680 - $16FF $1700 - $177F $1780 - $1787 t4U.com DataShee .com .com 8 DataSheet 4 U .com www..com SH67K93 2.2 Configuration of System Register Address $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C $0D $0E $0F $10 $11 $12 $13 $14 $15 Bit 3 IEX0 IRQEX0 TM0.3 TM1.3 TL0L.3 TC0L.3 TL0H.3 TC0H.3 TL1L.3 TC1L.3 TL1H.3 TC1H.3 PA.3 PB.3 PC.3 PD.3 PE.3 TBR.3 INX.3 DPL3 PUMP_ON LCDM3 PB2 - 0/CID Bit 2 IET0 IRQT0 TM0.2 TM1.2 TL0L.2 TC0L.2 TL0H.2 TC0H.2 TL1L.2 TC1L.2 TL1H.2 TC1H.2 PA.2 PB.2 PC.2 PD.2 PE.2 PF.2 TBR.2 INX.2 DPL2 DPM.2 DPH.2 LCDON LCDM2 O/S2 Bit 1 IET1 IRQT1 TM0.1 TM1.1 TL0L.1 TC0L.1 TL0H.1 TC0H.1 TL1L.1 TC1L.1 TL1H.1 TC1H.1 PA.1 PB.1 PC.1 PD.1 PE.1 PF.1 TBR.1 INX1 DPL1 DPM.1 DPH.1 BIAS LCDM1 O/S1 Bit 0 IEP IRQP TM0.0 TM1.0 TL0L.0 TC0L.0 TL0H.0 TC0H.0 TL1L.0 TC1L.0 TL1H.0 TC1H.0 PA.0 PB.0 PC.0 PD.0 PF.0 TBR.0 INX.0 DPL0 DPM.0 DPH.0 DUTY LCDM0 O/S0 R/W R/W R/W R/W R/W W R W R W R W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Interrupt enable flags Interrupt request flags Timer0 mode register Timer1 mode register Timer0 load low nibble Counter0 low nibble Timer0 load high nibble Counter0 high nibble Timer1 load low nibble Counter1 low nibble Timer1 load high nibble Counter1 high nibble PORTA PORTB PORTC PORTD PORTF Table branch register Index register (INX) Data pointer for INX low nibble Data pointer for INX middle nibble Data pointer for INX high nibble Bit0: Select LCD DUTY (1/16 or 1/8) Bit1: Select LCD Bias (1/4 or 1/5 Bias) Bit2: LCD on/off switch Bit3: LCD voltage Pump on Lcd contrast adjustment Bit2 - 0: Set LCD segment / I/O Port mode Bit3: PORTB2 - 0 shared with Caller ID control bit Bit3: Pull-high/low resistor control bit of PORTA0 0: Pull-high/low resistor disable 1: Pull-high/low resistor enable Bit2: Pull-low resistor or pull-high resistor selection control bit of PORTA0 0: Pull- high resistor enable, Pull-low resistor disable 1: Pull- high resistor disable, Pull-low resistor enable Bit1: Interrupt mode of FSK recevier (one source of INT0) 0: Falling edge interrupt of FSK receiver 1: Rising edge interrupt of FSK receiver Bit0: Interrupt mode of PORTA0 (one source of INT0) 0: Falling edge interrupt of PORTA0 1: Rising edge interrupt of PORTA0 Remarks t4U.com DataShee PE.0 R/W PORTE .com $16 PA0_PEN PL/PH INT0 _FSKIN0 INT0 _PA0 R/W .com 9 DataSheet 4 U .com www..com SH67K93 Configuration of System Register (Continued) Address Bit 3 Bit 2 Bit 1 Bit 0 R/W Remarks IRQ_PA0: the interrupt flag of the PORTA0 IRQ_FSKIN: the interrupt flag of the FSK CMP IRQ_FSKTX: the interrupt flag of the FSK generator after a FSK data is transmitted FSKIN_STAT: the status bit of FSKIN level 1: the source of FSKIN is high level 0: the source of FSKIN is low level Set PORTA to be output or input mode Set PORTB to be output or input mode Set PORTC to be output or input mode Set PORTD to be output or input mode Set PORTE to be output or input mode Set PORTF to be output or input mode Bit3: Port pull-High resistor control Bit2: Heavy load mode Bit1 CPU clocks select (1: OSCX/0: OSC) Bit0: Turn on OSCX oscillator $17 FSKIN_ STAT IRQ_ FSKTX IRQ_ FSKIN IRQ_PA0 R/W $18 $19 $1A $1B $1C $1D $1E PACR.3 PBCR.3 PCCR.3 PDCR.3 PECR.3 PPULL ROM BNK3 RDT.3 RDT.7 RDT.11 RDT.15 PACR.2 PBCR.2 PCCR.2 PDCR.2 PECR.2 PFCR.2 HLM ROM BNK2 RAM BNK2 RDT.2 RDT.6 RDT.10 RDT.14 PACR.1 PBCR.1 PCCR.1 PDCR.1 PECR.1 PFCR.1 OXM ROM BNK1 RAM BNK1 RDT.1 RDT.5 RDT.9 RDT.13 PACR.0 PBCR.0 PCCR.0 PDCR.0 PECR.0 PFCR.0 OXON R/W R/W R/W R/W R/W R/W R/W t4U.com $1F $20 $21 $22 $23 $24 ROM W ROM bank register BNK0 RAM W RAM bank register BNK0 .com RDT.0 RDT.4 RDT.8 RDT.12 R/W R/W R/W R/W Bit2 - 0: The number of data filter table Bit3: Flag indicate Digital filter calculation is finished. When DFL is off or calculation is finished, the flag is 1. 0: calculation is in process 1: calculation is finished DTMF/FSK control register ADCC: the flag while ADC convert finished Bit2 - 0: FSK control bits High nibble data of FSK Data to be transimitted Low nibble data of FSK Data to be transimitted/ Tone data register ROM Data table address / data register DataShee $25 DF_F DC2 DC1 DC0 R/W $26 FSK_ON FSK_ DTMF TGC_COL TGC_ROW R/W $27 ADCC R R/W FSK_MD FSK_PRE FSK_TXEN R/W R/W FSK_D6 FSK_D5 FSK_D4 R/W R/W $28 $29 FSK_D7 FSK_D3/ FSK_D2/ FSK_D1/ FSK_D0/ TGD3 TGD2 TGD1 TGD0 .com 10 DataSheet 4 U .com www..com SH67K93 Configuration of System Register (Continued) Address $2A $2B Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W W R R W W W Remarks CID interface control register AGC gain data ADC data register Bit3: Watchdog time-out flag bit (read operation to reset WDT) Bit2 - 0: Watchdog timer prescaler Bit3 - 2: the schmit-trigger voltage windows control bits Bit0: Set the segment35 - 24 as sacn output port or segment signal output for LCD 0: set Segment 35 - 24 as segment signal output for LCD 1: set Segment 35 - 24 as scan output port Bit1, 0: Bonding option (read only) AMP_ON AGC_ON DFIL_ON ADC_ON GCD3 ADCD3 WDT GCD2 ADCD2 WT2 GCD1 ADCD1 WT1 GCD0 ADCD0 WT0 $2C $2D CMPW1 CMPW0 - O/S3 R/W $2E - - B0 B1 R $2F CAS/ DTMF - - t4U.com Bit3: The DTMF/CAS decoder selected control bit 0: DTMF decoder 1: CAS decoder Bit0: The interrupt mode of FSK receiver control bit, when this INT0 R/W bit is set to 1, the bit of INT0_FSKIN0 is unused. _FSKIN1 0: the interrupt edge type of FSK receiver is set by INT0_FSKIN0 1: Dual edge interrupt mode (rising/falling edge) regardless of the bit of INT0_FSKIN0 .com DataShee .com 11 DataSheet 4 U .com www..com SH67K93 Configuration of System Register (Continued) Address $1740 $1741 $1742 $1743 $1744 $1745 $1746 $1747 $1748 $1749 $174A $174B $174C $174D $174E $174F Bit 3 D7 D3 D15 D11 D7 D3 D15 D11 D7 D3 D15 D11 D7 D3 D15 D11 D7 D3 D15 D11 D7 D3 D15 D11 D7 D3 D15 D11 D7 D3 D15 D11 D7 D3 D15 D11 Bit 2 D6 D2 D14 D10 D6 D2 D14 D10 D6 D2 D14 D10 D6 D2 D14 D10 D6 D2 D14 D10 D6 D2 D14 D10 D6 D2 D14 D10 D6 D2 D14 D10 D6 D2 D14 D10 Bit 1 D5 D1 D13 D9 D5 D1 D13 D9 D5 D1 D13 D9 D5 D1 D13 D9 D5 D1 D13 D9 D5 D1 D13 D9 D5 D1 D13 D9 D5 D1 D13 D9 D5 D1 D13 D9 Bit 0 D4 D0 D12 D8 D4 D0 D12 D8 D4 D0 D12 D8 D4 D0 D12 D8 D4 D0 D12 D8 D4 D0 D12 D8 D4 D0 D12 D8 D4 D0 D12 D8 D4 D0 D12 D8 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W FL3C/S: sum sin value of 852Hz Or FCAS2L/S: sum sin value of 4260Hz R/W .com R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W FH1R/S: sum sin value of 1209Hz FL4C/C: sum cos value of 941Hz Or FCAS2H/C: sum sin value of 5500Hz FL4C/S: sum sin value of 941Hz Or FCAS2H/S: sum sin value of 5500Hz FL3C/C: sum cos value of 852Hz Or FCAS2L/C: sum cos value of 4260Hz R/W FL2C/C: sum cos value of 770Hz Or FCAS1H/C: sum cos value of 2750Hz FL2C/S: sum sin value of 770Hz Or FCAS1H/S: sum sin value of 2750Hz FL1C/C: sum cos value of 697Hz Or FCAS1L/C: sum cos value of 2130Hz FL1C/S: sum sin value of 697Hz Or FCAS1L/S: sum sin value of 2130Hz Remarks t4U.com $1750 $1751 $1752 $1753 $1754 $1755 $1756 $1A57 $1758 $1759 $175A $175B $175C $175D $175E $175F $1760 $1761 $1762 $1763 DataShee .com 12 DataSheet 4 U .com www..com SH67K93 Configuration of System Register (Continued) Address $1764 $1765 $1766 $1767 $1768 $1769 $176A $176B $176C $176D $176E $176F $1770 $1771 $1772 $1773 Bit 3 D7 D3 D15 D11 D7 D3 D15 D11 D7 D3 D15 D11 D7 D3 D15 D11 D7 D3 D15 D11 D7 D3 D15 D11 D7 D3 D15 D11 DFTA11 DFTA7 DFTA3 D11 D7 D3 Bit 2 D6 D2 D14 D10 D6 D2 D14 D10 D6 D2 D14 D10 D6 D2 D14 D10 D6 D2 D14 D10 D6 D2 D14 D10 D6 D2 D14 D10 DFTA14 DFTA10 DFTA6 DFTA2 D10 D6 D2 Bit 1 D5 D1 D13 D9 D5 D1 D13 D9 D5 D1 D13 D9 D5 D1 D13 D9 D5 D1 D13 D9 D5 D1 D13 D9 D5 D1 D13 D9 DFTA13 DFTA9 DFTA5 DFTA1 D9 D5 D1 Bit 0 D4 D0 D12 D8 D4 D0 D12 D8 D4 D0 D12 D8 D4 D0 D12 D8 D4 D0 D12 D8 D4 D0 D12 D8 D4 D0 D12 D8 DFTA12 DFTA8 DFTA4 DFTA0 D8 D4 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W FH3R/C: .com sum cos value of 1477Hz R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Sample Dot-number register (12K sample rate) Digital filter data table start address FH4R/C: sum cos value of 1633Hz FH4R/S: sum sin value of 1633Hz R/W FH3R/S: sum sin value of 1477Hz FH2R/C: sum cos value of 1336Hz FH2R/S: sum sin value of 1336Hz Remarks FH1R/C: sum cos value of 1209Hz t4U.com $1774 $1775 $1776 $1777 $1778 $1779 $177A $177B $177C $177D $177E $177F $1780 $1781 $1782 $1783 $1784 $1785 $1786 DataShee .com 13 DataSheet 4 U .com www..com SH67K93 3. ROM The ROM can address 24576 Words X 16 bits of program area from $0000 to $5FFF. 3.1. Vector Address Area ($000 to $004) The program is sequentially executed. There is an area address $000 through $0004 that is reserved for a special interrupt service routine such as starting vector address. Address $000 $001 $002 $003 $004 Instruction JMP* JMP* JMP* JMP* JMP* Function Jump to RESET service routine Jump to INT0 service routine (PORTA.0/FSK IN/FSK Generator) Jump to Timer0 service routine Jump to Timer1 service routine Jump to INT1 service routine (PORTB, PORTC, PORTD) *JMP instruction can be replaced by any instruction. 3.2. Table Data Reference System Register Address $21 Bit 3 RDT.3 RDT.7 RDT.11 RDT.15 Bit 2 RDT.2 RDT.6 RDT.10 RDT.14 Bit 1 RDT.1 RDT.5 RDT.9 RDT.13 Bit 0 RDT.0 RDT.4 RDT.8 R/W R/W R/W R/W Remarks ROM Data table address/data register ROM Data table address/data register ROM Data table address/data register t4U.com $22 $23 $24 DataShee RDT.12 R/W ROM Data table address/data register .com The RDT register consists of a 16 bit write-only PC address load register (RDT.15- RDT.0) and a 16-bit read-only ROM table data read-out register (RDT.15 - RDT.0). To read out the ROM table data, users should write the ROM table address to RDT register first (high nibble first and then low nibble), after one instruction, users can read out the right data from RDT register. (Write lowest nibble of address into $21 will start the data read-out action). 3.3 Bank Switch Mapping Program Counter (PC11 - PC0) can only address 4K ROM Space. The bank switch technique is used to extend the CPU address space. The lower 2K of the CPU address space maps to the lower 2K of ROM space (BANK0). The upper 2K of the CPU address space maps to one of the 11 banks (BNK.3 - 0 = $00 - $0A) of the upper 22K of ROM. The bank switch mapping is as follows: CPU Address $000 - $7FF ROM Space BNK = $00 BNK = $01 BNK = $02 BNK = $03 BNK = $04 BNK = $05 BNK = $06 BNK = $07 0000 - 07FF 0000 - 07FF 0000 - 07FF 0000 - 07FF 0000 - 07FF 0000 - 07FF 0000 - 07FF 0000 - 07FF (BANK 0) (BANK 0) (BANK 0) (BANK 0) (BANK 0) (BANK 0) (BANK 0) (BANK 0) 0800 - 0FFF 1000 - 17FF 1800 - 1FFF 2000 - 27FF 2800 - 2FFF 3000 - 37FF 3800 - 3FFF 4000 - 47FF $800 - $FFF (BANK 1) (BANK 2) (BANK 3) (BANK 4) (BANK 5) (BANK 6) (BANK 7) (BANK 8) CPU Address $000 - $7FF $800 - $FFF ROM Space BNK = $08 BNK = $09 BNK = $0A 0000 - 07FF 0000 - 07FF 0000 - 07FF (BANK 0) (BANK 0) (BANK 0) 4800 - 4FFF 5000 - 57FF 5800 - 5FFF (BANK 9) (BANK 10) (BANK 11) .com 14 DataSheet 4 U .com www..com SH67K93 4. Initial State 4.1. System Register State Address $00 $01 $02 $03 $04 Bit3 IEX0 IRQEX0 TM0.3 TM1.3 TL0L.3 TC0L.3 TL0H.3 TC0H.3 TL1L.3 TC1L.3 TL1H.3 TC1H.3 PA.3 PB.3 PC.3 PD.3 PE.3 TBR.3 INX.3 DPL3 PUMP_ON LCDM3 PB2 - 0/CID Bit2 IET0 IRQT0 TM0.2 TM1.2 TL0L.2 TC0L.2 TL0H.2 TC0H.2 TL1L.2 TC1L.2 TL1H.2 TC1H.2 PA.2 PB.2 PC.2 PD.2 PE.2 PF.2 TBR.2 INX.2 DPL2 DPM.2 DPH.2 LCDON LCDM2 O/S2 Bit1 IET1 IRQT1 TM0.1 TM1.1 TL0L.1 TC0L.1 TL0H.1 TC0H.1 TL1L.1 TC1L.1 TL1H.1 TC1H.1 PA.1 PB.1 PC.1 PD.1 PE.1 PF.1 TBR.1 INX1 DPL1 DPM.1 DPH.1 BIAS LCDM1 O/S1 Bit0 IEP IRQP TM0.0 TM1.0 TL0L.0 TC0L.0 TL0H.0 TC0H.0 TL1L.0 TC1L.0 TL1H.0 TC1H.0 PA.0 Power-on Reset/Pin Reset 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx xxxx -xxx -xxx 0000 0110 0000 WDT Reset 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx xxxx -xxx -xxx 0000 0110 0000 $05 $06 $07 t4U.com $08 $09 $0A $0B $0C $0D $0E $0F $10 $11 $12 $13 $14 $15 DataShee .com PB.0 PC.0 PD.0 PE.0 PF.0 TBR.0 INX.0 DPL0 DPM.0 DPH.0 DUTY LCDM0 O/S0 .com 15 DataSheet 4 U .com www..com SH67K93 System Register State (Continued) Address $16 $17 $18 $19 $1A $1B $1C $1D $1E $1F $20 Bit3 PA0_PEN Bit2 PL/PH Bit1 Bit0 Power-on Reset/Pin Reset 0000 x000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1000 0000 0000 0000 0000 0000 1111 1000 0000 00 - 0 - - 10 0 - -0 WDT Reset 0000 x000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1000 0000 0000 0000 0000 0000 1111 1000 u000 00 - 0 - - 10 0 - -0 INT0_FSKIN0 INT0_PA0 IRQ_PA0 PACR.0 PBCR.0 PCCR.0 PDCR.0 PECR.0 PFCR.0 OXON FSKIN_STAT IRQ_FSKTX IRQ_FSKIN PACR.3 PBCR.3 PCCR.3 PDCR.3 PECR.3 PPULL PACR.2 PBCR.2 PCCR.2 PDCR.2 PECR.2 PFCR.2 HLM PACR.1 PBCR.1 PCCR.1 PDCR.1 PECR.1 PFCR.1 OXM ROM BNK3 ROM BNK2 ROM BNK1 ROM BNK0 RDT.3 RDT.7 RDT.11 RDT.15 DF_F FSK_ON ADCC FSK_D7 RAM BNK2 RAM BNK1 RAM BNK0 RDT.2 RDT.6 RDT.10 RDT.14 DC2 RDT.1 RDT.5 RDT.9 RDT.13 DC1 RDT.0 RDT.4 t4U.com $21 $22 $23 $24 $25 $26 $27 $28 $29 $2A $2B $2C $2D $2E $2F DataShee .com RDT.8 RDT.12 DC0 TGC_ROW FSK_TXEN FSK_D4 FSK_DTMF TGC_COL FSK_MD FSK_D6 FSK_PRE FSK_D5 FSK_D3/TGD3 FSK_D2/TGD2 FSK_D1/TGD1 FSK_D0/TGD0 AMP_ON GCD3 ADCD3 WDT CMPW1 CAS/DTMF AGC_ON GCD2 ADCD2 WT2 CMPW0 DFIL_ON GCD1 ADCD1 WT1 B0 ADC_ON GCD0 ADCD0 WT0 O/S3 B1 INT0_FSKIN1 .com 16 DataSheet 4 U .com www..com SH67K93 System Register State (Continued) Address $1740 $1741 $1742 $1743 $1744 $1745 $1746 $1747 $1748 $1749 $174A $174B $174C $174D $174E $174F $1750 $1751 $1752 $1753 $1754 $1755 $1756 $1A57 $1758 $1759 $175A $175B $175C $175D $175E $175F $1760 $1761 $1762 $1763 $1764 $1765 $1766 $1767 $1768 Bit3 D7 D3 D15 D11 D7 D3 D15 D11 D7 D3 D15 D11 D7 D3 D15 D11 D7 D3 D15 D11 D7 D3 D15 D11 D7 D3 D15 D11 D7 D3 D15 D11 D7 D3 D15 D11 D7 D3 D15 D11 D7 Bit2 D6 D2 D14 D10 D6 D2 D14 D10 D6 D2 D14 D10 D6 D2 D14 D10 D6 D2 D14 D10 D6 D2 D14 D10 D6 D2 D14 D10 D6 D2 D14 D10 D6 D2 D14 D10 D6 D2 D14 D10 D6 Bit1 D5 D1 D13 D9 D5 D1 D13 D9 D5 D1 D13 D9 D5 D1 D13 D9 D5 D1 D13 D9 D5 D1 D13 D9 D5 D1 D13 D9 D5 D1 D13 D9 D5 D1 D13 D9 D5 D1 D13 D9 D5 Bit0 D4 D0 D12 D8 D4 D0 D12 D8 D4 D0 D12 D8 D4 D0 D12 D8 D4 D0 D8 Power-on Reset/Pin Reset xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx WDT Reset xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx t4U.com DataShee D12 .com xxxx D4 D0 D12 D8 D4 D0 D12 D8 D4 D0 D12 D8 D4 D0 D12 D8 D4 D0 D12 D8 D4 .com 17 DataSheet 4 U .com www..com SH67K93 System Register State (Continued) Address $1769 $176A $176B $176C $176D $176E $176F $1770 $1771 $1772 $1773 $1774 $1775 $1776 $1777 $1778 Bit3 D3 D15 D11 D7 D3 D15 D11 D7 D3 D15 D11 D7 D3 D15 D11 D7 D3 D15 D11 D7 D3 D15 D11 DFTA11 DFTA7 DFTA3 D11 D7 D3 Bit2 D2 D14 D10 D6 D2 D14 D10 D6 D2 D14 D10 D6 D2 D14 D10 D6 D2 D14 D10 D6 D2 D14 D10 DFTA14 DFTA10 DFTA6 DFTA2 D10 D6 D2 Bit1 D1 D13 D9 D5 D1 D13 D9 D5 D1 D13 D9 D5 D1 D13 D9 D5 D1 D13 D9 D5 D1 D13 D9 DFTA13 DFTA9 DFTA5 DFTA1 D9 D5 D1 Bit0 D0 D12 D8 D4 D0 D12 D8 D4 D0 D12 D8 D4 D0 D12 D8 D4 D0 D12 D8 D4 D0 D12 D8 DFTA12 DFTA8 DFTA4 DFTA0 D8 D4 D0 Power-on Reset/Pin Reset xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 0000 0000 0000 WDT Reset xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 0000 0000 0000 t4U.com $1779 $177A $177B $177C $177D $177E $177F $1780 $1781 $1782 $1783 $1784 $1785 $1786 DataShee .com Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. 4.2. Others Initial States Others Program Counter (PC) CY Accumulator (AC) Data Memory After any Reset $000 Undefined Undefined Undefined .com 18 DataSheet 4 U .com www..com SH67K93 5. System Clock and Oscillator The oscillator generates the basic clock pulses that provide the system clock to supply CPU and on-chip peripherals. System clock = fOSC/4 5.1. Instruction Cycle Time: (1) 4/32.768kHz ( 122.12s) for 32.768kHz oscillator. (2) 4/262kHz( 15.27s) for 262kHz oscillator. (3) 4/1.8MHz ( 5.56s) for 1.8MHz oscillator. (4) 4/3.58MHz (= 1s) for 3.58MHz oscillator. 5.2. Circuit Configuration SH67K93 has two on-chip oscillation circuits OSC and OSCX. OSC is a low frequency crystal (Typ. 32.768kHz) or RC (Typ.262kHz) determined by the code option. This is designed for low frequency operation. OSCX also has two types: ceramic (Typ.3.58MHz) or RC (1.8MHz) determined by code option. It is designed for high frequency operation. It is possible to select the high speed CPU processing by a high frequency clock and select low power operation by low operation clock. At the starting of reset initialization, OSC starts oscillation and OSCX is turned off. Immediately after reset initialization, the OSC clock is automatically selected as the system clock input source. OSCI OSCO Low Frequency Clock Oscillator System clock Source Selector & Switching control High Frequency Clock Oscillator System clock Generator CPU Clock OSCXI t4U.com OSCXO DataShee Figure 1. Oscillator Block Diagram .com OSCX turn off OSCX turn on OSCXO OSCO SYS CLOCK High frequency operation Low frequency operation High frequency operation Switch from OSCX to OSC Switch from OSC to OSCX Figure 2. Timing of System Clock Switching .com 19 DataSheet 4 U .com www..com SH67K93 5.3. OSC Oscillation The OSC generates the basic clock pulses that provide the CPU and peripherals (Timer0, Timer1, LCD) with an operating clock. (1) OSC Crystal oscillator type 32.768kHz C1 OSCI Crystal OSCO C2 15p (for reference only) 15p (for reference only) (2) OSC RC oscillator type ROSC OSCI 120k (for reference only) t4U.com 5.4. OSCX Oscillator OSCX has two clock oscillators. The code options select the Ceramic/Crystal or RC as the CPU's clock. If the OSCX is not used, it must be masked to be Ceramic resonator and the OSCXI must be connected to GND. (1) OSCX Ceramic oscillator type DataShee OSCXI .com Ceramic C1 33p (for reference only) OSCXO 3.58MHz C2 33p (for reference only) (2) OSCX Crystal oscillator type C1 OSCXI Crystal OSCXO 3.579545MHz C2 12p (for reference only) 12p (for reference only) (3) OSCX RC oscillator type ROSC OSCXI 130k (for reference only) .com 20 DataSheet 4 U .com www..com SH67K93 5.5. Control of Oscillator The oscillator control register configuration is shown as blow. Address $1E OXON: Bit3 PPULL Bit2 HLM Bit1 OXM Bit0 OXON R/W R/W Remarks OSCX and System Clock control register OSCX oscillation on/off. 0: Turn off OSCX oscillation 1: Turn on OSCX oscillation OXM: switching system clock. 0: select OSC as system clock 1: select OSCX as system clock 5.6. Programming Notes It takes at least 5 ms for the OSCX oscillation circuit to go on until the oscillation stabilizes. When switching the CPU system clock from OSC to OSCX, one must wait a minimum of 5ms till the OSCX oscillation is active. However, the start time varies a lot with respect to oscillator characteristics and operational conditions. Therefore the waiting time depends on applications. When switching from OSCX to OSC, and turning off OSCX in one instruction, the OSCX turn off control would be delayed for one instruction cycle automatically to prevent CPU operation error. t4U.com DataShee .com .com 21 DataSheet 4 U .com www..com SH67K93 6. I/O PORT The MCU provides 24 bi-directional I/O pads. The PORT data put in register $08 - $0D. The PORT control register ($18 - $1E) controls the PORT as input or output. Each I/O port for PORTA [3:1], PORTB, PORTC, PORTD, PORTE, PORTF has an internal pull-high resistor, which is controlled by PPULL of $1E and the data of the port, when the PORT is used as input. PORTA.0 has an internal pull-high resistor and an internal pull-low resistor, which is controlled by PA0_PEN and PL/PH of $16 when the PORT is used as input. Port I/O mapping address is shown as follows: Address $08 $09 $0A $0B $0C $0D $18 $19 $1A $1B $1C Bit3 PA.3 PB.3 PC.3 PD.3 PE.3 PACR.3 PBCR.3 PCCR.3 PDCR.3 PECR.3 Bit2 PA.2 PB.2 PC.2 PD.2 PE.2 PF.2 PACR.2 PBCR.2 PCCR.2 PDCR.2 PECR.2 PFCR.2 Bit1 PA.1 PB.1 PC.1 PD.1 PE.1 PF.1 PACR.1 PBCR.1 PCCR.1 PDCR.1 PECR.1 PFCR.1 Bit0 PA.0 PB.0 PC.0 PD.0 PE.0 PF.0 PACR.0 PBCR.0 PCCR.0 PDCR.0 PECR.0 PFCR.0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W PORTA data PORTB data PORTC data PORTD data PORTE data PORTF data PORTA input/output control PORTB input/output control PORTC input/output contro PORTD input/output control PORTE input/output control PORTF input/output control Remarks t4U.com $1D PA (/B/C/D/E/F) CR.n, (n = 0, 1, 2, 3) 0: Set I/O as an input direction. (Power on initial) .com 1: Set I/O as an output direction. Note: For PORTA.3 - 1,PORTB, PORTC, PORTD, PORTE, PORTF When PXCR = 0, Data Register = 1 and PPULL = 1, the Pull-High resistor are enabled, else enabled when one of the above conditions does not match. Turn off the pull-high MOS individually for each port can be done by writing the data register with 0. For PORTA.0 When PACR.0 = 0, and PA0_PEN = 1, the Pull High/Low resistor is enabled, else enabled when one of the above conditions does not match. Equivalent Circuit for PORTA, PORTB VDD PA0_PEN PL/PH VDD I/O Control Register Weak Pull high DataShee I/O Pad DATA Regiser GND Weak Pull Low GND DATA READ DATA IN READ PORTA.0 .com 22 DataSheet 4 U .com www..com SH67K93 VDD PPULL VDD I/O Control Register Weak Pull high DATA Regiser I/O Pad GND DATA READ DATA IN READ PORTA[3:1], PORTB3 VDD PPULL VDD I/O Control Register DATA Regiser Weak Pull high PORTB shared register t4U.com I/O Pad DataShee .com GND DATA READ DATA IN READ CID Bolck FILIN AGCIN FILOUT PORTB[2:0] Equivalent Circuit for PORTC, PORTD, PORTE, PORTF VDD PPULL VDD I/O Control Register DATA Regiser Weak Pull high Segment shared register I/O Pad GND DATA READ DATA IN READ LCD driver Seg50 - 35 PORTC, PORTD, PORTE, PORTF .com 23 DataSheet 4 U .com www..com SH67K93 Equivalent Circuit for Scan Output Pads for Segment35 - 24 LCD segment output Output Switch Scan output port Segment 35 - 24 O/S3 0: output Segment signal 1: scan output port 6.1. System Register Address $15 $16 Bit3 PB2 - 0/CID PA0_PEN PPULL CMPW1 SCAN35 SCAN31 SCAN27 Bit2 O/S2 PL/PH HLM CMPW0 SCAN34 SCAN30 SCAN26 Bit1 O/S1 OXM SCAN33 SCAN29 SCAN25 Bit0 O/S0 OXON R/W R/W R/W R/W Remarks Bit2 - 0: Set LCD segment / I/O Port mode Bit3: PortB2 - 0 shared with Caller ID control bit PORTA.0 Pull-high/low control register Bit3: Port Pull-High resistor control bit for all port except PORTA.0 Bit2: Heavy Load mode t4U.com $1E $2D $3C8 $3C9 $3CA PA0_PEN: DataShee .com O/S3 R/W LCD scan output control bit SCAN32 SCAN28 SCAN24 R/W R/W R/W Scan output data register PL/PH: PB2 - 0/CID: HLM: PPULL: PORTA.0 Pull-high/low resistor control register 1: PORTA.0 pull-high/low resistor enable. 0: PORTA.0 pull-high/low resistor disable PORTA.0 pull -high or pull-low resistor selection bit 1: select pull-low resistor. 0: select pull-high resistor. PORTB [2:0] share with CID interface control bit 1: PORTB [2:0] set as input/output Port 0: PORTB.2 set as FILIN input pad PORTB.1 set as FILOUT pad PORTB.0 set as AGCIN input pad Heavy Load Mode control bit 0: Disable 1: Enable The Pull-High resistor control bit for all Ports except PORTA.0 0: Pull-High resistor control disable 1: Pull-High resistor control enable .com 24 DataSheet 4 U .com www..com SH67K93 O/S2 - 0: PORTC/Seg50 - 47, PORTD/Seg46 - 43, PORTE/Seg42 - 39, PORTF/Seg38 - 36 sharing control bit O/S2 0 0 0 0 1 1 1 1 O/S1 0 0 1 1 0 0 1 1 O/S0 0 1 0 1 0 1 0 1 Inhibited Seg50 - 47 Seg50 - 47 PortC PortC PortC PortC Seg46 - 43 Seg46 - 43 Seg46 - 43 PortD PortD PortD Seg42 - 39 Seg42 - 39 Seg42 - 39 Seg42 - 39 PortE PortE Seg38 - 36 Seg38 - 36 Seg38 - 36 Seg38 - 36 Seg38 - 36 PortF t4U.com O/S3: Segment35 - 24 scan output control bit SCAN35 - 24: Segment35 - 24 scan output data register 6.2. Heavy Load Mode (HLM) The MCU has a heavy load protection circuit when the battery load becomes heavy, such as, when an external buzzer sounds or an external speaker is turned on. In this mode, the crystal oscillator circuit has been backup for high gain. When this mode is set, more power would be provided to an oscillator circuit. Unless it is nessary, be careful not to set this mode with the software since the mode enter would delay for one instruction. Please activate heavy load driving only after setting HLM at least one instruction wait cycle through the software. The following shows the programming setting. HLM: 0 = Heavy load protection mode is released 1 = Heavy load protection mode is set. HLM 0 1 DataShee .com ON HEAVYLOAD OFF 1 Instruction Cycle Time 6.3. Port Interrupt The PORTB, PORTC and PORTD are used as port interrupt sources. The following is the port interrupt function block-diagram. IEP PORTB.n PORTC.n PORTD.n Port Interrupt PBCR.n PCCR.n PDCR.n Note: n = 0, 1, 2, 3 IRQP .com 25 DataSheet 4 U .com www..com SH67K93 Port Interrupt (PBCD INT) Programming Note If user wants to generate an interrupt when a falling edge from VDD to GND emerges on the port, the following must be executed. 1. Set the port as input port, fill port data register with 1 and avoid port floating. 2. Set the port into Pull-high (Use external pull high resistance or set PPULL to 1). Any further falling edge transition would not be able to make interrupt request until all of the pads return to VDD in PBCD INT application. Note: 1. When PORTC and PORTD are shared to segment, user can only generate interrupt on PORTB. 2. The Interrupt function is disable for PORTB2~0 while PORTB.2 - 0 are shared as CID interface. 6.4. External Interrupt ( INT0 ) PORTA0 is one of the three external interrupt sources (active low). t4U.com DataShee .com .com 26 DataSheet 4 U .com www..com SH67K93 7. Timer 0 and 1 SH67K93 has two 8-bit timers. The timer / counter has the following features: - 8-bit up-counting timer/counter. - Automatic re-load counter. - 8-level prescaler. - Interrupt on overflow from $FF to $00. The following is a simplified timer block diagram. tosc System clock SYNC 8-BIT COUNTER Pre-Scaler TM.2 TM.1 TM.0 The low-order digit should be written first, and then the high-order digit. The timer/counter is automatically loaded with the contents of the load register when the high-order digit is written or counter counts overflow from $FF to $00. Timer Load Register: The register H controls the physical READ and WRITE operations. Please follow these steps: Write Operation: Low nibble first High nibble to update the counter Read Operation: High nibble first Low nibble followed. t4U.com The timers provide the following functions: - Programmable interval timer function. - Read counter value. 7.1 TIMER0 and TIMER1 Configurations and Operation The Timer0 consists of an 8-bit write-only timer load register (TL0L, TL0H; TL1L, TL1H) and an 8-bit read-only timer counter (TC0L, TC0H; TC1L, TC1H). Each of them has both low-order digits and high-order digits. Writing data into the timer load register (TL0L, TL0H; TL1L, TL1H) can initialize the timer counter. Load Reg. L Load Reg. H 8-bit timer counter Latch Reg. L DataShee 7.2. Timer Mode Register (TM0, 1) .com The timer can be programmed in several different prescalers by setting Timer Mode register (TM0, TM1). The 8-bit counter prescaler overflows output pulses. The Timer Mode register (TM0, TM1) is 3-bit register used for the timer control as shown in Table 1. The mode register selects the input pulse sources into the timer. The TM0.3 control bit defines the clock source of timer0. The TM1.3 control bit selects the clock source of timer1. TM0.3 =0: timer0 clock source = system clock (OSCX/4 or OSC/4) TM0.3 =1: timer0 clock source is generated by OSC/4. TM1.3 =0: timer1 clock source = system clock (OSCX/4 or OSC/4) TM1.3 =1: timer1 clock source is generated by OSC/4. Table 1 Timer0, Timer1 Mode registers ($02, $03) TM1.3/TM0.3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 TM1.2/TM0.2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 TM1.1/TM0.1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 TM1.0/TM0.0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Prescaler /2048 /512 /128 /32 /8 /4 /2 /1 /2048 /512 /128 /32 /8 /4 /2 /1 OSC/4 System clock (OSCX/4 or OSC/4) Clock Source .com 27 DataSheet 4 U .com www..com SH67K93 8. LCD Driver The LCD driver contains a controller, a voltage generator, 16 common signal pads and 50 segment driver pads. There are 4 different programmable driving modes: 1/16 duty & 1/5 bias, 1/16 duty & 1/4 bias, 1/8 duty & 1/4 bias, 1/8 duty & 1/5 bias. The driving mode is controlled by the system register $13 and the power on initialization status is 1/16 duty, and 1/4 bias. The controller consists of display data RAM and a duty generator. The LCD SEG50 - 36 can also be used as I/O port (PORTC, PORTD, PORTE and PORTF), which is selected by bit 2 - 0 of the system register $15. LCD RAM could be used as data memory if needed. When the "STOP" instruction is executed, the LCD will be turned off, but the data of LCD RAM keeps the previous value. When LCD is off, both common and segment output low. 8.1. LCD Control Register Address $13 $15 $3C8 $3C9 $3CA Bit 3 PUMP_ON PB2 - 0/CID SCAN35 SCAN31 SCAN27 Bit 2 LCDON O/S2 SCAN34 SCAN30 SCAN26 Bit 1 BIAS O/S1 SCAN33 SCAN29 SCAN25 Bit 0 DUTY O/S0 SCAN32 SCAN28 SCAN24 R/W R/W LCD control register0 R/W LCD control register1 R/W R/W R/W Data Register of LCD SEG35 - 32 when SEG35 - 32 shared as output port. Data Register of LCD SEG31 - 28 when SEG20 - 17 shared as output port. Data Register of LCD SEG27 - 24 when SEG16 - 13 shared as output port. Remarks LCD ON/OFF control and LCD driving mode control register t4U.com Address $13 Bit 3 PUMP_ON 0 1 X X X X X X Bit 2 LCDON X X 0 1 X X X X Bit 1 BIAS X X X X 0 1 X X Bit 0 DUTY X X X X X X 0 1 R/W Remarks R/W LCD ON/OFF control and LCD driving mode control control LCD Pump ON LCD Display OFF LCD Display ON LCD driver = 1/4 bias LCD driver = 1/5 bias LCD driver = 1/1 6duty LCD driver = 1/8duty, COM15 - 8 output low level DataShee .com LCD Pump OFF LCD Segment shared setting register Address $15 Bit 3 PB2~0/CID Bit 2 O/S2 Bit 1 O/S1 Bit 0 O/S0 R/W Remarks R/W Refer to the description of I/O PORT The LCD freqence is 64Hz regardless of the OSC is 32.768kHz or 262kHz RC COM1 COM1 ONE FRAME When the CPU is in STOP mode, the COMx and SEGx are pulled low. .com 28 DataSheet 4 U .com www..com SH67K93 8.2. Configuration of LCD RAM Segment1- 50, 1/16 duty Address $300 $301 $302 $303 $304 $305 $306 $307 $308 $309 $30A $30B $30C $30D Bit3 COM4 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 Bit2 COM3 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 Bit1 COM2 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 Bit0 COM1 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 Address $319 $31A $31B $31C $31D $31E $31F $320 $321 $322 $323 $324 $325 $326 $327 $328 $32A $32B $32C $32D $32E $32F $330 $331 Bit3 COM4 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 Bit2 COM3 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 Bit1 COM2 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 Bit0 COM1 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 t4U.com $30E $30F $310 $311 $312 $313 $314 $315 $316 $317 $318 DataShee .com SEG42 SEG17 $329 .com 29 DataSheet 4 U .com www..com SH67K93 Segment1- 50, 1/16 duty (Continued) Address $332 $333 $334 $335 $336 $337 $338 $339 $33A $33B $33C $33D $33E $33F $340 Bit3 COM8 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 Bit2 COM7 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 Bit1 COM6 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 Bit0 COM5 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 Address $34B $34C $34D $34E $34F $350 $351 $352 $353 $354 $355 $356 $357 $358 $359 $35A $35B $35C $35D $35E $35F $360 $361 $362 $363 Bit3 COM8 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 Bit2 COM7 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 Bit1 COM6 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 Bit0 COM5 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 t4U.com $341 $342 $343 $344 $345 $346 $347 $348 $349 $34A DataShee .com .com 30 DataSheet 4 U .com www..com SH67K93 Segment1- 50, 1/16 duty (Continued) Address $364 $365 $366 $367 $368 $369 $36A $36B $36C $36D $36E $36F $370 $371 $372 Bit3 COM12 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 Bit2 COM11 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 Bit1 COM10 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 Bit0 COM9 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 Address $37D $37E $37F $380 $381 $382 $383 $384 $385 $386 $387 $388 $389 $38A $38B $38C $38D $38E $38F $390 $391 $392 $393 $394 $395 Bit3 COM12 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 Bit2 COM11 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 Bit1 COM10 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 Bit0 COM9 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 t4U.com $373 $374 $375 $376 $377 $378 $379 $37A $37B $37C DataShee .com .com 31 DataSheet 4 U .com www..com SH67K93 Segment1- 50, 1/16 duty (Continued) Address $396 $397 $398 $399 $39A $39B $39C $39D $39E $39F $3A0 $3A1 $3A2 $3A3 $3A4 Bit3 COM16 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 Bit2 COM15 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 Bit1 COM14 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 Bit0 COM13 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 Address $3AF $3B0 $3B1 $3B2 $3B3 $3B4 $3B5 $3B6 $3B7 $3B8 $3B9 $3BA $3BB $3BC $3BD $3BE $3BF $3C0 $3C1 $3C2 $3C3 $3C4 $3C5 $3C6 $3C7 Bit3 COM16 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 Bit2 COM15 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 Bit1 COM14 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 Bit0 COM13 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 t4U.com $3A5 $3A6 $3A7 $3A8 $3A9 $3AA $3AB $3AC $3AD $3AE DataShee .com .com 32 DataSheet 4 U .com www..com SH67K93 Segment1 - 50, 1/8 duty Address $300 $301 $302 $303 $304 $305 $306 $307 $308 $309 $30A $30B $30C $30D $30E Bit3 COM4 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 Bit2 COM3 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 Bit1 COM2 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 Bit0 COM1 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 Address $319 $31A $31B $31C $31D $31E $31F $320 $321 $322 $323 $324 $325 $326 $327 $328 $329 $32A $32B $32C $32D $32E $32F $330 $331 Bit3 COM4 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 Bit2 COM3 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 Bit1 COM2 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 Bit0 COM1 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 t4U.com $30F $310 $311 $312 $313 $314 $315 $316 $317 $318 DataShee .com .com 33 DataSheet 4 U .com www..com SH67K93 Segment1 - 50, 1/8 duty (Continued) Address $332 $333 $334 $335 $336 $337 $338 $339 $33A $33B $33C $33D $33E $33F $340 Bit3 COM8 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 Bit2 COM7 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 Bit1 COM6 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 Bit0 COM5 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 Address $34B $34C $34D $34E $34F $350 $351 $352 $353 $354 $355 $356 $357 $358 $359 $35A $35B $35C $35D $35E $35F $360 $361 $362 $363 Bit3 COM8 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 Bit2 COM7 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 Bit1 COM6 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 Bit0 COM5 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 t4U.com $341 $342 $343 $344 $345 $346 $347 $348 $349 $34A DataShee .com .com 34 DataSheet 4 U .com www..com SH67K93 8.3. LCD Power OSC/512 Code Option:Crystal or RC Power regualtor LCDON PUMP_ON LCDM3 - 0 /1 0 Scaler /8 1 MPX /2 DUTY VDD 1 MPX 0 BIAS LCD Power Supply Control Circuit LCD common driver COM1 - COM16 LCD segment driver SEG1 - SEG50 Figure 3. LCD block diagram for reference only The contrast control register can adjust the contrast of LCD. t4U.com Address $14 Bit 3 LCDM3 Bit 2 LCDM2 Bit 1 LCDM1 Bit 0 LCDM0 R/W R/W Remarks LCD contrast adjustment register VLCD (V) (VDD = 3.0V) DataShee .com LCDM3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 LCDM2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 LCDM1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 LCDM0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 PUMP_ON = 1 (Bit3 of $13) 1/4 Bias 2.77 2.84 2.92 3.00 3.09 3.18 3.27 (default) 3.37 3.48 3.60 3.72 3.86 4.00 4.15 4.32 4.50 1/5 Bias 3.00 3.07 3.14 3.21 3.29 3.37 3.46 (default) 3.55 3.65 3.75 3.86 3.97 4.09 4.22 4.35 4.50 PUMP_ON = 0 (Bit3 of $13) 1/4 Bias 1.85 1.89 1.95 2.00 2.06 2.12 2.18 (default) 2.25 2.32 2.40 2.48 2.57 2.67 2.77 2.88 3.00 1/5 Bias 2.00 2.05 2.09 2.14 2.19 2.25 2.31 (default) 2.37 2.43 2.50 2.57 2.65 2.73 2.81 2.90 3.00 .com 35 DataSheet 4 U .com www..com SH67K93 8.4. LCD Waveform 1/4 BIAS SELECT UNSELECT VLCD V1 V2=V3 COM V4 GND COM SELECT 1/5 BIAS UNSELECT VLCD V1 V2 V3 V4 GND SELECT SELECT UNSELECT VLCD V1 SEG V2=V3 V4 GND SEG UNSELECT VLCD V1 V2 V3 V4 GND Example: 1/8 duty, 1/4 bias VLCD V1 COM1 V2 V3 GND t4U.com DataShee .com VLCD V1 COM2 V2 V3 GND VLCD V1 COM3 V2 V3 GND VLCD V1 SEG V2 V3 GND .com 36 DataSheet 4 U .com www..com SH67K93 9. Watchdog Timer (WDT) The watchdog timer is a countdown counter, and its clock source is an independent built-in RC oscillator, so that it will always run even in the STOP mode. The watchdog timer automatically generates a device reset when it overflows. It can be enabled or disabled permanently by using the code option. The watchdog timer control bits ($2C bit2 - bit0) are used to select different overflow frequency. The watchdog timer overflow flag ($2C bit3) will be automatically set to "1" by hardware when the watchdog timer overflows. By reading or writing the system register $2C, the watchdog timer should re-count before the overflow happens. System Register $2C: Watchdog Timer (WDT) Address $2C Bit 3 WDT X X X X X X X X 0 0 0 0 1 1 1 1 X X 0 0 1 1 0 0 1 1 X X 0 1 0 1 0 1 0 1 X X Bit 2 WT2 Bit 1 WT1 Bit 0 WT0 R/W W R W W W W W W W W R Remarks Bit2 - Bit0: Watchdog timer control bits Bit3: Watchdog timer overflow flag (read only) Watchdog timer overflow period is about 1433.6ms Watchdog timer overflow period is about 358.4ms Watchdog timer overflow period is about 89.6ms Watchdog timer overflow period is about 44.8ms Watchdog timer overflow period is about 22.4ms Watchdog timer overflow period is about 11.2ms Watchdog timer overflow period is about 2.8ms Watchdog timer overflow period is about 0.7ms No watchdog timer overflow resets t4U.com 0 1 DataShee R Watchdog timer overflows, WDT reset happens .com .com 37 DataSheet 4 U .com www..com SH67K93 10. Interrupt Four interrupt sources are available on SH67K93: - External interrupt ( INT0 ) - Timer0 interrupt - Timer1 interrupt - Port's falling edge detection interrupt ( INT1 ) Interrupt Control Bits and Interrupt Service The interrupt control flags are mapped on $00 and $01 of the system register. They can be accessed or tested by the program. Those flags are cleared to "0" at initialization by the chip reset. System Register Address $00 $01 $16 $17 $2F Bit 3 IEX IRQEX0 PA0_PEN Bit 2 IET0 IRQT0 PL/PH Bit 1 IET1 IRQT1 Bit 0 IEP IRQP R/W R/W R/W Reamrks Interrupt Control Regiser 1: Enable/0: Disable Interrupt Flag Regiser 1: Request/0: No request INT0_FSKN0 INT0_PA0 R/W FSK receiver and PORTA0 interrupt mode control register FSKIN status register R/W FSK generator/FSK receiver/PORTA0 Interrupt Flag Regiser FSKIN_STAT IRQ_FSKTX IRQ_FSKIN IRQ_PA0 CAS/DTMF - t4U.com INT0_FSKIN1 R/W FSK receiver interrupt mode control register When IEx is set to "1" and the interrupt request is generated (IRQx is 1), the interrupt will be activated and vector address will be generated from the priority PLA corresponding to the interrupt sources. When an interrupt occurs, the PC and CY flag will be .com saved into stack memory and jump to interrupt service vector address. After the interrupt occurs, all interrupt enable flags (IEx) are cleared to "0" automatically, so when IRQx is 1 and IEx is set to "1" again, the interrupt will be activated and vector address will be generated from the priority PLA corresponding to the interrupt sources. Inst.cycle 1 2 3 4 5 DataShee Instruction Execution N Instruction Execution I1 Instruction Execution I2 Interrupt Generated Interrupt Accepted Vector Generated Stacking Fetch Vector address Reset IE.X Start at vector address Interrupt Servicing Sequence Diagram .com 38 DataSheet 4 U .com www..com SH67K93 Interrupt Nesting During the CPU interrupt service, the user can enable any interrupt enable flag before returning from the interrupt. The servicing sequence diagram shows the next interrupt and the next nesting interrupt occurrences. If the interrupt request is ready and the instruction of execution N is IE enabled, then the interrupt will start immediately after the next two instruction executions. However, if instruction I1 or instruction I2 disables the interrupt request or enable flag, then the interrupt service will be terminated. External Interrupt ( INT0 ) External Interrupt 0 is shared with the PORTA.0, the FSK receiver and FSK Generator output, falling or rising edge active. When the bit 3 of the register $0 (IEX) is set to "1", the interrupt0 is enabled. For PORTA.0, the interrupt will occur only at INPUT mode. When an interrupt0 occurred, one must read the IRQPA0, IRQ_FSKIN and IRQ_FSKTX first to judge whether the interrupt source is from PORTA.0, the FSK receiver or from the FSK Generator output. IEX: Interrupt0 on/off switch. 0: disable. 1: Enable IRQEX0: Interrupt0 interrupt request 0: No request 1: Request IRQ_PA0: PA0 interrupt request 0: No request 1: Request IRQ_FSKIN: FSK receiver interrupt request 0: No request 1: Request IRQ_FSKTX: FSK Generator interrupt request 0: the transmission is not completed 1: the transmission is completed INT0_FSKIN0: edge trigger type control bit of FSK receiver (one source of Interrupt0) while INT0_FSKIN1 = 0 0: falling edge type 1: rising edge type INT0_FSKIN1: edge trigger type of FSK receiver (one source of Interrupt0) 0: edge type is set by INT0_FSKIN0 .com 1: Dual edges interrupt type (falling/rising) regardless of INT0_FSKIN0 INT0_PA0: edge trigger type of PORTA.0 (one source of Interrupt0) 0: falling edge type 1: rising edge type FSKIN_STAT: the status bit of FSKIN level (output of FSK receiver) 1: the source of FSKIN is high level 0: the source of FSKIN is low level FSKIN_STAT t4U.com DataShee FSK receiver INT0_FSKIN INT0_FSKIN1 PA0 INT0_PA0 FSK Generator IRQ_FSKTX IRQ_FSKIN IRQ_PA0 IRQEX0 IEX0 CPU Timer Interrupt The input clocks of Timer0 and Timer1 are based on system clock. The timer overflow from $FF to $00 will generate an internal interrupt request (IRQT0 or IRQT1 = 1), If the interrupt enable flag is enabled (IET0 or IET1 = 1), a timer interrupt service routine will start. Timer interrupt can also be used to wake the CPU from HALT mode. .com 39 DataSheet 4 U .com www..com SH67K93 Port Falling Edge Interrupt ( INT1 ) Only the digital input port can generate a port interrupt. The analog input cannot generate an interrupt request. Any one of PORTB, PORTC and PORTD input pad transitions from VDD to GND would generate an interrupt request (IRQP = 1). Further falling edge transition would not be able to make a new interrupt request until all of the input pads have returned to VDD. Port Interrupt can be used to wake the CPU from HALT or STOP mode. When the PORTB shared as Caller ID interface, the PORTB interrupt will be disabled. When the PORTC, PORTD shared as segment output, the PORTC, PORTD interrupt will be disabled. PORTX.3 PXCR.3 Port interrupt request generator IEP PORTX.1 PXCR.1 Falling edge Detector X = B, C, D Falling edge Detector PORTX.2 PXCR.2 Falling edge Detector Interrupt CPU t4U.com PORTX.0 PXCR.0 Falling edge Detector DataShee .com .com 40 DataSheet 4 U .com www..com SH67K93 11. CID Interface TIP RING pre_amp OPOUT FILO high pass filter FILIN AIN AGC ADC D[3:0] FSK_CMP FSKOUT t4U.com 11.1. DTMF/FSKGenerator (Using Condition: System Clock is 3.579545MHz Crystal) DTMF Generator .com The SH67K93 has a built-in DTMF generator. The DTMF Generator control register and data register: Address $26 $29 FSK_ON: Bit3 FSK_ON Bit2 FSK/DTMF Bit1 TONE_COL Bit0 TONE_ROW R/W Remarks Low nibble data of FSK Generator Data of DTMF Generator DataShee R/W DTMF/FSK Generator control register FSK_D3/TGD3 FSK_D2/TGD2 FSK_D1/TGD1 FSK_D0/TGD0 R/W DTMF/FSK Generator power on/off switch 0: DTMF/FSK Generator power off 1: DTMF/FSK Generator power on FSK/DTMF: DTMF/FSK Generator select bit 0: DTMF Generator Enable, FSK Generator disable 1: DTMF Generator disable, FSK Generator Enable TONE_COL: Column signal output control 0: disable 1: Enable TONE_ROW: ROW signal output control 0: disable 1: Enable TGD3 - 0: DTMF Generator Data register This chip provides a dual tone multi-frequency (DTMF) tone generation circuit. The DTMF signal consists of two sine waves with which to access the switching system. The following table shows the relationship between the key pressed and its dual tone frequencies. .com 41 DataSheet 4 U .com www..com SH67K93 COL ROW 697Hz 770Hz 852Hz 941Hz 1209Hz 1 4 7 # 1336Hz 2 5 8 0 1477Hz 3 6 9 1633Hz A B C D The DTMF generator employs two D/A converters, which can generate two separated single-tone signals, low-frequency group for Row and high-frequency group for Column. These two signals would finally mix together to produce a Dual Tone Multi Frequency Signal. Each single-tone signal consists of 32-level waveform that guarantees low distortion signal quality. A write-only DTMF Generator control register controls DTMF generator, and the signal data would be prepared in this register. The row and column frequency of DTMF corresponding to each keypad and digits are listed in the following table. The output DTMF frequency is controlled by the tone generator data bit TGD3 - TGD0 in DTMF data register. The relationship between TGD bit and output DTMF frequency are also listed in the following table. DTMF Generator data Register: DTMF_data "1" TGD3 0 0 0 TGD2 1 0 1 0 0 1 0 0 1 0 0 0 1 1 1 1 TGD1 1 0 0 0 0 0 0 1 1 1 1 1 0 0 1 1 TGD0 1 0 0 0 1 1 1 0 0 0 1 1 0 1 0 1 Output Frequency 941 + 1336Hz 697 + 1209Hz 697 + 1336Hz 697 + 1477Hz 770 + 1209Hz 770 + 1336Hz 770 + 1477Hz 852 + 1209Hz 852 + 1336Hz 852 + 1477Hz 941 + 1209Hz 941 + 1477Hz 697 + 1633Hz 770 + 1633Hz 852 + 1633Hz 941 + 1633Hz Digit "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "*" "#" "A" "B" "C" "D" t4U.com 1 0 0 1 0 0 1 0 1 1 1 1 1 DataShee .com .com 42 DataSheet 4 U .com www..com SH67K93 FSK Generator The SH67K93 has a built-in FSK generator. The FSK Generator control register and data register: Address $26 $27 $28 $29 FSK_MD: Bit3 FSK_ON ADCC FSK_D7 Bit2 FSK/DTMF FSK_MD FSK_D6 Bit1 TONE_COL FSK_PRE FSK_D5 Bit0 TONE_ROW FSK_TXEN FSK_D4 R/W Remarks R/W FSK/DTMF Generator control register R/W FSK Generator mode control register R/W FSK/DTMF Generator data register FSK_D3/TGD3 FSK_D2/TGD2 FSK_D1/TGD1 FSK_D0/TGD0 FSK standard select bit 1: Select Bell 202 standard 0: Select V.23 standard FSK_PRE: 1: Indicate FSK_DATA is preamble data 0: Indicate FSK_DATA is message data FSK_TXEN: 1: Start transmiting FSK signal after FSK_DATA is ready 0: unused FSK_D7 - 0: FSK data to be transmitied The SH67K93 provides a programmable FSK generator that satisfies the standard of Bell202 and V.23. Setting the FSK_MD bit in FSK control register chooses Bell202 mode as well as clear of this bit chooses V.23 mode. Mark `1' Space `0' 2200 Hz 2100 Hz t4U.com Bell202 V.23 1200 Hz 1300 Hz DataShee .com In these two standards, FSK baud rate is 1200 baud. The baud rate clocks automatically enabled before transmiting FSK signal. The transmitted data is stored in FSK_TXDATA register. Then set FSK_TXEN bit to start to transmit the 8 bit data. After all the 8 bit data are transmitted, the FSK Generator will generate an interrupt if IEX0 in IE register is set, IRQ_FSKTX, to indicate it is ready for transmiting next byte data. Before next FSK_TXEN bit is set, the FSK modulator will transmit mark signal or the data stored in FSK_TXDATA register repeatedly until FSK Generator is disabled or next FSK data is ready to be transmitted. The FSK_PRE bit in FSK_CTRL register indicates whether the data in FSK_TXDATA register is preamble or real data. If FSK_PRE bit is set to 1, the data stored in FSK_TXDATA register is preamble and the FSK modulator will transmit FSK_TXDATA repeatedly. If this bit is clear to 0, the mark signal will be transmitted during two FSK data. The FSK_PRE bit also serves another function that it can control the insertion of start and stop bit in transmiting FSK signal. If the preamble FSK signal is transmitted, the FSK modulator will not insert the start and stop bit. While the FSK modulator will insert start and stop bit automatically when FSK_PRE bit is clear. Before FSK_ON is set, please make sure that the FSK_TXEN is cleared, and FSK_PRE is already set correctly. .com 43 DataSheet 4 U .com www..com SH67K93 11.2. Amplifier, ADC and Digital Filter The SH67K93 has a built-in Amplifier, ADC and Digital filter. The Amplifier, ADC and Digital filter control register and data register: Address $25 $27 $2A $2B $2D $1780 $1781 $1782 $1783 $1784 $1785 $1786 Bit3 DF_F ADCC AMP_ON GCD3 ADCD3 CMPW1 DFTA11 DFTA7 DFTA3 D11 D7 D3 Bit2 DC2 FSK_MD AGC_ON GCD2 ADCD2 CMPW0 DFTA14 DFTA10 DFTA6 DFTA2 D10 D6 D2 Bit1 DC1 DFIL_ON GCD1 ADCD1 DFT113 DFTA9 DFTA5 DFTA1 D9 D5 D1 Bit0 DC0 ADC_ON GCD0 ADCD0 O/S3 DFTA12 DFTA8 DFTA4 DFTA0 D8 D4 D0 R/W Sample Dot-number register R/W DF table start address register R/W R/W R/W W R R/W Remarks Digital Filter control register ADC conversion complete flag AMP/AGC/DF/ADC control register GAIN register ADC conversion result Comparator voltage window control register FSK_PRE FSK_TXEN R/W t4U.com AMP_ON: Pre-Amplifier, filter, AGC, FSK comparator power on/off switch 0: power OFF 1: power ON .com AGC_ON: AGC mode control 0: manual mode 1: Auto mode DFIL_ON: Digital filter control 0: Digital filter OFF 1: Digital filter ON, the digital filter will calculate the input data (output by ADC) when internal sample rate timer overflows. DF_F: Digital filter calculation is finished flag bit 0: Digital filter calculation is complete 1: Digital filter calculation is in process DC2 - 0: the number of frequence of Digital filter If Digital filter calculation is for DTMF, please write 07H If Digital filter calculation is for CAS, please write 03H D11 - 0: the number of sample dots for Digital filter CMPW1, CMPW0: The voltage window of schemitt-trigger of FSK comparator control bits DFTA14 - 0: Digital filter data table start address ADCON: 1: 4-bit ADC enable; 0: 4-bit ADC disable ADCC: 1: ADCC is set each time when a conversion is completed. 0: ADCC is cleared by reading the result data register or writing the status/control register. DataShee .com 44 DataSheet 4 U .com www..com SH67K93 Differential Input Amplifier gain Control Register table: GCR3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 GCR2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 GCR1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 GCR0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 dBm 3 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36 -39 -42 Gain 1 1.5 2 3 4 6 8 12 16 24 32 48 64 96 128 192 t4U.com Schemitt-trigger voltage windows control table: CMPW1 0 0 1 1 12. HALT and STOP Mode After the execution of HALT instruction, SH67K93 will enter HALT mode. In HALT mode, CPU will stop operating. But peripheral circuit (Timer, Base timer, DAC, AGC, ADC, FSK CMP) will keep the status. After the execution of STOP instruction, SH67K93 will enter STOP mode. In STOP mode, the whole chip (including oscillator) will stop operating. In HALT mode, SH67K93 can be waked up if any interrupt occurs. In STOP mode, SH67K93 can be waked up if port interrupt occurs (exclude the FSKIN and FSK generator interrupt). When CPU is awaked from the HALT/STOP by any initial source, it will execute the relevant initial serve subroutine first and then the instruction next to HALT/STOP will be executed. CMPW0 0 1 0 1 DataShee .com Voltage Window 0mV 20mV 50mV 200mV .com 45 DataSheet 4 U .com www..com SH67K93 13. Warm-up Timer The device has a built-in warm-up timer to eliminate unstable state of initial oscillation when oscillator starts oscillating in the following conditions: 13.1 Power-on Reset Warm-up time interval: 7 (1) In RC oscillator mode, the warm-up counter prescaler divide ratio is /2 (128). (2) In Crystal oscillator or Ceramic resonator mode, the warm-up counter prescaler divide ratio is /212 (4096). 13.2. Wake-up from STOP Mode Warm-up time interval: 12 (1) In RC oscillator mode, the warm-up counter prescaler divide ratio is /2 (4096). (2) In Crystal oscillator or Ceramic resonator mode, the warm-up counter prescaler divide ratio is /212 (4096). The clock source of warm-up timer is system clock. System clock is unchanged when system returns from STOP mode. 14. Bonding Option System Register: Address $2E Bit 3 X X X X Bit 2 X X X X GND B0 Bit 1 B0 0 0 1 1 Bit 0 B1 1 0 1 0 AVDD B1 R/W R R R R R Remarks B0, B1: bonding option B0 bond to GND & B1 bond to AVDD B0 bond to GND B1 bond to AVDD Default bonding option GND B0 AVDD B1 t4U.com DataShee .com PCB B0 = 1 GND B0 B1 = 0 AVDD B1 B0 = 1 GND B0 B0 = 1 AVDD B1 PCB B0 = 0 B1 = 0 B0 = 0 B1 = 1 Up to 4 different bonding options are possible for user's needs. The chip's program has 4 different program flows that vary depending on which bonding option is used. The readable contents of B1 and B0 will differ depending on bonding. .com 46 DataSheet 4 U .com www..com SH67K93 15. Code Option C: OSC clock source 0: 32.768kHz crystal 1: 262kHz RC L: OSCX clock source 0: 3.58MHz ceramic/3.579545MHz crystal 1: 1.8MHz RC WD: Watchdog control bit 00: WDT disable 01: WDT Enable and stop in STOP mode 10: WDT Enable and stop in STOP mode 11: WDT Enable and no stop in STOP mode K: LCD voltage Pump clock frequency select 0: 4kHz (default) 1: 8kHz T: CAS function control option 0: Enable (default) 1: Disable t4U.com DataShee .com .com 47 DataSheet 4 U .com www..com SH67K93 16. Instruction Set All instructions are one cycle and one-word instructions. The characteristic is memory-oriented operation. 16.1. Arithmetic and Logical Instruction 16.1.1. Accumulator Type Mnemonic ADC X (, B) ADCM X (, B) ADD X (, B) ADDM X (, B) SBC X (, B) SBCM X (, B) SUB X (, B) SUBM X (, B) EOR X (, B) EORM X (, B) OR X (, B) Instruction Code 00000 0bbb xxx xxxx 00000 1bbb xxx xxxx 00001 0bbb xxx xxxx 00001 1bbb xxx xxxx 00010 0bbb xxx xxxx 00010 1bbb xxx xxxx 00011 0bbb xxx xxxx 00011 1bbb xxx xxxx 00100 0bbb xxx xxxx 00100 1bbb xxx xxxx 00101 0bbb xxx xxxx 00101 1bbb xxx xxxx 00110 0bbb xxx xxxx Function AC <- Mx + AC + CY AC, Mx <- Mx + AC + CY AC <- Mx + AC AC, Mx <- Mx + AC AC <- Mx + -AC + CY AC, Mx <- Mx + -AC + CY AC <- Mx + -AC +1 AC, Mx <- Mx + -AC +1 AC <- Mx AC AC, Mx <- Mx AC AC <- Mx | AC AC, Mx <- Mx | AC AC <- Mx & AC Flag Change CY CY CY CY CY CY CY CY t4U.com ORM X (, B) AND X (, B) ANDM X (, B) SHR 16.1.2. Immediate Type Mnemonic ADI X, I ADIM X, I SBI X, I SBIM X, I EORIM X, I ORIM X, I ANDIM X, I DataShee 00110 1bbb xxx xxxx .com <- Mx & AC AC, Mx 11110 0000 000 0000 0 -> AC[3], AC[0] -> CY; AC shift right one bit CY Instruction Code 01000 iiii xxx xxxx 01001 iiii xxx xxxx 01010 iiii xxx xxxx 01011 iiii xxx xxxx 01100 iiii xxx xxxx 01101 iiii xxx xxxx 01110 iiii xxx xxxx Function AC <- Mx + I AC, Mx <- Mx + I AC <- Mx + -I +1 AC, Mx <- Mx + -I +1 AC, Mx <- Mx I AC, Mx <- Mx | I AC, Mx <- Mx & I Flag Change CY CY CY CY 16.1.3. Decimal Adjustment Mnemonic DAA X DAS X Instruction Code 11001 0110 xxx xxxx 11001 1010 xxx xxxx Function AC, Mx <- Decimal adjust for add AC, Mx <- Decimal adjust for sub Flag Change CY CY .com 48 DataSheet 4 U .com www..com SH67K93 16.2. Transfer Instruction Mnemonic LDA X (, B) STA X (, B) LDI X, I 16.3. Control Instruction Mnemonic BAZ X BNZ X BC X BNC X BA0 X BA1 X BA2 X BA3 X CALL X Instruction Code 10010 xxxx xxx xxxx 10000 xxxx xxx xxxx 10011 xxxx xxx xxxx 10001 xxxx xxx xxxx 10100 xxxx xxx xxxx 10101 xxxx xxx xxxx 10110 xxxx xxx xxxx 10111 xxxx xxx xxxx 11000 xxxx xxx xxxx 11010 000h hhh llll 11010 1000 000 0000 11011 0000 000 0000 11011 1000 000 0000 1110p xxxx xxx xxxx 11110 1111 111 1111 11111 1111 111 1111 PC <- X (Include p) PC <- (PC11-PC8) (TBR) (AC) No Operation Function PC <- X, if AC = 0 PC <- X, if AC 0 PC <- X, if CY = 1 PC <- X, if CY 1 PC <- X, if AC (0) = 1 PC <- X, if AC (1) = 1 PC <- X, if AC (2) = 1 PC <- X, if AC (3) = 1 ST <- CY, PC +1 PC <- X (Not include p) PC <- ST; TBR <- hhhh, AC <- lll CY, PC <- ST CY Flag Change Instruction Code 00111 0bbb xxx xxxx 00111 1bbb xxx xxxx 01111 iiii xxx xxxx Function AC <- Mx Mx <- AC AC, Mx <- I Flag Change t4U.com RTNW H, L RTNI HALT STOP JMP X TJMP NOP Where, PC AC -AC CY Mx p ST Program counter Accumulator Complement of accumulator Carry flag Data memory ROM page Stack DataShee .com I | & bbb Immediate data Logical exclusive OR Logical OR Logical AND RAM bank TBR Table Branch Register .com 49 DataSheet 4 U .com www..com SH67K93 Electrical Characteristics Absolute Maximum Rating* DC Supply Voltage . . . . . . . . . . . . . . . .-0.3V to +3.6V Input Voltage . . . . . . . . . . . . . . . -0.3V to VDD + 0.3V Operating Ambient Temperature . . . . -10 to +70 Storage Temperature . . . . . . . . . . . . .-55 to +125 *Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. DC Electrical Characteristics (VDD = 3.0V, GND = 0V, TA = 25, fOSC = 32.768kHz, OSCX is turned off, unless otherwise specified) Parameter Operating Voltage Operating Current Symbol VDD IOP Min. 2.4 Type 3 10 Max. 3.6 20 Unit V A All output pads unload execute NOP instruction exclude LCD bias current, LPD off, WDT off AGC/ADC/FSK_CMP/Pre-amplifier OFF All output pads unload (HALT mode) exclude LCD Bias current, LPD off WDT off AGC, ADC, FSK_CMP, Pre-amplifier OFF All output pads unload (STOP mode), LCD off, LPD off WDT off, AGC, ADC, FSK_CMP, Pre-amplifier OFF WDT current Conditions Standby Current Sleep Current ISB1 ISB2 IWDT VIH1 VIL1 VIH2 VIL2 VOH1 VOL1 VOH2 VOL2 VOL3 RLCD RON ROH ROL IDD 0.7 X VDD -0.3 0.85 X VDD -0.3 0.7 X VDD VDD - 0.6 - 3 10 - 6 1 13 A A A t4U.com WDT current Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Output high voltage Output low voltage Output high voltage Output low voltage Output low voltage LCD Voltage Divider Resistor LCD Driving on resistor Pull high resistance Pull low resistance LCD lighting DataShee .com VDD + 0.3 V PORTA.3 - 1, PORTB - PORTF 0.3 X VDD VDD + 0.3 V V PORTA.3 - 1, PORTB - PORTF INT0 , RESET (Schmitt trigger input) INT0 , RESET (Schmitt trigger input) PORTA.3 - 0, PORTB (IOH = -2mA) PORTA.2 - 0, PORTB (IOL = 2mA) PORTC, PORTD, PORTE, PORTF (IOH = -1mA) PORTC, PORTD, PORTE, PORTF (IOH = 1mA) PORTA.3 (IOL = 10mA) 0.15 X VDD V 275 5 200 200 30 0.8 0.8 0.4 40 V V V V V k k LCD COM1 - 16, LCD SEG1 - 50, the voltage variation of V1, V2, V3, V4 is less than 0.2V k PORTA - F (IOH = -10A) k PORTA.0 (IOH = 10A) A VDD = 3V, LCD Pump Enable, no glass load, exclude CPU core operation current .com 50 DataSheet 4 U .com www..com SH67K93 Analog Electrical Characteristics (TA = -10 to 70C, VDD = 3.0V, GND = 0V) Parameter Single Row Tone Output Amplitude Single Column Tone Output Amplitude DTMF output distortion DTMF pre-emphasis Tip/Ring input impedance Input sensitivity of Tip and Ring Signal reject level DTMF sensitivity CAS sensitivity Symbol VOR VOC DIS% Twist RIN1 PSIG SRL SD SC 1 400 -46 -51 -38 -38 -54 -3 0 0 -2 +1 -11 Min. 590 795 Typ. 660 870 2 2 500 Max. 730 945 5 3 600 Unit mVp-p mVp-p % dB k dBm dBm dBm dBm 60Hz 550Hz 1200Hz 2200Hz 3300Hz Conditions With 100k pull-high resistor With 100k pull-high resistor With 100k pull-high resistor With 100k pull-high resistor Input frequency = 0 SNR = 15dB, GCR = 1110 GCR = 1110 Frequency response of the Band Pass Filter dB t4U.com AC Characteristics (VDD = 3.0V, GND = 0V, TA = 25, fOSC = 32.768kHz, unless otherwise specified) Parameter Oscillation Start Time Frequency Stability Symbol tSTT |f|/f Min. Typ. 2 Max. 5 Unit s Conditions 32.768kHz Crystal Oscillator DataShee .com 1 PPM [f(3.0) - f(2.5)]/f(3.0), 32.768kHz Crystal Oscillator AC Characteristics (VDD = 3.0V, GND = 0V, TA = 25, fOSC = 262kHz, fOSCX stop, unless otherwise specified) Parameter Oscillation Start Time Frequency Stability Symbol tSTT |f|/f Min. Typ. Max. 100 10 Unit s % Conditions 262kHz RC Oscillator [f(3.0) - f(2.5)]/f(3.0), Bias resistance accuracy within 1% .com 51 DataSheet 4 U .com www..com SH67K93 RC Oscillator Characteristics Graphs (for reference only) RC Oscillator Resistor (OSC) vs. Frequency (VDD = 3.0V) 450.0 OSC Frequency (kHz) 400.0 350.0 300.0 250.0 200.0 150.0 300 350 400 450 500 Resistor (k) 550 600 650 700 t4U.com DataShee .com RC Oscillator Resistor (OSCX) vs. Frequency (VDD = 3.0V) 3000.0 OSCX Frequency (kHz) 2000.0 1000.0 150 200 250 300 Resistor (k) 350 400 .com 52 DataSheet 4 U .com www..com SH67K93 RC Oscillator (OSC) Frequency vs. Voltage (R = 498k) 300.0 200.0 100.0 0.0 2.40 OSC Frequency (kHz) 2.60 2.80 3.00 VDD (V) 3.20 3.40 3.60 RC Oscillator (OSCX) Frequency vs. Voltage (R = 256k) t4U.com OSCX Frequency (kHz) 1900.0 1880.0 1860.0 1840.0 1820.0 1800.0 2.40 DataShee .com 2.60 2.80 3.00 VDD (V) 3.20 3.40 3.60 .com 53 DataSheet 4 U .com www..com SH67K93 Application Circuit (for reference only) VDD 1K L+ VDD Zener 1K L300 300 OPOUT 104 204 FILOUT C1+ AGCIN 3300p FILIN VDD Matching Network CASTIP DTMF 104/250V 100K RING VDD 104/250V TIP SH67K93 C1VP1 VP2 GND VDD AVDD /RESET 32.768k crystal VDD 474 474 474 104 100K VDD 104 104 15p 15p 10p 10p 47K 47K 680K t4U.com VDD S24 S25 S34 S35 I/O I/O I/O C1 - 8 S35 - 1 OSCXI OSCXO OSCI DataShee .com OSCO C16 - 9 3.579545M crystal 3.0 - 5.1M 12 X 3 keypads .com DataSheet 4 U .com LC 54 www..com SH67K93 Bonding Diagram SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 C1+ C1VP2 VP1 VDD TIP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SH67K93 Y 68 67 66 65 64 63 62 61 60 (0,0) X 59 58 57 56 55 54 53 52 51 50 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 COM8 COM7 COM6 COM5 COM4 COM3 AVDD 32 33 34 35 36 OSCXI OSCXO GND 37 49 48 38 39 40 41 42 43 44 45 46 47 PORTA2 PORTA1 PORTA0 PORTB3 PORTB2 PORTB1 PORTA3 PORTB0 COM1 COM2 25 26 27 28 29 30 31 CASTIP OPOUT DTMF RING RESET TEST OSCI t4U.com OSCO B1 B0 3087um SEG44 2839um DataShee Pad Location Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Designation SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 C1+ X -1285.4 -1285.4 -1285.4 -1285.4 -1285.4 -1285.4 -1285.4 -1285.4 -1285.4 -1285.4 -1285.4 -1285.4 -1285.4 -1285.4 -1285.4 -1285.4 -1285.4 -1285.4 -1285.4 -1285.4 .com Y 1410 1280 1150 1020 900 780 660 550 440 330 220 110 0 -110 -220 -330 -440 -550 -660 -780 Pad No. 21 22 23 24 25 26 27 28 29 30 31 Bonding Option 32 33 34 35 36 Bonding Option 37 38 Designation C1VP2 VP1 VDD TIP RING CASTIP OPOUT DTMF RESET TEST B1 AVDD OSCXI OSCXO OSCI OSCO B0 GND PORTA3 X -1285.4 -1285.4 -1285.4 -1285.4 -1285.4 -1155.4 -1025.4 -905.4 -785.4 -665.4 -555.4 -440 -440 -330 -220 -110 0 110 110 225.4 unit:m Y -900 -1020 -1150 -1280 -1410 -1410 -1410 -1410 -1410 -1410 -1410 -1410 -1314 -1410 -1410 -1410 -1410 -1410 -1314 -1410 .com 55 DataSheet 4 U .com www..com SH67K93 Pad Location (Continued) Pad No. 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 Designation PORTA2 PORTA1 PORTA0 PORTB3 PORTB2 PORTB1 PORTB0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 X 335.4 445.4 555.4 665.4 785.4 905.4 1025.4 1155.4 1285.4 1285.4 1285.4 1285.4 1285.4 1285.4 1285.4 1285.4 1285.4 1285.4 1285.4 1285.4 1285.4 1285.4 1285.4 1285.4 1285.4 1285.4 1285.4 Y -1410 -1410 -1410 -1410 -1410 -1410 -1410 -1410 -1410 -1280 -1150 -1020 -900 -780 -660 -549.7 -440 -220 -110 0 110 220 330 440 550 660 Pad No. 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 84 85 86 87 88 89 90 91 92 Designation SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 X 1285.4 1285.4 1285.4 1285.4 1285.4 1285.4 1155.4 1025.4 905.4 785.4 660 550 440 330 220 110 0 -110 -220 -330 -440 -550 -665.4 -785.4 -905.4 -1025.4 -1155.4 Y 779.65 900 1020 1150 1280 1410 1410 1410 1410 1410 1410 1410 1410 1410 1410 1410 1410 1410 1410 1410 1410 1410 1410 1410 1410 1410 1410 t4U.com DataShee -330 83 .com .com 56 DataSheet 4 U .com www..com SH67K93 Ordering Information Part No. SH67K93 Package CHIP t4U.com DataShee .com .com 57 DataSheet 4 U .com www..com SH67K93 Data Sheet Revision History Version 1.0 Original Content Date Dec. 2004 t4U.com .com .com 58 DataSheet 4 U .com |
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