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NTD60N02R Power MOSFET Features 62 A, 25 V, N-Channel, DPAK * * * * * * Planar HD3e Process for Fast Switching Performance Low RDS(on) to Minimize Conduction Loss Low Ciss to Minimize Driver Loss Low Gate Charge Optimized for High Side Switching Requirements in High-Efficiency DC-DC Converters Pb-Free Packages are Available http://onsemi.com V(BR)DSS 25 V RDS(on) TYP 8.4 mW @ 10 V ID MAX 62 A MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Rating Drain-to-Source Voltage Gate-to-Source Voltage - Continuous Thermal Resistance Junction-to-Case Total Power Dissipation @ TC = 25C Drain Current Continuous @ TC = 25C, Chip Continuous @ TC = 25C, Limited by Package Continuous @ TA = 25C, Limited by Wires Thermal Resistance Junction-to-Ambient (Note 1) Total Power Dissipation @ TA = 25C Drain Current - Continuous @ TA = 25C Thermal Resistance Junction-to-Ambient (Note 2) Total Power Dissipation @ TA = 25C Drain Current - Continuous @ TA = 25C Operating and Storage Temperature Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 50 Vdc, VGS = 10.0 Vdc, IL = 11 Apk, L = 1.0 mH, RG = 25 W) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VGS RqJC PD ID ID ID RqJA PD ID RqJA PD ID TJ, and Tstg EAS Value 25 20 2.6 58 62 50 32 80 1.87 10.5 120 1.25 8.5 -55 to 175 60 Unit Vdc Vdc G C/W W A A A 4 C/W W A C/W W A C mJ 12 3 N-Channel D S 4 4 1 23 1 2 3 CASE 369AC CASE 369AA 3 IPAK DPAK (Surface Mount) (Straight Lead) STYLE 2 CASE 369D DPAK (Straight Lead) STYLE 2 MARKING DIAGRAM & PIN ASSIGNMENTS 4 Drain YWW T60 N02R 4 Drain YWW T60 N02R 123 Gate Drain Source Publication Order Number: NTD60N02R/D TL 260 C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. When surface mounted to an FR4 board using 0.5 in sq drain pad size. 2. When surface mounted to an FR4 board using the minimum recommended pad size. 2 1 3 Drain Gate Source Y = Year WW = Work Week 60N02R = Device Code ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. (c) Semiconductor Components Industries, LLC, 2005 1 February, 2005 - Rev. 11 NTD60N02R ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (Note 3) (VGS = 0 Vdc, ID = 250 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 20 Vdc, VGS = 0 Vdc) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 150C) Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 3) Gate Threshold Voltage (Note 3) (VDS = VGS, ID = 250 mAdc) Threshold Temperature Coefficient (Negative) Static Drain-to-Source On-Resistance (Note 3) (VGS = 4.5 Vdc, ID = 15 Adc) (VGS = 10 Vdc, ID = 20 Adc) (VGS = 10 Vdc, ID = 31 Adc) Forward Transconductance (VDS = 10 Vdc, ID = 15 Adc) (Note 3) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 4) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Gate Charge (VGS = 4.5 Vdc, ID = 31 Adc, VDS = 10 Vdc) (Note 3) SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 20 Adc, VGS = 0 Vdc) (Note 3) (IS = 31 Adc, VGS = 0 Vdc) (IS = 15 Adc, VGS = 0 Vdc, TJ = 125C) Ad Vd 125 C) (IS = 31 Adc, VGS = 0 Vdc, dIS/dt = 100 A/ms) (Note 3) Reverse Recovery Stored Charge 3. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%. 4. Switching characteristics are independent of operating junction temperatures. VSD - - - - - - - 0.88 1.15 0 80 0.80 29.1 13.6 15.5 0.02 1.2 - - - - - - mC Vdc (VGS = 10 Vdc, VDD = 10 Vdc, ID = 31 Adc, RG = 3.0 W) td(on) tr td(off) tf QT QGS QGD - - - - - - - 7.0 33 19 9.0 9.5 2.2 5.0 - - - - 14 - - nC ns (VDS = 20 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Ciss Coss Crss - - - 1000 480 180 1330 640 225 pF VGS(th) 1.0 - RDS(on) - - - gFS - 11.2 8.4 8.2 27 12.5 10.5 - - Mhos 1.5 4.1 2.0 - Vdc mV/C mW V(BR)DSS 25 - IDSS - - IGSS - - - - 1.5 10 100 nAdc 27.5 25.5 - - Vdc mV/C mAdc Symbol Min Typ Max Unit Reverse Recovery Time trr ta tb Qrr ns http://onsemi.com 2 NTD60N02R TYPICAL CHARACTERISTICS 140 120 100 80 60 40 20 0 0 2 VGS = 10 V 8.0 V 6.0 V 4.2 V 4.0 V 3.8 V 3.6 V 3.4 V 3.2 V 3.0 V 2.8 V 4 6 TJ = 25C 5.0 V 4.5 V ID, DRAIN CURRENT (A) 120 100 80 60 40 VDS w 10 V ID, DRAIN CURRENT (A) TJ = 175C 20 0 TJ = 25C TJ = -55C 0 2 4 6 8 VGS, GATE-TO-SOURCE VOLTAGE (V) 2.6 V 2.4 V 8 10 VDS, DRAIN-TO-SOURCE VOLTAGE (V) Figure 1. On-Region Characteristics RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) 0.05 ID = 62 A TJ = 25C RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) 0.05 Figure 2. Transfer Characteristics TJ = 25C 0.04 0.04 0.03 0.03 0.02 0.02 VGS = 4.5 V VGS = 10 V 0.01 0.01 0 2 4 6 8 10 0 20 40 60 80 100 120 140 VGS, GATE-TO-SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A) Figure 3. On-Resistance versus Gate-to-Source Voltage RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 -50 10 0 ID = 31 A VGS = 10 V IDSS, LEAKAGE (nA) 10000 100000 Figure 4. On-Resistance versus Drain Current and Gate Voltage VGS = 0 V TJ = 175C 1000 100 TJ = 100C -25 0 25 50 75 100 125 150 175 6 12 18 24 TJ, JUNCTION TEMPERATURE (C) VDS, DRAIN-TO-SOURCE VOLTAGE (V) Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-to-Source Leakage Current versus Voltage http://onsemi.com 3 NTD60N02R VGS, GATE-TO-SOURCE VOLTAGE (V) 2000 Ciss C, CAPACITANCE (pF) 1500 VDS = 0 V 1000 Crss Coss 500 Crss 0 10 5 0 5 10 15 20 VGS = 0 V Ciss TJ = 25C 5 QT 4 QGS 3 VDS 2 8 QDS VGS 20 VDS, DRAIN-TO-SOURCE VOLTAGE (V) 16 12 1 ID = 31 A TJ = 25C 0 2 4 6 8 Qg, TOTAL GATE CHARGE (nC) 4 0 VGS VDS 0 10 GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (V) Figure 7. Capacitance Variation Figure 8. Gate-to-Source and Drain-to-Source Voltage versus Total Charge 1000 IS, SOURCE CURRENT (A) VDD = 10 V ID = 31 A VGS = 10 V 100 t, TIME (ns) tr tf td(on) 80 70 60 50 40 30 20 10 VGS = 0 V TJ = 25C td(off) 10 1 1 10 RG, GATE RESISTANCE (W) 100 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VSD, SOURCE-TO-DRAIN VOLTAGE (V) Figure 9. Resistive Switching Time Variation versus Gate Resistance Figure 10. Diode Forward Voltage versus Current 100 VGS = 20 V SINGLE PULSE 10 ms ID, DRAIN CURRENT (A) TC = 25C 100 ms 10 1 ms 10 ms RDS(ON) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1 10 dc 1 100 VDS, DRAIN-TO-SOURCE VOLTAGE (V) Figure 11. Maximum Rated Forward Biased Safe Operating Area http://onsemi.com 4 NTD60N02R r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) 1.0 D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE t1 t2 DUTY CYCLE, D = t1/t2 0.001 0.01 t, TIME (s) 0.1 P(pk) RqJC(t) = r(t) RqJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RqJC(t) 0.01 0.00001 0.0001 1 10 Figure 12. Thermal Response ORDERING INFORMATION Order Number NTD60N02R NTD60N02RG NTD60N02RT4 NTD60N02RT4G NTD60N02R-1 NTD60N02R-1G NTD60N02R-35 NTD60N02R-35G Package DPAK-3 DPAK-3 (Pb-Free) DPAK-3 DPAK-3 (Pb-Free) DPAK-3 Straight Lead DPAK-3 Straight Lead (Pb-Free) DPAK-3 Straight Lead (3.5 0.15 mm) DPAK-3 Straight Lead (3.5 0.15 mm) (Pb-Free) Shipping 75 Units / Rail 75 Units / Rail 2500 / Tape & Reel 2500 / Tape & Reel 75 Units / Rail 75 Units / Rail 75 Units / Rail 75 Units / Rail For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 5 NTD60N02R PACKAGE DIMENSIONS DPAK CASE 369AA-01 ISSUE O -T- B V R 4 SEATING PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.025 0.035 0.018 0.024 0.033 0.045 0.018 0.023 0.090 BSC 0.180 0.215 0.025 0.040 0.020 --- 0.035 0.050 0.155 --- MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.63 0.88 0.46 0.61 0.83 1.14 0.46 0.58 2.29 BSC 4.57 5.45 0.63 1.01 0.51 --- 0.89 1.27 3.93 --- C E A S 1 2 3 Z U F L D 2 PL J DIM A B C D E F J L R S U V Z 0.13 (0.005) M T STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN SOLDERING FOOTPRINT* 6.20 0.244 2.58 0.101 5.80 0.228 3.0 0.118 1.6 0.063 6.172 0.243 SCALE 3:1 mm inches *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 6 NTD60N02R PACKAGE DIMENSIONS 3 IPAK, STRAIGHT LEAD CASE 369AC-01 ISSUE O NOTES: 1.. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2.. CONTROLLING DIMENSION: INCH. 3. SEATING PLANE IS ON TOP OF DAMBAR POSITION. 4. DIMENSION A DOES NOT INCLUDE DAMBAR POSITION OR MOLD GATE. INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.043 0.090 BSC 0.034 0.040 0.018 0.023 0.134 0.142 0.180 0.215 0.035 0.050 0.000 0.010 MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.09 2.29 BSC 0.87 1.01 0.46 0.58 3.40 3.60 4.57 5.46 0.89 1.27 0.000 0.25 B V R C E A SEATING PLANE W F G K J H D 3 PL 0.13 (0.005) W DIM A B C D E F G H J K R V W http://onsemi.com 7 NTD60N02R PACKAGE DIMENSIONS DPAK CASE 369D-01 ISSUE B B V R 4 C E NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.180 0.215 0.025 0.040 0.035 0.050 0.155 --- MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.45 0.63 1.01 0.89 1.27 3.93 --- Z A 3 S -T- SEATING PLANE 1 2 K F D G 3 PL J H 0.13 (0.005) M DIM A B C D E F G H J K R S V Z T STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 61312, Phoenix, Arizona 85082-1312 USA Phone: 480-829-7710 or 800-344-3860 Toll Free USA/Canada Fax: 480-829-7709 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Phone: 81-3-5773-3850 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. http://onsemi.com 8 NTD60N02R/D |
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