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| www..com 88PG8x7 Family Field Programmable DSP SwitcherTM 1 MHz, 4.5A Peak Current-Limit Step-Down Regulator with AnyVoltageTM Technology Advance Datasheet, Patent Pending Doc. No. MV-S102867-00, Rev. F October 30, 2007 88PG8x7 www..com 1 MHz, 4.5A Peak Current-Limit Step-Down Regulator with AnyVoltageTM Technology Document Status Advance Information Preliminary Information Final Information Revision Code: Advance This document contains design specifications for initial product development. Specifications may change without notice. Contact Marvell Field Application Engineers for more information. This document contains preliminary data, and a revision of this document will be published at a later date. Specifications may change without notice. Contact Marvell Field Application Engineers for more information. This document contains specifications on a product that is in final release. Specifications may change without notice. Contact Marvell Field Application Engineers for more information. Rev. F Technical Publication: 0.31 No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, for any purpose, without the express written permission of Marvell. Marvell retains the right to make changes to this document at any time, without notice. Marvell makes no warranty of any kind, expressed or implied, with regard to any information contained in this document, including, but not limited to, the implied warranties of merchantability or fitness for any particular purpose. Further, Marvell does not warrant the accuracy or completeness of the information, text, graphics, or other items contained within this document. Marvell products are not designed for use in life-support equipment or applications that would cause a life-threatening situation if any such products failed. Do not use Marvell products in these types of equipment or applications. With respect to the products described herein, the user or recipient, in the absence of appropriate U.S. government authorization, agrees: 1) Not to re-export or release any such information consisting of technology, software or source code controlled for national security reasons by the U.S. Export Control Regulations ("EAR"), to a national of EAR Country Groups D:1 or E:2; 2) Not to export the direct product of such technology or such software, to EAR Country Groups D:1 or E:2, if such technology or software and direct products thereof are controlled for national security reasons by the EAR; and, 3) In the case of technology controlled for national security reasons under the EAR where the direct product of the technology is a complete plant or component of a plant, not to export to EAR Country Groups D:1 or E:2 the direct product of the plant or major component thereof, if such direct product is controlled for national security reasons by the EAR, or is subject to controls under the U.S. Munitions List ("USML"). At all times hereunder, the recipient of any such information agrees that they shall be deemed to have manually signed this document in connection with their receipt of any such information. Copyright (c) 2007. Marvell International Ltd. All rights reserved. Marvell, the Marvell logo, Moving Forward Faster, Alaska, Fastwriter, Datacom Systems on Silicon, Libertas, Link Street, NetGX, PHYAdvantage, Prestera, Raising The Technology Bar, The Technology Within, Virtual Cable Tester, and Yukon are registered trademarks of Marvell. Ants, AnyVoltage, Discovery, DSP Switcher, Feroceon, GalNet, GalTis, Horizon, Marvell Makes It All Possible, RADLAN, UniMAC, and VCT are trademarks of Marvell. All other trademarks are the property of their respective owners. Doc. No. MV-S102867-00 Rev. F Page 2 Document Classification: Proprietary Information Copyright (c) 2007 Marvell October 30, 2007, Advance www..com 88PG8x7 1 MHz, 4.5A Peak Current-Limit Step-Down Regulator with AnyVoltageTM Technology OVERVIEW The 88PG8x7 family is intelligent digital synchronous Step-Down (Buck) switching regulators with on-chip Low-Drop-Out (LDO) regulator controllers housed in a 3 mm X 3 mm QFN-16 package. Internally self-compensated, these step-down regulators require no external compensation and work with low-ESR output capacitors to simplify the design, minimize the board space, and reduce the amount of external components. The switching frequency for the step-down regulator is 1 MHz, allowing the use of low profile surface mount inductors and low value capacitors. The stepdown regulator includes programmable output voltage to provide the user the ability to easily set the output voltage with external resistors, logic control, or serial data interface. The output voltage range is 0.72V to 3.63V. The LDO regulator controller with an external P-Channel MOSFET forms a low dropout regulator capable of driving 800 mA output current. The output voltage of the LDO regulator is fixed. See the "Ordering Information" section for more details. Other key features of the 88PG8x7 family include soft start and auto power MOSFET detection for the LDO regulator controller, an internal current limit for the step-down regulator, an undervoltage lockout, thermal shutdown, over voltage protection, and a Power-On Reset (POR) signal. R6 4 0.047 oh m 3 R3 100k POR SDI 10 12 11 14 15 R5 10k R4 0 R2 0 U1 1 ILIM POR SDI 2 LDR 16 Q1 FDC642P FEATURES * * * * * * * * * * * * * * * * * Tiny 3 mm X 3 mm QFN-16 package 1 MHz Switching frequency Low quiescent current of 1.9 mA (typ.) Stable with ceramic output capacitors No external compensation required Over 95% efficiency Peak switch current limit up to 4.5A Input voltage range: 2.75V to 5.5V Serial / Logic Programmability Any VoltageTM Technology provides 64 output voltage selections to provide flexibility Programmable output voltage range: - 0.72V to 3.63V P-Channel LDO regulator controller with programmable current limit Lead-free Packages Built-in undervoltage lockout Over voltage protection Thermal shutdown protection Output voltage margining capability APPLICATION * * * 1, 2, 5, 6 C6 10uF/6.3V LFB SW SW SFB CG SGND 7 L1 5 1.3uH 3 4 13 C3 22uF/6.3V C4 Portable computing Disk drive power supplies 3.3V PCI Express Bus Vout2 3.3V/400mA (See Figure 12) SHDN VSET PSET 88PG847B Vout1 0.8V/3A 22uF/6.3V PVIN 8 R1 SVIN 9 PGND 6 Vin +5V C5 22uF/6.3V C2 22uF/6.3V 10 ohm C1 0.1uF Figure 1: Typical High Efficiency 5V to 0.8V/3A Step-Down Regulator Copyright (c) 2007 Marvell October 30, 2007, Advance Document Classification: Proprietary Information Doc. No. MV-S102867-00, Rev. F Page 3 88PG8x7 www..com 1 MHz, 4.5A Peak Current-Limit Step-Down Regulator with AnyVoltageTM Technology Table of Contents SECTION 1. 1.1 1.2 1.3 SIGNAL DESCRIPTION................................................................. 10 Pin Configuration .........................................................................................................10 Pin Type Definitions .....................................................................................................11 Pin Description .............................................................................................................11 SECTION 2. 2.1 2.2 2.3 2.4 2.5 ELECTRICAL SPECIFICATIONS ..................................................... 13 Absolute Maximum Ratings ........................................................................................13 Recommended Operating Conditions ........................................................................13 Electrical Characteristics.............................................................................................14 Switching Step-down Regulator .................................................................................15 LDO Regulator Controller ............................................................................................17 SECTION 3. 3.1 3.2 3.1.1 FUNCTIONAL DESCRIPTION ......................................................... 18 Digital Soft Start................................................................................................................ 19 Regulation and Start-up...............................................................................................18 Output Voltage Setting.................................................................................................21 3.2.1 3.2.2 3.2.3 Serial Programmability ..................................................................................................... 21 Logic Programmability ...................................................................................................... 22 Output Voltage - AnyVoltageTM Technology .................................................................... 23 3.3 3.4 3.5 3.6 3.7 3.8 3.9 Programmable Current Limit for the LDO Regulator Controller ..............................26 3.3.1 Maximum LDO Output Current......................................................................................... 27 Undervoltage Lockout (UVLO) ....................................................................................27 Over Voltage Protection (OVP)....................................................................................28 Power-On Reset (POR).................................................................................................29 Thermal Shutdown .......................................................................................................30 Adaptive Transient Response .....................................................................................30 Using Ceramic Input Capacitors .................................................................................31 3.10 Sequential Power up ....................................................................................................32 3.11 Disable the LDO Function............................................................................................34 Doc. No. MV-S102867-00, Rev. F Page 4 Document Classification: Proprietary Information Copyright (c) 2007 Marvell October 30, 2007, Advance www..com SECTION 4. 4.1 4.2 4.3 4.4 FUNCTIONAL CHARACTERISTICS..................................................35 Start-up Waveforms ..................................................................................................... 35 Short-Circuit Waveforms............................................................................................. 36 Switching Waveforms.................................................................................................. 37 Load Transient Waveforms ......................................................................................... 39 4.4.1 4.4.2 Step-Down Regulator ....................................................................................................... 39 LDO Regulator ................................................................................................................. 41 4.5 4.6 Output Voltage Transient Waveforms........................................................................ 42 4.5.1 Step-Down Regulator ....................................................................................................... 42 Line Transient Waveforms .......................................................................................... 43 SECTION 5. 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.1.1 TYPICAL CHARACTERISTICS ........................................................44 Efficiency Graphs in log scale .......................................................................................... 44 Efficiency Graphs ........................................................................................................ 44 Load Regulation ........................................................................................................... 44 Dropout Voltage ........................................................................................................... 45 RDS (ON) Resistance................................................................................................... 45 IC Case and Inductor Temperature ............................................................................ 46 P-Channel MOSFET (FDS642P) Thermal Characteristics ........................................ 47 Input Voltage Graphs................................................................................................... 48 5.7.1 5.7.2 Step-Down Regulator ....................................................................................................... 49 LDO Regulator ................................................................................................................. 50 5.8 Temperature Graphs.................................................................................................... 51 5.8.1 5.8.2 Step-Down Regulator ....................................................................................................... 52 LDO Regulator ................................................................................................................. 54 SECTION 6. 6.1 6.2 6.1.1 APPLICATIONS INFORMATION ......................................................55 PC Board Layout Examples for 88PG8x7 ........................................................................ 58 PC Board Layout Considerations and Guidelines for 88PG8x7 .............................. 55 Bill of materials for 88PG8x7 ...................................................................................... 60 SECTION 7. 7.1 7.2 7.3 MECHANICAL DRAWING ..............................................................65 88PG8x7 Mechanical Drawing .................................................................................... 65 Dimensions................................................................................................................... 66 Typical Pad Layout Dimensions ................................................................................. 67 Copyright (c) 2007 Marvell October 30, 2007, Advance Document Classification: Proprietary Information Doc. No. MV-S102867-00, Rev. F Page 5 88PG8x7 www..com 1 MHz, 4.5A Peak Current-Limit Step-Down Regulator with AnyVoltageTM Technology 7.3.1 Recommended Solder Pad Layout................................................................................... 67 SECTION 8. 8.1 8.2 8.3 ORDERING INFORMATION............................................................ 68 Ordering Part Numbers and Package Markings ........................................................68 Sample Ordering Part Number ....................................................................................69 Package Marking ..........................................................................................................69 8.3.1 Sample Package Marking and Pin 1 Locations ................................................................ 69 Doc. No. MV-S102867-00, Rev. F Page 6 Document Classification: Proprietary Information Copyright (c) 2007 Marvell October 30, 2007, Advance www..com List of Tables Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Table 12: Table 13: Table 14: Table 15: Table 16: Table 17: Table 18: Product Selector Table ..........................................................................................................................10 Pin Type Definitions ..............................................................................................................................11 Pin Description ......................................................................................................................................11 Default Value of Data Field ...................................................................................................................22 Voltage and Percentage Set .................................................................................................................22 Output Voltage Setting ..........................................................................................................................22 Any Voltage Programming Table for 1% Resistors ..............................................................................23 Any Voltage Programming Table for 5% Resistors ..............................................................................24 Output Voltage Option Steps.................................................................................................................25 P-Channel MOSFET Selection..............................................................................................................26 88PG847 BOM ......................................................................................................................................60 88PG837 BOM ......................................................................................................................................60 88PG827 BOM ......................................................................................................................................61 88PG817 BOM ......................................................................................................................................62 88PG807 BOM ......................................................................................................................................63 LDO Option BOM ..................................................................................................................................63 Ceramic Capacitor Cross Reference.....................................................................................................64 88PG8x7 Ordering Part Numbers .........................................................................................................69 Copyright (c) 2007 October 30, 2007, Advance Document Classification: Proprietary Information Doc. No. MV-S102867-00 Rev. F Page 7 88PG8x7 1 MHz, 4.5A Peak Current-Limit Step-Down Regulator with AnyVoltageTM Technology www..com List of Figures Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: Figure 16: Figure 17: Figure 18: Figure 19: Figure 20: Figure 21: Figure 22: Figure 23: Figure 24: Figure 25: Figure 26: Figure 27: Figure 28: Figure 29: Figure 30: Figure 31: Figure 32: Figure 33: Figure 34: Figure 35: Figure 36: Figure 37: Figure 38: Figure 39: Figure 40: Typical High Efficiency 5V to 0.8V/3A Step-Down Regulator ............................................................... 3 88PG8x7 Family 3X3 mm QFN-16 Package - Top View .................................................................... 10 88PG8x7 Block Diagram..................................................................................................................... 18 Output Voltage Window ...................................................................................................................... 19 Soft Startup ......................................................................................................................................... 20 Soft Startup ......................................................................................................................................... 20 Inductor Current Steps at Startup ....................................................................................................... 20 First Switching Cycle........................................................................................................................... 20 Serial Programmability........................................................................................................................ 21 Startup Sequence .............................................................................................................................. 25 Soft Startup ......................................................................................................................................... 25 Maximum Output Current for the FDS642P P-Channel MOSFET...................................................... 27 UVLO and OVP Waveforms ............................................................................................................... 28 Power-On Reset Waveforms .............................................................................................................. 29 Adaptive Transient Response ............................................................................................................ 30 Inrush with 22 F Ceramic .................................................................................................................. 31 Inrush with 22 F Ceramic + 100 F TA ............................................................................................ 31 Start-Up Waveforms of two 88PG847 devices ................................................................................... 32 Power Sequence of Two 88PG8x7 devices........................................................................................ 33 88PG847B device without LDO Output .............................................................................................. 34 Startup Using the Shutdown Pin ........................................................................................................ 35 Turn Off Using the Shutdown Pin ....................................................................................................... 35 Startup Sequence .............................................................................................................................. 35 Soft Startup ......................................................................................................................................... 35 UVLO and OVP Thresholds................................................................................................................ 36 Step-Down Short-Circuit Response ................................................................................................... 36 LDO Short-Circuit Response .............................................................................................................. 36 Switching Waveforms - PWM mode .................................................................................................. 37 Switching Waveforms - PWM mode ................................................................................................... 37 Switching Waveforms - DCM Mode ................................................................................................... 37 Switching Waveforms - DCM Mode-Zoom.......................................................................................... 37 PWM Output Ripple Voltage .............................................................................................................. 38 Fast Load Rise Time .......................................................................................................................... 39 Slow Load Rise Time .......................................................................................................................... 39 Fast Load Fall Time ........................................................................................................................... 39 Slow Load Fall Time ........................................................................................................................... 39 Load Transient Response .................................................................................................................. 40 Double-Pulsed Load Response .......................................................................................................... 40 Load Transient Response .................................................................................................................. 40 Double-Pulsed Load Response .......................................................................................................... 40 Doc. No. MV-S102867-00 Rev. F Page 8 Document Classification: Proprietary Information Copyright (c) 2007 Marvell October 30, 2007, Advance www..com Figure 41: Figure 42: Figure 43: Figure 44: Figure 45: Figure 46: Figure 47: Figure 48: Figure 49: Figure 50: Figure 51: Figure 52: Figure 53: Figure 54: Figure 55: Load Transient Response .................................................................................................................. 41 VOUT = 1.0V to 1.2V with No Load .................................................................................................... 42 VOUT = 1.0V to 1.5V with No Load ..................................................................................................... 42 VOUT = 1.0V to 1.2V with ILOAD = 3A.................................................................................................. 42 VOUT = 1.0V to 1.2V with ILOAD = 3A.................................................................................................. 42 VOUT = 1.2V to 1.0V with ILOAD = 3A.................................................................................................. 43 VOUT = 1.5V to 1.0V with ILOAD = 3A.................................................................................................. 43 Line Transient @ VIN = 3.6 ................................................................................................................ 43 Line Transient @ VIN = 4.5 ................................................................................................................. 43 Simplified Schematic .......................................................................................................................... 56 88PG8x7 PCB Board Schematic ........................................................................................................ 57 Top Silk-Screen, Top Traces, Vias and Copper (Not to scale)........................................................... 58 Bottom Silk Screen, Bottom Trace, Vias, and Bottom Copper (Not to scale) ..................................... 59 Sample Part Number .......................................................................................................................... 68 88PG847 Package Marking and Pin 1 Location ................................................................................. 69 Copyright (c) 2007 Marvell October 30, 2007, Advance Document Classification: Proprietary Information Doc. No. MV-S102867-00 Rev. F Page 9 88PG8x7 1 MHz, 4.5A Peak Current-Limit Step-Down Regulator with AnyVoltageTM Technology www..com Table 1 provides information about other devices from the same product family. Table 1: Product Selector Table Peak Cu rre nt Li mi t 4.5A 3.0A 2.5A 1.5A 0.75A DC Loading 3.0A 2.0A 1.6A 1.0A 0.5A Part Num ber 88PG847x 88PG837x 88PG827x 88PG817x 88PG807x The devices listed in Table 1 have the same input and output voltage range for the step-down regulator. Section 1. Signal Description 1.1 Pin Configuration Figure 2: 88PG8x7 Family 3X3 mm QFN-16 Package - Top View LFB 16 PSET 15 VSET 14 SGND 13 ILIM 1 12 SDI LDR 2 11 SHDN SFB 3 10 POR CG 4 9 SVIN 5 SW 6 PGND 7 SW 8 PVIN Doc. No. MV-S102867-00 Rev. F Page 10 Document Classification: Proprietary Information Copyright (c) 2007 Marvell October 30, 2007, Advance Signalwww..com Description Pin Type Definitions 1.2 Pin Type Definitions Table 2: P in Typ e I O S NC GND Pin Type Definitions D ef in i t io ns Input only Output only Supply Not Connected Ground 1.3 Pin Description Table 3 provides pin descriptions for the 88PG8x7. Table 3: Pin # 1 Pin Description Pi n Na me ILIM Pi n Ty pe I Pin Fu nc ti o n Current-Limit Sense Pin for the LDO Regulator A built-in offset of 50 mV (typical) between SVIN and ILIM in conjunction with the sense resistor is used to set the current-limit threshold for the LDO regulator controller. Connecting this pin to SVIN disables the internal current limit circuitry. When the LDO controller is not used, the LDR pin must be left floating, the LFB pin must be connected to GND, and connect ILIM to VIN. This will reduce the supply current. LDO Regulator Controller Driver Connect to the gate of an external P-channel MOSFET. The external P-Channel MOSFET needs to have a threshold of -2.5V or -1.8V and input capacitance (Ciss) of less than 1000 pF. When the LDO controller is not used, the LDR pin must be left floating, the LFB pin must be connected to GND, and connect ILIM to VIN. This will reduce the supply current. Switching Regulator Feedback Senses the output voltage of the switching regulator. Connect to Ground This pin must be connected to ground. Switch Node Internal power MOSFET drain. This pin must connect to an external inductor. Power Ground The power ground must connect to the negative terminal of the input and output capacitors. 2 LDR O 3 4 5,7 SFB CG SW I I O 6 PGND GND Copyright (c) 2007 Marvell October 30, 2007, Advance Document Classification: Proprietary Information Doc. No. MV-S102867-00 Rev. F Page 11 88PG8x7 1 MHz, 4.5A Peak Current-Limit Step-Down Regulator with AnyVoltageTM Technology www..com Table 3: Pin # 8 Pin Description (Continued) Pi n Na me PVIN Pi n Ty pe S Pin Fu nc ti o n Power Input Voltage Internal power MOSFET source. Connect the decoupling capacitors between PVIN and PGND and position it as close as possible to the IC. Signal Input Voltage The input voltage is 2.75V to 5.5V for internal circuitry. Connect a 0.1 F decoupling capacitor between SVIN and SGND and position it as close as possible to the IC. Power-On Reset Power-On Reset is an open drain output to indicate the status of the output voltage. The output pin goes high 40 ms after the output voltage is within the specified tolerance. Shutdown Logic high (> 2.0V) disables the switching step-down regulator and the LDO regulator controller. In shutdown, the switch node for the step-down regulator is high impedance. Logic low (< 0.8V) enables the step-down switching regulator and the LDO regulator controller. The high signal has to be at least 20 s to disable both regulators. Serial Data Input: The input data into this pin is used to program the output voltage (see section 3.2). This pin must be connected to ground if not used. Signal ground: This pin must connect to the power ground. Voltage Set 1) This is used for selecting the output voltage level, when it is connected to SGND or SVIN in conjunction with PSET connection to SGND or SVIN. 2) Connect to an external resistor to ground to set the output voltage of the step-down switching regulator. See the "Electrical Characteristics" table for resistor values and Output Voltage Setting section. The total capacitance across this pin and SGND should be equal to 25 pF or less. Use resistors with tolerance 5% or better. Percent Set 1) This is used for selecting the output voltage level when it is connected to SGND or SVIN in conjunction with VSET connection to SGND or SVIN. 2) Connect an external resistor to ground to set the output voltage of the step-down switching regulator. See the "Electrical Characteristics" table for resistor values and Output Voltage Setting section. Use resistor value with tolerance 5% or better. LDO Regulator Controller Feedback Sense the output voltage of the LDO regulator. Connect to the drain of the P-channel MOSFET. When the LDO controller is not used, the LDR pin must be left floating, the LFB pin must be connected to GND, and connect ILIM to SVIN. This will reduce the supply current. 9 SVIN S 10 POR O 11 SHDN I 12 SDI I 13 14 SGND VSET GND I 15 PSET I 16 LFB I Doc. No. MV-S102867-00 Rev. F Page 12 Document Classification: Proprietary Information Copyright (c) 2007 Marvell October 30, 2007, Advance Absolute Maximum Ratings Electrical Specifications www..com Section 2. Electrical Specifications 2.1 Absolute Maximum Ratings1 P a r am e t e r Signal Input Voltage to SGND = PGND Power Input Voltage to SGND = PGND Switch Voltage to SGND = PGND Switching Regulator Feedback Voltage to SGND = PGND Voltage Set to SGND = PGND Percentage Set Voltage to SGND=PGND Current Limit Voltage to SGND=PGND LDO Regulator Controller Driver Voltage to SGND=PGND LDO Regulator Controller Feedback Voltage to SGND=PGND Shutdown Voltage to SGND = PGND POR Voltage to SGND = PGND SDI Voltage to SGND = PGND Operating Temperature Range2 Maximum Junction Temperature Storage Temperature Range ESD Rating3 Symbol SVIN PVIN VSW VSFB VVSET VPSET VILIM VLDR VLFB VSHDN VPOR VSDI TOP TJMAX TSTOR Range -0.3 to 6.0 -0.3 to 6.0 -0.3 to (SVIN +0.3) -0.3 to (SVIN +0.3) -0.3 to (SVIN +0.3) -0.3 to (SVIN +0.3) -0.3 to (SVIN +0.3) -0.3 to (SVIN +0.3) -0.3 to (SVIN +0.3) -0.3 to (SVIN +0.3) -0.3 to (SVIN +0.3) -0.3 to (SVIN +0.3) -40 to 85 125 -65 to 150 2 U n its V V V V V V V V V V V V C C C kV 1. Exceeding the absolute the maximum rating may damage the device 2. Specifications over the -40 C to 85 C operating temperature ranges are assured by design, characterization and correlation with statistical process controls 3. Devices are ESD sensitive. Handling precautions recommended. Human body model, 1.5 k in series with 100 pF 2.2 Recommended Operating Conditions1 P a r am e t e r Signal Input Voltage Power Input Voltage Package Thermal Resistance2 Symbol SVIN PVIN JA JC 1. This device is not guaranteed to function outside the specified operating range 2. Test on 4-layer (JESD51-7) and vias (JESD51-5) board Range 2.75 to 5.5 2.75 to 5.5 70 19 U n its V V C/W C/W Copyright (c) 2007 Marvell October 30, 2007, Advance Document Classification: Proprietary Information Doc. No. MV-S102867-00 Rev. F Page 13 88PG8x7 1 MHz, 4.5A Peak Current-Limit Step-Down Regulator with AnyVoltageTM Technology www..com 2.3 Electrical Characteristics The following applies unless otherwise noted: SVIN = PVIN = VVSET = VPSET = 5.0V, VOUT = 1.5V, VSHDN = VCG = SGND = PGND, L (BUCK) = 1.3 H, COUT (BUCK) = 2 x 22 F (Ceramic), PFET= FDC642P, COUT (LDO) = 10 F (Ceramic), TA = 25 C. Bold values indicate -40 C < TA < 85 C. Pa r a m e te r Signal Input Voltage Range Power Input Voltage Range Total Quiescent Current S y m b ol SVIN PVIN C o nd i ti on s SVIN = PVIN Min 2.75 2.75 Ty p e Max 5.5 5.5 U n i ts V V mA mA No load, with LDO No load, Without LDO, VLIM = PVIN, VLDR = Float, VLFB = 0V 1.9 1.2 Shutdown Supply Current Undervoltage Lockout ISVIN VUVLO VSHDN = SVIN = 5.0V High threshold, SVIN increasing Low threshold, SVIN decreasing 1 2.65 2.55 5.7 5.6 50 2.70 2.60 A V V V V Over-voltage Protection VOVP High threshold, SVIN increasing Low threshold, SVIN decreasing Shutdown Threshold Voltage VSHDN Enable regulators Disable regulators 2.0 0.8 V V Shutdown Pin Input Current ISHDN VSHDN = 5.0V VSHDN = 0V 5.0 5.0 150 105 A A C C Over-temperature Thermal Shutdown TOTS TJ increasing (Disable regulators) TJ decreasing (Enable regulators) Doc. No. MV-S102867-00 Rev. F Page 14 Document Classification: Proprietary Information Copyright (c) 2007 Marvell October 30, 2007, Advance Switching Step-down Regulator Electrical Specifications www..com 2.4 Switching Step-down Regulator The following applies unless otherwise noted: SVIN = PVIN = VVSET = VPSET = 5.0V, VOUT = 1.5V, VSHDN = VCG = SGND = PGND, L = 1.3 H, COUT = 2 x 22 F (Ceramic), TA = 25 C. Bold values indicate -40 C < TA < 85 C. Pa r a m e te r Output Voltage S y m b ol C o nd i ti on s RVSET = 11K, PWM mode VVSET = SGND, VPSET = SGND, PWM mode RVSET = 18.7K, PWM mode VVSET = SGND, VPSET = SVIN, PWM mode RVSET = 31.6K, PWM mode VVSET = SVIN, VPSET = SGND, PWM mode RVSET = 53.6K, PWM mode VVSET = SVIN, VPSET = SVIN, PWM mode RVSET = 97.6K, PWM mode RVSET = 165K, PWM mode RVSET = 280K, PWM mode RVSET = 475K, PWM mode M in Ty p 0.8 Max U n its 1.0 1.2 V 1.5 1.8 2.5 3.0 3.3 -10 -7.5 -5 -2.5 2.5 5 7.5 10 0.10 % 0.10 % % Percentage Set RPSET = 11K RPSET = 18.7K RPSET = 31.6K RPSET = 53.6K RPSET = 97.6K RPSET = 165K RPSET = 280K RPSET = 475K Output Voltage Line Regulation Output Voltage Load Regulation VLNREG SVIN = PVIN = 3.0V to 5.0V VOUT = 1.5V ILOAD = IOUT(MAX)/4 SVIN = PVIN = 5.0V VOUT = 1.5V ILOAD = IOUT(MAX)/4 to IOUT(MAX) PWN mode VLDREG Switching Frequency fSW 0.9 MHz Copyright (c) 2007 Marvell October 30, 2007, Advance Document Classification: Proprietary Information Doc. No. MV-S102867-00 Rev. F Page 15 88PG8x7 1 MHz, 4.5A Peak Current-Limit Step-Down Regulator with AnyVoltageTM Technology www..com 2.4 Switching Step-down Regulator (Continued) The following applies unless otherwise noted: SVIN = PVIN = VVSET = VPSET = 5.0V, VOUT = 1.5V, VSHDN = VCG = SGND = PGND, L = 1.3 H, COUT = 2 x 22 F (Ceramic), TA = 25 C. Bold values indicate -40 C < TA < 85 C. Pa r a m e te r Minimum Peak Switch Current Limit S y m b ol ILIM C o nd i ti on s 88PG847 88PG837 88PG827 88PG817 88PG807 M in Ty p 4.5 3.0 2.5 1.5 0.75 Max U ni ts A Output Current IOUT 88PG847 L = 1.3 H 88PG837 L = 2.0 H 88PG827 L = 3.3 H 88PG817 L = 4.7 H 88PG807 L = 4.7 H 3.0 2.0 1.6 1.0 0.5 1 1 VOUT* 90% VOUT130 mV 0.4 1 40 V 50 A Switch Leakage Current ILSW SVIN = PVIN = VSHDN = 5.0V VSW = 5V SVIN = PVIN = VSHDN = 5.0V VSW = 0V A Power-On Reset Threshold Voltage VPORTH VOUT > 1.35V VOUT < 1.32V V Power-On Reset Output Low Voltage Power-On Reset Leakage Current Power-On Reset Delay VPORL IPOR tRESET ISINK = 2 mA, VSHDN = SGND = PGND VSHDN = 5.0V A ms Doc. No. MV-S102867-00 Rev. F Page 16 Document Classification: Proprietary Information Copyright (c) 2007 Marvell October 30, 2007, Advance Electrical Specifications www..com LDO Regulator Controller 2.5 LDO Regulator Controller The following applies unless otherwise noted: SVIN = PVIN = 5.0V, VSHDN = SGND = PGND, PFET= FDC642P, COUT (LDO) = 10 F, TA = 25 C. Bold values indicate -40 C < TA < 85 C. Pa r a m e te r 88PG8X7B Output Voltage 88PG8X7E Output Voltage Output Voltage S y m b ol VOUT VOUT C o nd i ti on s ILOAD = 10 mA ILOAD = 10 mA Room Temp, ILOAD = 10 mA Over Temp, ILOAD = 10 mA M in Ty pe 3.3 2.5 1 Max U n its V V % 2 0.1 % Line Regulation VLNREG SVIN = PVIN = 3.5V to 5.0V, VOUT = 3.3V, ILOAD = 10 mA SVIN = PVIN = 5.0V, VOUT = 3.3V, ILOAD = 10 mA to 800 mA SVIN-VILIM Load Regulation VLDREG 0.1 % Current-Limit Threshold VILTH 50 mV Copyright (c) 2007 Marvell October 30, 2007, Advance Document Classification: Proprietary Information Doc. No. MV-S102867-00 Rev. F Page 17 88PG8x7 1 MHz, 4.5A Peak Current-Limit Step-Down Regulator with AnyVoltageTM Technology www..com Section 3. Functional Description Figure 3: 88PG8x7 Block Diagram Vin 2.75V to 5.5V C2 C1 R1 R6 SVIN INTERNAL CIRCUITRY POWER SUPPLY PVIN LDO UVLO OSCILLATOR CURRENT LIMIT LDO Enable ILIM LDR LDO Controller Q1 SHDN OFF ON LFB C6 Vout2 67 m ANALOGDIGITAL CONVERTER Serial Data Interface DSP PWM CONTROL 21 m L1 SW PGND Vout 1 C3 SDI R5 BAND-GAP VOLTAGE REFERENCE THERMAL SHUTDOWN 150C FAULT UNDERVOLTAGE LOCKOUT RESISTOR NETWORK PGood LDO UVLO RESISTOR SENSING CIRCUITRY 25us/40ms Vin SFB R3 POR VPOR LDO Enable SGND CG VSET R4 PSET R2 3.1 Regulation and Start-up The step-down switching regulator uses Pulse Width Modulation (PWM) and Pulse Frequency Modulation (PFM) modes to regulate the output voltage using digital control. The mode of operation depends on the level of output current and the output voltage. In steady states, the step-down switching regulator monitors the current flowing through the inductor to determine if the regulator is handling heavy or light load applications. For heavy load applications, the step-down regulator operates in the PWM mode (B and C) to minimize the ripple current for optimum efficiency and to minimize the ripple output voltage. The step-down regulator operates in the PFM and Discontinuous Conduction Mode (DCM) (A) to limit the switching actions for optimum efficiency in light load applications. In this mode, the average output voltage is slightly higher than the average output voltage for heavy transient load applications. Doc. No. MV-S102867-00 Rev. F Page 18 Document Classification: Proprietary Information Copyright (c) 2007 Marvell October 30, 2007, Advance Functionalwww..com Description Regulation and Start-up Figure 4: Output Voltage Window Typical V OUT A B C D PFM Mode PWM Mode PFM Mode 3.1.1 Digital Soft Start During start-up, the 88PG8x7 provides a soft start function. Soft start reduces surge currents from input voltage and provides well-controlled output voltage rise characteristics. Figure 5 shows that the rise time for a 88PG8x7 increases from 20 s at for a 0.8V output to 70 s for a 3.3V output with a 20 mA load. Higher load current or larger output capacitance will increase the rise time. The load current is increased to 3A (1.1 ohms) in Figure 6. The 3.3V output rise time nearly doubles to 130 s with this load. The 88PG8x7 has an internal switch current limit that operates on a cycle-by-cycle basis and limits the peak switch current. During soft start, the current limit threshold begins at approximately 34% of the peak current limit threshold and ramps to 100% in 7 steps at 25 s per step (see Figure 7). During the switch first cycle, the highside switch stays on until the switch current reaches the first current limit threshold (see Figure 8) which takes less than 1 s. Then, the high-side switch turns off for a fixed off-time. If the output voltage is still low in 25 s, then the current limit threshold increases to the next level. As can be seen from Figure 4, only 25 s or 1 current step is required for the output to reach 0.8V and 75 s or 3 current steps for 3.3V. During soft start, the 88PG8x7 feeds a relatively constant current to the output capacitor in the first two steps. The average switch current during this period is approximately 2A. If more then 2 steps are required, then the switch current limit (ILIM) will need to increase. The output voltage rise time is dependent on the value of the output capacitor, the output voltage, the load current (IOUT), and the internal switch current limit circuitry and can be calculated using the following equation. ( C OUT x V OUT ) Rise Time = -------------------------------------( I LIM - I OUT ) 2 x 22F x 3.3V = ---------------------------------------2.0A - 0A = 72.6S Copyright (c) 2007 Marvell October 30, 2007, Advance Document Classification: Proprietary Information Doc. No. MV-S102867-00 Rev. F Page 19 88PG8x7 1 MHz, 4.5A Peak Current-Limit Step-Down Regulator with AnyVoltageTM Technology www..com Figure 5: Soft Startup (0.8V, 1.2V, 1.8V, 2.5V, 3.3V) VOUT VBUCK 500 mV/DIV Figure 6: Soft Startup 1V/DIV IOUT 1A/DIV 10 s/DIV ILOAD = 20 mA COUT = 2 x 22 F VOUT = 3.3V ILOAD = 1.1 50 s/DIV Figure 7: Inductor Current Steps at Startup Figure 8: First Switching Cycle VBUCK 1V/DIV VSW VOUT 2V/DIV 500 mV/DIV IIND IIND 2A/DIV 1A/DIV 50 s/DIV ILOAD = Heavy Load 500 ns/DIV Doc. No. MV-S102867-00 Rev. F Page 20 Document Classification: Proprietary Information Copyright (c) 2007 Marvell October 30, 2007, Advance Functionalwww..com Description Output Voltage Setting 3.2 Output Voltage Setting 3.2.1 Serial Programmability The output voltage of the step-down switching regulator can also program by using 18-bit serial data into the SDI pin. Figure 9: Serial Programmability WRITE MODE Start Chip Select Registor Address DATA FIELD Stop "1" Pulse "0" "0" "1" pulse Pulse pulse "1" Pulse "0" "0" "0" "1" pulse pulse Pulse pulse "1" Pulse The period of a pulse is 1 s +/- 200 ns VHIGH > 2.4V VLow < 0.8V D7 BIT 7 D6 BIT 6 D5 BIT 5 D4 BIT 4 D3 BIT 3 D2 BIT 2 D1 BIT 1 D0 BIT 0 "1" pulse The write operation: 1) 2) 3) be Each write sequence needs 18 pulses to complete. During a non-write operation, the input needs to be at VLOW (<0.8V). In between two successive write operations, the SDI input needs to at VLOW (<0.8V) for a minimum of 10 s VHIGH VLOW For "1" pulse, the high is 0.75 s +/- 150 ns and the low period is 0.25 s+/-50 ns "0" pulse 1st Write sequence Low for at least 10 s 2nd Write sequence VLOW VHIGH For "0" pulse, the high is 0.25 s +/- 50 ns and the low period is 0.75 s+/-150 ns Copyright (c) 2007 Marvell October 30, 2007, Advance Document Classification: Proprietary Information Doc. No. MV-S102867-00 Rev. F Page 21 88PG8x7 1 MHz, 4.5A Peak Current-Limit Step-Down Regulator with AnyVoltageTM Technology www..com The first 4 bits (MSB-bits) of the data field are used to select the output voltage where the second 4 bits (LSB-bits) of the data field are used to trim the output voltage (percent of output voltage). The default value for the data field is as follows: Table 4: Default Value of Data Field Data Field Description Bits Default Value Voltage Set 7 0 6 0 5 1 4 0 Percent Set 3 0 2 1 1 0 0 0 On power up, the output voltage is set according to VPSET and VVSET. The output voltage can then be field programmed by setting bit 3 and bit 7 to "1". The output voltage and percent set are selected according to Table 5. Table 5: Voltage and Percentage Set Data Field V OUT (V) 4 0 1 0 1 0 1 0 1 0.8 1.0 1.2 1.5 1.8 2.5 3.0 3.3 Data Field 3 1 1 1 1 1 1 1 1 Perce nt Set 0 0 1 0 1 0 1 0 1 -10% -7.5% -5.0% -2.5% +2.5% +5.0% +7.5% +10% Bits Value 7 1 1 1 1 1 1 1 1 6 0 0 0 0 1 1 1 1 5 0 0 1 1 0 0 1 1 2 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 All combinations of the VSET (Table 7) can be used with all combinations of the PSET (Table 7) to provide maximum flexibility in output voltage selection (Table 5). 3.2.2 Logic Programmability The output voltage of the step-down switching regulator can be programmed by connecting VSET and PSET pins to SGND and/or SVIN. This can be very useful for standard output voltages. This method will eliminate the use of an external resistor to set the output voltage. Table 6: V VSET SGND SGND SVIN SVIN SGND Output Voltage Setting V PSET SGND SVIN SGND SVIN 11 k < RPSET< 475 k V OUT 0.8V 1.0V 1.2V 1.5V Hi-Z Doc. No. MV-S102867-00 Rev. F Page 22 Document Classification: Proprietary Information Copyright (c) 2007 Marvell October 30, 2007, Advance Functionalwww..com Description Output Voltage Setting 3.2.3 Output Voltage - AnyVoltageTM Technology The output voltage of the step-down switching regulator is programmed by using Table 7 or Table 8 to select resistor values for VSET and PSET pin. The VSET pin sets the output voltage and the PSET pin trims the set voltage to a percentage value. For example, to program 2.25V output, a 165 k resistor is selected for the VSET pin, and an 11 k resistor is selected for the PSET pin. The 165 k resistor sets the output voltage to 2.5V and the 11 k resistor trims the set voltage by -10%. Using the VSET resistor's value greater than 619 k or less than 7.68 k disables the step-down switching regulator and sets the SW pin to high impedance. If the VSET resistor's value is outside the 5% tolerance, the output can be either higher or lower than the set voltage. Using resistor values greater than 619 k or less than 7.68 k for the PSET pin does not affect the set voltage. When the PSET pin is not used, it must be connected to ground. Like the VSET resistor, the percent value can be either higher or lower if the PSET resistor's value is outside the 5% tolerance. Table 7: Any Voltage Programming Table for 1% Resistors PSET -10.0% 11k -7.5% 18. 7k 0.740 0.925 1.110 1.388 1.665 2.313 2.775 3.053 -5.0% 3 1. 6k 0.760 0.950 1.140 1.425 1.710 2.375 2.850 3.135 -2.5% 53 .6 k 0.780 0.975 1.170 1.463 1.755 2.438 2.925 3.218 0% GND 0.800 1.000 1.200 1.500 1.800 2.500 3.000 3.300 2. 5% 9 7.6k 0.820 1.025 1.230 1.538 1.845 2.563 3.075 3.383 5. 0% 165 k 0.840 1.050 1.260 1.575 1.890 2.625 3.150 3.465 7.5% 28 0k 0.860 1.075 1.290 1.613 1.935 2.688 3.225 3.548 1 0. 0% 4 75k 0.880 1.100 1.320 1.650 1.980 2.750 3.300 3.630 11 k 1 8.7 k 3 1.6 k VSET 5 3.6 k 9 7.6 k 1 65k 2 80k 4 75k 0.720 0.900 1.080 1.350 1.620 2.250 2.700 2.970 Copyright (c) 2007 Marvell October 30, 2007, Advance Document Classification: Proprietary Information Doc. No. MV-S102867-00 Rev. F Page 23 88PG8x7 1 MHz, 4.5A Peak Current-Limit Step-Down Regulator with AnyVoltageTM Technology www..com Table 8: Any Voltage Programming Table for 5% Resistors PSET -10.0% 11k -7.5% 18k 0.740 0.925 1.110 1.388 1.665 2.313 2.775 3.053 -5.0% 3 0k 0.760 0.950 1.140 1.425 1.710 2.375 2.850 3.135 -2.5% 51 k 0.780 0.975 1.170 1.463 1.755 2.438 2.925 3.218 0% GND 0.800 1.000 1.200 1.500 1.800 2.500 3.000 3.300 2.5% 1 00k 0.820 1.025 1.230 1.538 1.845 2.563 3.075 3.383 5.0% 160 k 0.840 1.050 1.260 1.575 1.890 2.625 3.150 3.465 7.5% 27 0k 0.860 1.075 1.290 1.613 1.935 2.688 3.225 3.548 1 0.0 % 4 70k 0.880 1.100 1.320 1.650 1.980 2.750 3.300 3.630 11 k 1 8k 3 0k VSET 5 1k 1 00k 1 60k 2 70k 4 70k 0.720 0.900 1.080 1.350 1.620 2.250 2.700 2.970 The VSET and PSET resistors are read once during start-up before the output voltage is turned on. After the output voltage is turned on, the output voltage can change to different values using serial programming interface. Otherwise to configure the output to a different voltage, power has to recycle or the 88PG8x7 has to turn OFF and back ON using the shutdown pin. Figure 10 shows the startup waveforms of the 88PG8x7. Once the input voltage (VIN) is above the under voltage lockout (UVLO) upper threshold (UTH), the VSET and PSET pin become active. Current is first sourced out of PSET pin and then the VSET pin, in exponentially increasing steps. After each step there is a blanking time before the VSET voltage is compared to an internal 1.2V reference. If the VSET voltage is below internal reference voltage, the current source proceeds to the next step. Once the VSET voltage is above the internal reference voltage the sequence stops and the output voltage (VOUT) is allowed to turn on. The Figure 11 shows the VSET waveform for VSET = 2.5V and PSET = -5% output. The 88PG8x7 keeps track of how many steps are required to determine the appropriate output voltage. Table 9 provides the number of steps necessary for each output voltage option. Using a VSET resistor of 165 k requires the current source to step 4 times, and a PSET resistor of 31.6 k requires 7 steps. Doc. No. MV-S102867-00 Rev. F Page 24 Document Classification: Proprietary Information Copyright (c) 2007 Marvell October 30, 2007, Advance Functionalwww..com Description Output Voltage Setting Figure 10: Startup Sequence Figure 11: Soft Startup VIN VOUT VVSET VPSET 2V/DIV VVSET 1V/DIV 500mV/DIV 1V/DIV VPSET 500mV/DIV 1V/DIV 2.0 ms/DIV 200 s/DIV Table 9: St ep 1 2 3 4 5 6 7 8 9 Output Voltage Option Steps VOUT (V ) 0 3.3 3.0 2.5 1.8 1.5 1.2 1.0 0.8 R VSET ( k) 0 475 280 165 97.6 53.6 31.6 18.7 11 St ep 1 2 3 4 5 6 7 8 9 PSET (%) 0 +10 +7.5 +5.0 +2.5 -2.5 -5.0 -7.5 -10 R PSET ( k) 0 475 280 165 97.6 53.6 31.6 18.7 11 The 88PG8x7 provides an innovative technique to set the output voltage. During start-up it reads the value of external resistors, which are located outside the regulator's feedback loop to program the output voltage. By placing the output voltage programming resistor outside the regulator's feedback loop, its tolerance does not affect the accuracy of the output voltage. Normally, adjustable regulators use 1% resistors to set the output voltage. However, these resistors are located inside the feedback loop, introducing as much as 2% of initial accuracy error to the output voltage, resulting in an overall initial accuracy of 3%. Whereas, the 88PG8x7 initial accuracy is 2% for any of the eight output voltages. The VSET and PSET pins are sensitive to excessive leakage currents and stray capacitance. The output voltage can potentially be programmed to the lower output voltage if there is contamination, which introduces excessive leakage current on the VSET and PSET pin, especially for the 3.3V output or +10%. The parasitic resistance on these nodes must be greater than 3 M and the stray capacitance must be less than 25 pF; otherwise, a 3.3V output can potentially end up at 3V. Copyright (c) 2007 Marvell October 30, 2007, Advance Document Classification: Proprietary Information Doc. No. MV-S102867-00 Rev. F Page 25 88PG8x7 1 MHz, 4.5A Peak Current-Limit Step-Down Regulator with AnyVoltageTM Technology www..com 3.3 Programmable Current Limit for the LDO Regulator Controller A sense resistor is placed between SVIN and ILIM pin to program the current limit of the LDO regulator controller. The following equation is used to determine the value of the sense resistor. 50mV ( Typical ) I LIM = ---------------------------------------R SENSE ( m ) When the LDO regulator controller is in current limit, the internal current-limit circuitry turns off the LDO regulator controller and holds the LDO regulator controller in the off state for 1ms (typical hold time). After the hold-time is expired, the LDO regulator controller is enabled. The current-limit circuitry continues to disable and enable the regulator until the current limit is removed. The LDO regulator P-channel MOSFET can be selected from the following list based on the required threshold voltage of either -2.5V or -1.8V and a gate capacitance of less than 1000 pF. Table 10: Pack age P-Channel MOSFET Selection Vish ay Fa ir child FDC642P FDC634P FDN340P FDN302P Si4433DY FDS9431A FDJ127P FDP4020P Si3443DV FDG330P Si2333DS Si5473DC Si1039X Si1012R/X Super SOT-6 Super SOT-3 / micro 3 SO-8 SC75-6 FLMP TO-263AB (D2-Pack) TSOP-6 SC70-6 SOT-23 1206-8 Chip FET SC-89 (6-lead) SC75A/SC-89 (3-lead) Doc. No. MV-S102867-00 Rev. F Page 26 Document Classification: Proprietary Information Copyright (c) 2007 Marvell October 30, 2007, Advance Undervoltage Lockout (UVLO) Functionalwww..com Description 3.3.1 Maximum LDO Output Current The FDS642P is design to provide up to 800 mA of continuous output current. However, the tiny Super SOT-6 package can dissipate up to 0.7W. If the input and output voltage are close, then the full 800 mA is achieved, see Figure 12. As the input voltage increases, the IC dissipates more power, limiting the maximum output current. The output current has to decrease in order to keep the power dissipation under its 0.7W limit. Figure 12: Maximum Output Current for the FDS642P P-Channel MOSFET Maximum LDO Output Current vs. Input Voltage 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 3 3.5 4 Input Voltage (V) 4.5 5 3.3V - 88PG8x7B 2.5V - 88PG8x7E 3.4 Undervoltage Lockout (UVLO) At start-up, the 88PG8x7 incorporates undervoltage-lockout circuitry to enable the step-down switching regulator and the LDO controller when the input voltage is above 2.65V (typical). After the 88PG8x7 is enabled and the input voltage is lowered, the highest value of the minimum input voltage for both regulators to remain enabled is 2.55V (typical). Copyright (c) 2007 Marvell October 30, 2007, Advance Document Classification: Proprietary Information Load Current (A) Doc. No. MV-S102867-00 Rev. F Page 27 88PG8x7 1 MHz, 4.5A Peak Current-Limit Step-Down Regulator with AnyVoltageTM Technology www..com 3.5 Over Voltage Protection (OVP) The 88PG8x7 incorporates an over voltage protection circuitry to disable the step-down switching regulator and LDO controller when the input voltage is above 5.7V (typical). The step-down switching regulator and LDO controller are enabled when the input voltage is below 5.6V (typical). Figure 13: UVLO and OVP Waveforms VOVP_HTH VOVP-LTH VUVLO-HTH VUVLO-LTH VIN BUCK Output Enable BUCK Output Disable LDO Output Enable LDO Output Disable Undefined Undefined Doc. No. MV-S102867-00 Rev. F Page 28 Document Classification: Proprietary Information Copyright (c) 2007 Marvell October 30, 2007, Advance Functionalwww..com Description Power-On Reset (POR) 3.6 Power-On Reset (POR) The Power-On Reset (POR) pin is an active-high, open-drain output pin. This output is held low when the output voltage of the step-down regulator is below the threshold. When the output voltage is above the threshold, the Power-On Reset pin goes high 40 ms later. Setting the output voltage greater than 1.35V, the threshold voltage is 0.9% * VOUT (typical). Setting the output voltage less than 1.32V, the threshold voltage is VOUT - 130 mV (typical). A built-in 25 s (tDELAY) delay is incorporated to prevent nuisance tripping. Figure 14: Power-On Reset Waveforms V POOD_TH V OUT >t DELAY V POR V PORH V PORL 40 ms Copyright (c) 2007 Marvell October 30, 2007, Advance Document Classification: Proprietary Information Doc. No. MV-S102867-00 Rev. F Page 29 88PG8x7 1 MHz, 4.5A Peak Current-Limit Step-Down Regulator with AnyVoltageTM Technology www..com 3.7 Thermal Shutdown When the junction temperature of the 88PG8x7 exceeds 150 C (typical), the thermal shutdown circuitry disables the step-down regulator. The step-down switching regulator is enabled when the junction temperature is decreased to 105 C (typical). 3.8 Adaptive Transient Response The 88PG8x7 device's Smart Technology allows the step-down switching regulator to quickly respond to the multiple step loads and maintain stability over a wide range of applications. Figure 15 shows an example of a second step-load applied while the output voltage of the step-down switching regulator increased due to the inductive kick from the first step-load. Condition: VIN = 5.0V, RSVIN = 10, CSVIN = 0.1 F, CPVIN = 10 F, L = 1.3 H, COUT = 2 x 22 F, VOUT = 1.2V, ILOAD = 1A to 3A. Figure 15: Adaptive Transient Response VOUT 100mV/DIV ILOAD 2A/DIV 20 s/DIV The worst case overshoot (VSOAR) during a full-load to light-load transient due to stored inductor energy (Figure 15) can be calculated as: V SOAR I LOAD ( MAX ) x L = ---------------------------------------------2 x C OUT x V OUT 2 Although the VSOAR cannot be eliminated, its amplitude can be controlled based on the COUT capacitor value. The appropriate COUT value can easily be calculated for the acceptable VSOAR level for each specific application. C OUT I LOAD ( MAX ) x L = ---------------------------------------------2 x V SOAR x V OUT 2 Doc. No. MV-S102867-00 Rev. F Page 30 Document Classification: Proprietary Information Copyright (c) 2007 Marvell October 30, 2007, Advance Using Ceramic Input Capacitors Functionalwww..com Description 3.9 Using Ceramic Input Capacitors Ceramic capacitors' low ESR, small case size and high ripple current ratings make them ideal for switching regulator applications. However, Tantalum or electrolytic capacitors must be placed in parallel with the ceramic capacitors in "Hot-Plug" application such as when using an AC-DC wall adaptor. If a wall adaptor is "Hot-Plugged" into the input supply, high transient current runs through the adaptor's long wires and produce ringing at the input (VIN) of the 88PG8x7, see Figure 16. During this period, the 88PG8x7 is still "OFF" and the current IIN is used to charge the input capacitor. At worst, these voltage spikes can be as high as twice the input voltage. To dampen the ringing, a small 47 F to 100 F Tantalum capacitor with an ESR in the range of 0.2 ohm to 1.0 ohm must be added, as shown in Figure 17. Figure 16: Inrush with 22 F Ceramic Figure 17: Inrush with 22 F Ceramic + 100 F TA VIN 2V/DIV VIN 2V/DIV IIN 5A/DIV IIN 5A/DIV 20 s/DIV 50 s/DIV Ceramic input capacitor must not be replaced with any other type of capacitor and choose only X5R or X7R dielectric. These have the best voltage and temperature characteristics. Any type of capacitor can be placed in parallel with the input capacitor as long as the Ceramic input capacitor in placed next to the IC. If Tantalum input capacitor is used, it must be rated for switching regulator applications and the operating voltage be derated by 50%. Copyright (c) 2007 Marvell October 30, 2007, Advance Document Classification: Proprietary Information Doc. No. MV-S102867-00 Rev. F Page 31 88PG8x7 1 MHz, 4.5A Peak Current-Limit Step-Down Regulator with AnyVoltageTM Technology www..com 3.10 Sequential Power up Figure 18 shows a detailed start-up sequence waveforms of two 88PG847 devices cascaded together as shown in Figure 19. When the input voltage is above the under-voltage-lockout upper threshold (UVLO UTH) of 2.65V, the LDO output (VOUT1) starts a slow ramp up and finishes in about 3 ms. Roughly, 3 ms after the input voltage is above the UVLO UTH the 2.5V (VOUT2) output ramps up. The power-on-reset (POR) signal goes high 45 ms after VOUT1 and VOUT2 outputs are regulating. The POR signal enables U2 and the 1.5V output (VOUT3) ramps up 3 ms later. Figure 18: Start-Up Waveforms of two 88PG847 devices VIN VOUT1 2V/DIV 2V/DIV VOUT2 1V/DIV VOUT3 1V/DIV 10 ms/DIV Doc. No. MV-S102867-00 Rev. F Page 32 Document Classification: Proprietary Information Copyright (c) 2007 Marvell October 30, 2007, Advance Functionalwww..com Description Sequential Power up Figure 19: Power Sequence of Two 88PG8x7 devices R5 4 0.047 ohm 3 R3 100k 10 12 11 14 15 R4 165k R2 0 U1 1 ILIM POR SDI 2 LDR 10uF/6.3V 16 LFB SW SW SFB CG SGND SVIN 9 R1 PGND 6 7 L1 5 1.3uH 3 4 13 C3 22uF/6.3V C4 Q1 FDC642P 1, 2, 5, 6 C6 Vout1 3.3V SHDN VSET PSET 88PG847B Vout2 2.5V/3A 22uF/6.3V PVIN 8 Vin +5V C5 22uF/6.3V C2 22uF/6.3V 10 ohm C1 0.1uF R10 100k R9 100k 10 12 11 U2 1 ILIM POR SDI 2 LDR 16 LFB SW SW SFB CG SGND 7 L2 5 1.3uH 3 4 13 C9 22uF/6.3V C10 POR SHDN VSET PSET 88PG847B Vout3 1.5V/3A D Q2 G S 2N7002 R7 53.6k 14 15 R8 0 22uF/6.3V PVIN 8 R6 SVIN 9 PGND 6 Vin +5V C7 22uF/6.3V C8 22uF/6.3V 10 ohm C11 0.1uF Copyright (c) 2007 Marvell October 30, 2007, Advance Document Classification: Proprietary Information Doc. No. MV-S102867-00 Rev. F Page 33 88PG8x7 1 MHz, 4.5A Peak Current-Limit Step-Down Regulator with AnyVoltageTM Technology www..com 3.11 Disable the LDO Function The LDO function can be disabled by connecting the ILIM pin to SVIN pin, and the LFB pin to ground. Also, the LDR pin is left floating, see Figure 20. Disabling the LDO function will lower the no-load supply current from 1.9 mA to 1.2 mA. Figure 20: 88PG847B device without LDO Output R3 100k POR SDI 10 12 11 14 15 R5 10k R4 0 R2 0 U1 1 ILIM POR SDI 2 LDR 16 LFB SW SW SFB CG SGND 7 L1 5 1.3uH 3 4 13 C3 22uF/6.3V C4 SHDN VSET PSET 88PG847B Vout1 0.8V/3A 22uF/6.3V PVIN 8 R1 SVIN 9 PGND 6 Vin +5V C5 22uF/6.3V C2 22uF/6.3V 10 ohm C1 0.1uF Doc. No. MV-S102867-00 Rev. F Page 34 Document Classification: Proprietary Information Copyright (c) 2007 Marvell October 30, 2007, Advance Functional Characteristics www..com Start-up Waveforms Section 4. Functional Characteristics The following applies unless otherwise noted: TA = 25C, RSVIN = 10, CSVIN = 0.1 F, CPVIN = 2 x 22 F, L = 1.3 H, COUT = 2 X 22 F, PFET = FDC642P, COUT (LDO) = 10 F. (BUCK) 4.1 Start-up Waveforms NOTE: When the input voltage rises above the UVLO's upper threshold, then there is a delay (4 ms typ) before the stepdown regulator's output voltage turns on. Figure 21: Startup Using the Shutdown Pin Figure 22: Turn Off Using the Shutdown Pin VSHDN 2V/DIV VSHDN VLDO 2V/DIV 2V/DIV VLDO VBUCK 2V/DIV VBUCK 1V/DIV 1V/DIV 1 ms/DIV VIN = 5.0V VLDO= 3.3V VBUCK= 1.2V ILOAD = No Load tDLY~ 4.0 ms VIN = 5.0V VLDO= 3.3V VBUCK= 1.2V 1 ms/DIV ILOAD = No Load Figure 23: Startup Sequence Figure 24: Soft Startup 5V/DIV VIN VLDO VBUCK VPOR 2V/DIV VIN VLDO VBUCK VPOR 5V/DIV 2V/DIV 1V/DIV 5V/DIV 1V/DIV 5V/DIV 10 ms/DIV VIN = 5.0V VLDO= 3.3V VBUCK= 1.2V ILOAD = No Load VIN = 5.0V VLDO= 3.3V 10 ms/DIV VBUCK= 1.2V ILOAD = No Load Copyright (c) 2007 Marvell October 30, 2007, Advance Document Classification: Proprietary Information Doc. No. MV-S102867-00 Rev. F Page 35 88PG8x7 1 MHz, 4.5A Peak Current-Limit Step-Down Regulator with AnyVoltageTM Technology www..com Figure 25: UVLO and OVP Thresholds VIN 2V/DIV VLDO VBUCK 2V/DIV 1V/DIV 100 ms/DIV VIN = 0 to 6.0V VLDO= 3.3V VBUCK= 1.0V ILOAD(BUCK) = 1A ILOAD(BUCK) = 500 mA VUVLO(HTH) = 2.65V VUVLO(LTH)= 2.55V VOVP(HTH) = 5.8V VOVP(LTH) = 5.7V 4.2 Short-Circuit Waveforms Figure 26: Step-Down Short-Circuit Response Figure 27: LDO Short-Circuit Response VSW 5V/DIV Switch turns Off ~ 32 s VBUCK 2nd Peak-Current Limit IIND 5A/DIV 1st Peak-Current Limit IIN Short-Circuit 500 mV/DIV Current Limit LDO Turns Off ~ 1 ms 1A/DIV VLDO Short-Circuit 1V/DIV 200 s/DIV 1 ms/DIV Doc. No. MV-S102867-00 Rev. F Page 36 Document Classification: Proprietary Information Copyright (c) 2007 Marvell October 30, 2007, Advance Functional Characteristics www..com Switching Waveforms 4.3 Switching Waveforms NOTE: For repeatability of measuring output ripple (VBUCK (P-P)) for the BUCK regulator, the standard test procedure limits the scope bandwidth to 20 MHz and uses a coax cable with very short leads terminated into 50. The coax leads must be routed away from the switching node as much as possible. Figure 28: Switching Waveforms PWM mode VSW 5V/DIV IIND 2A/DIV VBUCK 10 mV/DIV VIN 200 mV/DIV VIN VBUCK IIND VSW Figure 29: Switching Waveforms PWM mode 5V/DIV 2A/DIV 10 mV/DIV 100 mV/DIV 500 ns/DIV CIN = 22 F VIN = 5.0V VBUCK= 1.2V IOUT = 3.0A VOUT(P-P) = 6.7 mV (Note) VIN(P-P) = 190 mV IIND(P-P) = 1.05A IIND(PK) = 3.4A Freq = 912 kHz CIN = 2 x 22 F VIN = 5.0V VBUCK= 1.2V IOUT = 3.0A 500 ns/DIV VIN(P-P) = 89 mV IIND(P-P) = 1.05A IIND(PK) = 3.4A Freq = 912 kHz VOUT(P-P) = 6.7 mV (Note) Figure 30: Switching Waveforms DCM Mode Figure 31: Switching Waveforms - DCM Mode-Zoom VSW 5V/DIV VSW 5V/DIV VBUCK IIND 20 mV/DIV VBUCK 20 mV/DIV 1A/DIV IIND 1A/DIV 5 s/DIV VIN = 5.0V VBUCK= 1.2V IOUT = 24 mA VOUT(P-P) =22 mV (Note) IIND(PK) = 920 mA Freq = 53 kHz VIN = 5.0V VBUCK= 1.2V IOUT = 24 mA 500 ns/DIV Ringing Freq = 7.5 MHz Copyright (c) 2007 Marvell October 30, 2007, Advance Document Classification: Proprietary Information Doc. No. MV-S102867-00 Rev. F Page 37 88PG8x7 1 MHz, 4.5A Peak Current-Limit Step-Down Regulator with AnyVoltageTM Technology www..com Figure 32: PWM Output Ripple Voltage VBUCK 10 mV/DIV 100 ms/DIV VIN = 5.0V VBUCK= 1.2V IOUT = 3.0A VOUT(P-P) = 21 mV (Note) Doc. No. MV-S102867-00 Rev. F Page 38 Document Classification: Proprietary Information Copyright (c) 2007 Marvell October 30, 2007, Advance Functional Characteristics www..com Load Transient Waveforms 4.4 Load Transient Waveforms 4.4.1 Step-Down Regulator Figure 33: Fast Load Rise Time Figure 34: Slow Load Rise Time VSW VSW VBUCK IIND ILOAD 2A/DIV IIND 2A/DIV IIND ILOAD 5V/DIV VBUCK 50 mV/DIV IIND 5V/DIV 50 mV/DIV 2A/DIV 2A/DIV 2 s/DIV VIN = 5.0V VBUCK= 1.2V IOUT = 1 A to 3A COUT = 2 x 22 F tRISE = 12 A/s VIN = 5.0V VBUCK= 1.2V IOUT = 1 A to 3A 2 s/DIV COUT = 2 x 22 F tRISE = 1 A/s Figure 35: Fast Load Fall Time Figure 36: Slow Load Fall Time VSW VBUCK ILOAD IIND 5V/DIV VSW 50 mV/DIV VBUCK IIND 2A/DIV ILOAD 2A/DIV IIND 2A/DIV IIND 50 mV/DIV 5V/DIV 2A/DIV 2 s/DIV VIN = 5.0V VBUCK= 1.2V IOUT = 1 A to 3A COUT = 2 x 22 F tFALL = 122 A/s VIN = 5.0V VBUCK= 1.2V IOUT = 1 A to 3A 2 s/DIV COUT = 2 x 22 F tFALL = 1 A/s Copyright (c) 2007 Marvell October 30, 2007, Advance Document Classification: Proprietary Information Doc. No. MV-S102867-00 Rev. F Page 39 88PG8x7 1 MHz, 4.5A Peak Current-Limit Step-Down Regulator with AnyVoltageTM Technology www..com Figure 37: Load Transient Response Figure 38: Double-Pulsed Load Response VBUCK 100 mV/DIV VBUCK 100 mV/DIV ILOAD 2A/DIV ILOAD 2A/DIV 20 s/DIV VIN = 5.0V VBUCK= 1.2V COUT = 2 x 22 F VCG = GND ILOAD = 1A to 3A tRISE = 12 A/s tFALL = 122 A/s VIN = 5.0V VBUCK= 1.2V 20 s/DIV ILOAD = 1A to 3A tRISE = 12 A/s tFALL = 122 A/s COUT = 2 x 22 F VCG = GND Figure 39: Load Transient Response Figure 40: Double-Pulsed Load Response VBUCK 100 mV/DIV VBUCK 100 mV/DIV ILOAD 2A/DIV ILOAD 2A/DIV 20 s/DIV VIN = 5.0V VBUCK= 1.2V COUT = 4 x 22 F VCG = GND ILOAD = 1A to 3A tRISE = 12 A/s tFALL = 122 A/s VIN = 5.0V VBUCK= 1.2V 20 s/DIV ILOAD = 1A to 3A tRISE = 12 A/s tFALL = 122 A/s COUT = 4 x 22 F VCG = GND Doc. No. MV-S102867-00 Rev. F Page 40 Document Classification: Proprietary Information Copyright (c) 2007 Marvell October 30, 2007, Advance Functional Characteristics www..com Load Transient Waveforms 4.4.2 LDO Regulator Figure 41: Load Transient Response VLDO 20 mV/DIV ILOAD 500 mA/DIV 200 s/DIV VIN = 5.0V VLDO= 3.3V COUT = 10 F ILOAD = 100 mA to 800 mA Copyright (c) 2007 Marvell October 30, 2007, Advance Document Classification: Proprietary Information Doc. No. MV-S102867-00 Rev. F Page 41 88PG8x7 1 MHz, 4.5A Peak Current-Limit Step-Down Regulator with AnyVoltageTM Technology www..com 4.5 Output Voltage Transient Waveforms The following graphs show the effect of changing the step-down regulator's output voltage using the serial interface. Depending on the change in the step-size of the output voltage, the output load, and the output capacitance, the power-on reset pin de-asserts when the changes of the output voltage occur beyond the 25 s (typical) delay. 4.5.1 Step-Down Regulator Figure 42: VOUT = 1.0V to 1.2V with No Load Figure 43: VOUT = 1.0V to 1.5V with No Load VBUCK 500 mV/DIV VBUCK 500 mV/DIV VPOR SDI 5V/DIV VPOR 5V/DIV SDI 5V/DIV 5V/DIV 10 s/DIV VIN = 5.0V COUT= (2 x 22) + 1000 F VIN = 5.0V 50 s/DIV COUT= (2 x 22) +1000 F Figure 44: VOUT = 1.0V to 1.2V with ILOAD = 3A Figure 45: VOUT = 1.0V to 1.2V with ILOAD = 3A VBUCK VBUCK VPOR SDI 500 mV/DIV 500 mV/DIV 5V/DIV VPOR SDI 5V/DIV 5V/DIV 5V/DIV 50 s/DIV VIN = 5.0V COUT= (2 x 22) + 1000 F VIN = 5.0V 50 s/DIV COUT= (2 x 22) +1000 F Doc. No. MV-S102867-00 Rev. F Page 42 Document Classification: Proprietary Information Copyright (c) 2007 Marvell October 30, 2007, Advance Functional Characteristics www..com Line Transient Waveforms Figure 46: VOUT = 1.2V to 1.0V with ILOAD = 3A Figure 47: VOUT = 1.5V to 1.0V with ILOAD = 3A VBUCK VBUCK 500 mV/DIV VPOR VPOR SDI 5V/DIV SDI 5V/DIV 500 mV/DIV 5V/DIV 5V/DIV 50 s/DIV 50 s/DIV VIN = 5.0V COUT= (2 x 22)+1000 F VIN = 5.0V COUT= (2 x 22)+1000 F 4.6 Line Transient Waveforms Figure 48: Line Transient @ VIN = 3.6 Figure 49: Line Transient @ VIN = 4.5 VIN 3.2V 3.6V 1V/DIV VIN 4.1V 4.5V 1V/DIV VBUCK 20 mV/DIV 20 mV/DIV VBUCK 2 ms/DIV VIN = 3.6V CIN= 22 F VBUCK = 1.2V ILOAD = 3A VIN = 4.5V CIN= 22 F 2 ms/DIV VBUCK = 1.2V ILOAD = 3A Copyright (c) 2007 Marvell October 30, 2007, Advance Document Classification: Proprietary Information Doc. No. MV-S102867-00 Rev. F Page 43 88PG8x7 1 MHz, 4.5A Peak Current-Limit Step-Down Regulator with AnyVoltageTM Technology www..com Section 5. Typical Characteristics 5.1 Efficiency Graphs Efficiency vs. Output Current Vin = 5.0V 100 90 Efficiency (%) Efficiency (%) 100 90 80 70 60 50 1.8V 1.5V 1.2V 1.0V 0.8V 0.0 0.5 1.0 1.5 2.0 Output Current (A) 2.5 3.0 Efficiency vs. Output Current Vin = 3.3V 80 70 60 50 0.0 0.5 1.0 1.5 2.0 Output Current (A) 2.5 3.0 3.3V 3.0V 2.5V 1.8V 1.5V 1.2V 1.0V 0.8V 5.1.1 Efficiency Graphs in log scale Efficiency vs. Output Current Vin = 3.3V 100 90 Efficiency (%) 80 1.8V 70 60 50 0.01 1.5V 1.2V 1.0V 0.8V 10 Efficiency vs. Output Current Vin = 5.0V 100 90 Efficiency (%) 80 70 60 50 0.01 3.3V 3.0V 2.5V 1.8V 1.5V 1.2V 1.0V 0.8V 0.1 1 Output Current (A) 0.1 1 Output Current (A) 10 5.2 Load Regulation Output Voltage vs. Output Current Vout = 1.5V 1.60 Output Voltage (V) 1.55 1.50 3.3V 5.0V 1.40 0.0 0.5 1.0 1.5 2.0 Output Current (A) 2.5 3.0 1.45 Doc. No. MV-S102867-00 Rev. F Page 44 Document Classification: Proprietary Information Copyright (c) 2007 Marvell October 30, 2007, Advance Typical Characteristics www..com Dropout Voltage 5.3 Dropout Voltage Step-Down Regulator Dropout vs. Load Current Vin = 3.2, Vout = 3.3V 0.4 Buck Dropout (V) 0.3 0.2 0.1 0 0.0 0.5 1.0 1.5 2.0 Load Current(A) 2.5 3.0 LDO Dropout(V) 0.2 LDO Regulator Dropout vs. Load Current Vin = 3.3V, Vout = 3.3V TA = 85C TA = 25C TA = -40C 0.15 0.1 0.05 0 0 TA = 85C TA = 25C TA = -40C 0.2 0.4 Load Current(A) 0.6 0.8 5.4 RDS (ON) Resistance Top FET Resistance vs. Temperature 0.095 Bottom FET Resistance vs. Temperature 0.031 Resistance ( ) Resistance ( ) 0.085 0.027 Vin = 3.0V Vin = 4.0V Vin = 5.0V 0.075 0.023 0.065 0.055 -40 -20 0 20 40 Temperature (C) Vin = 3.0V Vin = 4.0V Vin = 5.0V 60 80 0.019 0.015 -40 -20 0 20 40 60 80 Temperature (C) Top FET Resistance vs. Input Voltage 0.095 Bottom FET Resistance vs. Input Voltage 0.026 TA = 25C 0.075 Resistance ( ) Resistance () 0.085 0.024 TA = 25C 0.022 0.065 0.020 0.055 3.0 3.5 4.0 Input Voltage(V) 4.5 5.0 0.018 3.0 3.5 4.0 Input Voltage(V) 4.5 5.0 Copyright (c) 2007 Marvell October 30, 2007, Advance Document Classification: Proprietary Information Doc. No. MV-S102867-00 Rev. F Page 45 88PG8x7 1 MHz, 4.5A Peak Current-Limit Step-Down Regulator with AnyVoltageTM Technology www..com 5.5 IC Case and Inductor Temperature The following data was taken using a 1.4 square inch PCB 1 oz. copper and L = 1.3 H. Actual results depend upon the size of the PCB proximity to other heat emitting components. Input Current vs. Output Current Vin = 5V, TA = 25C 3.00 3.3V 3.0V 2.5V 1.8V 1.5V 1.2V 1.0V 0.8V 3.00 2.5V 1.8V 1.5V 1.2V 1.0V 0.8V Input Current vs. Output Current Vin = 3.3V, TA = 25C Input Current (A) Input Current (A) 2.25 2.25 1.50 1.50 0.75 0.75 0.00 0.0 0.5 1.0 1.5 2.0 Output Current (A) 2.5 3.0 0.00 0.0 0.5 1.0 1.5 2.0 Output Current (A) 2.5 3.0 IC Case Temprature vs. Output Current Vin = 5V, TA = 25C 60 IC Temprature (C) IC Case Temprature vs. Output Current Vin = 3.3V, TA = 25C 80 IC Temprature (C) 2.5V 1.8V 1.5V 1.2V 1.0V 0.8V 50 40 30 3.3V 3.0V 2.5V 1.8V 1.5V 1.2V 1.0V 0.8V 70 60 50 40 30 20 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Output Current (A) 20 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Output Current (A) Inductor Temprature vs. Output Current Vin = 5V, TA = 25C 60 3.3V 3.0V 2.5V 1.8V 1.5V 1.2V 1.0V 0.8V 60 2.5V 1.8V 1.5V 1.2V 1.0V 0.8V Inductor Temprature vs. Output Current Vin = 3.3V, TA = 25C L Temprature (C) 40 L Temprature (C) 0.5 1.0 1.5 2.0 Output Current (A) 2.5 3.0 50 50 40 30 30 20 0.0 20 0.0 0.5 1.0 1.5 2.0 Output Current (A) 2.5 3.0 Doc. No. MV-S102867-00 Rev. F Page 46 Document Classification: Proprietary Information Copyright (c) 2007 Marvell October 30, 2007, Advance P-Channel MOSFET (FDS642P) Thermal Characteristics Typical Characteristics www..com 5.6 P-Channel MOSFET (FDS642P) Thermal Characteristics The following data was taken using 1.4 square inch PCB 1 oz. Copper. Actual results depend upon the size of the PCB and proximity to other heat emitting components. FET Temperature vs. Output Current Vin = 3.3V and 5.0V, Vout = 2.5V, T = 25C 130 120 110 100 90 80 70 60 50 40 30 20 0 FET Temperature vs. Output Current Vout = 4.0V and 5.0V, T = 25C 110 3.3V 100 Temperature (C) 90 80 70 60 50 40 30 VIN = 4.0V VIN = 5.0V Temperature (C) 5.0V 0.2 0.4 0.6 0.8 1 0 0.2 0.4 0.6 0.8 1 Output Current (A) Output Current (A) IC Power Loss vs. Output Current Vin = 3.3V and 5.0V, Vout = 2.5V, T = 25C 2.500 2.000 Power Loss (W) 1.500 1.000 0.500 0.000 0 0.2 0.4 0.6 0.8 1 Output Current (A) 3.3V IC Power Loss vs. Output Current Vout = 4.0V and 5.0V, T = 25C 1.600 1.400 Power Loss (W) 1.200 1.000 0.800 0.600 0.400 0.200 0.000 0 0.2 0.4 0.6 0.8 1 Output Current (A) VIN = 4.0V VIN = 5.0V 5.0V Input Current vs. Output Current Vin = 3.3V and 5.0V, Vout = 2.5V, T = 25C 0.900 0.800 0.700 0.600 0.500 0.400 0.300 0.200 0.100 0.000 0 0.900 3.3V Input Current vs. Output Current Vout = 4.0V and 5.0V, T = 25C 0.800 Input Current (A) 5.0V 0.700 0.600 0.500 0.400 0.300 0.200 0.100 0.000 VIN = 4.0V VIN =5.0V Input Current (A) 0.2 0.4 0.6 0.8 1 0 0.2 0.4 0.6 0.8 1 Output Current (A) Output Current (A) Copyright (c) 2007 Marvell October 30, 2007, Advance Document Classification: Proprietary Information Doc. No. MV-S102867-00 Rev. F Page 47 88PG8x7 1 MHz, 4.5A Peak Current-Limit Step-Down Regulator with AnyVoltageTM Technology www..com 5.7 Input Voltage Graphs Supply Current vs. Input Voltage 4.0 4.0 Supply Current vs. Output Votlage Supply Current (mA) 3.0 With PFet Without PFet Supply Current (mA) 3.0 With PFet Without PFet 2.0 2.0 1.0 1.0 0.0 2.5 3.0 3.5 4.0 Input Voltage (V) 4.5 5.0 0.0 0.5 1.0 1.5 2.0 2.5 Output Voltage (V) 3.0 3.5 Load = No Load VIN = 5.0V Load = No Load Shutdown Threshold vs. Input Voltage 2.0 Shutdown Treshold (V) LTH - Enable 1.5 UTH - Disable 1.0 0.5 0.0 2.5 3.0 3.5 4.0 Input Voltage (V) 4.5 5.0 Doc. No. MV-S102867-00 Rev. F Page 48 Document Classification: Proprietary Information Copyright (c) 2007 Marvell October 30, 2007, Advance Typical Characteristics www..com Input Voltage Graphs 5.7.1 Step-Down Regulator Output Voltage vs. Input Voltage 1.60 Efficiency vs. Input Voltage 100% Output Voltage (V) 1.55 95% Efficiency (%) 3.0 3.5 4.0 Input Voltage (V) 4.5 5.0 1.50 90% 1.45 85% 1.40 80% 3.0 3.5 4.0 Input Voltage (V) 4.5 5.0 IOUT(BUCK) = 750 mA VOUT(BUCK) = 1.5V IOUT(BUCK) = 1.5A Load Regulation vs. Input Voltage 0.40% Frequency vs. Input Voltage 1200 Load Regulation (%) 0.00% Frequency (kHz) 3.0 3.5 4.0 Input Voltage (V) 4.5 5.0 0.20% 1100 1000 -0.20% 900 -0.40% 800 3.0 3.5 4.0 Input Voltage (V) 4.5 5.0 VOUT(BUCK) = 1.5V IOUT(BUCK) = 750 mA VOUT(BUCK) = 1.5V IOUT(BUCK) = 1.5A Average Output Current Limit vs. Input Voltage 7.0 Current Limit (A) 6.5 6.0 5.5 5.0 3.0 3.5 4.0 Input Voltage (V) 4.5 5.0 Copyright (c) 2007 Marvell October 30, 2007, Advance Document Classification: Proprietary Information Doc. No. MV-S102867-00 Rev. F Page 49 88PG8x7 1 MHz, 4.5A Peak Current-Limit Step-Down Regulator with AnyVoltageTM Technology www..com 5.7.2 LDO Regulator Output Voltage vs. Input Voltage 4.0 Load Regulation vs. Input Voltage 0.20% Load Regulation (%) Output Voltage (V) 3.5 0.10% 3.0 0.00% 2.5 -0.10% 2.0 3.0 3.5 4.0 Input Voltage (V) 4.5 5.0 -0.20% 4.00 4.25 4.50 Input Voltage (V) 4.75 5.00 IOUT(LDO) = 10 mA VOUT(LDO) = 3.3V IOUT(LDO) = 10 mA - 800 mA Average Output Current Limit vs. Input Voltage 1.8 Current Limit (A) 1.6 1.4 1.2 1.0 2.5 3.0 3.5 4.0 Input Voltage (V) 4.5 5.0 Doc. No. MV-S102867-00 Rev. F Page 50 Document Classification: Proprietary Information Copyright (c) 2007 Marvell October 30, 2007, Advance Typical Characteristics www..com Temperature Graphs 5.8 Temperature Graphs Supply Current vs. Temperature 4 UVLO vs. Temperature 2.8 Supply Current (mA) 2.7 UVLO (V) 3 2.6 2 2.5 1 -40 -20 0 20 40 Temperature (C) 60 80 2.4 -40 -20 0 20 40 60 80 Temperature (C) IOUT(BUCK) = No Load IOUT(LDO) = No Load IOUT(BUCK) = 10 mA Shutdown Threshold vs. Temperature 2.0 Shutdown Treshold (V) 1.5 1.0 0.5 UTH - Disable LTH - Enable 0.0 -40 -20 0 20 40 Temperature (C) 60 80 VIN= 5V Copyright (c) 2007 Marvell October 30, 2007, Advance Document Classification: Proprietary Information Doc. No. MV-S102867-00 Rev. F Page 51 88PG8x7 1 MHz, 4.5A Peak Current-Limit Step-Down Regulator with AnyVoltageTM Technology www..com 5.8.1 Step-Down Regulator Output Voltage vs. Temperature 1.6 Efficiency vs. Temperature 100% Output Voltage (V) 1.55 95% Efficiency (%) -40 -20 0 20 40 Temperature (C) 60 80 1.5 90% 1.45 85% 1.4 80% -40 -20 0 20 40 Temperature (C) 60 80 VIN = 5.0V IOUT(LDO) = 750 mA VIN = 5.0V VOUT(BUCK) = 1.5V IOUT(BUCK) = 1.5A Load Regulation vs. Temperature 0.20% Line Regulation vs. Temperature 0.20% Load Regulation (%) Line Regulation (%) 0.10% 0.10% 0.00% 0.00% -0.10% -0.10% -0.20% -40 -20 0 20 40 Temperature (C) 60 80 -0.20% -40 -20 0 20 40 60 80 Temperature (C) VIN = 5.0V VOUT(BUCK) = 1.5V IOUT(BUCK) = 750 mA - 3A VIN = 3.0V - 5.0V VOUT(BUCK) = 1.5V IOUT(BUCK) = 1.5A Doc. No. MV-S102867-00 Rev. F Page 52 Document Classification: Proprietary Information Copyright (c) 2007 Marvell October 30, 2007, Advance Typical Characteristics www..com Temperature Graphs Average Output Current Limit vs. Temperature 8 Frequency vs. Temperature 1000 Current Limit (A) 6 Frequency (kHz) -40 -20 0 20 40 Temperature (C) 60 80 7 950 900 5 850 4 800 -40 -20 0 20 40 Temperature (C) 60 80 VIN = 5.0V IOUT(BUCK) = 1.5A Copyright (c) 2007 Marvell October 30, 2007, Advance Document Classification: Proprietary Information Doc. No. MV-S102867-00 Rev. F Page 53 88PG8x7 1 MHz, 4.5A Peak Current-Limit Step-Down Regulator with AnyVoltageTM Technology www..com 5.8.2 LDO Regulator Load Regulation vs. Temperature Output Voltage vs. Temperature 3.40 Load Regulation (%) 0.04% Output Voltage (V) 3.35 0.02% 3.30 0.00% 3.25 -0.02% 3.20 -40 -20 0 20 40 Temperature (C) 60 80 -0.04% -40 -20 0 20 40 Temperature (C) 60 80 VIN = 5.0V IOUT(LDO) = 10 mA VIN = 5.0V VOUT(LDO) = 3.3V IOUT(LDO) = 10 mA - 800 mA Line Regulation vs. Temperature 0.40% 2.00 Average Output Current Limit vs. Temperature Line Regulation (%) 0.20% Current Limit (A) -40 -20 0 20 40 Temperature (C) 60 80 1.75 0.00% 1.50 -0.20% 1.25 -0.40% 1.00 -40 -20 0 20 40 Temperature (C) 60 80 VIN = 3.5V - 5.0V VOUT(LDO) = 3.3V IOUT(LDO) = 10 mA VIN = 5.0V Doc. No. MV-S102867-00 Rev. F Page 54 Document Classification: Proprietary Information Copyright (c) 2007 Marvell October 30, 2007, Advance PC Board Layout Considerations and Guidelines for 88PG8x7 Applicationswww..com Information Section 6. Applications Information 6.1 PC Board Layout Considerations and Guidelines for 88PG8x7 Warning If you want to avoid noise and abnormal operating behavior, follow these layout recommendations. 1. 2. This is a 2-layer board with 1 ground plane and 1 routing layer. Copy the routing layer in Figure 52 as much as possible and place it on the top layer. The ground plane in Figure 53 can be placed on any other layer. Use the recommend BOM in Table 11 through Table 16. Contact the factory where substitutions are made. Review the recommended solder pad layout and notes on page 67. Make sure that you place a dot on the top silk screen to indicated the location of pin 1 for the 88PG8x7 and the FDS742P, see Figure 52. Ensure that the dot is outside the package outline. This way you can visually inspect the package orientation after assembly. Do not replace the Ceramic input capacitor with any other type of capacitor. Any type of capacitor can be placed in parallel with the input capacitor as long as the Ceramic input capacitor in placed next to the IC. If Tantalum input capacitor is used, it must be rated for switching regulator applications and the operating voltage be derated by 50%. Use either X7R or X5R type ceramic capacitors. If Y5V or Z5U type capacitor are used, then you must double the recommended capacitance value. Any type of capacitor can be placed in parallel with the output capacitor. Low-ESR capacitors like the POSCAP from Sanyo can replace the Ceramic output capacitors as long as the capacitor value is the same or greater. Note that the Ceramic capacitors provide the lowest noise and smallest foot print solution. Use planes for the ground, input and outputs power to maintain good voltage filtering and to keep power losses low. If there is not enough space for a power plane for the input supply, then the input supply trace must be at least 3/8 inch wide. If there is not enough space for a power plane for the output supplies, then place the output as close to the load as possible with a trace of at least 3/8 inch wide. Do not lay out the inductor first. The input capacitor placement is the most critical for proper operation. The AC current circulating through the input capacitor and loop 1 (LP1) are square wave with rise and fall times of 8 ns and slew rates as high as 300 A/s (see Figure 50). At these fast slew rates, stray PCB inductance can generate a voltage spike as high as 3V per inch of PCB trace, VIND = L * di/dt. Therefore, the Ceramic input capacitor must be place as close as possible to the PVIN and PGND pins with as short and wide trace as possible. Also, the PVIN and PGND traces must be placed on the top layer. This will isolate the fast AC currents from interfering with the analog ground plane. The 88PG8x7 has two internal grounds, analog (SGND) and power (PGND). The analog ground ties to all the noise sensitive signals (PSET, VSET, and SVIN) while the power ground ties to the higher current power paths. Noise on an analog ground can cause problems with the IC's internal control and bias signals. For this reason, separate analog and power ground traces are recommended. The signal ground is connected to the power ground at one point, which is the (-) terminal of the output capacitor. Keep loop 2 (LP2) as small as possible and connect the (-) terminal of the output capacitor as close to the (-) terminal of the input capacitor. A back-to-back placing of bypass capacitors, as shown in Figure 51, is recommended for best results. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Copyright (c) 2007 Marvell October 30, 2007, Advance Document Classification: Proprietary Information Doc. No. MV-S102867-00 Rev. F Page 55 88PG8x7 1 MHz, 4.5A Peak Current-Limit Step-Down Regulator with AnyVoltageTM Technology www..com 14. Keep the switching node (SW) away from the SFB pin and all sensitive signal nodes, minimizing capacitive coupling effects. If the SFB trace must cross the SW node, cross it at a right angle. 15. Try not to route analog or digital lines in close proximity to the power supply especially the VSW node. If this can't be avoided, shield these lines with a power plane placed between the VSW node and the signal lines. 16. The type of solder paste recommended for QFN packages is "No clean", due to the difficulty of cleaning flux residues from beneath the QFN package. Figure 50: Simplified Schematic U1 R PSET PSET R VSET VSET SVIN R 10 C 0.1uF SFB L PVIN PGND SW SGND Vin Vout I Cin LP1 LP2 I Cout Ci n Cou t LP1 LP2 Doc. No. MV-S102867-00 Rev. F Page 56 Document Classification: Proprietary Information Copyright (c) 2007 Marvell October 30, 2007, Advance PC Board Layout Considerations and Guidelines for 88PG8x7 Applicationswww..com Information Figure 51: 88PG8x7 PCB Board Schematic Q1 FDC642P R6 4 3 Vout2 C6 1, 2, 5, 6 R2 R4 15 16 14 13 U1 LFB PSET VSET 1 2 3 4 SGND R5 SDI 12 11 10 9 C1 0.1uF POR ILIM LDR SFB CG SW 88PG8x7 PGND SW SHDN POR PVIN 8 SVIN 5 6 7 R1 10 R3 100k L1 Vout1 C4 C3 C2 C5 Vin 2.75V - 5.5V Copyright (c) 2007 Marvell October 30, 2007, Advance Document Classification: Proprietary Information Doc. No. MV-S102867-00 Rev. F Page 57 88PG8x7 1 MHz, 4.5A Peak Current-Limit Step-Down Regulator with AnyVoltageTM Technology www..com 6.1.1 PC Board Layout Examples for 88PG8x7 * * * Actual board size = 700 mil x 700 mil; Area = 0.490 Sq. Inches. Total copper layers = 2 (Top and Bottom) All the components are on the top layer Figure 52: Top Silk-Screen, Top Traces, Vias and Copper (Not to scale) Actual board size = 700 mil x 700 mil Total copper layer = 2 Connect to the ground plane of the board Connect to the LDO output voltage plane of the board Connect to the input output voltage at this point Connect to the ground plane of the board Connect to the input output voltage at this point Connect to the input output voltage at this point Connect to the BUCK output voltage plane of the board Connect to the ground plane of the board Connect to the input output voltage at this point Doc. No. MV-S102867-00 Rev. F Page 58 Document Classification: Proprietary Information Copyright (c) 2007 Marvell October 30, 2007, Advance PC Board Layout Considerations and Guidelines for 88PG8x7 Applicationswww..com Information Figure 53: Bottom Silk Screen, Bottom Trace, Vias, and Bottom Copper (Not to scale) Connect to the ground plane of the board Connect to the ground plane of the board Connect to SDI Connect to the ground plane of the board Connect to SHDN Connect to POR Connect to the ground plane of the board Connect to the ground plane of the board Copyright (c) 2007 Marvell October 30, 2007, Advance Document Classification: Proprietary Information Doc. No. MV-S102867-00 Rev. F Page 59 88PG8x7 1 MHz, 4.5A Peak Current-Limit Step-Down Regulator with AnyVoltageTM Technology www..com 6.2 Bill of materials for 88PG8x7 The following tables list the components used with the 88PG8x7. Table 11: Item 1 2 3 4 5 6 7 8 9 10 11 12 88PG847 BOM R ef U1 C1 C2 C3 C4 C5 L1 R1 R2 R3 R4 R5 Panasonic-ECG ERJ-2GEJ103X Panasonic-ECG ERJ-2GEJ104X Manufacturer Marvell Semiconductor TDK TDK TDK TDK TDK Toko Panasonic-ECG Ma nu factu rer Pa rt # 88PG847x C1005X5R1A104K C2012X5R0J226MT C2012X5R0J226MT C2012X5R0J226MT C2012X5R0J226MT #A918BY-1R3M=P3 ERJ-2RKF10R0X Desc ription 1 MHz, 4.5A Peak Current-Limit Step-Down Regulator with LDO Regulator Controller 0.1 F, 10%, X5R, 10V, 0402 Case Size, Ceramic 22 F, 20%, X5R, 6.3V, 0805 Case Size, Ceramic 22 F, 20%, X5R, 6.3V, 0805 Case Size, Ceramic 22 F, 20%, X5R, 6.3V, 0805 Case Size, Ceramic 22 F, 20%, X5R, 6.3V, 0805 Case Size, Ceramic 1.3 H, 3.1A, 28.6 m, H = 2 mm, L = 6.2 mm, W = 6.3 mm 10, 1/16W, 1%, 0402 Case Size See Any Voltage Programming Table, 1/16W, 1%, 0402 Case Size 100 k, 1/16W, 5%, 0402 Case Size See Any Voltage Programming Table, 1/16W, 1%, 0402 Case Size 10 k, 1/16W, 5%, 0402 Case Size Table 12: Item 1 2 3 88PG837 BOM Re f U1 C1 C2 M anufacturer Marvell Semiconductor TDK C1005X5R1A104K Man ufac t ure r Part # 88PG837x De scr ip tio n 1 MHz, 3.0A Peak Current-Limit Step-Down Regulator with LDO Regulator Controller 0.1 F, 10%, X5R, 10V, 0402 Case Size, Ceramic Doc. No. MV-S102867-00 Rev. F Page 60 Document Classification: Proprietary Information Copyright (c) 2007 Marvell October 30, 2007, Advance Bill of materials for 88PG8x7 Applicationswww..com Information Table 12: Item 4 5 6 7 8 9 10 11 12 88PG837 BOM (Continued) Re f C3 C4 C5 L1 R1 R2 R3 R4 R5 Panasonic-ECG ERJ-2GEJ103X Panasonic-ECG ERJ-2GEJ104X TDK Toko Panasonic-ECG C2012X5R0J226MT A918CY-2R0M=P3 ERJ-2RKF10R0X 22 F, 20%, X5R, 6.3V, 0805 Case Size, Ceramic 2.0 H, 2.47A, 24 m, H = 2 mm, L = 6.2 mm, W = 6.3 mm 10, 1/16W, 1%, 0402 Case Size See Any Voltage Programming Table, 1/16W, 1%, 0402 Case Size 100 k, 1/16W, 5%, 0402 Case Size See Any Voltage Programming Table, 1/16W, 1%, 0402 Case Size 10 k, 1/16W, 5%, 0402 Case Size M anufacturer TDK Man ufac t ure r Part # C2012X5R0J226MT De scr ip tio n 22 F, 20%, X5R, 6.3V, 0805 Case Size, Ceramic Table 13: Item 1 2 3 4 5 6 7 8 9 88PG827 BOM Ref U1 C1 C2 C3 C4 C5 L1 R1 R2 TDK Toko Panasonic-ECG C2012X5R0J226MT A918BCY-3R3M=P3 ERJ-2RKF10R0X 22 F, 20%, X5R, 6.3V, 0805 Case Size, Ceramic 3.3 H, 1.99A, 39 m, H = 2 mm, L = 6.2 mm, W = 6.3 mm 10, 1/16W, 1%, 0402 Case Size See Any Voltage Programming Table, 1/16W, 1%, 0402 Case Size TDK C2012X5R0J226MT 22 F, 20%, X5R, 6.3V, 0805 Case Size, Ceramic Manu facturer Marvell Semiconductor TDK Man ufac tu rer Part # 88PG827x C1005X5R1A104K Des cription 1 MHz, 2.5A Peak Current-Limit Step-Down Regulator with LDO Regulator Controller 0.1 F, 10%, X5R, 10V, 0402 Case Size, Ceramic Copyright (c) 2007 Marvell October 30, 2007, Advance Document Classification: Proprietary Information Doc. No. MV-S102867-00 Rev. F Page 61 88PG8x7 1 MHz, 4.5A Peak Current-Limit Step-Down Regulator with AnyVoltageTM Technology www..com Table 13: Item 10 11 12 88PG827 BOM (Continued) Ref R3 R4 R5 Panasonic-ECG ERJ-2GEJ103X Manu facturer Panasonic-ECG Man ufactu rer Part # ERJ-2GEJ104X Des cription 100 k, 1/16W, 5%, 0402 Case Size See Any Voltage Programming Table, 1/16W, 1%, 0402 Case Size 10 k, 1/16W, 5%, 0402 Case Size Table 14: Item 1 2 3 4 5 6 7 8 9 10 11 12 88PG817 BOM Ref U1 C1 C2 C3 C4 C5 L1 R1 R2 R3 R4 R5 Panasonic-ECG ERJ-2GEJ103X Panasonic-ECG ERJ-2GEJ104X TDK Toko Panasonic-ECG C2012X5R0J106MT A918BCY-4R7M=P3 ERJ-2RKF10R0X 10 F, 20%, X5R, 6.3V, 0805 Case Size, Ceramic 4.7 H, 1.59A, 55 m, H = 2 mm, L = 6.2 mm, W = 6.3 mm 10, 1/16W, 1%, 0402 Case Size See Any Voltage Programming Table, 1/16W, 1%, 0402 Case Size 100 k, 1/16W, 5%, 0402 Case Size See Any Voltage Programming Table, 1/16W, 1%, 0402 Case Size 10 k, 1/16W, 5%, 0402 Case Size TDK C2012X5R0J106MT 10 F, 20%, X5R, 6.3V, 0805 Case Size, Ceramic Manu facturer Marvell Semiconductor TDK Man ufactu rer Part # 88PG817x C1005X5R1A104K Des cription 1MHz, 1.5A Peak Current-Limit Step-Down Regulator with LDO Regulator Controller 0.1 F, 10%, X5R, 10V, 0402 Case Size, Ceramic Doc. No. MV-S102867-00 Rev. F Page 62 Document Classification: Proprietary Information Copyright (c) 2007 Marvell October 30, 2007, Advance Bill of materials for 88PG8x7 Applicationswww..com Information Table 15: Ite m 1 88PG807 BOM Ref U1 M anu f actu rer Marvell Semiconductor TDK Man ufac tu rer Pa rt # 88PG807x Des criptio n 1 MHz, 0.75A Peak Current-Limit StepDown Regulator with LDO Regulator Controller 0.1 F, 10%, X5R, 10V, 0402 Case Size, Ceramic 2 3 4 5 6 7 8 9 10 11 12 C1 C2 C3 C4 C5 L1 R1 R2 R3 R4 R5 C1005X5R1A104K TDK C2012X5R0J106MT 10 F, 20%, X5R, 6.3V, 0805 Case Size, Ceramic TDK TDK Panasonic-ECG C2012X5R0J106MT VLF3010AT-4R7MR70 ERJ-2RKF10R0X 10 F, 20%, X5R, 6.3V, 0805 Case Size, Ceramic 4.7 H, 0.7A, 240 m, H = 1 mm, L = 2.6 mm, W = 2.8 mm 10, 1/16W, 1%, 0402 Case Size See Any Voltage Programming Table, 1/16W, 1%, 0402 Case Size Panasonic-ECG ERJ-2GEJ104X 100 k, 1/16W, 5%, 0402 Case Size See Any Voltage Programming Table, 1/16W, 1%, 0402 Case Size Panasonic-ECG ERJ-2GEJ103X 10 k, 1/16W, 5%, 0402 Case Size Table 16: Item 1 2 3 LDO Option BOM Ref Q1 C6 R6 Manu facturer Fairchild TDK Susumu Co Ltd. Man ufac tu rer Part # FDC642P C2012X5R0J106MT RL1220T-R047-J Des cription PFET, 2.5V, SuperSOT-6 Package 10 F, 20%, X5R, 6.3V, 0805 Case Size, Ceramic 0.047, 1/4W, 5%, 0805 Case Size Copyright (c) 2007 Marvell October 30, 2007, Advance Document Classification: Proprietary Information Doc. No. MV-S102867-00 Rev. F Page 63 88PG8x7 1 MHz, 4.5A Peak Current-Limit Step-Down Regulator with AnyVoltageTM Technology www..com Table 17: Ceramic Capacitor Cross Reference Manu factu rer Part # Taiyo-Yuden TDK Murata Des cription CE JMK212BJ226MG-T C2012X5R0J226MT GRM21BR60J226ME39L CE JMK212BJ106MG-T C2012X5R0J106MT GRM219R60J106KE190 RM LMK105 BJ104KV-F C1005X5R1A104K Manu facturer 22 F 10 F Taiyo-Yuden TDK Murata 0.1 F Taiyo-Yuden TDK Doc. No. MV-S102867-00 Rev. F Page 64 Document Classification: Proprietary Information Copyright (c) 2007 Marvell October 30, 2007, Advance 88PG8x7 Mechanical Drawing Mechanical Drawing www..com Section 7. Mechanical Drawing 7.1 88PG8x7 Mechanical Drawing Copyright (c) 2007 Marvell October 30, 2007, Advance Document Classification: Proprietary Information Doc. No. MV-S102867-00 Rev. F Page 65 88PG8x7 1 MHz, 4.5A Peak Current-Limit Step-Down Regulator with AnyVoltageTM Technology www..com 7.2 Dimensions D i m e n s i on s in m m Symbol A A1 A3 b D E e L aaa bbb ccc 0.30 ---0.20 2.90 2.90 MIN 0.80 0.00 NOM 0.90 0.02 0.20 REF 0.25 3.00 3.00 0.50 BSC 0.40 ---0.50 0.15 0.10 0.10 0.012 ---0.30 3.10 3.10 0.008 0.114 0.114 MAX 1.00 0.05 D i m e nsi on s i n in c h M IN 0.031 0.000 NOM 0.035 0.001 0.008 REF 0.010 0.118 0.118 0.020 BSC 0.016 ---0.020 0.006 0.004 0.004 0.012 0.122 0.122 M AX 0.039 0.002 Notes: 1. 2. 3. 4. 5. DIMENSIONS AND TOLERANCES CONFORM TO ASME Y14.5M-1994 DRAWINGS NOT TO SCALE DIMENSIONS ARE IN MILLIMETERS TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION PIN 1 (0.5 mm) IS LONGER THAN OTHER PINS (0.4 mm) Doc. No. MV-S102867-00 Rev. F Page 66 Document Classification: Proprietary Information Copyright (c) 2007 Marvell October 30, 2007, Advance Typical Pad Layout Dimensions Mechanical Drawing www..com 7.3 Typical Pad Layout Dimensions 7.3.1 Recommended Solder Pad Layout 0.65 Package Outline 1 0.50 2.20 3.30 0.25 0.55 2.20 3.30 3x3 QFN-16 Land Pattern (mm) 0.25 mm Pad SM Pad SM 0.25 mm Pad 0.051 mm 2.0 mils 0.148 mm Non-Solder Mask Defined Terminal See Notes 4 and 5 Notes: 1. 2. 3. 4. 5. 6. 7. TOP VIEW DRAWING NOT TO SCALE DIMENSIONS ARE IN MILLIMETERS OVERSIZE SOLDER MASK BY 4 MILS OVER PAD SIZE (2 MIL ANNULAR RING) 0.148 mm SOLDER MASK (SM) BETWEEN PADS TOLERANCE 0.05 mm PIN 1 IS LONGER THAN OTHER PINS BY 0.1 mm Copyright (c) 2007 Marvell October 30, 2007, Advance Document Classification: Proprietary Information Doc. No. MV-S102867-00 Rev. F Page 67 88PG8x7 www..com 1 MHz, 4.5A Peak Current-Limit Step-Down Regulator with AnyVoltageTM Technology Section 8. Ordering Information 8.1 Ordering Part Numbers and Package Markings Figure 54 shows the ordering part numbering scheme for the 88PG8x7 devices. Contact Marvell(R) FAEs or sales representatives for complete ordering information. Figure 54: Sample Part Number 88PG8X7 X XX Part Number 88PG847 88PG837 88PG827 88PG817 88PG807 LDO Output Voltage Options B = 3.3V E = 2.5V Custom Code - XXX 1 C000 - T Custom (optional) Custom Code Environmental 1 = RoHS 6/6 compliant "-" = RoHS 5/6 compliant Package Code NAM = 16-pin QFN Doc. No. MV-S102867-00, Rev. F Page 68 Document Classification: Proprietary Information Copyright (c) 2007 Marvell October 30, 2007, Advance Sample Ordering Part Number Orderingwww..com Information 8.2 Sample Ordering Part Number The standard ordering part numbers for the respective solutions are as follows: Table 18: 88PG8x7 Ordering Part Numbers1 Ma r k in g LD O A m bient Tem per atur e Range 2 -40 C to 85 C -40 C to 85 C -40 C to 85 C -40 C to 85 C -40 C to 85 C -40 C to 85 C -40 C to 85 C -40 C to 85 C -40 C to 85 C -40 C to 85 C Pa cka ge 3 Mark eting Part Numbe r 88PG847B-NAM1 88PG837B-NAM1 88PG827B-NAM1 88PG817B-NAM1 88PG807B-NAM1 88PG847E-NAM1 88PG837E-NAM1 88PG827E-NAM1 88PG817E-NAM1 88PG807E-NAM1 G47B G37B G27B G17B G07B G47E G37E G27E G17E G07E 3.3V 3.3V 3.3V 3.3V 3.3V 2.5V 2.5V 2.5V 2.5V 2.5V 3 X 3 QFN-16 3 X 3 QFN-16 3 X 3 QFN-16 3 X 3 QFN-16 3 X 3 QFN-16 3 X 3 QFN-16 3 X 3 QFN-16 3 X 3 QFN-16 3 X 3 QFN-16 3 X 3 QFN-16 1. Contact Marvell(R) for details. 2. Specifications over the -40 C to 85 C operating temperature range are assured by design, characterization and correlation with statistical process controls. 3. Package dimensions are in mm. 8.3 Package Marking 8.3.1 Sample Package Marking and Pin 1 Locations Figure 55 is an example of the package marking and pin 1 location for the 88PG847 part. Markings for the other variants are similar. Figure 55: 88PG847 Package Marking and Pin 1 Location M a r v e l l S e m ic o n du c to r Marking Year, Work week, Assembly code Y WW = Last digit of year = Work week P = Assembly code MRVL G47B YWWP Pin 1 location Note: The above example is not drawn to scale. Locations of markings are approximate. Copyright (c) 2007 Marvell October 30, 2007, Advance Document Classification: Proprietary Information Doc. No. MV-S102867-00, Rev. F Page 69 www..com Marvell Semiconductor, Inc. 700 First Avenue Sunnyvale, CA 94089 Phone 408.222.2500 Fax 408.752.9028 www.marvell.com Worldwide Corporate Offices Marvell Semiconductor, Inc. 700 First Avenue Sunnyvale, CA 94089, USA Tel: 1.408.222.2500 Fax: 1.408.752.9028 Marvell Semiconductor, Inc. 5400 Bayfront Plaza Santa Clara, CA 95054, USA Tel: 1.408.222.2500 Marvell Asia Pte, Ltd. 151 Lorong Chuan, #02-05 New Tech Park, Singapore 556741 Tel: 65.6756.1600 Fax: 65.6756.7600 Marvell Japan K.K. Shinjuku Center Bldg. 44F 1-25-1, Nishi-Shinjuku, Shinjuku-ku Tokyo 163-0644, Japan Tel: 81.(0).3.5324.0355 Fax: 81.(0).3.5324.0354 Marvell Semiconductor Israel, Ltd. 6 Hamada Street Mordot HaCarmel Industrial Park Yokneam 20692, Israel Tel: 972.(0).4.909.1500 Fax: 972.(0).4.909.1501 Marvell Semiconductor Korea, Ltd. Rm. 603, Trade Center 159-2 Samsung-Dong, Kangnam-Ku Seoul 135-731, Korea Tel: 82.(0).2.551-6070/6079 Fax: 82.(0).2.551.6080 Radlan Computer Communications, Ltd. Atidim Technological Park, Bldg. #4 Tel Aviv 61131, Israel Tel: 972.(0).3.645.8555 Fax: 972.(0).3.645.8544 Worldwide Sales Offices Western US Marvell 700 First Avenue Sunnyvale, CA 94089, USA Tel: 1.408.222.2500 Fax: 1.408.752.9028 Sales Fax: 1.408.752.9029 Marvell 5400 Bayfront Plaza Santa Clara, CA 95054, USA Tel: 1.408.222.2500 Central US Marvell 9600 North MoPac Drive, Suite #215 Austin, TX 78759, USA Tel: 1.512.343.0593 Fax: 1.512.340.9970 Eastern US/Canada Marvell Parlee Office Park 1 Meeting House Road, Suite 1 Chelmsford, MA 01824 , USA Tel: 1.978.250.0588 Fax: 1.978.250.0589 Europe Marvell 5 Marchmont Gate Boundary Way Hemel Hempstead Hertfordshire, HP2 7BF United Kingdom Tel: 44.(0).1442.211668 Fax: 44.(0).1442.211543 Worldwide Sales Offices Western US Marvell 700 First Avenue Sunnyvale, CA 94089, USA Tel: 1.408.222.2500 Fax: 1.408.752.9028 Sales Fax: 1.408.752.9029 Marvell 5400 Bayfront Plaza Santa Clara, CA 95054, USA Tel: 1.408.222.2500 Central US Marvell 9600 North MoPac Drive, Suite #215 Austin, TX 78759, USA Tel: 1.512.343.0593 Fax: 1.512.340.9970 Eastern US/Canada Marvell Parlee Office Park 1 Meeting House Road, Suite 1 Chelmsford, MA 01824 , USA Tel: 1.978.250.0588 Fax: 1.978.250.0589 Europe Marvell 5 Marchmont Gate Boundary Way Hemel Hempstead Hertfordshire, HP2 7BF United Kingdom Tel: 44.(0).1442.211668 Fax: 44.(0).1442.211543 For more information, visit our website at: www.marvell.com |
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