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12-Bit, 20/40/65 MSPS 3 V A/D Converter AD9235
FEATURES
Single 3 V supply operation (2.7 V to 3.6 V) SNR = 70 dBc to Nyquist at 65 MSPS SFDR = 85 dBc to Nyquist at 65 MSPS Low power: 300 mW at 65 MSPS Differential input with 500 MHz bandwidth On-chip reference and SHA DNL = 0.4 LSB Flexible analog input: 1 V p-p to 2 V p-p range Offset binary or twos complement data format Clock duty cycle stabilizer
VIN+ SHA VIN- REFT REFB CORRECTION LOGIC 12 OUTPUT BUFFERS OTR D11 D0 CLOCK DUTY CYCLE STABILIZER REF SELECT 0.5V MODE SELECT
02461-001
FUNCTIONAL BLOCK DIAGRAM
AVDD DRVDD 8-STAGE 1 1/2-BIT PIPELINE 16
MDAC1 4 A/D
A/D 3
AD9235
VREF
APPLICATIONS
Ultrasound equipment IF sampling in communications receivers IS-95, CDMA-One, IMT-2000 Battery-powered instruments Hand-held scopemeters Low cost digital oscilloscopes
SENSE
AGND
CLK
PDWN
MODE
DGND
Figure 1.
GENERAL DESCRIPTION
The AD9235 is a family of monolithic, single 3 V supply, 12-bit, 20/40/65 MSPS analog-to-digital converters (ADCs). This family features a high performance sample-and-hold amplifier (SHA) and voltage reference. The AD9235 uses a multistage differential pipelined architecture with output error correction logic to provide 12-bit accuracy at 20/40/65 MSPS data rates and guarantee no missing codes over the full operating temperature range. The wide bandwidth, truly differential SHA allows a variety of user-selectable input ranges and offsets including single-ended applications. It is suitable for multiplexed systems that switch full-scale voltage levels in successive channels and for sampling single-channel inputs at frequencies well beyond the Nyquist rate. Combined with power and cost savings over previously available ADCs, the AD9235 is suitable for applications in communications, imaging, and medical ultrasound. A single-ended clock input is used to control all internal conversion cycles. A duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance. The digital output data is presented in straight binary or twos complement formats. An out-of-range (OTR) signal indicates an overflow condition that
Rev. C
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can be used with the most significant bit to determine low or high overflow. Fabricated on an advanced CMOS process, the AD9235 is available in a 28-lead TSSOP and a 32-lead LFCSP and is specified over the industrial temperature range (-40C to +85C).
PRODUCT HIGHLIGHTS
1. The AD9235 operates from a single 3 V power supply and features a separate digital output driver supply to accommodate 2.5 V and 3.3 V logic families. 2. Operating at 65 MSPS, the AD9235 consumes a low 300 mW. 3. The patented SHA input maintains excellent performance for input frequencies up to 100 MHz and can be configured for single-ended or differential operation. 4. The AD9235 pinout is similar to the AD9214-65, a 10-bit, 65 MSPS ADC. This allows a simplified upgrade path from 10 bits to 12 bits for 65 MSPS systems. 5. The clock DCS maintains overall ADC performance over a wide range of clock pulse widths. 6. The OTR output bit indicates when the signal is beyond the selected input range.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
AD9235 TABLE OF CONTENTS
Specifications..................................................................................... 3 DC Specifications ......................................................................... 3 Digital Specifications ................................................................... 4 Switching Specifications .............................................................. 4 AC Specifications.......................................................................... 5 Absolute Maximum Ratings............................................................ 7 Explanation of Test Levels........................................................... 7 ESD Caution.................................................................................. 7 Pin Configurations and Function Descriptions ........................... 8 Definitions of Specifications ........................................................... 9 Equivalent Circuits ......................................................................... 10 Typical Performance Characteristics ........................................... 11 Applying the AD9235 .................................................................... 15 Theory of Operation.................................................................. 15 Analog Input ............................................................................... 15 Clock Input Considerations...................................................... 16 Power Dissipation and Standby Mode .................................... 17 Digital Outputs ........................................................................... 18 Voltage Reference ....................................................................... 18 Operational Mode Selection ..................................................... 19 TSSOP Evaluation Board .......................................................... 19 LFCSP Evaluation Board........................................................... 20 Outline Dimensions ....................................................................... 36 Ordering Guide .......................................................................... 37
REVISION HISTORY
10/04--Data Sheet changed from Rev. B to Rev. C Changes to Format .............................................................Universal Changes to Specifications .................................................................3 Changes to the Ordering Guide.................................................... 37 5/03--Data Sheet changed from Rev. A to Rev. B Added CP-32 Package (LFCSP)........................................Universal Changes to Several Pin Names .........................................Universal Changes to Features...........................................................................1 Changes to Product Description .....................................................1 Changes to Product Highlights........................................................1 Changes to Specifications .................................................................2 Replaced Figure 1 ..............................................................................3 Changes to Absolute Maximum Ratings ........................................5 Changes to Ordering Guide .............................................................5 Changes to Pin Function Descriptions...........................................6 New Definitions of Specifications Section .....................................7 Changes to TPCs 1 to 12...................................................................9 Changes to Theory of Operation Section.................................... 13 Changes to Analog Input Section..................................................13 Changes to Single-ended Input Configuration Section .............14 Replaced Figure 8 ............................................................................14 Changes to Clock Input Considerations Section ........................14 Changes to Table I ...........................................................................15 Changes to Power Dissipation and Standby Mode Section .......15 Changes to Digital Outputs Section..............................................15 Changes to Timing Section ............................................................15 Changes to Figure 13.......................................................................16 Changes to Figures 16 to 26 ...........................................................17 Added LFCSP Evaluation Board Section .....................................17 Inserted Figures 27 to 35 ................................................................25 Added Table III ................................................................................30 Updated Outline Dimensions........................................................31 8/02--Data Sheet changed from Rev. 0 to Rev. A Updated RU-28 Package................................................................ 24
Rev. C | Page 2 of 40
AD9235 SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, TMIN to TMAX, unless otherwise noted. Table 1.
Parameter RESOLUTION ACCURACY No Missing Codes Guaranteed Offset Error Gain Error1 Differential Nonlinearity (DNL)2 Integral Nonlinearity (INL)2 TEMPERATURE DRIFT Offset Error Gain Error INTERNAL VOLTAGE REFERENCE Output Voltage Error (1 V Mode) Load Regulation @ 1.0 mA Output Voltage Error (0.5 V Mode) Load Regulation @ 0.5 mA INPUT REFERRED NOISE VREF = 0.5 V VREF = 1.0 V ANALOG INPUT Input Span, VREF = 0.5 V Input Span, VREF = 1.0 V Input Capacitance3 REFERENCE INPUT RESISTANCE POWER SUPPLIES Supply Voltages AVDD DRVDD Supply Current IAVDD2 IDRVDD2 PSRR POWER CONSUMPTION DC Input4 Sine Wave Input2 Standby Power5 Temp Full Full Full Full Full 25C Full 25C Full Full Full Full Full Full 25C 25C Full Full Full Full Test Level VI VI VI VI IV I IV I V V VI V V V V V IV IV V V AD9235BRU/BCP-20 Min Typ Max 12 12 0.30 0.30 0.35 0.35 0.45 0.40 2 12 5 0.8 2.5 0.1 0.54 0.27 1 2 7 7 35 1.20 2.40 0.65 0.80 AD9235BRU/BCP-40 Min Typ Max 12 12 0.50 0.50 0.35 0.35 0.50 0.40 2 12 5 0.8 2.5 0.1 0.54 0.27 1 2 7 7 35 1.20 2.50 0.75 0.90 AD9235BRU/BCP-65 Min Typ Max 12 12 0.50 0.50 0.40 0.35 0.70 0.45 3 12 5 0.8 2.5 0.1 0.54 0.27 1 2 7 7 35 1.20 2.60 0.80 1.30 Unit Bits Bits % FSR % FSR LSB LSB LSB LSB ppm/C ppm/C mV mV mV mV LSB rms LSB rms V p-p V p-p pF k
Full Full Full Full Full Full Full Full
IV IV V V V V VI V
2.7 2.25
3.0 3.0 30 2 0.01 90 95 1.0
3.6 3.6
2.7 2.25
3.0 3.0 55 5 0.01 165 180 1.0
3.6 3.6
2.7 2.25
3.0 3.0 100 7 0.01 300 320 1.0
3.6 3.6
V V mA mA % FSR mW mW mW
110
205
350
1 2
Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.0 V external reference). Measured at maximum clock rate, fIN = 2.4 MHz, full-scale sine wave, with approximately 5 pF loading on each output bit. 3 Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 5 for the equivalent analog input structure. 4 Measured with dc input at maximum clock rate. 5 Standby power is measured with a dc input, the CLK pin inactive (i.e., set to AVDD or AGND).
Rev. C | Page 3 of 40
AD9235
DIGITAL SPECIFICATIONS
Table 2.
Parameter LOGIC INPUTS High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance LOGIC OUTPUTS1 DRVDD = 3.3 V High-Level Output Voltage (IOH = 50 A) High-Level Output Voltage (IOH = 0.5 mA) Low-Level Output Voltage (IOL = 1.6 mA) Low-Level Output Voltage (IOL = 50 A) DRVDD = 2.5 V High-Level Output Voltage (IOH = 50 A) High-Level Output Voltage (IOH = 0.5 mA) Low-Level Output Voltage (IOL = 1.6 mA) Low-Level Output Voltage (IOL = 50 A) Temp Full Full Full Full Full Test Level IV IV IV IV V AD9235BRU/BCP-20 Min Typ Max 2.0 -10 -10 2 0.8 +10 +10 AD9235BRU/BCP-40 Min Typ Max 2.0 -10 -10 2 0.8 +10 +10 AD9235BRU/BCP-65 Min Typ Max 2.0 -10 -10 2 0.8 +10 +10 Unit V V A A pF
Full Full Full Full
IV IV IV IV
3.29 3.25 0.2 0.05
3.29 3.25 0.2 0.05
3.29 3.25 0.2 0.05
V V V V
Full Full Full Full
IV IV IV IV
2.49 2.45 0.2 0.05
2.49 2.45 0.2 0.05
2.49 2.45 0.2 0.05
V V V V
1
Output voltage levels measured with 5 pF load on each output.
SWITCHING SPECIFICATIONS
Table 3.
Parameter CLOCK INPUT PARAMETERS Maximum Conversion Rate Minimum Conversion Rate CLK Period CLK Pulse-Width High1 CLK Pulse-Width Low1 DATA OUTPUT PARAMETERS Output Delay2 (tPD) Pipeline Delay (Latency) Aperture Delay (tA) Aperture Uncertainty Jitter (tJ) Wake-Up Time3 OUT-OF-RANGE RECOVERY TIME Temp Full Full Full Full Full Full Full Full Full Full Full Test Level VI V V V V V V V V V V AD9235BRU/BCP-20 Min Typ Max 20 1 50.0 15.0 15.0 3.5 7 1.0 0.5 3.0 1 25.0 8.8 8.8 3.5 7 1.0 0.5 3.0 1 AD9235BRU/BCP-40 Min Typ Max 40 1 15.4 6.2 6.2 3.5 7 1.0 0.5 3.0 2 AD9235BRU/BCP-65 Min Typ Max 65 1 Unit MSPS MSPS ns ns ns ns Cycles ns ps rms ms Cycles
1 2 3
For the AD9235-65 model only, with duty cycle stabilizer enabled. DCS function not applicable for -20 and -40 models. Output delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load on each output. Wake-up time is dependent on value of decoupling capacitors; typical values shown with 0.1 F and 10 F capacitors on REFT and REFB.
Rev. C | Page 4 of 40
AD9235
N N-1 ANALOG INPUT N+1 N+2 N+8 N+3 N+4 N+5 N+7 N+6
tA
CLK DATA OUT N-9 N-8 N-7 N-6 N-5 N-4 N-3 N-2 N-1 N
tPD = 6.0ns MAX
2.0ns MIN
Figure 2. Timing Diagram
AC SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, AIN = -0.5 dBFS, 1.0 V internal reference, TMIN to TMAX, unless otherwise noted. Table 4.
Parameter SIGNAL-TO-NOISE RATIO fINPUT = 2.4 MHz fINPUT = 9.7 MHz fINPUT = 19.6 MHz fINPUT = 32.5 MHz fINPUT = 100 MHz SIGNAL-TO-NOISE RATIO AND DISTORTION fINPUT = 2.4 MHz fINPUT = 9.7 MHz fINPUT = 19.6 MHz fINPUT = 32.5 MHz fINPUT = 100 MHz TOTAL HARMONIC DISTORTION fINPUT = 2.4 MHz fINPUT = 9.7 MHz fINPUT = 19.6 MHz fINPUT = 32.5 MHz fINPUT = 100 MHz WORST HARMONIC (SECOND OR THIRD) fINPUT = 9.7 MHz fINPUT = 19.6 MHz fINPUT = 32.5 MHz Temp 25C Full 25C Full 25C Full 25C 25C Test Level V IV I IV I IV I V AD9235BRU/BCP-20 Min Typ Max 70.8 70.4 70.6 69.9 AD9235BRU/BCP-40 Min Typ Max 70.6 AD9235BRU/BCP-65 Min Typ Max 70.5 Unit dBc dBc dBc dBc dBc dBc dBc dBc
70.0
70.3 70.4 68.7 69.7 70.1 68.3
68.7
68.5
25C Full 25C Full 25C Full 25C 25C 25C Full 25C Full 25C Full 25C 25C
V IV I IV I IV I V V IV I IV I IV I V
69.9
70.6 70.3 70.5 69.7
70.5
02461-002
70.4
70.2 70.3 68.3 69.5 69.9 67.8 -87.5
68.6 -88.0 -86.0 -87.4
68.3 -89.0 -79.0 -85.5 -86.0 -79.0
dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc
-84.0
-82.5
-81.8 -82.0 -78.0
-74.0
Full Full Full
IV IV IV
-90.0
-80.0 -90.0 -80.0 -83.5 -74.0
dBc dBc dBc
Rev. C | Page 5 of 40
AD9235
Parameter SPURIOUS-FREE DYNAMIC RANGE fINPUT = 2.4 MHz fINPUT = 9.7 MHz fINPUT = 19.6 MHz fINPUT = 32.5 MHz fINPUT = 100 MHz Temp 25C Full 25C Full 25C Full 25C 25C Test Level V IV I IV I IV I V AD9235BRU/BCP-20 Min Typ Max 92.0 88.5 91.0 80.0 AD9235BRU/BCP-40 Min Typ Max 92.0 AD9235BRU/BCP-65 Min Typ Max 92.0 Unit dBc dBc dBc dBc dBc dBc dBc dBc
80.0
89.0 90.0 74.0 83.0 85.0 80.5
84.0
85.0
Rev. C | Page 6 of 40
AD9235 ABSOLUTE MAXIMUM RATINGS
Table 5.
With Respect to Pin Name ELECTRICAL AVDD AGND DRVDD DGND AGND DGND AVDD DRVDD DGND Digital Outputs CLK, MODE AGND VIN+, VIN- AGND VREF AGND SENSE AGND REFB, REFT AGND PDWN AGND ENVIRONMENTAL1 Operating Temperature Junction Temperature Lead Temperature (10 sec) Storage Temperature Min -0.3 -0.3 -0.3 -3.9 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -40 Max +3.9 +3.9 +0.3 +3.9 DRVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 +85 150 300 +150 Unit V V V V V V V V V V V C C C C
Absolute maximum ratings are limiting values to be applied individually and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability.
EXPLANATION OF TEST LEVELS
Test Levels I II III IV V VI Description 100% production tested. 100% production tested at 25C and sample tested at specified temperatures. Sample tested only. Parameter is guaranteed by design and characterization testing. Parameter is a typical value only. 100% production tested at 25C; guaranteed by design and characterization testing for industrial temperature range; 100% production tested at temperature extremes for military devices.
-65
1
Typical thermal impedances (28-lead TSSOP), JA = 67.7C/W; (32-lead LFCSP), JA = 32.5C/W, JC = 32.71C/W. These measurements were taken on a 4-layer board in still air, in accordance with EIA/JESD51-1.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. C | Page 7 of 40
AD9235 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
OTR 1 MODE 2 SENSE 3 VREF 4 REFB 5 REFT 6 AVDD
7 28 27 26 25
D11 (MSB) D10 D9 D8 DRVDD DGND D7 D6 D5 D4 D2 D0 (LSB)
02461-003
AD9235
TOP VIEW (Not to Scale)
24 23 22 21 20 19 18 17 16 15
AGND 8 VIN+ 9 VIN- 10 AGND 11 AVDD 12 CLK 13 PDWN 14
DNC CLK DNC PDWN DNC DNC (LSB)D0 D1
32 AVDD 31 AGND 30 VIN- 29 VIN+ 28 AGND 27 AVDD 26 REFT 25 REFB
1 2 3 4 5 6 7 8
PIN 1 INDICATOR
AD9235
TOP VIEW (Not to Scale)
24 VREF 23 SENSE 22 MODE 21 OTR 20 D11(MSB) 19 D10 18 D9 17 D8
D1
DNC = DO NOT CONNECT
Figure 3. 28-Lead TSSOP Pin Configuration
Figure 4. 32-Lead LFCSP Pin Configuration
Table 6. Pin Function Descriptions
Pin No. 28-Lead TSSOP 1 2 3 4 5 6 7, 12 8, 11 9 10 13 14 15 to 22, 25 to 28 23 24 Pin No. 32-Lead LFCSP 21 22 23 24 25 26 27, 32 28, 31 29 30 2 4 7 to 14, 17 to 20 15 16 1, 3, 5, 6 Mnemonic OTR MODE SENSE VREF REFB REFT AVDD AGND VIN+ VIN- CLK PDWN D0 (LSB) to D11 (MSB) DGND DRVDD DNC Description Out-of-Range Indicator. Data Format and Clock Duty Cycle Stabilizer (DCS) Mode Selection. Reference Mode Selection. Voltage Reference Input/Output. Differential Reference (-). Differential Reference (+). Analog Power Supply. Analog Ground. Analog Input Pin (+). Analog Input Pin (-). Clock Input Pin. Power-Down Function Selection (Active High). Data Output Bits. Digital Output Ground. Digital Output Driver Supply. Must be decoupled to DGND with a minimum. 0.1 F capacitor. Recommended decoupling is 0.1 F in parallel with 10 F. Do Not Connect.
Rev. C | Page 8 of 40
02461-004
D3
D2 9 D3 10 D4 11 D5 12 D6 13 D7 14 DGND 15 DRVDD 16
AD9235 DEFINITIONS OF SPECIFICATIONS
Analog Bandwidth (Full Power Bandwidth) The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay (tA) The delay between the 50% point of the rising edge of the clock and the instant at which the analog input is sampled. Aperture Jitter (tJ) The sample-to-sample variation in aperture delay. Integral Nonlinearity (INL) The deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs 1/2 LSB before the first code transition. Positive full scale is defined as a level 1 1/2 LSBs beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line. Differential Nonlinearity (DNL, No Missing Codes) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to 12-bit resolution indicates that all 4096 codes must be present over all operating ranges. Offset Error The major carry transition should occur for an analog value 1/2 LSB below VIN+ = VIN-. Offset error is defined as the deviation of the actual transition from that point. Gain Error The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition should occur at an analog value 1 1/2 LSB below the positive full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. Temperature Drift The temperature drift for offset error and gain error specifies the maximum change from the initial (25C) value to the value at TMIN or TMAX. Power Supply Rejection Ratio The change in full scale from the value with the supply at the minimum limit to the value with the supply at its maximum limit. Total Harmonic Distortion (THD)1 The ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal. Signal-to-Noise and Distortion (SINAD)1 The ratio of the rms signal amplitude (set 0.5 dB below full scale) to the rms value of the sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. Effective Number of Bits (ENOB) The ENOB for a device for sine wave inputs at a given input frequency can be calculated directly from its measured SINAD using the following formula N = (SINAD - 1.76)/6.02 Signal-to-Noise Ratio (SNR)1 The ratio of the rms signal amplitude (set at 0.5 dB below full scale) to the rms value of the sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. Spurious-Free Dynamic Range (SFDR)1 The difference in dB between the rms amplitude of the input signal and the peak spurious signal. Two-Tone SFDR1 The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. Clock Pulse Width and Duty Cycle Pulse-width high is the minimum amount of time that the clock pulse should be left in the Logic 1 state to achieve rated performance. Pulse-width low is the minimum time the clock pulse should be left in the low state. At a given clock rate, these specifications define an acceptable clock duty cycle. Minimum Conversion Rate The clock rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit. Maximum Conversion Rate The clock rate at which parametric testing is performed. Output Propagation Delay (tPD) The delay between the clock logic threshold and the time when all bits are within valid logic levels. Out-of-Range Recovery Time The time it takes for the ADC to reacquire the analog input after a transition from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale.
1
AC specifications may be reported in dBc (degrades as signal levels are lowered) or in dBFS (always related back to converter full scale). Rev. C | Page 9 of 40
AD9235 EQUIVALENT CIRCUITS
AVDD
DRVDD
VIN+, VIN-
02461-005
D11-D0, OTR
02461-007
Figure 5. Equivalent Analog Input Circuit
AVDD
Figure 7. Equivalent Digital Output Circuit
AVDD
MODE 20k
02461-006
CLK, PDWN
02461-008
Figure 6. Equivalent MODE Input Circuit
Figure 8. Equivalent Digital Input Circuit
Rev. C | Page 10 of 40
AD9235 TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 3.0 V, DRVDD = 2.5 V, fSAMPLE = 65 MSPS with DCS disabled, TA = 25C, 2 V differential input, AIN = -0.5 dBFS, VREF = 1.0 V, unless otherwise noted.
0
SNR = 70.3dBc SINAD = 70.2dBc ENOB = 11.4 BITS THD = -86.3dBc SFDR = 89.9dBc 100 95 90 85
SFDR (2V DIFF)
-20
MAGNITUDE (dBFS)
-40
SNR/SFDR (dBc)
80
SNR (2V SE)
75 70 65 60 55
-60
-80
SNR (2V DIFF)
-100
SFDR (2V SE)
45 50 55 SAMPLE RATE (MSPS) 60 65
02461-012 02461-014 02461-013
0
6.5
13.0 19.5 FREQUENCY (MHz)
26.0
32.5
Figure 9. Single Tone 8K FFT with fIN = 10 MHz
02461-009
-120
50 40
Figure 12. AD9235-65: Single Tone SNR/SFDR vs. fCLK with fIN = Nyquist (32.5 MHz)
100
0 SNR = 69.4dBc SINAD = 69.1dBc ENOB = 11.2 BITS THD = -81.0dBc SFDR = 83.8dBc
95 90 85
-20
MAGNITUDE (dBFS)
-40
SNR/SFDR (dBc)
SFDR (2V DIFF)
80 75 70 65
-60
SNR (2V SE)
SNR (2V DIFF)
-80
SFDR (2V SE)
-100
60 55
02461-010
-120 65.0
71.5
78.0 84.5 FREQUENCY (MHz)
91.0
50 20
25
30 SAMPLE RATE (MSPS)
35
40
Figure 10. Single Tone 8K FFT with fIN = 70 MHz
0 SNR = 68.5dBc SINAD = 66.5dBc ENOB = 10.8 BITS THD = -71.0dBc SFDR = 71.2dBc
Figure 13. AD9235-40: Single Tone SNR/SFDR vs. fCLK with fIN = Nyquist (20 MHz)
100 95 90 85
SFDR (2V DIFF)
-20
MAGNITUDE (dBFS)
-40
SNR/SFDR (dBc)
SFDR (2V SE)
80 75 70 65 60 55
SNR (2V DIFF) SNR (2V SE)
-60
-80
-100
02461-011
-120 97.5
50 0 5 10 SAMPLE RATE (MSPS) 15 20
104.0
110.5 117.0 FREQUENCY (MHz)
123.5
130.0
Figure 11. Single Tone 8K FFT with fIN = 100 MHz
Figure 14. AD9235-20: Single Tone SNR/SFDR vs. fCLK with fIN = Nyquist (10 MHz)
Rev. C | Page 11 of 40
AD9235
100 SFDR SINGLE-ENDED (dBFS) SFDR DIFFERENTIAL (dBc) 80 SFDR DIFFERENTIAL (dBFS) 95
90
90
SFDR
SNR/SFDR (dBFS and dBc)
70 SNR SINGLE-ENDED (dBFS) 60 SFDR SINGLE-ENDED (dBc)
SNR/SFDR (dBc)
SNR DIFFERENTIAL (dBFS)
85
80
75
SNR
50
SNR SINGLE-ENDED (dBc)
70
SNR DIFFERENTIAL (dBc)
02461-015
-25
-20
-15 AIN (dBFS)
-10
-5
0
0
25
50 75 INPUT FREQUENCY (MHz)
100
125
Figure 15. AD9235-65: Single Tone SNR/SFDR vs. AIN with fIN = Nyquist (32.5 MHz)
100 SFDR DIFFERENTIAL (dBFS) SFDR SINGLE-ENDED (dBFS)
95
Figure 18. AD9235-65: SNR/SFDR vs. fIN
90
90
SFDR
SNR/SFDR (dBFS and dBc)
SNR/SFDR (dBc)
80
SFDR DIFFERENTIAL SNR DIFFERENTIAL (dBc) (dBFS)
85
70 SNR SINGLE-ENDED (dBFS) SNR DIFFERENTIAL (dBc) SFDR SINGLE-ENDED (dBc)
80
60
75 SNR 70
50 SNR SINGLE-ENDED (dBc)
02461-016
-25
-20
-15 AIN (dBFS)
-10
-5
0
0
25
50 75 INPUT FREQUENCY (MHz)
100
125
Figure 16. AD9235-40: Single Tone SNR/SFDR vs. AIN with fIN = Nyquist (20 MHz)
100 SFDR DIFFERENTIAL (dBFS) 90 SFDR DIFFERENTIAL (dBc) SFDR SINGLE-ENDED(dBc)
90 95
Figure 19. AD9235-40: SNR/SFDR vs. fIN
SNR/SFDR (dBFS and dBc)
SFDR SINGLE-ENDED (dBFS) 80 SNR DIFFERENTIAL (dBFS)
SFDR 85
SNR/SFDR (dBc)
70 SNR SINGLE-ENDED (dBFS) 60 SNR DIFFERENTIAL(dBc)
80
75 SNR 70
50 SNR SINGLE-ENDED (dBc)
02461-017
-25
-20
-15 AIN (dBFS)
-10
-5
0
0
25
50 75 INPUT FREQUENCY (MHz)
100
125
Figure 17. AD9235-20: Single Tone SNR/SFDR vs. AIN with fIN = Nyquist (10 MHz)
Figure 20. AD9235-20: SNR/SFDR vs. fIN
Rev. C | Page 12 of 40
02461-020
40 -30
65
02461-019
40 -30
65
02461-018
40 -30
65
AD9235
0
SNR = 64.6dBFS SFDR = 81.6dBFS 95 2V SFDR 90 85
-20
1V SFDR
MAGNITUDE (dBFS)
SNR/SFDR (dBFS)
-40
80 75 2V SNR 1V SNR
-60
-80
70
-100
65 60 -24
02461-021
39.0
45.5 52.0 FREQUENCY (MHz)
58.5
65.0
-21
-18
-15 AIN (dBFS)
-12
-9
-6
Figure 21. Dual Tone 8K FFT with fIN1 = 45 MHz and fIN2 = 46 MHz
0 SNR = 64.3dBFS SFDR = 81.1dBFS -20
Figure 24. Dual Tone SNR/SFDR vs. AIN with fIN1 = 45 MHz and fIN2 = 46 MHz
95 2V SFDR 90 1V SFDR 85
MAGNITUDE (dBFS)
SNR/SFDR (dBFS)
-40
80 75 2V SNR 70 1V SNR
-60
-80
-100
65 60 -24
02461-022
71.5
78.0 84.5 FREQUENCY (MHz)
91.0
97.5
-21
-18
-15 AIN (dBFS)
-12
-9
-6
Figure 22. Dual Tone 8K FFT with fIN1 = 69 MHz and fIN2 = 70 MHz
0 SNR = 62.5dBFS SFDR = 75.6dBFS -20
Figure 25. Dual Tone SNR/SFDR vs. AIN with fIN1 = 69 MHz and fIN2 = 70 MHz
95
90 85
2V SFDR 1V SFDR
MAGNITUDE (dBFS)
SNR/SFDR (dBFS)
-40
80 75
-60
-80
70
2V SNR 1V SNR
-100
65 60 -24
02461-023
136.5
143.0 149.5 FREQUENCY (MHz)
156.0
162.0
-21
-18
-15 AIN (dBFS)
-12
-9
-6
Figure 23. Dual Tone 8K FFT with fIN1 = 144 MHz and fIN2 = 145 MHz
Figure 26. Dual Tone SNR/SFDR vs. AIN with fIN1 = 144 MHz and fIN2 = 145 MHz
Rev. C | Page 13 of 40
02461-026
-120 130.0
02461-025
-120 65.0
02461-024
-120 32.5
AD9235
75 12.2
20 15
72
AD9235-20: 2V SINAD
AD9235-40: 2V SINAD
AD9235-65: 11.7 2V SINAD
10
GAIN DRAFT (ppm/C)
02461-027
SINAD (dBc)
AD9235-20: 1V SINAD
AD9235-40: 1V SINAD
ENOB (Bits)
69
11.2
5 0 -5 -10 -15
02461-030 02461-032 02461-031
66
AD9235-65: 1V SINAD
10.7
63
10.2
60 0 10 20 30 40 SAMPLE RATE (MSPS) 50 60
9.7
-20 -40
-20
0
20 40 TEMPERATURE (C)
60
80
Figure 27. SINAD vs. fCLK with fIN = Nyquist
90 SFDR: DCS ON
Figure 30. A/D Gain vs. Temperature Using an External Reference
1.0 0.8
80 SFDR: DCS OFF SINAD: DCS ON
0.6 0.4 0.2
SINAD/SFDR (dBc)
70
60
SINAD: DCS OFF
INL (LSB)
60 65
02461-028
0 -0.2 -0.4 -0.6 -0.8
50
40
30 35
-1.0 0 500 1000 1500 2000 2500 CODE 3000 3500 4000
40
45
50 55 DUTY CYCLE (%)
Figure 28. SINAD/SFDR vs. Clock Duty Cycle
90 85 80 SFDR 2V DIFF
Figure 31. Typical INL
1.0 0.8 0.6
SINAD/SFDR (dBc)
75 70 65 60 55
SFDR 1V DIFF
0.4
SINAD 2V DIFF
DNL (LSB)
60 70 80
02461-029
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 500 1000 1500 2000 2500 CODE 3000 3500 4000
SINAD 1V DIFF
50 -40 -30 -20 -10
0 10 20 30 40 50 SAMPLE RATE (MSPS)
Figure 29. SINAD/SFDR vs. Temperature with fIN = 32.5 MHz
Figure 32. Typical DNL
Rev. C | Page 14 of 40
AD9235 APPLYING THE AD9235
THEORY OF OPERATION
The AD9235 architecture consists of a front end SHA followed by a pipelined switched capacitor ADC. The pipelined ADC is divided into three sections, consisting of a 4-bit first stage followed by eight 1.5-bit stages and a final 3-bit flash. Each stage provides sufficient overlap to correct for flash errors in the preceding stages. The quantized outputs from each stage are combined into a final 12-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate on a new input sample while the remaining stages operate on preceding samples. Sampling occurs on the rising edge of the clock. Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched capacitor DAC and interstage residue amplifier (MDAC). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. The input stage contains a differential SHA that can be ac- or dc-coupled in differential or single-ended modes. The outputstaging block aligns the data, carries out the error correction, and passes the data to the output buffers. The output buffers are powered from a separate supply, allowing adjustment of the output voltage swing. During power-down, the output buffers go into a high impedance state. For best dynamic performance, the source impedances driving VIN+ and VIN- should be matched such that common-mode settling errors are symmetrical. These errors are reduced by the common-mode rejection of the ADC.
H
T 5pF VIN+ CPAR
T
T 5pF VIN- CPAR T
02461-033
H
Figure 33. Switched-Capacitor SHA Input
An internal differential reference buffer creates positive and negative reference voltages, REFT and REFB, respectively, that define the span of the ADC core. The output common mode of the reference buffer is set to midsupply, and the REFT and REFB voltages and span are defined as: REFT = 1/2(AVDD + VREF) REFB = 1/2(AVDD - VREF) Span = 2 x (REFT - REFB) = 2 x VREF It can be seen from the equations above that the REFT and REFB voltages are symmetrical about the midsupply voltage and, by definition, the input span is twice the value of the VREF voltage.
90
THD 2.5MHz 2V DIFF
ANALOG INPUT
The analog input to the AD9235 is a differential switched capacitor SHA that has been designed for optimum performance while processing a differential input signal. The SHA input can support a wide common-mode range and maintain excellent performance, as shown in Figure 34. An input common-mode voltage of midsupply minimizes signaldependent errors and provides optimum performance. Referring to Figure 33, the clock signal alternatively switches the SHA between sample mode and hold mode. When the SHA is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within one-half of a clock cycle. A small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source. Also, a small shunt capacitor can be placed across the inputs to provide dynamic charging currents. This passive network creates a low-pass filter at the ADC's input; therefore, the precise values are dependent upon the application. In IF undersampling applications, any shunt capacitors should be removed. In combination with the driving source impedance, they would limit the input bandwidth.
-90 -85 -80
THD 35MHz 2V DIFF
85 80 75
SNR (dBc)
70 65 60 55 50 0 0.5 1.0 1.5 2.0 COMMON-MODE LEVEL (V) 2.5
SNR 35MHz 2V DIFF
-70 -65 -60 -55
Figure 34. AD9235-65: SNR, THD vs. Common-Mode Level
Rev. C | Page 15 of 40
02461-034
-50 3.0
THD (dBc)
SNR 2.5MHz 2V DIFF
-75
AD9235
The internal voltage reference can be pin-strapped to fixed values of 0.5 V or 1.0 V, or adjusted within the same range as discussed in the Internal Reference Connection section. Maximum SNR performance is achieved with the AD9235 set to the largest input span of 2 V p-p. The relative SNR degradation is 3 dB when changing from 2 V p-p mode to 1 V p-p mode. The SHA may be driven from a source that keeps the signal peaks within the allowable range for the selected reference voltage. The minimum and maximum common-mode input levels are defined as: VCMMIN = VREF/2 VCMMAX = (AVDD + VREF)/2 The minimum common-mode input level allows the AD9235 to accommodate ground-referenced inputs. Although optimum performance is achieved with a differential input, a single-ended source may be driven into VIN+ or VIN-. In this configuration, one input accepts the signal, while the opposite input should be set to midscale by connecting it to an appropriate reference. For example, a 2 V p-p signal may be applied to VIN+ while a 1 V reference is applied to VIN-. The AD9235 then accepts an input signal varying between 2 V and 0 V. In the single-ended configuration, distortion performance may degrade significantly as compared to the differential case. However, the effect is less noticeable at lower input frequencies and in the lower speed grade models (AD9235-40 and AD9235-20). differential transformer coupling is the recommended input configuration, as shown in Figure 36.
22 15pF 2Vp-p 49.9 22 1k 15pF 0.1F 1k
AVDD VIN+
AD9235
VIN- AGND
02461-036
Figure 36. Differential Transformer-Coupled Configuration
The signal characteristics must be considered when selecting a transformer. Most RF transformers saturate at frequencies below a few MHz, and excessive signal power can also cause core saturation, which leads to distortion.
Single-Ended Input Configuration
A single-ended input may provide adequate performance in cost-sensitive applications. In this configuration, there is degradation in SFDR and in distortion performance due to the large input common-mode swing. However, if the source impedances on each input are matched, there should be little effect on SNR performance. Figure 37 details a typical singleended input configuration.
0.33F 2Vp-p 49.9
1k 1k 1k
22 15pF 22 15pF
AVDD VIN+
Differential Input Configurations
As previously detailed, optimum performance is achieved while driving the AD9235 in a differential input configuration. For baseband applications, the AD8138 differential driver provides excellent performance and a flexible interface to the ADC. The output common-mode voltage of the AD8138 is easily set to AVDD/2, and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal.
AD9235
VIN-
02461-037
10F
0.1F
1k
AGND
Figure 37. Single-Ended Input Configuration
CLOCK INPUT CONSIDERATIONS
Typical high speed ADCs use both clock edges to generate a variety of internal timing signals, and as a result, may be sensitive to clock duty cycle. Commonly a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD9235 contains a clock duty cycle stabilizer (DCS) that retimes the nonsampling edge, providing an internal clock signal with a nominal 50% duty cycle. This allows a wide range of clock input duty cycles without affecting the performance of the AD9235. As shown in Figure 30, noise and distortion performance are nearly flat over a 30% range of duty cycle. The duty cycle stabilizer uses a delay-locked loop (DLL) to create the nonsampling edge. As a result, any changes to the sampling frequency require approximately 100 clock cycles to allow the DLL to acquire and lock to the new rate.
1Vp-p
49.9 499 22 1k 499 15pF AD8138 22 499 15pF
02461-035
AVDD VIN+
AD9235
VIN- AGND
0.1F
1k
523
Figure 35. Differential Input Configuration Using the AD8138
At input frequencies in the second Nyquist zone and above, the performance of most amplifiers is not adequate to achieve the true performance of the AD9235. This is especially true in IF undersampling applications where frequencies in the 70 MHz to 100 MHz range are being sampled. For these applications,
Rev. C | Page 16 of 40
AD9235
High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given full-scale input frequency (fINPUT) due only to aperture jitter (tJ) can be calculated by
TOTAL POWER (mW)
325 300 275 250 225 200 175 150 125 100 75 AD9235-20 0 10 20 30 40 SAMPLE RATE (MSPS) 50 60
02461-038
AD9235-65
SNR Degradation = -20 x log10[2 x fINPUT x tJ] In the equation, the rms aperture jitter, tJ, represents the rootsum square of all jitter sources, which include the clock input, analog input signal, and ADC aperture jitter specification. Undersampling applications are particularly sensitive to jitter. The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9235. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal-controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step.
AD9235-40
50
Figure 38. Total Power vs. Sample Rate with fIN = 10 MHz
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 38, the power dissipated by the AD9235 is proportional to its sample rate. The digital power dissipation does not vary substantially between the three speed grades because it is determined primarily by the strength of the digital drivers and the load on each output bit. The maximum DRVDD current can be calculated as IDRVDD = VDRVDD x CLOAD x fCLK x N where N is the number of output bits, 12 in the case of the AD9235. This maximum current occurs when every output bit switches on every clock cycle, i.e., a full-scale square wave at the Nyquist frequency, fCLK/2. In practice, the DRVDD current is established by the average number of output bits switching, which is determined by the encode rate and the characteristics of the analog input signal.
For the AD9235-20 speed grade, the digital power consumption can represent as much as 10% of the total dissipation. Digital power consumption can be minimized by reducing the capacitive load presented to the output drivers. The data in Figure 38 was taken with a 5 pF load on each output driver. The analog circuitry is optimally biased so that each speed grade provides excellent performance while affording reduced power consumption. Each speed grade dissipates a baseline power at low sample rates that increases linearly with the clock frequency. By asserting the PDWN pin high, the AD9235 is placed in standby mode. In this state, the ADC typically dissipates 1 mW if the CLK and analog inputs are static. During standby, the output drivers are placed in a high impedance state. Reasserting the PDWN pin low returns the AD9235 into its normal operational mode. Low power dissipation in standby mode is achieved by shutting down the reference, reference buffer, and biasing networks. The decoupling capacitors on REFT and REFB are discharged when entering standby mode and then must be recharged when returning to normal operation. As a result, the wake-up time is related to the time spent in standby mode, and shorter standby cycles result in proportionally shorter wake-up times. With the recommended 0.1 F and 10 F decoupling capacitors on REFT and REFB, it takes approximately 1 sec to fully discharge the reference buffer decoupling capacitors and 3 ms to restore full operation.
Rev. C | Page 17 of 40
AD9235
Table 7. Reference Configuration Summary
Selected Mode External Reference Internal Fixed Reference Programmable Reference Internal Fixed Reference SENSE Voltage AVDD VREF 0.2 V to VREF AGND to 0.2 V Internal Switch Position N/A SENSE SENSE Internal Divider Resulting VREF (V) N/A 0.5 0.5 x (1 + R2/R1) 1.0 Resulting Differential Span (V p-p) 2 x External Reference 1.0 2 x VREF (See Figure 40) 2.0
DIGITAL OUTPUTS
The AD9235 output drivers can be configured to interface with 2.5 V or 3.3 V logic families by matching DRVDD to the digital supply of the interfaced logic. The output drivers are sized to provide sufficient output current to drive a wide variety of logic families. However, large drive currents tend to cause current glitches on the supplies that may affect converter performance. Applications requiring the ADC to drive large capacitive loads or large fan-outs may require external buffers or latches. As detailed in Table 8, the data format can be selected for either offset binary or twos complement.
SENSE pin. This puts the reference amplifier in a noninverting mode with the VREF output defined as VREF = 0.5 x (1 + R2/R1)
VIN+ VIN- REFT 0.1F ADC CORE 0.1F REFB 0.1F VREF 10F + 0.1F SELECT LOGIC SENSE 0.5V + 10F
Timing
The AD9235 provides latched data outputs with a pipeline delay of seven clock cycles. Data outputs are available one propagation delay (tPD) after the rising edge of the clock signal. Refer to Figure 2 for a detailed timing diagram. The length of the output data lines and loads placed on them should be minimized to reduce transients within the AD9235; these transients can detract from the converter's dynamic performance. The lowest typical conversion rate of the AD9235 is 1 MSPS. At clock rates below 1 MSPS, dynamic performance may degrade.
AD9235
Figure 39. Internal Reference Configuration
In all reference configurations, REFT and REFB drive the A/D conversion core and establish its input span. The input range of the ADC always equals twice the voltage at the reference pin for either an internal or an external reference.
VIN+ VIN- REFT 0.1F ADC CORE 0.1F REFB + 10F
VOLTAGE REFERENCE
A stable and accurate 0.5 V voltage reference is built into the AD9235. The input range can be adjusted by varying the reference voltage applied to the AD9235, using either the internal reference or an externally applied reference voltage. The input span of the ADC tracks reference voltage changes linearly. If the ADC is being driven differentially through a transformer, the reference voltage can be used to bias the center tap (common-mode voltage).
0.1F VREF 10F + 0.1F R2 SELECT LOGIC 0.5V
Internal Reference Connection
A comparator within the AD9235 detects the potential at the SENSE pin and configures the reference into one of four possible states, which are summarized in Table 7. If SENSE is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 39), setting VREF to 1 V. Connecting the SENSE pin to VREF switches the reference amplifier output to the SENSE pin, completing the loop and providing a 0.5 V reference output. If a resistor divider is connected as shown in Figure 40, the switch is again set to the
Rev. C | Page 18 of 40
SENSE R1
AD9235
Figure 40. Programmable Reference Configuration
02461-040
02461-039
AD9235
External Reference Operation
The use of an external reference may be necessary to enhance the gain accuracy of the ADC or to improve thermal drift characteristics. When multiple ADCs track one another, a single reference (internal or external) may be necessary to reduce gain matching errors to an acceptable level. A high precision external reference may also be selected to provide lower gain and offset temperature drift. Figure 41 shows the typical drift characteristics of the internal reference in both 1 V and 0.5 V modes.
1.2
OPERATIONAL MODE SELECTION
As discussed earlier, the AD9235 can output data in either offset binary or twos complement format. There is also a provision for enabling or disabling the clock DCS. The MODE pin is a multilevel input that controls the data format and DCS state. The input threshold values and corresponding mode selections are outlined in Table 8. Table 8. Mode Selection
MODE Voltage AVDD 2/3 AVDD 1/3 AVDD AGND (Default) Data Format Twos Complement Twos Complement Offset Binary Offset Binary Duty Cycle Stabilizer Disabled Enabled Enabled Disabled
1.0
VREF = 1.0V
VREF ERROR (%)
0.8
VREF = 0.5V
0.6
The MODE pin is internally pulled down to AGND by a 20 k resistor.
TSSOP EVALUATION BOARD
0.4 0.2
0
10 20 30 40 50 TEMPERATURE (C)
60
70
80
Figure 41. Typical VREF Drift
When the SENSE pin is tied to AVDD, the internal reference is disabled, allowing the use of an external reference. An internal reference buffer loads the external reference with an equivalent 7 k load. The internal buffer still generates the positive and negative full-scale references, REFT and REFB, for the ADC core. The input span is always twice the value of the reference voltage; therefore, the external reference must be limited to a maximum of 1 V. If the internal reference of the AD9235 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 42 depicts how the internal reference voltage is affected by loading.
0.05
02461-041
0 -40 -30 -20 -10
The AD9235 evaluation board provides the support circuitry required to operate the ADC in its various modes and configurations. The converter can be driven differentially, through an AD8138 driver or a transformer, or single-ended. Separate power pins are provided to isolate the DUT from the support circuitry. Each input configuration can be selected by proper connection of various jumpers (refer to the schematics). Figure 43 shows the typical bench characterization setup used to evaluate the ac performance of the AD9235. It is critical that signal sources with very low phase noise (<1 ps rms jitter) be used to realize the ultimate performance of the converter. Proper filtering of the input signal, to remove harmonics and lower the integrated noise at the input, is also necessary to achieve the specified noise performance. The AUXCLK input should be selected in applications requiring the lowest jitter and SNR performance, i.e., IF undersampling characterization. It allows the user to apply a clock input signal that is 4x the target sample rate of the AD9235. A low-jitter, differential divide-by-4 counter, the MC100LVEL33D, provides a 1x clock output that is subsequently returned back to the CLK input via JP9. For example, a 260 MHz signal (sinusoid) is divided down to a 65 MHz signal for clocking the ADC. Note that R1 must be removed with the AUXCLK interface. Lower jitter is often achieved with this interface since many RF signal generators display improved phase noise at higher output frequencies and the slew rate of the sinusoidal output signal is 4x that of a 1x signal of equal amplitude. Complete schematics and layout plots follow and demonstrate the proper routing and grounding techniques that should be applied at the system level.
0
-0.05
0.5V ERROR (%)
ERROR (%)
-0.10 1V ERROR (%) -0.15
-0.20
0
0.5
1.0
1.5 LOAD (mA)
2.0
2.5
3.0
Figure 42. VREF Accuracy vs. Load
Rev. C | Page 19 of 40
02461-042
-0.25
AD9235
LFCSP EVALUATION BOARD
The typical bench setup used to evaluate the ac performance of the AD9235 is similar to the TSSOP Evaluation Board connections (refer to the schematics for connection details). The AD9235 can be driven single-ended or differentially through a transformer. Separate power pins are provided to isolate the DUT from the support circuitry. Each input configuration can be selected by proper connection of various jumpers (refer to the schematics). An alternative differential analog input path using an AD8351 op amp is included in the layout but is not populated in production. Designers interested in evaluating the op amp with the ADC should remove C15, R12, and R3 and populate the op amp circuit. The passive network between the AD8351 outputs and the AD9235 allows the user to optimize the frequency response of the op amp for the application.
3V - + -
3V + -
3V + -
3V +
REFIN
HP8644, 2V p-p SIGNAL SYNTHESIZER
BAND-PASS FILTER
AVDD GND DUT GND DUT S4 AVDD DRVDD XFMR INPUT
DVDD DATA CAPTURE AND PROCESSING
AD9235
J1
Figure 43. TSSOP Evaluation Board Connections
Rev. C | Page 20 of 40
02461-043
10MHz REFOUT
HP8644, 2V p-p CLOCK SYNTHESIZER
CLOCK DIVIDER
TSSOP EVALUATION BOARD S1 CLOCK
AD9235
RP3 22 D0O D1O D2O D3O
1 2 3 4
8 7 6 5
RP5 22 D0 D1 D2 D3 D8O D9O D10O D11O
1 2 3 4
8 7 6 5
D8 D9 D10 D11
RP3 22 RP3 22 RP3 22
RP5 22 RP5 22 RP5 22
RP4 22 D4O D5O D6O D7O
1 2 3 4
8 7 6 5
RP6 22 D4 D5 D6 D7 OTRO
1 2 3 4
8 7 6 5
RP4 22 RP4 22 RP4 22
RP6 22 RP6 22 RP6 22 OTR R3 10k C57 0.1F WHT TP5 JP23 JP22 DUTAVDD JP25 JP24 R4 10k C21 + 10F 10V C22 + 10F 10V C36 0.1F C39 0.001F
DUTAVDDIN TB1 2 C58 + 22F 25V
2
FBEAD L1
TP2 RED
1
JP12 DUTAVDD
AGND TB1 3
C59 0.1F
AD9235
C35 0.1F WHT TP17
7 AVDD 8 AGND 3 SENSE
OTR 1 D11 28 D10 27 D9 26 D8 25 D7 22 D6 21 D5 20 U1 D4 19 D3 18 D2 17 D1 16 D0 15 CLK 13
OTRO D0O D1O D2O D3O D4O D5O D6O D7O D8O D9O D10O D11O DUTCLK WHT TP6
AVDDIN TB1 1 C47 + 22F 25V
2
FBEAD L2
TP1 RED
1
C34 0.1F AVDD C20 10F + 10V C33 0.1F C32 0.1F JP13 AVDD R27 5k JP11 DUTDRVDD R17 1k R42 1k
AVDD
4 VREF 14 PDWN 5 REFB 6 REFT
C52 0.1F
SHEET 3 C50 0.1F
2 MODE
VIN+ VIN-
9 VIN+ 10 VIN- 11 AGND 12 AVDD
DRVDDIN TB1 5 C48 + 22F 25V
2
FBEAD L3
TP3 RED
1
R20 1k
JP7
23 DGND 24 DRVDD
JP6 DUTAVDD JP1 C23 + 10F 10V C38 0.1F C41 0.001F C1 + 10F 10V C37 0.1F
AGND TB1 4
C53 0.1F
DUTDRVDD C40 0.001F
JP2
DVDDIN TB1 6 C6 + 22F 25V
2
FBEAD L4
TP4 RED
1
TP9 BLK DVDD
TP10 BLK
TP15 BLK
TP16 BLK
Figure 44. TSSOP Evaluation Board Schematic, DUT
Rev. C | Page 21 of 40
02461-044
C14 0.1F
TP11 BLK
TP12 BLK
TP13 BLK
TP14 BLK
AD9235
DVDD C12 0.1F R25 10k AVDD
6
AUXCLK S5
1 2
C4 10F 10V
2 1 19 2 3 4 5 6 7
+
1
1
2 4 6 8 HEADER RIGHT ANGLE MALE NO EJECTORS 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 HDR40RAM J1
T1-1T 1
2 3
R11 49.9
5 4
1N5712
D2 D1
1N5712 D0 D1 D2 D3 D4 D5 D6 D7
G1 G2 A1 A2 A3 A5 A6 A7 A8 C11 0.1F C5 10F 10V +
2 1
VCC GND Y1 Y2
20 10 18 17 16
3 5
T2 MC100LVEL33D 1 U3 NC INA 3 INB 4 INCOM AVDD C24 0.1F
2
AVDD
8 7 6 5
VCC OUT REF VEE
R26 10k
Y3 U6 15 A4 74VHC541 Y4 Y5 Y6 Y7 Y8
14 13 12 11
RP2 22 16 DD0 2 RP2 22 15 DD1 3 RP2 22 14 DD2
1
7 9 11 13 15 17 19 21 23 25 27 29 31 33
RP2 22 13 DD3 5 RP2 22 12 DD4 6 RP2 22 11 DD5
4
8
9
AVDD
AVDD
+
R12 113 R14 90
C27 0.1F
R13 113 R15 90
C28 10F 10V
RP2 22 10 DD6 8 RP2 22 9 DD7 1 RP2 22 16 DD8
7
U8 DECOUPLING C26 0.1F
1
RP2 22 15 DD9 3 RP2 22 14 DD10 4 RP2 22 13 DD11
2
G1 G2 A1 A2 A3 A5 A6 A7 A8
VCC GND Y1 Y2
20 10 18 17 16
RP2 22 12 6 RP2 22 11 7 RP2 22 10
5 8
DOTR
DACLK 35
37 39
JP9 D8 R19 500 CLOCK S1
1 2
19 2 3 4 5 6 7
RP2 22 9
R2 10
R18 500 WHT TP7
1
D9 AVDD U8
2
CW C13 0.1F R1 49.9
74VHC04
D10 AVDD; 14 AVDD; 7 D11 R7 U8 22 DUTCLK OTR 5 6 74VHC04 JP4 U8
3 4
Y3 U7 15 A4 74VHC541 Y4 Y5 Y6 Y7 Y8
14 13 12 11
8
9
JP3
R9 22
74VHC04 U8
13 12
AVDD C10 0.1F U9 DECOUPLING
74VHC04 U8
11 10
C8 10F 10V
9
8
74VHC04
Figure 45. TSSOP Evaluation Board Schematic, Clock Inputs and Output Buffering
Rev. C | Page 22 of 40
02461-045
U8
AD9235
C7 0.1F AVDD
JP5 SINGLE INPUT S3
1 2
R23 1k
R5 49.9 C15 10F 10V
1 2
C9 0.33F
R41 1k
JP42 JP40 JP45 R21 22
AVDD
AVDD
C44 15pF VIN+
C69 0.1F C2 VAL R37 499 R34 523 AMP INPUT S2
1 2
R32 1k JP46 R33 1k C8 0.1F R6 40 C42 VAL JP41 JP43 R22 22
C44B
VIN- C43 15pF
-IN
1
3
VCC
4
VO+
2
R35 499 R31 49.9 +IN
AD8138
U2
8 6 5
VOC
VO-
R10 40
VEE C45 VAL
C18 0.1F C19 10F 10V
2 2 A B
R36 499 XFMR INPUT ALT VEE TP8 RED
3
AVDD
1 2
+
1
C17 VAL
S4
6
T1-1T 1
2 3
R16 1k
R24 49.9
5 4
T2
02461-046
1
JP8
R8 1k
C25 0.33F
C16 0.1F
Figure 46. TSSOP Evaluation Board Schematic, Analog Inputs
DACLK
AD9762
U4 DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9 DD10 DD11
1 MSB-DB11 2 DB10 3 DB19 4 DB8 5 DB7 6 DB6 7 DB5 8 DB4 9 DB3 10 DB2 11 DB1 12 DB0 13 NC1 14 NC2
CLOCK 28 DVDD 27 DCOM 26 NC3 25 AVDD 24 COMP2 23 IOUTA 22 IOUTB 21 ACOM 20 COMP1 19 FSADJ 18 REFIO 17 REFLO 16 SLEEP 15 C49 0.1F R30 2k C56 0.1F C30 0.1F C31 0.01F
DVDD
C29 0.1F
C46 0.01F WHT TP18 R29 49.9 C55 22pF R28 49.9
02461-047
S6
C51 0.1F
C54 22pF
Figure 47. TSSOP Evaluation Board Schematic, Optional DAC
Rev. C | Page 23 of 40
AD9235
Figure 48. TSSOP Evaluation Board Layout, Primary Side
Rev. C | Page 24 of 40
02461-048
AD9235
Figure 49. TSSOP Evaluation Board Layout, Secondary Side
Rev. C | Page 25 of 40
02461-049
AD9235
Figure 50. TSSOP Evaluation Board Layout, Ground Plane
Rev. C | Page 26 of 40
02461-050
AD9235
_
Figure 51. TSSOP Evaluation Board Power Plane
Rev. C | Page 27 of 40
02461-051
AD9235
Figure 52. TSSOP Evaluation Board Layout, Primary Silkscreen
Rev. C | Page 28 of 40
02461-052
AD9235
Figure 53. TSSOP Evaluation Board Layout, Secondary Silkscreen
Rev. C | Page 29 of 40
02461-053
AD9235
EXTREF 1V MAX E1 R1 10k R9 10k C12 0.1F P7 A GND AVDD P9 B E P10 GND GND C29 10F P8 C P11 D C13 0.10F GND C22 10F
GND AVDD P6 R5 1k C11 0.1F P1 R7 1k P3 R6 1k GND P4 1
1 2 3 4 5 6
H1 GND MTHOLE6 P2 H2 MTHOLE6 H3 MTHOLE6 H4 MTHOLE6
MODE
2.5V DRVDD
P5
+
C8 0.1F GND
3.0V
2.5V
C7 0.1F GND
3
OVERRANGE BIT 4
(MSB)
5.0V
1 2 3 4 5 6 7 8
GND
VAMP
AVDD
GND
GND
VDL
C9 0.10F
22
24 23 22 21 20 19 18 17
C6 0.1F
R42 0 AVDD AMPIN R36 1k R26 1k GND AVDD GND VIN+ R12 0 C26 10pF R2 XX C19 15pF R4 33k C21 10pF GND VIN- GND AVDD
25 26 27 28 29 30 31 32
REFB
DRVDD 16 DGND 15 D7 14 DRVDD GND
REFT AVDD
AGND VIN+ VIN- AGND AVDD
16 15 14 13 12 11 10 9
DRX D13X D12X D11X D10X D9X D8X D7X
VREF
SENSE
D11
D9
MODE
OTR
D10
D8
XOUT C15 0.1F L1 10nH AMP GND T1 ADT 1-1 WT XFRIN1 1 NC
5 3 6 2 4
AD9235
U4
D6 13 D5 12 D4 11 D3 10 D2 9
1 2 3 4 5 (LSB) 6 7 8
RP2 220
J1
R10 36
DNC
DNC
DNC
DNC
CLK
CT E 45 C16 0.1F GND R11 36 XOUTB
PRI SEC GND OPTIONAL XFR T2 FT C1-1-13
C5 GND 0.1F
OR L1 FOR FILTER
1
2
3
4
5
6
7
8
16 15 14 13 12 11 10 9
D6X D5X D4X D3X D2X D1X D0X
PDWN
D0
D1
RP1 220 GND R3 0 GND C23 10pF CLK R8 1k P14 AVDD P13 GND SENSE PIN SOLDERABLE JUMPER E TO A EXTERNAL VOLTAGE DIVIDER E TO B INTERNAL 1V REFERENCE (DEFAULT) E TO C EXTERNAL REFERENCE E TO D INTERNAL 0.5V REFERENCE MODE PIN SOLDERABLE JUMPER 5 TO 1 TWOS COMPLEMENT/DCS OFF 5 TO 2 TWOS COMPLEMENT/DCS OFF 5 TO 3 OFFSET BINARY/DCS ON 5 TO 4 OFFSET BINARY/DCS OFF
X FRIN
1
5 2
3
4
XOUT CT XOUTB
AMPINB C18 0.1F
R15 33 AVDD R13 1k R25 1k
PRI SEC GND
GND
R18 R SINGLE ENDED 25 R3, R17, R18 ONLY ONE SHOULD BE ON BOARD AT A TIME GND
Figure 54. LFCSP Evaluation Board Schematic, Analog Inputs and DUT
Rev. C | Page 30 of 40
02461-054
AD9235
74LVTH162374 U1 2OE 24 2QB 23 2Q7
22
CLKAT/DAC MSB DRX D13X GND D12X D11X DRVDD D10X D9X GND D8X D7X D6X D5X GND D4X D3X DRVDD D2X D1X GND LSB D0X
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
2CLK 2DB 2D7 GND 2D6 2D5 VCC 2D4 2D3 GND 2D2 2D1 1D8 1D7 GND 1D6 1D5 VCC 1D4 1D3 GND 1D2 1D1
GND
DRY
2
HEADER 40 GND 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 11 33 55 77 99 11 11 13 13 15 15 17 17 19 19 21 21 23 23 25 25 27 27 29 29 31 31 33 33 35 35 37 37 39 39 GND DR
4 6
GND 21 2Q6 20 2Q5 19 VCC 18 2Q4 17 2Q3 16 GND 15 2Q2 14 2Q1 13 1Q8
12
GND MSB DRVDD GND
8 10 12 14 16
GND
18 20 22 24 26
1Q7 11 GND 10 1Q6 9 1Q5 8 7 V
CC
GND
28 30
DRVDD DRY GND GND GND
32 34 36 38 40
1Q4 6 1Q3 5 GND 4 1Q2 3 1Q1 2 1 1OE 1
CLKLAT/DAC
48
1CLK
IN
OUT R38 1k C44 0.1F POWER DOWN USE R40 OR R41 VAMP R41 10k R41 10k GND GND R40 10k PWDN
1 2 3 4 5
VAMP
R39 1k GND C24 10F + C45 GND 0.1F R14 25
VAMP
AD8351
U3
10 9 8 7 6
VOCM VPOS OPH1 OPLO COMM GND
GND
AMP IN AMP
C28 0.1F
RGP1 INHI INLO
R16 0
C27 0.1F AMPINB
R19 50 GND
R35 25 GND
C35 0.10F R33 25
RPG2
R17 0
AMPIN C17 0.1F
02461-055
R34 1.2k
Figure 55. LFCSP Evaluation Board Schematic, Digital Path
Rev. C | Page 31 of 40
AD9235
VDL DRVDD AVDD AVDD DRVDD C25 10F C30 0.001F LATCH BYPASSING GND C31 C34 C36 0.1F 0.1F 0.1F C38 0.001F C39 0.001F C1 C47 0.1F 0.1F C48 0.001F C49 0.001F ANALOG BYPASSING GND DIGITAL BYPASSING C33 C32 0.001F 0.1F C14 C41 0.001F 0.1F C37 0.1F + C2 22F + C20 10F VDL C40 0.001F
+ + + C10 C4 C3 22F 10F 10F
GND
GND VAMP + C46 10F GND
DUT BYPASSING
CLOCK TIMING ADJUSTMENTS
FOR A BUFFERED ENCODE USE R28 FOR A DIRECT ENCODE USE R27 R28 0 ENC 74VCX86 ENCX
3 6 1 1A 2 1B 4 2A
CLK
ENCX E50 R27 0 R32 1k 2Y
8
E51 1Y GND GND
11 7
ENC R23 0
SCHEMATIC SHOWS TWO GATE DELAY SETUP FOR ONE DELAY REMOVE R22 AND R37 AND ATTACH Rx (Rx = 0)
5 2B
VDL 3Y PWR 4Y
14 10 3B
GND E52 E53
13 4B 12 4A
9 3A
CLKAT/DAC
R37 25
Rx DNP DR
Figure 56. LFCSP Evaluation Board Schematic, Clock Input
VDL
Rev. C | Page 32 of 40
VDL R20 1k C43 0.1F VDL E31 R21 1k GND VDL E43 R24 1k VDL GND E44 GND E35 GND R31 1k R30 1k
R22 0
ENCODE
J2
GND
R29 50
GND
02461-056
AD9235
02461-057
Figure 57. LFCSP Evaluation Board Layout, Primary Side
Figure 59. LFCSP Evaluation Board Layout, Ground Plane
Figure 58. LFCSP Evaluation Board Layout, Secondary Side
02461-058
Figure 60. LFCSP Evaluation Board Layout, Power Plane
Rev. C | Page 33 of 40
02461-060
02461-059
AD9235
02461-061
Figure 61. LFCSP Evaluation Board Layout, Primary Silkscreen
Figure 62. LFCSP Evaluation Board Layout, Secondary Silkscreen
Rev. C | Page 34 of 40
02461-062
AD9235
Table 9. LFCSP Evaluation Board Bill of Materials (BOM)
Item Qty. Omit1 Reference Designator 1 18 C1, C5, C7, C8, C9, C11, C12, C13, C15, C16, C31, C33, C34, C36, C37, C41, C43, C47 8 C6, C18, C27, C17, C28, C35, C45, C44 2 8 C2, C3, C4, C10, C20, C22, C25, C29 2 C46, C24 3 8 C14, C30, C32, C38, C39, C40, C48, C49 4 3 C19, C21, C23 5 1 C26 6 9 E31, E35, E43, E44, E50, E51, E52, E53 2 E1, E45 7 2 J1, J2 8 1 L1 9 10 11 12 13 1 1 5 6 2 14 P2 P12 R3, R12, R23, R28, RX R37, R22, R42, R16, R17, R27 R4, R15 R5, R6, R7, R8, R13, R20, R21, R24, R25, R26, R30, R31, R32, R36 R10, R11 R29 R19 RP1, RP2 T1 U1 U4 U5 PCB U3 T2 R9, R1, R2, R38, R39 R18, R14, R35 R40, R41 R34 R33 Device Chip Capacitor Package 0603 Value 0.1 F Recommended Vendor/ Supplied Part Number by ADI
Tantalum Capacitor
TAJD
10 F
Chip Capacitor Chip Capacitor Chip Capacitor Header
0603 0603 0603 EHOLE
0.001 F 10 pF 10 pF Jumper Blocks
SMA Connector/50 Inductor Terminal Block
SMA 0603 TB6
10 nH
Header Dual 20-Pin RT Angle HEADER40 Chip Resistor 0603 0 Chip Resistor Chip Resistor 0603 0603 33 1k
Coilcraft/ 0603CS-10NXGBU Wieland/25.602.2653.0, z5-530-0625-0 Digi-Key S2131-20-ND
14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Total
2 1 1 2 1 1 1 1 1 1 1 5 3 2 1 1 34
Chip Resistor Chip Resistor Resistor Pack ADT1-1WT 74LVTH162374 CMOS Register AD9235BCP ADC (DUT) 74VCX86M AD92XXBCP/PCB AD8351 Op Amp MACOM Transformer Chip Resistor Chip Resistor Chip Resistor Chip Resistor Chip Resistor
0603 0603 R_742 AWT1-1T TSSOP-48 LFCSP-32 SOIC-14 PCB MSOP-8 ETC1-1-13 0603 0603 0603
36 50 220 Digi-Key CTS/742C163220JTR Mini-Circuits
1-1 TX SELECT 25 10 k 1.2 k 100
Analog Devices, Inc. Fairchild Analog Devices, Inc. Analog Devices, Inc. M/A-COM/ETC1-1-13
X X X
82
1
These items are included in the PCB design but are omitted at assembly.
Rev. C | Page 35 of 40
AD9235 OUTLINE DIMENSIONS
9.80 9.70 9.60
28
15
4.50 4.40 4.30 6.40 BSC
1 14
PIN 1 0.65 BSC 0.15 0.05 COPLANARITY 0.10 0.30 0.19 1.20 MAX 8 0 0.75 0.60 0.45
SEATING PLANE
0.20 0.09
COMPLIANT TO JEDEC STANDARDS MO-153AE
Figure 63. 28-Lead Thin Shrink Small Outline Package [TSSOP] (RU-28) Dimensions shown in millimeters
5.00 BSC SQ
0.60 MAX 0.60 MAX
25 24 32 1
PIN 1 INDICATOR
PIN 1 INDICATOR TOP VIEW 4.75 BSC SQ
0.50 BSC
EXPOSED PAD (BOTTOM VIEW)
17 16 8
3.25 3.10 SQ 2.95
0.50 0.40 0.30 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM SEATING PLANE 0.30 0.23 0.18 0.20 REF
9
0.25 MIN 3.50 REF
12 MAX
1.00 0.85 0.80
COPLANARITY 0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 64. 32-Lead Lead Frame Chip Scale Package [LFCSP] 5 mm x 5 mm Body (CP-32-2) Dimensions shown in millimeters
Rev. C | Page 36 of 40
AD9235
ORDERING GUIDE
Model AD9235BRU-20 AD9235BRURL7-20 AD9235BRUZ-201 AD9235BRUZRL7-201 AD9235BRU-40 AD9235BRURL7-40 AD9235BRUZ-401 AD9235BRUZRL7-401 AD9235BRU-65 AD9235BRURL7-65 AD9235BRUZ-651 AD9235BRUZRL7-651 AD9235BCP-202 AD9235BCPRL7-202 AD9235BCPZ-201, 2 AD9235BCPZRL7-201, 2 AD9235BCP-402 AD9235BCPRL7-402 AD9235BCPZ-401, 2 AD9235BCPZRL7-401, 2 AD9235BCP-652 AD9235BCPRL7-652 AD9235BCPZ-651, 2 AD9235BCPZRL7-651, 2 AD9235-20PCB AD9235-40PCB AD9235-65PCB AD9235BCP-20EB AD9235BCP-40EB AD9235BCP-65EB Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C Package Description 28-Lead Thin Shrink Small Outline Package (TSSOP) 28-Lead Thin Shrink Small Outline Package (TSSOP) 28-Lead Thin Shrink Small Outline Package (TSSOP) 28-Lead Thin Shrink Small Outline Package (TSSOP) 28-Lead Thin Shrink Small Outline Package (TSSOP) 28-Lead Thin Shrink Small Outline Package (TSSOP) 28-Lead Thin Shrink Small Outline Package (TSSOP) 28-Lead Thin Shrink Small Outline Package (TSSOP) 28-Lead Thin Shrink Small Outline Package (TSSOP) 28-Lead Thin Shrink Small Outline Package (TSSOP) 28-Lead Thin Shrink Small Outline Package (TSSOP) 28-Lead Thin Shrink Small Outline Package (TSSOP) 32-Lead Lead Frame Chip Scale Package (LFCSP) 32-Lead Lead Frame Chip Scale Package (LFCSP) 32-Lead Lead Frame Chip Scale Package (LFCSP) 32-Lead Lead Frame Chip Scale Package (LFCSP) 32-Lead Lead Frame Chip Scale Package (LFCSP) 32-Lead Lead Frame Chip Scale Package (LFCSP) 32-Lead Lead Frame Chip Scale Package (LFCSP) 32-Lead Lead Frame Chip Scale Package (LFCSP) 32-Lead Lead Frame Chip Scale Package (LFCSP) 32-Lead Lead Frame Chip Scale Package (LFCSP) 32-Lead Lead Frame Chip Scale Package (LFCSP) 32-Lead Lead Frame Chip Scale Package (LFCSP) TSSOP Evaluation Board TSSOP Evaluation Board TSSOP Evaluation Board LFCSP Evaluation Board LFCSP Evaluation Board LFCSP Evaluation Board Package Option RU-28 RU-28 RU-28 RU-28 RU-28 RU-28 RU-28 RU-28 RU-28 RU-28 RU-28 RU-28 CP-32-2 CP-32-2 CP-32-2 CP-32-2 CP-32-2 CP-32-2 CP-32-2 CP-32-2 CP-32-2 CP-32-2 CP-32-2 CP-32-2
1 2
Z = Pb-free part. It is recommended that the exposed paddle be soldered to the ground plane. There is an increased reliability of the solder joints and maximum thermal capability of the package is achieved with exposed paddle soldered to the customer board.
Rev. C | Page 37 of 40
AD9235 NOTES
Rev. C | Page 38 of 40
AD9235 NOTES
Rev. C | Page 39 of 40
AD9235 NOTES
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C02461-0-10/04(C)
Rev. C | Page 40 of 40

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