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NT3966
TFT LCD Source Driver
Features n Output : 420 output channels n 6-bit resolution /64 gray scale n Dot inversion with polarity control n V1 ~ V10 for adjusting Gamma correction n Power for analog circuit : 6.5 ~ 10 V n Output dynamic range : 0.1 ~ AVDD-0.1V n Power consumption of analog circuit : 3mA General Description The NT3966 is a data driver IC for a color TFT LCD panel, SXGA+(1400*1050) applications. For better performance, dot inversion and a wide range voltage output have been designed into this chip, and for reducing EMI, data inversion control has been incorporated. This chip supplies 10 sections of voltage-reference for Gamma correction. n Power for interface circuit : 2.5~3.6V n Operating frequency : 65MHz n Output deviation : 10 ~ 20mV n Data inversion for reducing EMI n Cascade function with bi-direction shift control n CMOS silicon gate ( p-type substrate ) n TCP package
Block diagram
OUT1 OUT2
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OUT3
OUT420 OUT419
Out Driver Buffer ( 420 channels )
V1 ~ V10
10
Digit to Analog Converter
6 6 6 6 6
POL
REV1
D00 ~ D05 D10 ~ D15 D20 ~ D25 D30 ~ D35 D40 ~ D45 D50 ~ D55
Level Shift
6 6 6 6 6 6 Decoder
1 64
6 Decoder 18
6
6
6
6
Line Latch ( 420 X 6 bits X 2 )
18
LD
REV2 DIO1
70-bit Shift Register
DIO2
Vcc
GND
AVDD
AVSS
CLK
SHL
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NT3966 TFT LCD Source Driver
NT3966 Pads configuration (Face up): This figure does not specify the TCP package.
DIO2 D55 D54 D53 D52 D51 D50 D45 D44 D43 D42 D41 D40 D35 D34 D33 D32 D31 D30 Vcc SHL V10 V9 V8 V7 V6 AVDD AVSS V5 V4 V3 V2 V1 GND CLK LD POL REV1 REV2 D25 D24 D23 D22 D21 D20 D15 D14 D13 D12 D11 D10 D05 D04 D03 D02 D01 D00 DIO1
OUT420 OUT419 OUT418 OUT417 OUT416
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NT3966
OUT5 OUT4 OUT3 OUT2 OUT1
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Pin Description Designation D05 ~ D00 D15 ~ D10 D25 ~ D20 D35 ~ D30 D45 ~ D40 D55 ~ D50 REV1 REV2 CLK V1 ~ V10 OUT1 ~ OUT420 SHL I/O I Description Data input. For six 6-bit data,2 pixels, of color data (R, G, B) DX5 : MSB; DX0 : LSB
I I I I O I
Controls whether the data of D00~D25 are inverted or not. When "REV1"=1 these data will be inverted. EX. "00" a " 3F", "07"a " 38", "15"a "2A", and so on. Controls whether the data of D30~D55 are inverted or not, same as REV1. Clock input; latching data onto the line latches at the rising edge. Gamma correction reference voltage. The voltage of these pins must be AVSS< V10< V9< V8DIO1 DIO2
LD
POL
AVDD AVSS Vcc GND
Selects left or right shift; SHL="1" : DIO1 /OUT1,2,3,4,5,6/OUT7,8,9,10,11,12--/OUT415,416,417,418,419,420= DIO2 SHL="0" : DIO1=OUT1,2,3,4,5,6oOUT7,8,9,10,11,12o-- OUT415,416,417,418,419,420oDIO2 SHL DIO1 DIO2 SHIFT 1 Input Output Right 0 Output Input Left I/O Start pulse signal input/output When SHL is applied high (SHL="1"), a start high-pulse on DIO1 is latched at the rising edge of the CLK. Then the data are latched serially onto internal latches at the rising edge of the CLK. After all line latches are filled with data, 70 clocks, a pulse is shifted out through the DIO2 pin at the rising edge of the CLK. This function can cascade two or more devices for dot-size expansion. In normal applications, the DIO2 signal of the first device is connected to the DIO1 of the second stage, the www..com DIO2 of the second one is connected to the DIO1 of the third, and so on, in a chain. In contrast, when SHL is applied low, a start pulse inputs on DIO2, and a pulse outputs through DIO1. *Remark: The input pulse-width of DIO1/2 may exceed 1 clock-cycle. I Latches the polarity of outputs and switches the new data to outputs. 1. At the rising edge, the pin latches the "POL" signal to control the polarity of the outputs. 2. The pin also controls the switch of the line registers that switches the new incoming data to outputs. *Remark: The LD may switch the new data to outputs at anytime even if the line data are not completely full. I Polarity selector for the dot-inversion control. Available at the rising edge of LD "POL" value is latched at the rising edge of "LD" to control the polarity of the even or odd outputs. "POL=1" indicates that even outputs are of positive polarity with a voltage range from V1~V5, and odd outputs are of negative polarity with a voltage range from V6 to V10. On the other hand, if LD receives low level "POL", even outputs are of negative polarity and odd outputs are of positive polarity. POL=1: Even outputs range from V1 ~ V5 Odd outputs range from V6 ~ V10 POL=0: Even outputs range from V6 ~ V10 Odd outputs range from V1 ~ V5 I Power supply for analog circuit I Ground pin for analog circuit I Power supply for digital circuit I Ground pin for digital circuit
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Power on/off sequence:
This IC is a high-voltage LCD driver, so it may be damaged by a large current flow when an incorrect power sequence is used. The recommended sequence should be: digital power (Vcc&GND)e logic signals eanalog power (AVDD&AVSS) eGamma correction reference voltage(V1~V10). Reverse this sequence to shut down, or turn off all signals and power simultaneously. Relationship between the order of input data and output channels (1) SHL="1", Start pulse from DIO1, shift right Output OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 Order First data Data D05~D00 D15~D10 D25~D20 D35~D30 D45~D40 D55~D50 (2) SHL="0", Start pulse from DIO2, shift left Output OUT415 OUT416 OUT417 OUT418 OUT419 OUT420 Order First data Data D05~D00 D15~D10 D25~D20 D35~D30 D45~D40 D55~D50
- ---a - -- ---a - --
OUT420 Last data D55~D50 OUT6 Last data D55~D50
Relationship between input data and output voltage The figure below shows the relationship among the input data and the output voltage and the polarity. The range of V1~V5 is for positive polarity, and V6 ~ V10 for negative polarity. Please refer to the following page to get the relative resistor value and voltage calculation method.
Gamma correction diagram Vout AVDD V1
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V2 V3 V4 V5 Vcom V6 V7 V8 Negative polarity V9 Positive polarity
V10 AVSS 00H 08H 10H 18H 20H 28H 30H 38H 3FH Input Data
Remark: AVDD-0.1 > V1 > V2 > V3 > V4 > V5; V6 > V7 > V8 > V9 > V10 >AVSS+0.1V
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Gamma correction resistor V1, V10
Name
R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31
resistor
800 750 700 650 600 550 550 500 500 400 400 350 350 350 300 300 300 250 250 www..com 250 200 200 200 150 150 150 150 100 100 100 100 100
Name
R32 R33 R34 R35 R36 R37 R38 R39 R40 R41 R42 R43 R44 R45 R46 R47 R48 R49 R50 R51 R52 R53 R54 R55 R56 R57 R58 R59 R60 R61 R62
resistor
100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 150 150 150 200 200 250 250 300 500 800
V3, V8
1.6K
8.05K
V2, V9
V4, V7
2.75K
3.45K
V5, V6
V3, V8
Total impedance, Rn=R0 ~ R62, equals 15.85K
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Output Voltage VS Input Data Data Output Voltage ( Positive polarity ) 00H V1 01H V2 + ( V1 - V2) X 7250/8050 02H V2 + ( V1 - V2) X 6500/8050 03H V2 + ( V1 - V2) X 5800/8050 04H V2 + ( V1 - V2) X 5150/8050 05H V2 + ( V1 - V2) X 4550/8050 06H V2 + ( V1 - V2) X 4000/8050 07H V2 + ( V1 - V2) X 3450/8050 08H V2 + ( V1 - V2) X 2950/8050 09H V2 + ( V1 - V2) X 2450/8050 0AH V2 + ( V1 - V2) X 2050/8050 0BH V2 + ( V1 - V2) X 1650/8050 0CH V2 + ( V1 - V2) X 1300/8050 V2 + ( V1 - V2) X 950/8050 0DH V2 + ( V1 - V2) X 600/8050 0EH V2 + ( V1 - V2) X 300/8050 0FH V2 10H V3 + (V2 - V3) X2450/2750 11H V3 + (V2 - V3) X 2200/2750 12H V3 + (V2 - V3) X 1950/2750 13H V3 + (V2 - V3) X 1700/2750 14H V3 + (V2 - V3) X 1500/2750 15H V3 + (V2 - V3) X 1300/2750 16H V3 + (V2 - V3) X 1100/2750 17H V3 + (V2 - V3) X 950/2750 18H V3 + (V2 - V3) X 800/2750 19H V3 + (V2 - V3) X 650/2750 1AH V3 + (V2 - V3) X 500/2750 1BH V3 + (V2 - V3) X 400/2750 1CH V3 + (V2 - V3) X 300/2750 1DH V3 + (V2 - V3) X 200/2750 1EH V3 + (V2 - V3) X 100/2750 1FH V3 20H V4 + (V3 - V4) X 1500/1600 21H V4 + (V3 - V4) X 1400/1600 22H V4 + (V3 - V4) X 1300/1600 23H V4 + (V3 - V4) X 1200/1600 24H V4 + (V3 - V4) X 1100/1600 25H V4 + (V3 - V4) X 1000/1600 26H V4 + (V3 - V4) X 900/1600 27H V4 + (V3 - V4) X 800/1600 28H V4 + (V3 - V4) X 700/1600 29H V4 + (V3 - V4) X 600/1600 2AH V4 + (V3 - V4) X 500/1600 2BH V4 + (V3 - V4) X 400/1600 2CH V4 + (V3 - V4) X 300/1600 2DH V4 + (V3 - V4) X 200/1600 2EH V4 + (V3 - V4) X 100/1600 2FH Version 1.0 Output Voltage ( Negative polarity ) V10
V10 + ( V9 - V10) X 800/8050 V10 + ( V9 - V10) X 1550/8050 V10 + ( V9 - V10) X 2250/8050 V10 + ( V9 - V10) X 2900/8050 V10 + ( V9 - V10) X 3500/8050 V10 + ( V9 - V10) X 4050/8050 V10 + ( V9 - V10) X 4600/8050 V10 + ( V9 - V10) X 5100/8050 V10 + ( V9 - V10) X 5600/8050 V10 + ( V9 - V10) X 6000/8050 V10 + ( V9 - V10) X 6400/8050 V10 + ( V9 - V10) X 6750/8050 V10 + ( V9 - V10) X 7100/8050 V10 + ( V9 - V10) X 7450/8050 V10 + ( V9 - V10) X 7750/8050 V9 V9 + ( V8 - V9) X 300/2750 V9 + ( V8 - V9) X 550/2750 V9 + ( V8 - V9) X 800/2750 V9 + ( V8 - V9) X 1050/2750 www..com V9 + ( V8 - V9) X 1250/2750 V9 + ( V8 - V9) X 1450/2750 V9 + ( V8 - V9) X 1650/2750 V9 + ( V8 - V9) X 1800/2750 V9 + ( V8 - V9) X 1950/2750 V9 + ( V8 - V9) X 2100/2750 V9 + ( V8 - V9) X 2250/2750 V9 + ( V8 - V9) X 2350/2750 V9 + ( V8 - V9) X 2450/2750 V9 + ( V8 - V9) X 2550/2750 V9 + ( V8 - V9) X 2650/2750 V8 V8 + ( V7 - V8) X 100/1600 V8 + ( V7 - V8) X 200/1600 V8 + ( V7 - V8) X 300/1600 V8 + ( V7 - V8) X 400/1600 V8 + ( V7 - V8) X 500/1600 V8 + ( V7 - V8) X 600/1600 V8 + ( V7 - V8) X 700/1600 V8 + ( V7 - V8) X 800/1600 V8 + ( V7 - V8) X 900/1600 V8 + ( V7 - V8) X 1000/1600 V8 + ( V7 - V8) X 1100/1600 V8 + ( V7 - V8) X 1200/1600 V8 + ( V7 - V8) X 1300/1600 V8 + ( V7 - V8) X 1400/1600 V8 + ( V7 - V8) X 1500/1600
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NT3966 TFT LCD Source Driver
Output Voltage VS Input Data (continued) Data 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH Output Voltage ( Positive polarity )
V4 V5 + (V4 - V5) X 3350/3450 V5 + (V4 - V5) X 3250/3450 V5 + (V4 - V5) X 3150/3450 V5 + (V4 - V5) X 3050/3450 V5 + (V4 - V5) X 2950/3450 V5 + (V4 - V5) X 2800/3450 V5 + (V4 - V5) X 2650/3450 V5 + (V4 - V5) X 2500/3450 V5 + (V4 - V5) X 2300/3450 V5 + (V4 - V5) X 2100/3450 V5 + (V4 - V5) X 1850/3450 V5 + (V4 - V5) X 1600/3450 V5 + (V4 - V5) X 1300/3450 V5 + (V4 - V5) X 800/3450 V5
Output Voltage ( Negative polarity )
V7 V7 + ( V6 - V7) X 100/3450 V7 + ( V6 - V7) X 200/3450 V7 + ( V6 - V7) X 300/3450 V7 + ( V6 - V7) X 400/3450 V7 + ( V6 - V7) X 500/3450 V7 + ( V6 - V7) X 650/3450 V7 + ( V6 - V7) X 800/3450 V7 + ( V6 - V7) X 950/3450 V7 + ( V6 - V7) X 1150/3450 V7 + ( V6 - V7) X 1350/3450 V7 + ( V6 - V7) X 1600/3450 V7 + ( V6 - V7) X 1850/3450 V7 + ( V6 - V7) X 2150/3450 V7 + ( V6 - V7) X 2650/3450 V6
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Absolute Maximum Ratings*
Logic supply voltage, Vcc Supply voltage, AVDD Supply voltage, V1~ V5 Supply voltage, V6 ~ V10 Storage temperature Operating temperature -0.5V to 5V -0.5V to +12V 0.4AVDD ~AVDD+0.3 -0.3 ~ 0.6AVDD -55J to 100J -10J to 75J
*Comments
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only. Functional operation of this device at these or under any other conditions above those indicated in the operational sections of this specification are not implied and exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC Electrical Characteristics (Vcc =3.3V , AV DD=10V, AVSS=GND=0V, TA=-10J~75J)
(For the digital circuit)
Parameter Supply Voltage Low Level Input Voltage High Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current Digital Operating Current Symbol Vcc Vil Vih Voh Vol Ii Icc Min. 2.5 0 0.7xVcc Vcc-0.4 GND Typ. 3 Max. Unit 3.6 V 0.3xVcc V Vcc V V GND+0.4 V +1 A 5 mA Conditions Digital power For the digital circuit For the digital circuit DIO1, DIO2, Ioh=1mA DIO1, DIO2, Iol=-1mA For the digital circuit Fclk=45 MH z, FLD=50KHz
(For the analog circuit)
Parameter Supply Voltage Input level of V1 ~ V5 Input level of V6 ~ V10 Voltage Output Deviation between Pins Dynamic Range of Output Sinking Current of outputs Driving Current of outputs Impedance of Gamma Correction Analog Operating Current Symbol Min. AVDD 6.5 Vref 0.4AVDD Vref 0.1 Vvd Typ. Max. www..com 8.4 10 AVDD-0.1 0.6AVDD +20 +25 +10 -180 200 Rn 7 +20 AVDD-0.1 1.3Rn 10 Unit V V V mV mV V A A ohm mA Conditions For the analog circuit power Gamma correction voltage Gamma correction voltage Vo=0.1V ~ 1.5V & AVDD-1.5 ~ AVDD0.1V Vo=1.5V ~ AVDD-1.5V OUT1 ~ OUT420 OUT1 ~ OUT420; Vo=0.1V V.S 1V OUT1 ~ OUT420; Vo=9.9V V.S 9V Rn=15850 ohm, from V1 ~ V5 & V6~V10 No load, Fclk=33MHz, FLD=50KHz
Vdr IOL IOH Ri IDD
0.1 -150 150 0.8Rn -
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NT3966 TFT LCD Source Driver
AC1 Electrical Characteristics (Vcc =3.0~3.6V , AVDD=6.5~10V, AVSS=GND=0V, TA= -10~75J) Parameter CLK frequency CLK period cycle CLK pulse width Data set-up time Data hold time Propagation delay of DIO2/1 Time that the last data to LD Pulse width of LD Time that LD to DIO1/2 POL set-up time POL hold time Output stable time Output loading Symbol Fclk Tcph Tcw Tsu Thd Tphl Tld Twld Tlds Tpsu Tphd Tst CL Min. 15 6 4 2 1 2 2 6 6 Typ. 4.5 Max. 65 11 8 Unit Mhz ns ns ns ns ns Tcph Tcph Tcph ns ns us pF Conditions
D00 ~ D55, REVx and DIO1/2 to CLK D00 ~ D55, REVx and DIO1/2 to CLK CL=25pF ( Output )
150
POL to LD POL to LD 96% final value or below with 30mV precision , CL=75pF, R=5K ohm For OUT1 ~ OUT420
AC2 Electrical Characteristics (Vcc =2.5~3.0V , AVDD=6.5~10V, AVSS=GND=0V, TA= -10~75J) Parameter CLK frequency CLK period cycle CLK pulse width Data set-up time Data hold time Propagation delay of DIO2/1 Time that the last data to LD Pulse width of LD Time that LD to DIO1/2 POL set-up time POL hold time Output stable time Output loading Symbol Fclk Tcph Tcw Tsu Thd Tphl Tld Twld Tlds Tpsu Tphd Tst CL Min. 22 8 6 4 1 2 2 6 6 Typ. Max. 45 www..com 15 4.5 8 Unit Mhz ns ns ns ns ns Tcph Tcph Tcph ns ns us pF Conditions
D00 ~ D55, REVx and DIO1/2 to CLK D00 ~ D55, REVx and DIO1/2 to CLK CL=25pF ( Output )
150
POL to LD POL to LD 96% final value or below with 30mV precision , CL=75pF, R=5K ohm For OUT1 ~ OUT420
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Timing Diagram
Tcph CLK Tsu DIO1/2 ( Input ) Tsu Data, REVx Thd Second data Tphl DIO1/2 ( Output ) Last data Tphl Thd Tcw Tcw 69 70
First data
CLK
Last Tld
LD
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Twld Tlds
DIO1/2 ( Input ) LD
Tpsu Tpdh
POL
96% Odd outputs
High-Z
Positive 96%
High-Z
Even outputs
Tst
High-Z
Negative Tst
Output load condition : Output
1K
1K
1K
1K
1K
15P
15P
15P
15P
15P
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Function operation
CLK DIO1/2 ( Input )
1CLK ( min.) 2CLK ( min.)
LD
1CLK
Data, REVx
N-2
N-1
N
1
2
3
Last Data
First Data
LD
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POL
Odd Outputs
Vcom
V1 ~V5 V6 ~V10
Even Outputs
V1 ~V5 V6 ~V10
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