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YSS901
SD
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Preliminary
Stereo dipole
g Outline
YSS901 is a device that uses the stereo dipole system (SD) with which the transaural system can be constructed. When a stereophonic signal that has been processed with the SD system of this device is inputted to two speakers located adjacently at the center of the field (or to two speakers contained in one cabinet), the virtual sound positioning function of this system produces the stereophonic sound similar to the one that can be obtained by using an ordinary stereophonic sound replay system through the central two speakers. YSS901 has built-in one bit Delta-Sigma type A/D and D/A converters for each of the two channels at its input and output respectively. Thanks to these built-in converters, this device can process analog stereophonic sound signal through the converters in addition to digital stereophonic sound signal. This device performs an advanced convolution through DSP using the FIR filter.
g Features
n Two channel virtual sound positioning by using the stereo dipole system. n Processes analog or digital signals at each of the two channels. n Four types of digital data format are available, including 48 fs Serial-DAC16, 18 and 20 bits, and 64 fs. n Six types of parameter coefficients are built in the device. Additional parameter coefficients can be
downloaded externally. n The parameter control is made through the DC switches or synchronous three-wire serial system. n Uses a clock of 2.822 MHz from the crystal. External clock can also be used. n Has a built-in PLL circuit for generating clock for operation. n Internal operating frequency of 512 fs. n Allows fading in or out the output of the results of the convolution when switching the coefficient. n Power supply voltage: 5 V n Si-gate CMOS process. n 64 QFP
YAMAHA CORPORATION
YSS901CATALOG CATALOG No.: LSI-4SS901A0 1999. 1
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TSTNO TSTNI TST1 XTAL ROUT LOUT DVSS PLLC AVSS TSTCK EXTAL
g Pin configuration
51 N.C DVDD TSTSEL CSEL2 CSEL1 CSEL0 RESETN BSFT1 BSFT0 SCK SI DVSS N.C 1 2 3 4 5 6 64 7 8 9 10 11 12 13 14 15 16 17 18 63 62 61 60 59 58 57 56 55 54 53 52
N.C N.C N.C N.C N.C
50
N.C
49
N.C
48
N.C
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33 32 31 30 29 28 27 N.C AVDD VREF AIL AILOUT AILRET 26 25 24 23 22 21 20 19 AIR AIROUT AIRRET AVSS DVSS TST2 N.C
<64QFP TOP VIEW>
YSS901
N.C
N.C
N.C
N.C
CSN
DIN
N.C
N.C
N.C
N.C
DVDD
BCLK
DOUT
DVDD
SYNCN
DSEL2
DSEL1
DSEL0
CTLSEL
YSS901
YSS901
g Pin Description
No. Pin name 5 6 7 8 9 10 11 12 13 www..com 14 15 21 22 23 24 25 26 27 28 29 30 31 37 38 39 40 41 42 43 44 45 46 47 53 54 55 56 57 58 59 60 61 62 63 DVDD CTLSEL SYNCN BCLK CSN DOUT DIN DSEL2 DSEL1 DSEL0 DVDD TST2 DVSS AVSS AIRRET AIROUT AIR AILRET AILOUT AIL VREF AVDD LOUT ROUT PLLC AVSS EXTAL XTAL DVSS TSTCK TST1 TSTNI TSTNO DVDD TSTSEL CSEL2 CSEL1 CSEL0 RESETN BSFT1 BSFT0 SCK SI DVSS I/O I I I I O I I I I AO AO AI AO AO AI AI AO AO AI I O I O I I I I I I I I Function Digital signal power supply : +5 V Selection of control method Digital input/output synchronization signal Digital input/output bit clock Serial control interface chip select signal Digital signal output Digital signal input Analog/digital input selection Digital input/output format selection Digital input/output format selection Digital signal power supply : +5 V Test (To be open.) Digital signal ground Analog signal ground Right channel analog signal input return Right channel analog signal input out Right channel analog signal input Left channel analog signal input return Left channel analog signal input out Left channel analog signal input Analog signal VREF Analog signal power supply : +5 V Left channel analog signal output Right channel analog signal output PLL auxiliary input Analog signal ground Crystal clock input Crystal clock output Digital signal ground Test (Connect with DVSS.) Test (To be open.) Test (Connect with DVSS.) Test (To be open.) Digital signal power supply: +5 V Test (Connect with DVSS.) Coefficient selection (Enabled when CTLSEL = 0) Coefficient selection (Enabled when CTLSEL = 0) Coefficient selection (Enabled when CTLSEL = 0) Reset signal input Bit shift selection (Enabled when CTLSEL = 0) Bit shift selection (Enabled when CTLSEL = 0) Serial control interface clock input Serial control interface data input Digital signal ground
Notes: 1. Pins of No. 1 to 4, 16 to 20, 32 to 36, 48 to 52 and 64 are to be open. 2. I: input pin O: output pin AI: analog signal input pin AO: analog output pin.
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SI CSN XTAL PLLC EXTAL CSEL0 CSEL1 CSEL2 BSFT0 BSFT1 RESETN CTLSEL
g Block Diagram
Timing stereo dipole COEF
Serial Control
AIL
AILOUT
Lch Lch
AILRET
LOUT
AIR
Lch
AD
COEF 1 COEF 2
DA
ROUT
AIROUT
AIRRET
Rch
Bit Shift
COEF 2
Fader
SYNCN
Rch
COEF 1
Rch
Digital Out
DOUT
BCLK
Digital In
DIN
Noise Gate
(Input Level Check)
NGO
VREF
AVSS
AVDD
DVSS
DVDD
YSS901
DSEL0
DSEL1
DSEL2
NGATE
YSS901
g Outline of Functions
1. Clock signals XTAL, EXTAL and PLLC
For the clock signal, use the crystal connected to XTAL EXTAL pin with which the clock signal is obtained by the self-oscillation at the crystal oscillation circuit, or external signal supplied through EXTAL pin. The frequency of the clock obtained by the self-oscillation is 2.822 MHz (or 44.1 kHz * 64). The internal operation is carried out with 512 fs clock that is made by the PLL. Insert an analog filter in between PLLC and GND pins.
2. Data input/output signals
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Analog/digital input selection pin: DSEL2
This pin is used to select a type of the input signal. DSEL2 = 0 selects the digital signal input, or DSEL2 = 1 selects the analog signal input.
2-1) Digital signal Digital signal input/output pins: DIN, BCLK, SYNCN and DOUT
Digital signals should be inputted through DIN, BCLK and SYNCN pins. DIN signal (PCM data) must be in synchronous with BCLK (bit clock) and SYNCN (word clock) signals. Digital signal is outputted from DOUT pin.
Input/output format designation pins: DSEL1 and DSEL0
These pins are used to designate a data format for DAC. The settings of DSEL1 and DSEL0 and their output formats are as follows. DSEL1 0 0 1 1 DSEL0 0 1 0 1
DAC output format 48 fs 16 bits Data LSB justified 48 fs 18 bits Data LSB justified (Bits 1 and 0 are "0".) 48 fs 20 bits Data LSB justified (Bits 3 through 0 are "0".) 64 fs 16 bits Data MSB justified (Delay by one bit)
For the details of the format, refer to "Serial Data Interface" explained later in this document. 2-2) Analog signal Analog input/output pins: AIL, AILOUT, AILRET, LOUT, AIR, AIROUT, AIRRET and ROUT
Analog signals should be inputted through AIL and AIR pins. The signals that have been processed by the stereo dipole (SD) are outputted from LOUT and ROUT pins respectively. Add an analog filter circuit, an example of which is shown later in this document.
Center voltage pin
VREF
This pin outputs a reference voltage for analog signal processing. Connect an appropriate capacitor between VREF and GND pins.
3. Controlling functions 3-1) Control method selection pin: CTLSEL
This pin is used for selection of a control method as described below.
CTLSEL = 0 : Selection of CSEL2, CSEL1 or CSEL0 by means of DC switch (H/L) is enabled. CTLSEL = 1 : Selection of CSN, SI or SCK through the microcomputer is enabled.
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YSS901
3-2) Speaker arrangement angle and virtual sound position angle 3-2-1) Setting by means of DC switches: CSEL2, CSEL1, CSEL0 and CTLSEL
By setting CTLSEL to "0", and setting CSEL 2, 1 and 0 as following, the positioning angle between the front two speakers and the virtual sound positioning angle can be selected.
Stereo Input
CSEL2 CSEL1 CSEL0
Speaker positioning angle (a) 10 degrees 10 degrees 15 degrees 15 degrees 20 degrees 20 degrees
Virtual sound position (b) 60 degrees 120 degrees 60 degrees 120 degrees 60 degrees 120 degrees
stereo dipole
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L L R R
0 0 0
Virtual Source
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Real Source
0 1 1 1 1
a
b
External coefficien1t downloadable Through (SD effect is disabled.)
Listener
* Your original coefficients can be written by an external microprocessor. (Technical material is under preparation)
3-2-2) Control through CPU
CSN, SCK, SI and CTLSEL
Data can be written into the control registers through the serial microcomputer interface by using three pins including CSN, SCK and SI. For the details of the read/write timing, refer to the format diagram shown in the next page.
3-3) Bit shift
BSFT1, BSFT0 and CTLSEL
This function is used to specify the amount of bit shift after the addition of the results of filtering. CTLSEL = 0 enables the settings of BSF1 and BSF0. The relation between the combinations of settings of BSF1 and BSF0 and the amount of bit shift is as shown below. BSFT1 0 0 1 1 BSFT 0 0 1 0 1 Bit shift None -1 bit -2 bit -3 bit
CTLSEL = 1 enables the control of bit shift amount through the microcomputer interface.
4. Initial clear
RESETN
This LSI requires an initial clear at power on moment.
5. LSI test pins
TST1, TST2, TSTCK, TSTSEL, TSTNI and TSTNO
TST1, TST2 and TST0 are to be open. TSTCK, TSTSEL and TSTNI should be connected with DVSS.
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YSS901
g Serial Microcomputer Interface
Format for writing data through microcomputer
After setting the address (A0 and A1) through SI, it is possible to write data (D0 to D7) into the specified address when R/W bit has been set to "0". The address map is as shown below.
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Address A1, A0 00
Data D0 D1 D2 D3 D4 D5 to D7 D0 D1 D2 D3 to D7 D7 to D0 D7 to D0
Description CSEL0 CSEL1 CSEL2 BSFT0 BSFT1 To be "0". Write address selection Write address counter clear RAM clear To be "0". Coefficient data to be written (higher byte) Coefficient data to be written (lower byte)
0
1
1 1
0 1
How to write coefficient data into RAM
Two coefficients are used as a set, each constituted with 16 bits x 125 taps. The first coefficient ("coef1" shown in the block diagram) is written into RAM address 0-124, and the second one ("coef2" shown in the block diagram) into RAM address 125-249. The address counter for writing the data uses seven (7) bits, the upper bit (8th bit) uses "write address selection" of D2 with A1, A0 = 0 1.
Data writing procedure (1) Clear the RAM and write address counter. (RAM clear needs up to 2 fs to be completed.) (2) When the RAM has been cleared, write data into higher byte and then into lower byte starting at the first byte of the first coefficient. (When the writing into the lower byte has been completed, the data is actually written into RAM. Wait 1 fs before writing the data into higher byte of the next coefficient.) (3) When the first coefficient has been written, write the second one by using the same procedure. Set the "write address selection" bit to "1" when writing data into the 4th tap and after of the second coefficient.
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15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
(1) Dac 48fs 16bit format
BCLK
SYNCN
g Serial Data Interface
DIN,DOUT
02 01 00
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
(2) Dac 48fs 18bit format
BCLK
SYNCN
Timing of the serial data interface as shown below
DIN,DOUT
17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
02 01 00
17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
(3) Dac 48fs 20bit format
BCLK
SYNCN
DIN,DOUT
02 01 00
19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
19 18 17
(4) 64fs YAMAHA-DSP format
BCLK
SYNCN
YSS901
DIN,DOUT
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
15 14 13 12 11 10
YSS901
g Electrical Characteristics
1. Absolute Maximum Rating
Items Power supply Voltage Input Voltage Input Current Storage Temperature Symbol VDD VI II Tstg Min. Vss-0.5 Vss-0.5 -20 -50 Max. Vss+7.0 VDD1+0.5 +20 125 Unit V V mA C
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2. Recommended Operating Conditions
Items Power supply Voltage Operating Temperature Symbol VDD Top Min. 4.75 0 Typ. 5.0 25 Max. 5.25 70 Unit V C
3. DC Characteristics (Condition: Under Recommended Operating Conditions)
Items Symbol Condition Min. Typ. Max. Input Voltage H level VIH2 *1 2.2 Input Voltage L level VIL2 *1 0.8 Output Voltage H level VOH IOH = -80 mA *2 VDD1-1.0 Output Voltage L level VOL IOL = 1.6 mA *2 0.4 Output Capacitance CO *2 50 PD 500 Power Consumption *1 Applicable to input terminals other than analog terminals *2 Applicable to output terminals other than analog terminals Unit V V V V pF mW
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YSS901
4. AC Characteristics (Condition: Under Recommended Operating Conditions)
Items XI Clock Frequency Duty SCK,SI,CSN Set up time Hold Time BCLK,SYNCN,DIN,DOUT Set up time Hold time Output Delay time
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Symbol Xin Xduty Tset Thold Tset Thold Td
Condition
Min.
Typ. 2.822 50 -
Max.
Unit MHz % ns ns ns ns ns
40 40 40 40 40 -
60 40
SCK
Tset Thold
SI,CSN
BCLK
Tset Thold
DIN,SYNCN
Td
DOUT
BCLK
Tset Thold
DIN,SYNCN
Td
DOUT
10
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10 1k
2.8224M 22p
22p
XTAL
470p 10k
100k
Rout
YSS901
g Design Example
680 1M
Lout
TSTNO TSTNI TST1 XTAL ROUT LOUT DVSS PLLC AVSS TSTCK EXTAL
51 32 N.C AVDD VREF
0.1 10/16
N.C N.C N.C N.C N.C
49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
50
N.C
N.C
N.C
N.C 31 30 29 28 27 AIL AILOUT AILRET 26 25 24 23 22 21 20 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 AIR AIROUT AIRRET AVSS DVSS TST2 N.C
220 220 560
52
Analog I/O
Control
DVDD
53
TSTSEL
54
8.2k 1.8k 1 1000p 10k 100k
CSEL2
55
Lin
DC Switch
CSEL1
56
CSEL0
57
RESETN
58
YSS901
Rin
OR
BSFT1
59
BSFT0
60
The figure below shows basic design example that uses YSS901.
SCK
61
Serial Ctl
SI
62
(from CPU)
DVSS
63
N.C
64
1
2
N.C
N.C
N.C
N.C
CSN
DIN
N.C
N.C
N.C
N.C
DVDD
BCLK
DOUT
DVDD
SYNCN
DSEL2
DSEL1
DSEL0
CTLSEL
Digital I/O
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YSS901
g External Dimensions
C-PK64FP-1
24.80 +/- 0.40
20.00 +/- 0.30
0.15 +/- 0.05 (LEAD THICKNESS)
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51
33
52
32
14.00 +/- 0.30
64 20
1 19
P-1.00TYP
2.95 MAX.
0.35 +/- 0.10 or 0.40 +/- 0.10
(2.40)
0-15 deg.
0 MIN. (STAND OFF)
1.20 +/- 0.20
(UNIT) : mm (millimeters) The figure in the parenthesis ( ) should be used as a reference. Plastic body dimensions do not include burr of resin. UNIT: mm
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18.80 +/- 0.40
YSS901
Memo
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YSS901
IMPORTANT NOTICE
1. Yamaha reserves the right to make changes to its Products and to this document without notice. The information contained in this document has been carefully checked and is believed to be reliable. However, Yamaha assumes no responsibilities for inaccuracies and makes no commitment to update or to keep current the information contained in this document. 2. These Yamaha Products are designed only for commercial and normal industrial applications, and are not suitable for other uses, such as medical life support equipment, nuclear facilities, critical care equipment or any other application the failure of which could lead to death, personal injury or environmental or property damage. Use of the Products in any such application is at the customer's sole risk and expense. 3. Yamaha assumes no liability for incidental , consequential, or special damages or injury that may result from misapplication or improper use or operation of the Products. 4. Yamaha makes no warranty or representation that the Products are subject to intellectual property license from Yamaha or any third party, and Yamaha makes no warranty excludes any liability to the Customer or any third party arising from or related to the Products' infringement of any third party's intellectual property rights, including the patent, copyright, trademark or trade secret rights of any third party. 5. Examples of use described herein are merely to indicate the characteristics and performance of Yamaha products. Yamaha assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. Yamaha makes no warranty with respect to the products, express or implied, including, but not limited to the warranties of merchantability, fitness for a particular use and title.
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The specifications of this product are subject to improvement changes without prior notice.
AGENCY
Address inquiries to: Semiconductor Sales & Marketing Department Head Office 203, Matsunokijima, Toyooka-mura Iwata-gun, Shizuoka-ken, 438-0192 Electronic Equipment Business section Tel. 81-539-62-4918 Fax. 81-539-62-5054 2-17-11, Takanawa, Minato-ku, Tokyo, 108-8568 Tel. 81-3-5488-5431 Fax. 81-3-5488-5088 Namba Tsujimoto Nissei Bldg, 4F 1-13-17, Namba Naka, Naniwa-ku, Osaka City, Osaka, 556-0011 Tel. 81-6-6633-3690 Fax. 81-6-6633-3691 YAMAHA Systems Technology. 100 Century Center Court, San Jose, CA95112 Tel. 1-408-467-2300 Fax. 1-408-437-8791
Tokyo Office Osaka Office
U.S.A. Office
All rights reserved (c) 1999

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