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19-2934; Rev 0; 7/03
10Gbps Modulator Driver
General Description
The MAX3942 is designed to drive high-speed optical modulators at data rates up to 10.7Gbps. It functions as a modulation circuit, with an integrated control op amp externally programmed by a DC voltage. A high-bandwidth, fully differential signal path is internally implemented to minimize jitter accumulation. When a clock signal is available, the integrated data-retiming function can be selected to reject input-signal jitter. The MAX3942 receives differential CML signals (groundreferenced) with on-chip line terminations of 50. Each of the differential outputs has an on-chip 50 resistor for back termination. The driver is able to deliver a modulation current of 40mA P-P to 120mA P-P, with an edge speed of 23ps (typical 20% to 80%). This modulation current reflects a modulation voltage of 1.0VP-P to 3.0VP-P single ended or 2.0VP-P to 6.0VP-P differential. The MAX3942 also includes an adjustable pulse-width control circuit to precompensate for asymmetrical modulator characteristics. It is available in a compact 4mm 4mm, 24-pin thin QFN package and operates over the -40C to +85C temperature range. o 23ps Edge Speed o Single-Ended Modulation Voltage Up to 3VP-P o Differential Modulation Voltage Up to 6VP-P o Selectable Data-Retiming Latch o Up to 10.7Gbps Operation o 50 On-Chip Input and Output Terminations o Pulse-Width Adjustment o Enable and Polarity Controls o ESD Protection
Features
MAX3942
Applications
Mach Zehnder Modulators Packaged Direct-Modulated Lasers SONET OC-192 and SDH STM-64 Transmission Systems DWDM Systems Long/Short-Reach Optical Transmitters 10Gbps Ethernet
Ordering Information
PART MAX3942ETG TEMP RANGE -40C to +85C PIN-PACKAGE 24 Thin QFN (4mm 4mm)
Pin Configuration appears at end of data sheet.
Typical Application Circuit
50
-5.2V
L2 0.01F DATA+ 0.01F 50 DATA+ PLRT MODEN RTEN GND OUT0.01F 50 MACH ZEHNDER MODULATOR 50 10Gbps SERIALIZER CLK+ 0.01F CLK50 CLKPWC+ 2k PWCMODSET + VMODSET -5.2V 1000pF 0.1F OUT+ VEE 0.01F 50 CLK+
MAX3952
DATA-
50
DATA-
MAX3942
L1 0.01F 50
-5.2V
-5.2V
L1 AND L2 ARE HIGH-FREQUENCY FERRITE BEADS REPRESENTS A CONTROLLED-IMPEDANCE TRANSMISSION LINE.
________________________________________________________________ Maxim Integrated Products
1
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10Gbps Modulator Driver MAX3942
ABSOLUTE MAXIMUM RATINGS
Supply Voltage VEE ..............................................-6.0V to +0.5V Voltage at MODEN, RTEN, PLRT, MODSET............................(VEE - 0.5V) to +0.5V Voltage at DATA+, DATA-, CLK+, and CLK-......-1.65V to +0.5V Voltage at OUT+, OUT- ..........................................-4V to +0.5V Voltage at PWC+, PWC- ...................(VEE - 0.5V) to (VEE + 1.7V) Continuous Power Dissipation (TA = +85C) 24-Pin Thin QFN (derate 20.8mW/ above +85C) ....1354mW Current into or out of OUT+, OUT-...................................80mA Storage Temperature Range ...........................-55C to +150C Operating Temperature Range ..........................-40C to +85C Lead Temperature (soldering, 10s)..............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VEE = -5.5V to -4.9V, TA = -40C to +85C. Typical values are at VEE = -5.2V, IMOD = 100mA, and TA = +25C, unless otherwise noted.)
PARAMETER Power-Supply Voltage Supply Current Power-Supply Noise Rejection SIGNAL INPUT (Note 3) Input Data Rates Single-Ended Input Resistance Single-Ended Input Voltage Differential Input Voltage Differential Input Return Loss MODULATION (Note 5) Maximum Modulation Current Minimum Modulation Current MODSET Voltage Range Equivalent Modulation Resistance Modulation Set Bandwidth MODSET Input Resistance Modulation-Current Temperature Stability Modulation-Current-Setting Error Output Resistance ROUT (Note 6) 50 driver load, TA = +25C OUT+ and OUT- to GND -980 -10 42.5 50 VMODSET RMODEQV (Note 7) Modulation depth 10%, 50 driver load VMODSET = VEE VEE 11.1 5 20 0 +10 58.5 112 120 37 40 VEE + 1 mAP-P mAP-P V MHz k ppm/C % RIN VIS VID RLIN NRZ Input to GND DC-coupled, Figure 1a AC-coupled, Figure 1b DC-coupled (Note 4) AC-coupled (Note 4) 15GHz 42.5 -1 -0.4 0.2 0.2 15 10.7 50 58.5 0 +0.4 2.0 1.6 Gbps V VP-P dB SYMBOL VEE IEE PSNR Excluding IMOD (Note 1) Retime disabled Retime enabled CONDITIONS MIN -5.5 125 140 15 TYP MAX -4.9 175 200 UNITS V mA dB
f 2MHz (Note 2); see Figure 3
2
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10Gbps Modulator Driver
ELECTRICAL CHARACTERISTICS (continued)
(VEE = -5.5V to -4.9V, TA = -40C to +85C. Typical values are at VEE = -5.2V, IMOD = 100mA, and TA = +25C, unless otherwise noted.)
PARAMETER Off Current Differential Output Return Loss Output Edge Speed Setup/Hold Time Pulse-Width Adjustment Range Pulse-Width Control Input Range (Single Ended) Pulse-Width Control Input Range (Differential) Output Overshoot Driver Random Jitter Driver Deterministic Jitter CONTROL INPUTS Input High Voltage Input Low Voltage Input Current VIH VIL (Note 10) (Note 10) (Note 10) -80 VEE + 2.0 VEE + 0.8 +200 V V A RJDR DJDR tSU, tHD RLOUT SYMBOL CONDITIONS MODEN = VEE, MODSET = VEE, DATA+ = high, DATA- = low IMOD = 50mA Figure 2 (Note 6) (Notes 6, 8) For PWC+ and PWC(PWC+) - (PWC-) (Notes 6, 8) (Note 6) PWC- = GND (Notes 6, 9) 10GHz 25 30 VEE + 0.5 -0.5 5 0.3 8 0.8 13 50 VEE + 1.5 +0.5 10 23 32 20% to 80% (Notes 6, 8) MIN TYP MAX 1.6 UNITS mA dB ps ps ps V V % psRMS psP-P
MAX3942
Note 1: Supply current remains elevated once the retiming function has been enabled. Power must be cycled to reduce supply current after the retiming function has been disabled. Note 2: Power-supply noise rejection is specified as PSNR = 20Log(Vnoise (on Vcc) / VOUT). VOUT is the voltage across a 50 load. Vnoise (on Vcc) = 100mVP-P. Note 3: For DATA+, DATA-, CLK+, and CLK-. Note 4: CLK input characterized at 10.7Gbps. Note 5: Minimum voltage on OUT+ and OUT- is VEE + 1.9V. Note 6: Guaranteed by design and characterization using the circuit shown in Figure 3. Note 7: RMODEQV = (VMODSET - VEE) / (IMOD - 37mA). Note 8: 50 load, characterized at 10.7Gbps with a 1111 1111 0000 0000 pattern. Note 9: Deterministic jitter is defined as the arithmetic sum of PWD (pulse-width distortion) and PDJ (pattern-dependent jitter). Measured with a 10.7Gbps 27 - 1 PRBS pattern with 80 zeros and 80 ones inserted in the data pattern. Note 10: For MODEN and PLRT.
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10Gbps Modulator Driver MAX3942
Test Circuits and Timing Diagrams
0V
100mV
1.0V -0.5V
-1.0V (a) DC-COUPLED SINGLE-ENDED CML INPUT
0.4V
800mV 0V 100mV
-0.4V
(b) AC-COUPLED SINGLE-ENDED (CML OR PECL) INPUT
Figure 1. Definition of Single-Ended Input Voltage Range
CLK+
CLKtSU DATAtHD
VIS = 0.1VP-P TO 1VP-P DC-COUPLED 0.1VP-P TO 0.8VP-P AC-COUPLED
DATA+
(DATA+) - (DATA-)
VID = 0.2VP-P TO 2VP-P DC-COUPLED 0.2VP-P TO 1.6VP-P AC-COUPLED
IOUT+
IMOD = 40mAP-P TO 120mAP-P IOUTNOTE: IOUT+ AND IOUT- RELATE TO RETIMED DATA. SEE FIGURE 3 FOR POLARITY.
Figure 2. Setup and Hold Timing Definition
4
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10Gbps Modulator Driver
Test Circuits and Timing Diagrams (continued)
MAX3942
PLRT 50 50 PATTERN GENERATOR 50 50 DATA+ DATAVEE CLK+
RTEN
MODEN
PWC+
PWCIOUT-
CLK-
OSCILLOSCOPE OUT50
MAX3942
OUT+ IOUT+
50 50 ZL
MODSET
GND
-5.2V 0.1F 1000pF
VMODSET VEE
Figure 3. AC Characterization Circuit
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5
10Gbps Modulator Driver MAX3942
Typical Operating Characteristics
(Typical values are at VEE = -5.2V, IMOD = 100mA, TA = +25C, unless otherwise noted.)
10.7Gbps ELECTRICAL EYE DIAGRAM (VMOD = 2VP-P DIFFERENTIAL, 231 - 1 PRBS)
MAX3942 toc01
10.7Gbps ELECTRICAL EYE DIAGRAM (VMOD = 6VP-P DIFFERENTIAL, 231 - 1 PRBS)
MAX3942 toc02
SUPPLY CURRENT vs. TEMPERATURE (50 LOAD, EXCLUDES IMOD)
MAX3942 toc03
170 160 150 RETIMING ENABLED IEE (mA) 140 130 120 RETIMING DISABLED 110 100
16ps/div
16ps/div
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 TEMPERATURE (C)
PULSE WIDTH vs. RPWC
RPWC- () 2000 1750 1500 1250 1000 750 500 250 850 PULSE-WIDTH POSITIVE PULSE (ps) 840 830 820 810 800 790 780 770 760 750 0 250 500 750 1000 1250 1500 1750 2000 RPWC+ () MEASURED AT 1.25Gbps WITH A 1010 PATTERN 0
MAX3942 toc04
PULSE-WIDTH DISTORTION vs. TEMPERATURE
MAX3942 toc05
DIFFERENTIAL VMOD vs. VMODSET (ZL = 50 ON OUT+ AND OUT-)
VMODSET IS RELATIVE TO VEE 6 DIFFERENTIAL VMOD (VP-P) 5 4 3 2 1 0
MAX3942 toc06
2.0 1.8 PULSE-WIDTH DISTORTION (ps) 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 -50 -30 -10 10 30 50 70
7
90
0
0.25
0.50 VMODSET (V)
0.75
1.00
TEMPERATURE (C)
POWER-SUPPLY NOISE REJECTION vs. FREQUENCY
MAX3942 toc07
DIFFERENTIAL S11 vs. FREQUENCY (DEVICE POWERED)
MAX3942 toc08
DIFFERENTIAL S22 vs. FREQUENCY (DEVICE POWERED)
-3 -6 -9 |S22| (dB) -12 -15 -18 -21
MAX3942 toc09
30 25 20 PSNR (dB) 15 10 5
0 -5 -10 IS11I (dB) -15 -20 -25 -30 -35
0
-24 -27 -30 0 3 6 9 12 15 0 3 6 9 12 15 FREQUENCY (GHz) FREQUENCY (GHz)
0 1 10 100 FREQUENCY (Hz) 1k 10k
-40
6
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10Gbps Modulator Driver
Pin Description
PIN 1 2 3, 4, 14, 17 5 6 7, 11, 12, 13, 18, 19, 21, 24 8 9 10 15 16 20 22 23 EP NAME DATA+ DATAGND CLK+ CLKVEE PWC+ PWCMODSET OUTOUT+ PLRT MODEN RTEN Exposed Pad FUNCTION Noninverting Data Input, with 50 On-Chip Termination Inverting Data Input, with 50 On-Chip Termination Ground. All pins must be connected to board ground. Noninverting Clock Input for Data Retiming, with 50 On-Chip Termination Inverting Clock Input for Data Retiming, with 50 On-Chip Termination Negative Supply Voltage. All pins must be connected to board VEE. Positive Input for Modulation Pulse-Width Adjustment (see the Design Procedure section). Negative Input for Modulation Pulse-Width Adjustment. Ground to disable the pulse-width adjustment feature (see the Design Procedure section). Modulation Current Set. Apply a voltage to set the modulation current of the driver output. Inverting Driver Output. Provides modulation output with 50 back termination. Sinks current when PLRT is high and when differential data is high. Noninverting Driver Output. Provides modulation output with 50 back termination. Sinks current when PLRT is high and when differential data is low. Differential Data Polarity Swap Input. Set high or float for normal operation. Set low to invert the differential signal polarity. Contains an internal 100k pullup to GND. TTL/CMOS Modulation Enable Input. Set low or float for normal operation. Set high to put the EAM in the absorption (logic 0) state. Contains an internal 100k pulldown to VEE. Data-Retiming Input. Connect to VEE for retimed data. Connect to GND to bypass retiming latch. Ground. Must be soldered to the circuit board ground for proper thermal and electrical performance. See the Layout Considerations section.
MAX3942
Detailed Description
The MAX3942 modulator driver accepts differential clock and data inputs that are compatible with PECL and CML logic levels. The modulation output stage is composed of a highspeed differential pair and a programmable current source with a maximum modulation current of 120mA. The rise and fall times are typically 23ps. The modulation current is designed to produce a modulation voltage up to 3.0VP-P single endedly, or 6.0VP-P differentially when driving a 50 module. The 3.0VP-P results from 120mAP-P through the parallel combination of the 50 modulator load and the internal 50 back termination.
Polarity Switch
The MAX3942 includes a polarity switch. When the PLRT pin is high or left floating, the outputs maintain the polarity of the input data. When the PLRT pin is low, the outputs are inverted relative to the input data.
Clock/Data Input Logic Levels
The MAX3942 is directly compatible with ground-reference CML. Either DC- or AC-coupling may be used for CML referenced to ground. For all other logic types, AC-coupling should be used.
Optional Data Input Latch
To reject pattern-dependent jitter in the input data, a synchronous differential clock signal should be connected to the CLK+ and CLK- inputs, and the RTEN control input should be connected to VEE.
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7
10Gbps Modulator Driver MAX3942
The input data is retimed on the rising edge of CLK+. If RTEN is connected to ground, the retiming function is disabled and the input data is directly connected to the output stage. Leave CLK+ and CLK- open when retiming is disabled. An internal, independent current source drives a constant 37mA to the modulation circuitry and any voltage above VEE on the MODSET pin adds to this. The input impedance of the MODSET pin is typically 20k. Note that the minimum output voltage is VEE + 1.9V.
Pulse-Width Control
The pulse-width control circuit can be used to compensate for pulse-width distortion introduced by the modulator. The differential voltage between PWC+ and PWCadjusts the pulse-width compensation. The adjustment range is typically 50ps. Optional single-ended operation is possible by forcing a voltage on the PWC+ pin while leaving the PWC- pin unconnected. When PWCis connected to ground, the pulse-width control circuit is automatically disabled.
Programming the Pulse-Width Control
Three methods of control are possible when pulse predistortion is desired to minimize distortion at the receiver. The pulse width may be set with a 2k potentiometer with the center tapped to VEE (or equivalent fixed resistors), or by applying a voltage to the PWC+ pin, or by applying a differential voltage across the PWC+ and PWC- pins. See Table 1 for the desired effect of the pulse-width setting. Pulse width is defined as (positive pulse width)/((positive pulse width + negative pulse width)/2).
Modulation Output Enable
The MAX3942 incorporates a modulation currentenable input. When MODEN is low or floating, the modulation outputs OUT+ and OUT- are enabled. When MODEN is high, the drive current is switched to OUT+. The typical enable time is 2ns and the typical disable time is 2ns.
Input Termination Requirement
The MAX3942 data and clock inputs are CML compatible. However, it is not necessary to drive the IC with a standard CML signal. As long as the specified input voltage swings are met, the MAX3942 operates properly.
Applications Information
Layout Considerations
To minimize loss and crosstalk, keep the connections between the MAX3942 output and the modulator as short as possible. Use good high-frequency layout techniques and multilayer boards with an uninterrupted ground plane to minimize EMI and crosstalk. Circuit boards should be made using low-loss dielectrics. Use controlled-impedance lines for the clock and data inputs, as well as for the data output.
Design Procedure
Programming the Modulation Voltage
The modulation voltage results from I MOD passing through the load impedance (ZL) in parallel with the internal 50 termination resistor (ROUT): VMOD IMOD x ZL x ROUT ZL + ROUT
To program the desired modulation current, force a voltage at the MODSET pin (see the Typical Application Circuit). The resulting IMOD current can be calculated by the following equation: IMOD VMODSET + 37mA 11.1
Table 1. Pulse-Width Control
PULSE WIDTH (%) 100 >100 <100 RPWC+, RPWC- FOR RPWC+ + RPWC- = 2k RPWC+ = RPWCRPWC+ > RPWCRPWC+ < RPWCVPWC+ (PWC- OPEN) (V) VEE + 1 > VEE + 1 < VEE + 1 VPWC+ VPWC(V) 0 >0 <0
8
_______________________________________________________________________________________
10Gbps Modulator Driver MAX3942
RTEN
MODEN
PLRT 50 50 50 OUTOUT+ 50
50 CLK+ CLK-
50 VEE DQ 0 MUX 1 PWC IMOD
POLARITY
DATA+ DATA50 50
MAX3942
VEE
PWC+ 2k
PWC+ -
MODSET VMODSET
VEE
VEE
Figure 4. Functional Diagram
GND
Interface Schematics
Figures 5 and 6 show simplified input and output circuits of the MAX3942 modulator driver. To minimize inductance, keep the connections from OUT, GND, and VEE as short as possible. This is crucial for optimal performance.
50 50
MAX3942
Laser Safety and IEC 825
Using the MAX3942 EAM driver alone does not ensure that a transmitter design is compliant with IEC 825. The entire transmitter circuit and component selections must be considered. Each customer must determine the level of fault tolerance required by their application, recognizing that Maxim products are not designed or authorized for use as components in systems intended for surgical implant into the body, for applications intended to support or sustain life, or for any other application where the failure of a Maxim product could create a situation where personal injury or death may occur.
DATA+/CLK+
DATA-/CLK-
VEE
Figure 5. Simplified Input Circuit 9
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10Gbps Modulator Driver MAX3942
Exposed-Pad Package
GND GND
MAX3942
GND OUTVEE 50 50 GND OUT+
The exposed pad on the 24-pin QFN provides a very low thermal resistance path for heat removal from the IC. The pad is also electrical ground on the MAX3942 and must be soldered to the circuit board ground for proper thermal and electrical performance. Refer to Maxim Application Note HFAN-08.1: Thermal Considerations for QFN and Other Exposed-Pad Packages for additional information.
Chip Information
VEE
TRANSISTOR COUNT: 1918 PROCESS: SiGe Bipolar
Figure 6. Simplified Output Circuit
Pin Configuration
RTEN PLRT
TOP VIEW
VEE
MODEN
VEE
24
23
22
21
20
19
VEE
Package Information
DATA+ DATAGND GND CLK+ CLK-
1 2 3 4 5 6 10 11 12 7 8 9
18 17 16
VEE GND OUT+ OUTGND VEE
For the latest package outline information, go to www.maxim-ic.com/packages.
PART MAX3942ETG PACKAGE TYPE 24 Thin QFN (4mm 4mm 0.8mm) PACKAGE CODE T2444-1
MAX3942
15 14 13
VEE
VEE.
PWC+
PWC-
24 THIN QFN (4mm x 4mm)
EXPOSED PAD CONNECTED TO GROUND
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
MODSET
VEE

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