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(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S M5M467805/465805DJ,DTP -5,-6,-5S,-6S M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
PRELIMINARY DESCRIPTION
The M5M467405/465405DJ,DTP is a 16777216-word by 4-bit, M5M467805/465805DJ,DTP is a 8388608-word by 8-bit, and M5M465165DJ,DTP is a 4194304-word by 16-bit dynamic RAMs, fabricated with the high performance CMOS process, and are suitable for large-capacity memory systems with high speed and low power dissipation. Some of contents are subject to change without notice.
FEATURES
Type name M5M467405DXX-5,5S M5M467805DXX-5,5S M5M467405DXX-6,6S M5M467805DXX-6,6S M5M465405DXX-5,5S M5M465805DXX-5,5S M5M465405DXX-6,6S M5M465805DXX-6,6S Address Power RAS OE CAS Cycle access access access access dissipatime tion time time time time (max.ns) (max.ns) (max.ns) (max.ns) (min.ns) (typ.mW) Type name Power Address RAS CAS OE Cycle dissipaaccess access access access time time tion time time time (max.ns) (max.ns) (max.ns) (max.ns) (min.ns) (typ.mW)
50 60 50 60
13 15 13 15
25 30 25 30
13 15 13 15
84 104 84 104
300 250 390 325
M5M465165DXX-5,5S M5M465165DXX-6,6S
50 60
13 15
25 30
13 15
84 104
420 390
XX=J,TP
Standard 32 pin SOJ, 32 pin TSOP (M5M467405Dxx/M5M465405Dxx/M5M467805Dxx/M5M465805Dxx) Standard 50 pin SOJ, 50 pin TSOP (M5M465165Dxx) Single 3.3 0.3V supply Low stand-by power dissipation 1.8mW (Max) LVCMOS input level Low operating power dissipation M5M467405Dxx-5,5S / M5M467805Dxx-5,5S 360.0mW (Max) M5M467405Dxx-6,6S / M5M467805Dxx-6,6S 324.0mW (Max) M5M465405Dxx-5,5S / M5M465805Dxx-5,5S 468.0mW (Max) M5M465405Dxx-6,6S / M5M465805Dxx-6,6S 432.0mW (Max) M5M465165Dxx-5,5S 504.0mW (Max) M5M465165Dxx-6,6S 468.0mW (Max) Self refresh capability* Self refresh current 400A (Max) EDO mode , Read-modify-write, CAS before RAS refresh, Hidden refresh capabilities Early-write mode , OE and W to control output buffer impedance All inputs, outputs LVTTL compatible and low capacitance * :Applicable to self refresh version(M5M467405/465405/467805/465805/465165DJ,DTP-5S,-6S:option) only
ADDRESS
Part No.
Row Add. Col. Add.
Refresh
Refresh Cycle Normal S-version
RAS Only Ref,Normal R/W 8192/64ms 8192/128ms
M5M467405Dxx A0-A12 M5M465405Dxx A0-A11 M5M467805Dxx A0-A12 M5M465805Dxx A0-A11 M5M465165Dxx A0-A11
A0-A10
CBR Ref,Hidden Ref
4096/64ms 4096/128ms
A0-A11 RAS Only Ref,Normal R/W 4096/64ms 4096/128ms CBR Ref,Hidden Ref
RAS Only Ref,Normal R/W 8192/64ms 8192/128ms
A0-A9
CBR Ref,Hidden Ref
4096/64ms 4096/128ms
A0-A10 A0-A9
RAS Only Ref,Normal R/W 4096/64ms 4096/128ms CBR Ref,Hidden Ref RAS Only Ref,Normal R/W 4096/64ms 4096/128ms CBR Ref,Hidden Ref
APPLICATION
Main memory unit for computers, Microcomputer memory, Refresh memory for CRT
1
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S M5M467805/465805DJ,DTP -5,-6,-5S,-6S M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
PIN DESCRIPTION
M5M467405Dxx / M5M465405Dxx Pin Name A0-A12 DQ1-DQ4 RAS CAS W OE Vcc Vss NC Function Address Inputs Data Inputs / Outputs Row Address Strobe Input Column Address Strobe Input Write Control Input Output Enable Input Power Supply (+3.3V) Ground (0V) No Connection M5M467805Dxx / M5M465805Dxx Pin Name A0-A12 DQ1-DQ8 RAS CAS W OE Vcc Vss NC Function Address Inputs Data Inputs / Outputs Row Address Strobe Input Column Address Strobe Input Write Control Input Output Enable Input Power Supply (+3.3V) Ground (0V) No Connection
M5M465165Dxx Pin Name A0-A11 Function Address Inputs
DQ1-DQ16 Data Inputs / Outputs Row Address Strobe Input RAS Upper byte control UCAS Column Address Strobe Input Lower byte control LCAS Column Address Strobe Input Write Control Input W OE Vcc Vss NC Output Enable Input Power Supply (+3.3V) Ground (0V) No Connection
XX=J, TP
M5M467400/465400DJ, DTP
PIN CONFIGURATION (TOP VIEW)
Vcc DQ1 DQ2 NC NC NC NC W RAS A0 A1 A2 A3 A4 A5 Vcc
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
Vss DQ4 DQ3 NC NC NC CAS OE A12/NC(Note) A11 A10 A9 A8 A7 A6 Vss
Vcc DQ1 DQ2 NC NC NC NC W RAS A0 A1 A2 A3 A4 A5 Vcc
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
Vss DQ4 DQ3 NC NC NC CAS OE A12/NC(Note) A11 A10 A9 A8 A7 A6 Vss
Outline 32P0N (400mil SOJ)
M5M465405DJ
M5M467405DJ
Outline 32P3N (400mil TSOP Normal Bend)
Note : A12...M5M467405Dxx, NC...M5M465405Dxx : NO CONNECTION NC
M5M465405DTP
M5M467405DTP
2
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S M5M467805/465805DJ,DTP -5,-6,-5S,-6S M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
M5M467805/465805DJ, DTP
Vcc DQ1 DQ2 DQ3 DQ4 NC Vcc W RAS A0 A1 A2 A3 A4 A5 Vcc
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
PIN CONFIGURATION (TOP VIEW)
Vss DQ8 DQ7 DQ6 DQ5 Vss CAS OE A12/NC(Note) A11 A10 A9 A8 A7 A6 Vss Vcc DQ1 DQ2 DQ3 DQ4 NC Vcc W RAS A0 A1 A2 A3 A4 A5 Vcc
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
Vss DQ8 DQ7 DQ6 DQ5 Vss CAS OE A12/NC(Note) A11 A10 A9 A8 A7 A6 Vss
Outline 32P0N (400mil SOJ)
M5M465165DJ, DTP
Vcc DQ1 DQ2 DQ3 DQ4 Vcc DQ5 DQ6 DQ7 DQ8 NC Vcc W RAS NC NC NC NC A0 A1 A2 A3 A4 A5 Vcc
1 2 3 4 5 6 7 8 9 10 50 49 48 47 46 45 44 43 42 41
M5M465805DJ
11 12 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Outline 50P0G (400mil SOJ)
M5M467805DJ M5M465165DJ
Outline 32P3N (400mil TSOP Normal Bend)
Note : A12...M5M467800Dxx, NC...M5M465800Dxx : NO CONNECTION NC
PIN CONFIGURATION (TOP VIEW)
Vss DQ16 DQ15 DQ14 DQ13 Vss DQ12 DQ11 DQ10 DQ9 NC Vss LCAS UCAS OE NC NC NC A11 A10 A9 A8 A7 A6 Vss Vcc DQ1 DQ2 DQ3 DQ4 Vcc DQ5 DQ6 DQ7 DQ8 NC Vcc W RAS NC NC NC NC A0 A1 A2 A3 A4 A5 Vcc
1 2 3 4 5 6 7 8 9 10 11 12 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41
M5M465805DTP M5M465165DTP
M5M467805DTP
Vss DQ16 DQ15 DQ14 DQ13 Vss DQ12 DQ11 DQ10 DQ9 NC Vss LCAS UCAS OE NC NC NC A11 A10 A9 A8 A7 A6 Vss
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
Outline 50P3G (400mil TSOP Normal Bend)
NC : NO CONNECTION
3
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S M5M467805/465805DJ,DTP -5,-6,-5S,-6S M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
FUNCTION
The M5M467405(805)/465405(805,165)DJ, DTP provide, in addition to normal read, write, and read-modify-write operations, a number of other functions, e.g., EDO mode, CAS before RAS refresh, and delayed-write. The input conditions for each are shown in Table 1.
Table 1 Input conditions for each mode
M5M467405Dxx / M5M465405Dxx / M5M467805Dxx / M5M465805Dxx
Inputs Operation RAS Read Write (Early write) Write (Delayed write) Read-modify-write RAS-only refresh Hidden refresh CAS before RAS refresh Standby ACT ACT ACT ACT ACT ACT ACT NAC CAS ACT ACT ACT ACT NAC ACT ACT DNC W NAC ACT ACT ACT DNC NAC NAC DNC OE ACT DNC DNC ACT DNC ACT DNC DNC Row address APD APD APD APD APD DNC DNC DNC Column address APD APD APD APD DNC DNC DNC DNC Input/Output Refresh Input OPN VLD VLD VLD OPN OPN DNC DNC Output VLD OPN IVD VLD OPN VLD OPN OPN NO NO NO NO YES YES YES NO EDO mode identical Remark
M5M465165Dxx
Inputs Operation RAS Lower byte read Upper byte read Word read Lower byte write Upper byte write Word write RAS-only refresh Hidden refresh CAS before RAS refresh Stand-by ACT ACT ACT ACT ACT ACT ACT ACT ACT NAC LCAS ACT NAC ACT ACT NAC ACT NAC ACT ACT DNC UCAS NAC ACT ACT NAC ACT ACT NAC ACT ACT DNC W NAC NAC NAC ACT ACT ACT DNC NAC DNC DNC OE ACT ACT ACT NAC NAC NAC DNC ACT DNC DNC Row address APD APD APD APD APD APD APD DNC DNC DNC Column address APD APD APD APD APD APD DNC DNC DNC DNC Input/Output DQ1~DQ8 VLD OPN VLD DIN DNC DIN OPN VLD OPN OPN DQ9~DQ16 OPN VLD VLD DNC DIN DIN OPN VLD OPN OPN Refresh NO NO NO NO NO NO YES YES YES NO EDO mode identical Remark
Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : Invalid, APD : applied, OPN : open
4
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S M5M467805/465805DJ,DTP -5,-6,-5S,-6S M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
M5M467405Dxx / M5M465405Dxx BLOCK DIAGRAM
COLUMN ADDRESS STROBE INPUT ROW ADDRESS STROBE INPUT WRITE CONTROL INPUT Vcc (3.3V) CAS RAS CLOCK GENERATOR CIRCUIT Vss (0V)
W (4) DATA IN BUFFERS A0~A11 (Note)
A0 A1 A2 ROW & COLUMN ADDRESS BUFFER A3 A4 A5 ADDRESS INPUTS A6 A7 A8 A9 A10 A11 A12 (Note) Note
COLUMN DECODER
SENSE REFRESH AMPLIFIER & I /O CONTROL ROW DECODER
DQ1 DQ2 DQ3 (4) DATA OUT BUFFERS DQ4 DATA INPUTS / OUTPUTS
A0~ A12 (Note)
MEMORY CELL (67108864 BITS)
OE OUTPUT ENABLE INPUT
:
Refer to Page 1 (ADDRESS)
M5M467805Dxx / M5M465805Dxx BLOCK DIAGRAM
COLUMN ADDRESS STROBE INPUT ROW ADDRESS STROBE INPUT WRITE CONTROL INPUT Vcc (3.3V) CAS RAS CLOCK GENERATOR CIRCUIT Vss (0V)
W (8) DATA IN BUFFERS A0~A10 A0 A1 A2 A3 ROW & COLUMN ADDRESS BUFFER A4 A5 SENSE REFRESH AMPLIFIER & I /O CONTROL ROW DECODER (Note) COLUMN DECODER
DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DATA INPUTS / OUTPUTS
A7 A8 A9 A10 A11 A12 (Note)
A0~ A12 (Note)
MEMORY CELL (67108864 BITS)
(8) DATA OUT BUFFERS
ADDRESS INPUTS
A6
OE OUTPUT ENABLE INPUT Note
:
Refer to Page 1 (ADDRESS)
5
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S M5M467805/465805DJ,DTP -5,-6,-5S,-6S M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
M5M465165Dxx BLOCK DIAGRAM
ROW ADDRESS RAS STROBE INPUT LOWER BYTE CONTROL LCAS COLUMN ADDRESS STROBE INPUT UPPER BYTE CONTROL UCAS COLUMN ADDRESS STROBE INPUT WRITE CONTROL INPUT W
CLOCK GENERATOR CIRCUIT (8)LOWER
VCC (3.3V) VSS (0V) LOWER UPPER
BUFFERS DATA IN
DQ1 DQ2 LOWER DATA INPUTS / OUTPUTS DQ8
DATA OUT DATA IN
(8)LOWER
A0~A9 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 COLUMN DECODER
BUFFERS (8)UPPER
BUFFERS
ADDRESS BUFFER
ROW & COLUMN
SENSE REFRESH AMPLIFIER & I /O CONTROL
DQ9 DQ10 UPPER DATA INPUTS / OUTPUTS DQ16
ROW DECODER
A0 ~ A11
MEMORY CELL (67108864BITS)
BUFFERS
(8)UPPER
ADDRESS INPUTS
DATA OUT
OE OUTPUT ENABLE INPUT
6
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S M5M467805/465805DJ,DTP -5,-6,-5S,-6S M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol Vcc VI V0 I0 Pd Topr Tstg Supply voltage Input voltage Output voltage Output current Power dissipation Operating temperature Storage temperature Ta=25 C 0 With respect to Vss Parameter Conditions Ratings Unit V V V mA mW C C
~ 4.6 -0.5 ~ 4.6 -0.5 ~ 4.6
-0.5 50 1000
~ 70 -65 ~ 150 ~ 70 C, unless
Nom 3.3 0 Max 3.6 0 Vcc+0.3 0.8
RECOMMENDED OPERATING CONDITIONS
Symbol Vcc Vss VIH VIL Supply voltage Supply voltage High-level input voltage, all inputs Low-level input voltage, all inputs Parameter
(Ta=0
otherwise noted) (Note 1) Unit V V V V
Limits Min 3.0 0 2.0 -0.3
Note 1 : All voltage values are with respect to Vss.
ELECTRICAL CHARACTERISTICS [M5M467405D / M5M467805D]
Symbol VOH VOL IOZ II ICC1 (AV) Parameter High-level output voltage Low-level output voltage Off-state output current Input current Average supply current from Vcc operating (Note 3,4,5)
(Ta=0
~ 70 C , Vcc=3.3 0.3V, Vss=0V, unless
otherwise noted) (Note 2)
Test conditions IOH=-2mA IOL=2mA Q floating 0V VOUT M5M467405D-5,5S M5M467805D-5,5S M5M467405D-6,6S M5M467805D-6,6S M5M467405D-5,5S -6,6S M5M467805D-5,5S -6,6S M5M467405D-5,6 M5M467805D-5,6 M5M467405D-5S,6S M5M467805D-5S,6S M5M467405D-5,5S M5M467805D-5,5S M5M467405D-6,6S M5M467805D-6,6S M5M467405D-5,5S M5M467805D-5,5S M5M467405D-6,6S M5M467805D-6,6S
Limits Min 2.4 0 Typ Max Vcc 0.4 10 10 100
Unit V V
0VVIN Vcc+0.3V, Other input pins=0V
Vcc
-10 -10
A A
mA
RAS, CAS cycling tRC=tWC=min. output open
90
RAS= CAS =VIH, output open
1 mA 0.5
ICC2 (AV)
Average supply current from Vcc (Note 6) stand-by
RAS= CAS Vcc -0.2V,output open 0.3 RAS=VIL, CAS cycling tHPC=min. output open CAS before RAS refresh cycling tRC=min. output open 100 mA 90 130 mA 120
ICC4 (AV)
Average supply current from Vcc EDO-Mode (Note 3,4,5) Average supply current from Vcc CAS before RAS refresh (Note 3,5) mode
ICC6 (AV)
Note 2: Current flowing into an IC is positive, out is negative. 3: Icc1 (AV) , Icc4 (AV) and Icc6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate. 4: Icc1 (AV) and Icc4 (AV) are dependent on output loading. Specified values are obtained with the output open. 5: Column Address can be changed once or less while RAS=VIL and CAS=VIH.
7
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S M5M467805/465805DJ,DTP -5,-6,-5S,-6S M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
ELECTRICAL CHARACTERISTICS [M5M465405D / M5M465805D]
Symbol VOH VOL IOZ II ICC1 (AV) Parameter High-level output voltage Low-level output voltage Off-state output current Input current Average supply current from Vcc operating (Note 3,4,5) M5M465405D-5,5S M5M465805D-5,5S M5M465405D-6,6S M5M465805D-6,6S M5M465405D-5,5S -6,6S M5M465805D-5,5S -6,6S IOH=-2mA IOL=2mA Q floating 0V VOUT (Ta=0
~ 70 C, Vcc=3.3 0.3V, Vss=0V, unless
Test conditions
otherwise noted) (Note 2)
Limits Min 2.4 0 Typ Max Vcc 0.4 10 10 130
Unit V V
0VVIN Vcc+0.3V, Other input pins=0V
Vcc
-10 -10
A A
mA
RAS, CAS cycling tRC=tWC=min. output open
120
RAS= CAS =VIH, output open
1 mA 0.5 0.3 100 mA 90 130 mA 120
ICC2 (AV)
Average supply current from Vcc (Note 6) stand-by
ICC4 (AV)
Average supply current from Vcc EDO-Mode (Note 3,4,5) Average supply current from Vcc CAS before RAS refresh (Note 3,5) mode
M5M465405D-5,6 M5M465805D-5,6 RAS= CAS Vcc -0.2V,output open M5M465405D-5S,6S M5M465805D-5S,6S M5M465405D-5,5S RAS=VIL, CAS cycling M5M465805D-5,5S tHPC=min. M5M465405D-6,6S output open M5M465805D-6,6S M5M465405D-5,5S M5M465805D-5,5S M5M465405D-6,6S M5M465805D-6,6S CAS before RAS refresh cycling tRC=min. output open
ICC6 (AV)
[M5M465165D]
Symbol VOH VOL IOZ II ICC1 (AV) Parameter High-level output voltage Low-level output voltage Off-state output current Input current Average supply current M5M465165D-5,5S from Vcc (Note 3,4,5) M5M465165D-6,6S operating Average supply current from Vcc (Note 6) stand-by M5M465165D-5,5S -6,6S M5M465165D-5,6 M5M465165D-5S,6S IOH=-2mA IOL=2mA Q floating 0V VOUT Vcc
0V
Test conditions
Limits Min 2.4 0 -10 -10 Typ Max Vcc 0.4 10 10 140 130 1 0.5 0.3 120 110 140
Unit V V
VIN
Vcc+0.3V, Other input pins=0V
A A
mA
RAS, CAS cycling tRC=tWC=min. output open RAS= CAS =VIH, output open RAS= CAS
ICC2 (AV)
Vcc -0.2V, output open
mA
ICC4 (AV)
Average supply current M5M465165D-5,5S from Vcc (Note 3,4,5) M5M465165D-6,6S EDO-Mode Average supply current from Vcc CAS before RAS refresh (Note 3,5) mode M5M465165D-5,5S M5M465165D-6,6S
RAS=VIL, CAS cycling tHPC=min. output open CAS before RAS refresh cycling tRC=min. output open
mA
ICC6 (AV)
mA 130
8
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S M5M467805/465805DJ,DTP -5,-6,-5S,-6S M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
CAPACITANCE
Symbol CI (A) CI (OE) CI (W) CI (RAS) CI (CAS) CI / O (Ta=0
~ 70 C , Vcc=3.3 0.3V, Vss=0V, unless
Parameter
otherwise noted) Test conditions Limits Min Typ Max 5 7 7 7 7 7 Unit pF pF pF pF pF pF
Input capacitance,address inputs Input capacitance, OE input Input capacitance, write control input Input capacitance, RAS input Input capacitance, CAS input Input/Output capacitance, data ports VI=Vss f=1MHZ Vi=25mVrms
SWITCHING CHARACTERISTICS
(Ta=0 ~ 70 C , Vcc=3.3 0.3V, Vss=0V, unless otherwise noted , see notes 6,14,15) Limits
Symbol
Parameter
M5M46X405D-5,5S M5M46X405D-6,6S M5M46X805D-5,5S M5M46X805D-6,6S M5M465165D-5,5S M5M465165D-6,6S Min Max 13 50 25 28 13 5 (Note 13) (Note 7) (Note 12) (Note 12) (Note 12,13) (Note 12,13) 5 5 13 13 13 13 5 5 5 15 15 15 15 Min Max 15 60 30 33 15
Unit
tCAC tRAC tAA tCPA tOEA tOHC tOHR tCLZ tOEZ tWEZ tOFF tREZ
Access time from CAS Access time from RAS Column address access time Access time from CAS precharge Access time from OE Output hold time from CAS Output hold time from RAS Output low impedance time from CAS low Output disable time after OE high Output disable time after W high Output disable time after CAS high Output disable time after RAS high
(Note 7,8) (Note 7,9) (Note 7,10) (Note 7,11) (Note 7)
ns ns ns ns ns ns ns ns ns ns ns ns
Note 6: An initial pause of 500s is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh or CAS before RAS refresh). Note the RAS may be cycled during the initial pause. And any eight initialization cycles are required after prolonged periods (greater than 64 ms) of RAS inactivity before proper device operation is achieved. 7: Measured with a load circuit equivalent to VOH=2.4V(IOH=-2mA) / VOL=0.4V(IOL=2mA) loads and 100pF. The reference levels for measuring of output signals are VOH=2.0V and VOL=0.8V. 8: Assumes that tRCD tRCD(max) and tASC tASC(max) and tCP tCP(max). 9: Assumes that tRCD tRCD(max) and tRAD tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC will increase by amount that tRCD exceeds the value shown. 10: Assumes that tRAD tRAD(max) and tASC tASC(max). 11: Assumes that tCP tCP(max) and tASC tASC(max). 12: tOEZ(max), tWEZ(max), tOFF(max) and tREZ(max) defines the time at which the output achieves the high impedance state (IOUT 10 A) and is not reference to VOH(min) or VOL(max). 13: Output is disabled after both RAS and CAS go to high.
9
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S M5M467805/465805DJ,DTP -5,-6,-5S,-6S M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write ,Refresh, and EDO Mode Cycles)
(Ta=0 ~ 70 C , Vcc=3.3 0.3V, Vss=0V, unless otherwise noted See notes 14,15) Limits M5M46X405D-5,5S M5M46X405D-6,6S M5M46X805D-5,5S M5M46X805D-6,6S M5M465165D-5,5S M5M465165D-6,6S Min tREF tREF tRP tRCD tCRP tRPC tCPN tRAD tASR tASC tRAH tCAH tDZC tDZO tRDD tCDD tODD tWED tT Refresh cycle time Refresh cycle time (S-version only) RAS high pulse width Delay time, RAS low to CAS low Delay time, CAS high to RAS low Delay time, RAS high to CAS low CAS high pulse width
Column address delay time from RAS low
Symbol
Parameter
Unit
Max 64 128
Min
Max 64 128 ms ms ns 45 ns ns ns ns 30 13 ns ns ns ns ns ns ns ns ns ns 50 ns ns
30 (Note16) 14 5 0 8 (Note17) (Note18) 10 0 0 8 8 (Note19) (Note19) (Note20) (Note20) (Note20) (Note20) (Note21) 0 0 13 13 13 13 1 50 10 25 37
40 14 5 0 10 12 0 0 10 10 0 0 15 15 15 15 1
Row address setup time before RAS low
Column address setup time before CAS low
Row address hold time after RAS low Column address hold time after CAS low Delay time, data to CAS low Delay time, data to OE low Delay time, RAS high to data Delay time, CAS high to data Delay time, OE high to data Delay time, W low to data Transition time
Note 14: The timing requirements are assumed tT =2ns. 15: VIH(min) and VIL(max) are reference levels for measuring timing of input signals. 16: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access time is controlled exclusively by tCAC or tAA. 17: tRAD(max) is specified as a reference point only. If tRAD tRAD(max) and tASC tASC(max), access time is controlled exclusively by tAA. 18: tASC(max) is specified as a reference point only. If tRCD tRCD(max) and tASC tASC(max), access time is controlled exclusively by tCAC. 19: Either tDZC or tDZO must be satisfied. 20: Either tRDD or tCDD or tODD or tWED must be satisfied. 21: tT is measured between VIH(min) and VIL(max).
Read and Refresh Cycles
Symbol Parameter Limits M5M46X405D-5,5S M5M46X405D-6,6S M5M46X805D-5,5S M5M46X805D-6,6S M5M465165D-5,5S M5M465165D-6,6S Min tRC tRAS tCAS tCSH tRSH tRCS tRCH tRRH tRAL tCAL tORH tOCH Read cycle time RAS low pulse width CAS low pulse width CAS hold time after RAS low RAS hold time after CAS low Read Setup time before CAS low Read hold time after CAS high Read hold time after RAS high Column address to RAS hold time Column address to CAS hold time RAS hold time after OE low CAS hold time after OE low (Note 22) (Note 22) 84 50 8 35 13 0 0 0 25 13 13 13 10000 10000 Max Min 104 60 10 40 15 0 0 0 30 18 15 15 10000 10000 Max ns ns ns ns ns ns ns ns ns ns ns ns Unit
Note 22: Either tRCH or tRRH must be satisfied for a read cycle.
10
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S M5M467805/465805DJ,DTP -5,-6,-5S,-6S M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Write Cycle (Early Write and Delayed Write)
Limits Symbol Parameter M5M46X405D-5,5S M5M46X405D-6,6S M5M46X805D-5,5S M5M46X805D-6,6S M5M465165D-5,5S M5M465165D-6,6S Min tWC tRAS tCAS tCSH tRSH tWCS tWCH tCWL tRWL tWP tDS tDH Write cycle time RAS low pulse width CAS low pulse width CAS hold time after RAS low RAS hold time after CAS low Write setup time before CAS low Write hold time after CAS low CAS hold time after W low RAS hold time after W low Write pulse width Data setup time before CAS low or W low Data hold time after CAS low or W low (Note 24) 84 50 8 35 13 0 8 8 8 8 0 8 10000 10000 Max Min 104 60 10 40 15 0 10 10 10 10 0 10 10000 10000 Max ns ns ns ns ns ns ns ns ns ns ns ns Unit
Read-Write and Read-Modify-Write Cycles
Limits Symbol Parameter M5M46X405D-5,5S M5M46X405D-6,6S M5M46X805D-5,5S M5M46X805D-6,6S M5M465165D-5,5S M5M465165D-6,6S Min tRWC tRAS tCAS tCSH tRSH tRCS tCWD tRWD tAWD tOEH Read write/read modify write cycle time RAS low pulse width CAS low pulse width CAS hold time after RAS low RAS hold time after CAS low Read setup time before CAS low Delay time, CAS low to W low Delay time, RAS low to W low Delay time, address to W low OE hold time after W low (Note24) (Note24) (Note24) (Note23) 109 75 38 70 38 0 28 65 40 13 10000 10000 Max Min 133 89 44 82 44 0 32 77 47 15 10000 10000 Max ns ns ns ns ns ns ns ns ns ns Unit
Note 23: tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT. 24: tWCS, tCWD, tRWD and tAWD and, tCPWD are specified as reference points only. If tWCS tWCS(min) the cycle is an early write cycle and the DQ pins will remain high impedance throughout the entire cycle. If tCWD tCWD(min), tRWD tRWD (min), tAWD tAWD(min) and tCPWD tCPWD(min) (for EDO mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address. If neither of the above condition (delayed write) is satisfied, the DQ (at access time and until CAS or OE goes back to VIH ) is indeterminate.
11
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S M5M467805/465805DJ,DTP -5,-6,-5S,-6S M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Cycle (Read, Early Write, Read-Write, Read-Modify-Write Cycle, Read Write Mix Cycle, Hi-Z control by OE or W)
Limits Symbol Parameter M5M46X405D-5,5S M5M46X405D-6,6S M5M46X805D-5,5S M5M46X805D-6,6S M5M465165D-5,5S M5M465165D-6,6S Min tHPC tHPRWC tDOH tRAS tCP tCPRH tCPWD tCHOL tOEPE tWPE tHCWD tHAWD tHPWD tHCOD tHAOD tHPOD EDO mode read/write cycle time EDO Mode read write / read modify write cycle time Output hold time from CAS low RAS low pulse width for read write cycle CAS high pulse width RAS hold time after CAS precharge (Note24) Delay time, CAS precharge to W low Hold time to maintain the data Hi-Z until CAS access OE Pulse Width (Hi-Z control) W Pulse Width (Hi-Z control) Delay time, CAS low to W low after read Delay time, Address to W low after read Delay time, CAS precharge to W low after read Delay time, CAS low to OE high after read Delay time, Address to OE high after read Delay time, CAS precharge to OE high after read (Note26) (Note27) 20 55 5 65 8 28 43 7 7 7 28 40 43 13 25 28 100000 13 Max Min 25 66 5 77 10 33 50 7 7 7 32 47 50 15 30 33 100000 16 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
(Note 25)
Note 25: All previously specified timing requirements and switching characteristics are applicable to their respective EDO mode cycle. 26: tRAS(min) is specified as two cycles of CAS input are performed. 27: tCP(max) is specified as a reference point only. If tCP tCP(max) , access time is controlled exclusively by tCAC.
CAS before RAS Refresh Cycle
(Note 28) Limits M5M46X405D-5,5S M5M46X405D-6,6S M5M46X805D-5,5S M5M46X805D-6,6S Unit M5M465165D-5,5S M5M465165D-6,6S Min Max Min 5 10 10 10 Max ns ns ns ns 5 10 10 10
Symbol
Parameter
tCSR tCHR tRSR tRHR
CAS setup time before RAS low CAS hold time after RAS low Read setup time before RAS low Read hold time after RAS low
Note 28: Eight or more CAS before RAS cycles instead of eight RAS cycles are necessary for proper operation of CAS before RAS refresh mode.
12
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S M5M467805/465805DJ,DTP -5,-6,-5S,-6S M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
SELF REFRESH SPECIFICATIONS
Self refresh devices are denoted by "S" after speed item, like -5S / -6S . The other characteristics and requirements than the below are same as normal devices.
ELECTRICAL CHARACTERISTICS
Symbol Parameter
(Ta=0 ~ 70 C , Vcc=3.3V
0.3V, Vss=0V, unless
otherwise noted) (Note 2) Limits Typ Unit
Test conditions
CAS before RAS refresh cycling input high level Vcc-0.2V input low level 0.2V output = OPEN , tRC = 31.25s tRAS = tRAS(min) ~ 300ns
Min
Max
ICC8 (AV)
Average supply current M5M46X405D-5S,6S from Vcc M5M46X805D-5S,6S Extended - Refresh cycle M5M465165D-5S,6S (note 5,6) Average supply current from Vcc Self - Refresh cycle (note 6)
500
A
ICC9 (AV)
M5M46X405D-5S,6S M5M46X805D-5S,6S M5M465165D-5S,6S
RAS = CAS
0.2V
output = OPEN
400
A
TIMING REQUIREMENTS
(Ta=0 ~ 70 C , Vcc=3.3V
0.3V, Vss=0V, unless
Limits
otherwise noted See notes 14,15)
Symbol
Parameter
M5M46X405D-5S M5M46X405D-6S M5M46X805D-5S M5M46X805D-6S M5M465165D-5S M5M465165D-6S Min Max Min 100 104 - 50 Max 100 84 - 50
Unit
tRASS tRPS tCHS
Self Refresh RAS low pulse width Self Refresh RAS high precharge time Self Refresh CAS hold time
S
ns ns
SELF REFRESH ENTRY & EXIT CONDITIONS
(1) In case of CBR distributed refresh The last / first full refresh cycles must be made within on the condition of tNS 128 ms and tSN 128 ms. tNS
Self refresh period
DISTRIBUTED REFRESH < 128 ms > DISTRIBUTED REFRESH < 128 ms >
tNS / tSN before / after self refresh ,
tSN
(2) In case of burst refresh The last / first full refresh cycles must be made within tNS / tSN before / after self refresh , on the condition of tNS 16 ms and tSN 16 ms. tNS
Self refresh period
BURST REFRESH < 128 ms > BURST REFRESH < 128 ms >
tSN
13
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S M5M467805/465805DJ,DTP -5,-6,-5S,-6S M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Timing Diagrams Read Cycle
(Note 29)
tRC tRAS VIH RAS VIL tCSH tCRP CAS VIH tRAL tCAL tASC tCAH tRCD tCAS tCPN tRAD tASR VIH tRAH tRSH tRPC tCRP tRP
LCAS / UCAS VIL
(at M5M465165Dxx only)
tASR
ROW ADDRESS
Address
VIL
ROW ADDRESS
COLUMN ADDRESS
tRCS VIH VIL tDZC
tRRH tRCH
W
tCDD tRDD
Hi-Z
DQ1 ~ DQ4 (8,16) VIH (INPUTS) VIL tCAC tAA tCLZ DQ1 ~ DQ4 (8,16) VOH (OUTPUTS) VOL
Hi-Z
tREZ
tWEZ tOFF tOHC tOHR
Hi-Z
DATA VALID
tRAC tDZO VIH VIL tOEA tOCH OE tORH tOEZ tODD
Note 29:
Indicates the don't care input. VIH(min) VIN VIH(max) or VIL(min)
VIN VIL(max)
Indicates the invalid output.
Indicates the skew of the two inputs. (at M5M465165Dxx only)
14
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S M5M467805/465805DJ,DTP -5,-6,-5S,-6S M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Write Cycle (Early Write)
tWC tRAS VIH RAS VIL tCSH tCRP VIH VIL tASR VIH tRAH
ROW ADDRESS
tRP
tRCD tCAS
tRSH
tRPC
tCRP
CAS LCAS / UCAS
(at M5M465165Dxx only)
tASC
tASR tCAH
COLUMN ADDRESS ROW ADDRESS
Address
VIL
tWCS W VIH VIL tDS
tWCH
tDH
DQ1 ~ DQ4 (8,16) (INPUTS)
VIH
DATA VALID
VIL
VOH DQ1 ~ DQ4 (8,16) (OUTPUTS) VOL
Hi-Z
OE
VIH VIL
15
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S M5M467805/465805DJ,DTP -5,-6,-5S,-6S M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Write Cycle (Delayed Write)
tWC tRAS VIH RAS VIL tCSH tCRP VIH tRCD tRSH tCAS tRPC tCRP tRP
CAS
LCAS / UCAS VIL
(at M5M465165Dxx only)
tASR VIH
tRAH
tASC
tCAH
tASR
ROW ADDRESS
Address
VIL
ROW ADDRESS
COLUMN ADDRESS
tCWL tRCS W VIH VIL tWCH tDZC VIH DQ1 ~ DQ4 (8,16) (INPUTS) VIL
Hi-Z
tRWL tWP
tDS
tDH
DATA VALID
tCLZ
DQ1 ~ DQ4 (8,16) VOH (OUTPUTS) VOL
Hi-Z
Hi-Z
tDZO VIH VIL
tOEZ tODD
tOEH
OE
16
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S M5M467805/465805DJ,DTP -5,-6,-5S,-6S M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Read-Write, Read-Modify-Write Cycle
tRWC tRAS VIH RAS VIL tCSH tCRP CAS VIH tRAD tASR tRAH tASC VIH tCAH tASR tRCD tRSH tCAS tRPC tCRP tRP
LCAS / UCAS VIL
(at M5M465165Dxx only)
Address
VIL
ROW ADDRESS
COLUMN ADDRESS
ROW ADDRESS
tRCS VIH W VIL
tAWD tCWD tRWD
tCWL tRWL tWP
tDZC DQ1 ~ DQ4 (8,16) (INPUTS) VIH VIL tAA tCLZ DQ1 ~ DQ4 (8,16) (OUTPUTS) VOH VOL tRAC tDZO VIH OE VIL tOEA tOEZ
Hi-Z DATA VALID Hi-Z
tDS
tDH
DATA VALID
tCAC
Hi-Z
tODD
tOEH
17
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S M5M467805/465805DJ,DTP -5,-6,-5S,-6S M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Read Cycle
tRAS VIH RAS VIL tCSH tCRP CAS VIH tRCD tCAS tCP tHPC tCAS tCP tRSH tCAS tRPC
tRP
tCRP
LCAS / UCAS VIL
(at M5M465165Dxx only)
tRAD tASR tRAH tASC tCAH
COLUMN ADDRESS-1
tCPRH tASC tCAH tASC tCAH tASR
VIH
Address
VIL
ROW ADDRESS
COLUMN ADDRESS-2
COLUMN ADDRESS-3
ROW ADDRESS
tRCS tCAL W VIH VIL tDZC VIH DQ1 ~ DQ4 (8,16) (INPUTS) VIL tAA tCLZ VOH DQ1 ~ DQ4 (8,16) (OUTPUTS) VOL
Hi-Z DATA VALID-1
tRAL tCAL tCAL
tRRH tRCH
tWEZ tRDD tCDD
Hi-Z
tCAC
tCAC tAA tDOH
DATA VALID-2
tCAC tAA tDOH
tREZ tOHR tOFF tOHC
DATA VALID-3
tRAC tDZO VIH VIL tOEA tOCH OE
tCPA
tCPA tOEZ
tODD
18
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S M5M467805/465805DJ,DTP -5,-6,-5S,-6S M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Write Cycle (Early Write)
tRAS VIH RAS VIL tCSH tCRP CAS VIH tRCD tCAS tCP tHPC tCAS tCP tRSH tCAS tRPC tCRP tRP
LCAS / UCAS VIL
(at M5M465165Dxx only)
tCAL tASR tRAH tASC tCAH
COLUMN ADDRESS-1
tCAL tASC tCAH
COLUMN ADDRESS-2
tCAL tASC tCAH
COLUMN ADDRESS-3
tASR
VIH
Address
VIL
ROW ADDRESS
ROW ADDRESS
tWCS VIH VIL tDS DQ1 ~ DQ4 (8,16) (INPUTS) VIH VIL
tWCH
tWCS
tWCH
tWCS
tWCH
W
tDH
tDS
tDH
tDS
tDH
DATA VALID-1
DATA VALID-2
DATA VALID-3
DQ1 ~ DQ4 (8,16) VOH (OUTPUTS) VOL
Hi-Z
OE
VIH VIL
19
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S M5M467805/465805DJ,DTP -5,-6,-5S,-6S M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Read-Write, Read-Modify-Write Cycle
tRAS VIH RAS VIL tCSH tCRP CAS VIH tRAD tASR VIH tRAH tASC tCAH tASC tCAH tCWL tASR
ROW ADDRESS
tRP
tRPC tRWL tCAS tCP tHPRWC tCAS tCRP
tRCD
LCAS / UCAS VIL
(at M5M465165Dxx only)
Address
VIL
ROW ADDRESS
COLUMN ADDRESS-1
COLUMN ADDRESS-2
tAWD tRCS VIH VIL tRWD tDZC tDS DQ1 ~ DQ4 (8,16) VIH (INPUTS) VIL tAA tCLZ DQ1 ~ DQ4 (8,16) VOH (OUTPUTS) VOL
Hi-Z
DATA VALID -1
tCWL tWP tRCS
tCWD
tAWD tCWD tWP
W
tCPWD tDH
DATA VALID-1
tDZC tDS
Hi-Z
tDH
DATA VALID-2
Hi-Z
tCAC tAA tCLZ
Hi-Z
tCAC
DATA VALID -2
Hi-Z
tRAC tDZO tOEA
tODD tOEZ tOEH
tCPA tDZO tOEA
tODD tOEH tOEZ
OE
VIH VIL
20
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S M5M467805/465805DJ,DTP -5,-6,-5S,-6S M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Mix Cycle (1)
(Note 30)
tRAS tRWL VIH RAS VIL tCSH tCRP CAS VIH tRAD tASR VIH tRAH tASC tCAH
COLUMN ADDRESS-1
tRP
tRPC tHPC tCAS tCP tCAS tCP tHPRWC tCAS tCWL tCRP
tRCD
(at M5M465165Dxx only)
LCAS / UCAS VIL tASC tCAH tASC tCAH tASR
Address
VIL
ROW ADDRESS
COLUMN ADDRESS-2
COLUMN ADDRESS-3
ROW ADDRESS
tRCS tCAL W VIH VIL tDZC
tWCS
tWCH tCAL
tCPWD tAWD tCWD tWP
tDS VIH DQ1 ~ DQ4 (8,16) (INPUTS) VIL
tDH
tDZC
tDS
tDH
tCAC tAA tCLZ
DATA VALID-2
tAA tCAC tCLZ
DATA VALID -3
DATA VALID-3
tWED tWEZ
DATA VALID -1
DQ1 ~ DQ4 (8,16) (OUTPUTS)
VOH VOL
Hi-Z
tRAC tDZO OE VIH VIL
tCPA tOEA tOCH tOEZ tDZO tOEA tOEZ tOEH
tODD
tODD
Note 30: OE=L; W Hi-Z control OE=H; OE Hi-Z control
21
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S M5M467805/465805DJ,DTP -5,-6,-5S,-6S M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Mix Cycle (2)
(Note 30)
VIH RAS VIL tHPC CAS LCAS / UCAS VIH VIL tCP tASC tCAS tCAH
COLUMN ADDRESS-1
(at M5M465165Dxx only)
tCAS tASC tCAH tASC tCAH
Address
VIH VIL
COLUMN ADDRESS-2
COLUMN ADDRESS-3
tCAL
tRCH tWCS
tCAL tWCH
VIH W VIL tHAWD tHPWD VIH VIL tHCWD tDH tDS
DATA VALID-2
tDZC
Hi-Z
DQ1 ~ DQ4 (8,16) (INPUTS)
Hi-Z
tCAC tAA tCPA tWED tWEZ
DATA VALID-1 Hi-Z
tCAC tAA tCPA tCLZ
DATA VALID-3
DQ1 ~ DQ4 (8,16) (OUTPUTS) VOL
VOH
VIH OE VIL
tHCOD tHAOD tHPOD
tOEZ tODD
tDZC
tOEA
Note 30: OE=L; W Hi-Z control OE=H; OE Hi-Z control
22
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S M5M467805/465805DJ,DTP -5,-6,-5S,-6S M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Read Cycle (Hi-Z control by OE)
tRAS VIH RAS VIL tCSH tCRP CAS VIH tRCD tCAS tCP tHPC tCAS tCP tRSH tCAS tRPC tCRP tRP
(at M5M465165Dxx only)
LCAS / UCAS VIL tASR VIH tRAD tRAH tASC tCAH tASC tCAH tCPRH tASC tCAH tASR
Address
VIL
ROW ADDRESS
COLUMN ADDRESS-1
COLUMN ADDRESS-2
COLUMN ADDRESS-3
ROW ADDRESS
tRAL tRCS W VIH VIL
tRRH tRCH
tWEZ tDZC VIH VIL tAA tCLZ DQ1 ~ DQ4 (8,16) VOH (OUTPUTS) VOL
Hi-Z DATA VALID-1
tRDD tCDD
Hi-Z
DQ1 ~ DQ4 (8,16) (INPUTS)
tCAC tAA
tCAC tAA
tCAC
tDOH
DATA VALID -1
tCLZ
DATA VALID-2 Hi-Z
tREZ tOHR tOFF tOHC
DATA VALID-3
tRAC tDZO tOEA
tOEZ tOCH tOEA
tCPA tCHOL
tCPA tOEZ tOEZ
OE
VIH VIL
tOEPE
tOEPE
tODD
23
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S M5M467805/465805DJ,DTP -5,-6,-5S,-6S M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Read Cycle (Hi-Z control by W)
tRAS VIH RAS VIL tCSH tCRP CAS VIH tRCD tCAS tCP tHPC tCAS tCP tRSH tCAS tRPC tCRP tRP
LCAS / UCAS VIL
(at M5M465165Dxx only)
tRAD tASR tRAH tASC tCAH
COLUMN ADDRESS-1
tASC
tCAH
tASC
tCPRH tCAH
tASR
ROW ADDRESS
Address
VIH VIL
ROW ADDRESS
COLUMN ADDRESS-2
COLUMN ADDRESS-3
tRAL tRCS W VIH VIL tDZC VIH VIL tAA tCLZ VOH DQ1 ~ DQ4 (8,16) (OUTPUTS) VOL
Hi-Z DATA VALID-1 Hi-Z
tRRH tRCH
tRCH tRCS
tWPE
tWEZ tRDD tCDD
DQ1 ~ DQ4 (8,16) (INPUTS)
tCAC
tCAC tAA tDOH tAA tWEZ
DATA VALID-2 Hi-Z
tCAC tCLZ
tREZ tOHR tOFF tOHC
DATA VALID-3
tRAC tDZO VIH OE VIL tOEA tOCH
tCPA
tCPA tOEZ
tODD
24
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S M5M467805/465805DJ,DTP -5,-6,-5S,-6S M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
RAS-only Refresh Cycle
tRC tRAS VIH RAS VIL tRPC tRP
tCRP CAS VIH
tCRP
LCAS / UCAS VIL (at M5M465165Dxx only) tASR tRAH tASR
VIH
Address
VIL
ROW ADDRESS
ROW ADDRESS
W
VIH VIL
VIH DQ1 ~ DQ4 (8,16) (INPUTS) VIL
VOH DQ1 ~ DQ4 (8,16) (OUTPUTS) VOL
Hi-Z
OE
VIH VIL
25
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S M5M467805/465805DJ,DTP -5,-6,-5S,-6S M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
CAS before RAS Refresh Cycle
tRC tRP VIH RAS VIL tRPC tCSR CAS VIH tCHR tRPC tCSR tCHR tRPC tRAS tRAS tRC tRP
tCRP
(at M5M465165Dxx only)
LCAS / UCAS VIL tCPN tASR VIH
Address
VIL tRRH tRCH tRSR W VIH VIL tRHR tRSR tRHR
ROW ADDRESS
COLUMN ADDRESS
tRCS
tCDD DQ1 ~ DQ4 (8,16) (INPUTS) VIL VIH tREZ tOHR tOFF tOHC
Hi-Z
DQ1 ~ DQ4 (8,16) (OUTPUTS)
VOH VOL tOEZ VIH
tODD
OE VIL
26
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S M5M467805/465805DJ,DTP -5,-6,-5S,-6S M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Hidden Refresh Cycle (Read)
(Note 31)
tRC tRAS VIH RAS VIL tRP tRAS
tRC tRP
tRPC tCRP VIH tRCD tRSH tCHR tCRP
CAS
LCAS / UCAS VIL
(at M5M465165Dxx only)
tRAD tASR tRAH
ROW ADDRESS
tASC
tCAH
COLUMN ADDRESS
tASR
Address
VIH VIL
ROW ADDRESS
tRCS tRAL W VIH VIL
tRRH tRSR
tRHR
tCDD tDZC VIH DQ1 ~ DQ4 (8,16) (INPUTS) VIL
Hi-Z
tRDD
tCAC tAA tCLZ
Hi-Z DATA VALID
tREZ tOHR tOFF tOHC
Hi-Z
DQ1 ~ DQ4 (8,16) (OUTPUTS)
VOH VOL
tRAC tDZO VIH VIL
tOEA tORH
tOEZ tODD
OE
Note 31: Early write, delayed write, read write, or read modify write cycle is applicable instead of read cycle. Timing requirements and output state are the same as that of each cycle shown above.
27
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S M5M467805/465805DJ,DTP -5,-6,-5S,-6S M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Self Refresh Cycle
tRP VIH RAS VIL tRPC tRPC tCSR CAS VIH tCHS tCRP tRASS tRPS
LCAS / UCAS VIL
(at M5M465165Dxx only)
tCPN tASR
Address
VIH VIL tRRH tRCH tRSR tRHR
ROW ADDRESS
W
VIH VIL
tCDD DQ1 ~ DQ4 (8,16) (INPUTS) VIH VIL tREZ tOHR tOFF tOHC
Hi-Z
VOH DQ1 ~ DQ4 (8,16) (OUTPUTS) VOL tOEZ OE VIH VIL
28
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S M5M467805/465805DJ,DTP -5,-6,-5S,-6S M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Upper / (Lower) Byte Read Cycle (at M5M465165Dxx only)
tRAS VIH VIL tCSH tCRP LCAS (or UCAS) VIH VIL tRPC tCAS UCAS (or LCAS) VIH VIL tRAD tASR VIH tRAH tASC tCAH tRAL tCAL tASR
ROW ADDRESS
tRC tRP
RAS
tRPC tRSH
tCRP
tRCD
tCPN
Address
VIL
ROW ADDRESS
COLUMN ADDRESS
tRRH tRCS VIH W VIL tRCH
DQ1 ~ DQ8 VIH (or DQ9 ~ DQ16) (INPUTS) VIL
DQ1 ~ DQ8 VOH (or DQ9 ~ DQ16) (OUTPUTS) VOL tDZC DQ9 ~ DQ16 VIH (or DQ1 ~ DQ8) (INPUTS) VIL tCAC tAA tCLZ VOH DQ9 ~ DQ16 (or DQ1 ~ DQ8) (OUTPUTS) VOL
Hi-Z
Hi-Z
tCDD tRDD
Hi-Z
tREZ tOHR tOFF tOHC
DATA VALID Hi-Z
tWEZ
tRAC tDZO tOEA tOCH
tOEZ tODD
VIH OE VIL tORH
29
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S M5M467805/465805DJ,DTP -5,-6,-5S,-6S M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Upper / (Lower) Byte Write Cycle (Early Write) (at M5M465165Dxx only)
tWC tRAS VIH VIL tCSH tCRP LCAS (or UCAS) VIH VIL tCAS UCAS (or LCAS) VIH VIL tASR VIH tRAH
ROW ADDRESS
tRP
RAS
tRCD
tRSH
tRPC
tCRP
tRPC
tCRP
tASC
tCAH
tASR
Address
VIL
COLUMN ADDRESS
ROW ADDRESS
tWCS VIH W VIL
tWCH
DQ1 ~ DQ8 VIH (or DQ9 ~ DQ16) (INPUTS) VIL
DQ1 ~ DQ8 VOH (or DQ9 ~ DQ16) (OUTPUTS) VOL tDS VIH DQ9 ~ DQ16 (or DQ1 ~ DQ8) (INPUTS) VIL tDH
Hi-Z
DATA VALID
VOH DQ9 ~ DQ16 (or DQ1 ~ DQ8) (OUTPUTS) VOL
Hi-Z
VIH OE VIL
30
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S M5M467805/465805DJ,DTP -5,-6,-5S,-6S M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Upper / (Lower) Byte Write Cycle (Delayed Write) (at M5M465165Dxx only)
tWC tRAS RAS VIH VIL tCSH tCRP LCAS (or UCAS) VIH VIL tRPC tCRP tCAS UCAS (or LCAS) VIH VIL tASR tRAH tCAH tASR
COLUMN ADDRESS ROW ADDRESS
tRP
tRPC tCRP tRSH
tRCD
tASC
VIH
Address
VIL
ROW ADDRESS
tCWL tRCS VIH W VIL tRWL tWP
DQ1 ~ DQ8 VIH (or DQ9 ~ DQ16) (INPUTS) VIL
VOH DQ1 ~ DQ8 (or DQ9 ~ DQ16) (OUTPUTS) VOL
Hi-Z
tWCH tDZC tDS
Hi-Z
tDH
DATA VALID
DQ9 ~ DQ16 (or DQ1 ~ DQ8) (INPUTS) VIL
VIH
tCLZ VOH DQ9 ~ DQ16 (or DQ1 ~ DQ8) (OUTPUTS) VOL
Hi-Z
Hi-Z
tDZO VIH OE VIL
tOEZ tODD
tOEH
31
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S M5M467805/465805DJ,DTP -5,-6,-5S,-6S M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Upper / (Lower) Byte Read-Write, Upper / (Lower) Byte Read-Modify-Write Cycle. (at M5M465165Dxx only)
tRWC tRAS RAS VIH VIL tCSH tCRP LCAS (or UCAS) VIH VIL tRPC tCAS UCAS (or LCAS) VIH VIL tRAD tASR tRAH tASC tCAH tASR tCRP tRCD tRSH tRPC tCRP tRP
VIH
Address
VIL
ROW ADDRESS
COLUMN ADDRESS
ROW ADDRESS
tRCS tRWD VIH W VIL
tAWD tCWD
tCWL tRWL tWP
DQ1 ~ DQ8 VIH (or DQ9 ~ DQ16) (INPUTS) VIL
VOH DQ1 ~ DQ8 (or DQ9 ~ DQ16) (OUTPUTS) VOL tDZC VIH DQ9 ~ DQ16 (or DQ1 ~ DQ8) (INPUTS) VIL
Hi-Z
Hi-Z
tDS
tDH
DATA VALID
tCAC tAA tCLZ
DQ9 ~ DQ16 VOH (or DQ1 ~ DQ8) (OUTPUTS) VOL
Hi-Z
DATA VALID
Hi-Z
tRAC tDZO VIH OE VIL tOEA tOEZ
tODD
tOEH
32
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S M5M467805/465805DJ,DTP -5,-6,-5S,-6S M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Byte Read Cycle (at M5M465165Dxx only)
RAS VIH VIL tCSH tCRP LCAS (or UCAS) VIH VIL tRPC tCAS UCAS (or LCAS) VIH VIL tRAD tASR VIH tRAH tASC tCAH
COLUMN ADDRESS-1
tRAS
tRP
tHPC tCP tCAS tCP
tRSH tRPC tCRP
tRCD
tCRP
tCAS
tCPRH tASC tCAH tASC tCAH tASR
Address
VIL
ROW ADDRESS
COLUMN ADDRESS-2
COLUMN ADDRESS-3
ROW ADDRESS
tRCS tCAL W VIH VIL tDZC tCAL
tRAL tCAL
tRRH tRCH
DQ1 ~ DQ8 VIH (or DQ9 ~ DQ16) (INPUTS) VIL tCAC tAA DQ1 ~ DQ8 VOH (or DQ9 ~ DQ16) (OUTPUTS) VOL
Hi-Z
Hi-Z
tREZ tOHR
DATA VALID-2
tCLZ tDZC VIH DQ9 ~ DQ16 (or DQ1 ~ DQ8) (INPUTS) VIL tCPA tRDD tCDD
Hi-Z
tCAC tAA tCLZ
tCAC tAA tDOH
DATA VALID-1
tWEZ tOFF tOHC
DATA VALID-3
DQ9 ~ DQ16 VOH (or DQ1 ~ DQ8) (OUTPUTS) VOL
Hi-Z
tRAC tDZO VIH VIL tOEA tOCH OE
tCPA
tODD tOEZ
33
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S M5M467805/465805DJ,DTP -5,-6,-5S,-6S M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Byte Write Cycle (Early Write) (at M5M465165Dxx only)
tRAS RAS VIH VIL tCSH tCRP LCAS (or UCAS) VIH VIL tRPC tRCD VIH VIL tCAL tASR VIH tRAH
ROW ADDRESS
tRP
tHPC
tRSH tRPC tCRP
tCAS
tCP
tCAS
tCP
tCAS
tCRP
UCAS (or LCAS)
tCAL tASC tCAH
COLUMN ADDRESS-2
tCAL tASC tCAH
COLUMN ADDRESS-3
tASC
tCAH
COLUMN ADDRESS-1
tASR
Address
VIL
ROW ADDRESS
tWCS VIH W VIL
tWCH
tWCS
tWCH
tWCS
tWCH
tDS VIH DQ1 ~ DQ8 (or DQ9 ~ DQ16) (INPUTS) VIL
tDH
DATA VALID-2
VOH DQ1 ~ DQ8 (or DQ9 ~ DQ16) (OUTPUTS) VOL tDS VIH DQ9 ~ DQ16 (or DQ1 ~ DQ8) (INPUTS) VIL tDH
Hi-Z
tDS
tDH
DATA VALID-1
DATA VALID-3
DQ9 ~ DQ16 VOH (or DQ1 ~ DQ8) (OUTPUTS) VOL
Hi-Z
VIH OE VIL
34
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S M5M467805/465805DJ,DTP -5,-6,-5S,-6S M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Upper/(Lower) Byte Read-Write, Upper/(Lower) Byte Read-Modify-Write Cycle (at M5M465165Dxx only)
tRAS RAS VIH VIL tCSH tCRP tRWL tCRP LCAS (or UCAS) VIH VIL tRPC tRCD UCAS (or LCAS) VIH VIL tASR VIH tRAD tRAH tCAH tASC tCAH tCWL tCAS tHPRWC tCP tCAS tCRP tRPC tRP
tASC
tASR
ROW ADDRESS
Address
VIL
ROW ADDRESS
COLUMN ADDRESS-1
COLUMN ADDRESS-2
tRCS W VIH VIL
tAWD tCWD
tAWD tCWL tWP tRCS tCWD tWP
tRWD DQ1 ~ DQ8 VIH (or DQ9 ~ DQ16) (INPUTS) VIL
tCPWD
DQ1 ~ DQ8 VOH (or DQ9 ~ DQ16) (OUTPUTS) VOL tDZC DQ9 ~ DQ16 VIH (or DQ1 ~ DQ8) (INPUTS) VIL
Hi-Z
Hi-Z
tDS
tDH
DATA VALID-1
tDZC
Hi-Z
tDS
tDH
DATA VALID-2
tCAC tAA tCLZ
tCAC tAA tCLZ
DATA VALID -1
VOH DQ9 ~ DQ16 (or DQ1 ~ DQ8) (OUTPUTS) VOL
Hi-Z
Hi-Z
DATA VALID -2
Hi-Z
tRAC tDZO VIH OE VIL tOEA
tODD tOEZ tOEH
tCPA tDZO tOEA
tODD tOEH tOEZ
35
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S M5M467805/465805DJ,DTP -5,-6,-5S,-6S M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Upper / (Lower) CAS before RAS Refresh Cycle (at M5M465165Dxx only)
tRP VIH RAS VIL tRPC LCAS (or UCAS) VIH VIL tRPC tRPC UCAS (or LCAS) VIH VIL tCPN tASR VIH
ROW ADDRESS
tRC tRAS tRAS
tRC tRP
tCRP
tRPC
tCRP
tRPC
tCRP
tCRP
tCSR tCHR
tRPC
tCSR tCHR
Address
VIL tRCH tRSR tRHR tRSR tRHR
tRCS
W
VIH VIL
DQ1 ~ DQ8 VIH (or DQ9 ~ DQ16) (INPUTS) VIL tOFF tOHC tREZ tOHR
Hi-Z
A @ A @ A @ A @
VOH DQ1 ~ DQ8 (or DQ9 ~ DQ16) (OUTPUTS) VOL tOEZ
tCDD VIH DQ9 ~ DQ16 (or DQ1 ~ DQ8) (INPUTS) VIL tOFF
DQ9 ~ DQ16 VOH (or DQ1 ~ DQ8) (OUTPUTS) VOL tOEZ
Hi-Z
tODD VIH OE VIL
36
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S M5M467805/465805DJ,DTP -5,-6,-5S,-6S M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Upper / (Lower) Hidden Refresh Cycle (Byte Read) (at M5M465165Dxx only)
tRC tRAS VIH RAS tRPC VIL tRPC tCRP LCAS (or UCAS) VIH VIL tCRP tCRP UCAS (or LCAS) VIH VIL tRAD tASR VIH tRAH tASC tCAH
COLUMN ADDRESS (Note 31)
tRC tRP tRAS tRP
tRCD
tRSH
tCRP
tCHR
tASR
ROW ADDRESS
Address
VIL
ROW ADDRESS
tRCS VIH W VIL
tRAL
tRRH
tRSR
tRHR
DQ1 ~ DQ8 VIH (or DQ9 ~ DQ16) (INPUTS) VIL
A @ A @ A @ A @
Hi-Z
DQ1 ~ DQ8 VOH (or DQ9 ~ DQ16) (OUTPUTS) VOL tDZC DQ9 ~ DQ16 (or DQ1 ~ DQ8) (INPUTS) VIH VIL tCLZ DQ9 ~ DQ16 VOH (or DQ1 ~ DQ8) (OUTPUTS) VOL
Hi-Z
tCDD
Hi-Z
tCAC
tOFF tREZ tOFF tOHC tOHR
DATA VALID
tAA tRAC tDZO VIH OE VIL tOEA tORH tOEZ tODD
37
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S M5M467805/465805DJ,DTP -5,-6,-5S,-6S M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Byte Self Refresh Cycle (at M5M465165Dxx only)
tRP VIH RAS VIL tCRP tRASS tRPS
tRPC LCAS (or UCAS) VIH VIL
tRPC
tCRP
tRPC tRPC UCAS (or LCAS) VIH VIL tCPN tASR VIH
ROW ADDRESS
tCSR
tCHS
tCRP
Address
VIL tRCH tRSR tRHR
W
VIH VIL A @ A @ A @ A @
Hi-Z
DQ1 ~ DQ8 VIH (or DQ9 ~ DQ16) (INPUTS) VIL tOFF tOHC tREZ tOHR
VOH DQ1 ~ DQ8 (or DQ9 ~ DQ16) (OUTPUTS) VOL tOEZ
tCDD DQ9 ~ DQ16 VIH (or DQ1 ~ DQ8) (INPUTS) VIL tOFF
DQ9 ~ DQ16 VOH (or DQ1 ~ DQ8) (OUTPUTS) VOL tOEZ
Hi-Z
tODD VIH OE VIL
38
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S M5M467805/465805DJ,DTP -5,-6,-5S,-6S M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Keep safety first in your circuit designs!
* Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable,but there is always the possibility that trouble may occur with them. Trouble with semiconductors consideration to safety when making your circuit designs,with appropriate measures such as (i) placement of substitutive, auxiliary circuits,(ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
*These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application;they do not convey any license under any intellectual property rights,or any other rights,belonging to Mitsubishi Electric Corporation or a third party. *Mitsubishi Electric Corporation assumes no responsibility for any damage,or infringement of any third-party's rights,originating in the use of any product data,diagrams,charts or circuit application examples contained in these materials. * All information contained in these materials,including product data,diagrams and charts, represent information on products at the time of publication of these materials,and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. * Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for special applications,such as apparatus or systems for transportation,vehicular, medical,aerospace,nuclear,or undersea repeater use. *The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. *If these products or technologies are subject the Japanese export control restrictions,they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. *Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
39 Aug. 1999
MITSUBISHI ELECTRIC

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