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W29C040 512K x 8 CMOS FLASH MEMORY
GENERAL DESCRIPTION
The W29C040 is a 4-megabit, 5-volt only CMOS page mode Flash Memory organized as 512K x 8 bits. The device can be written (erased and programmed) in-system with a standard 5V power supply. A 12-volt VPP is not required. The unique cell architecture of the W29C040 results in fast write (erase/ program) operations with extremely low current consumption (compared to other comparable 5-volt flash memory products.) The device can also be erased and programmed by using standard EPROM programmers.
FEATURES
* *
Single 5-volt write (erase and program) operations Fast page-write operations - 256 bytes per page - Page write (erase/program) cycle: 5 mS (typ.) - Effective byte-write (erase/program) cycle time: 19.5 S - Optional software-protected data write
* *
Software and hardware data protection Low power consumption - Active current: 25 mA (typ.) - Standby current: 20 A (typ.)
* *
Automatic write (erase/program) timing with internal VPP generation End of write (erase/program) detection - Toggle bit - Data polling
* * * * *
Fast chip-erase operation: 50 mS Two 16 KB boot blocks with lockout Page write (erase/program) cycles: 50K (typ.) Read access time: 70/90/120 nS Ten-year data retention
* * * *
Latched address and data All inputs and outputs directly TTL compatible JEDEC standard byte-wide pinouts Available packages: 32-pin 600 mil DIP, TSOP and PLCC
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Publication Release Date: May 6, 2002 Revision A9
W29C040
PIN CONFIGURATIONS
A18 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27
BLOCK DIAGRAM
VDD #WE A17 A14 A13 A8 A9 A11 #OE A10 #CE DQ7 DQ6 DQ5 DQ4 DQ3
VDD VSS #CE #OE #WE CONTROL OUTPUT BUFFER DQ0 . . DQ7
32-pin DIP
26 25 24 23 22 21 20 19 18 17
A0 . . . A18 DECODER
16K Byte Boot Block (Optional)
A 1 2 4 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 5 6 7 8 9 10 11 12 13
A 1 5 3
AA 11 68 2 1
V D D
# W E
A 1 7
CORE ARRAY
16K Byte Boot Block (Optional)
32 31 30 29 28 27 A14 A13 A8 A9 A11 #OE A10 #CE DQ7
32-pin PLCC
26 25 24 23 22 21
14 15 16 17 18 19 20
PIN DESCRIPTION
SYMBOL
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
D Q 1
D Q 2
V s s
D Q 3
D Q 4
D Q 5
D Q 6
PIN NAME Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Power Supply Ground
A11 A9 A8 A13 A14 A17 #WE VDD A18 A16 A15 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
#OE A10 #CE DQ7 DQ6 DQ5 DQ4 DQ3 Vss DQ2 DQ1 DQ0 A0 A1 A2 A3
A0 - A18 DQ0 - DQ7 #CE #OE #WE VDD VSS
32-pin TSOP
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W29C040
FUNCTIONAL DESCRIPTION
Read Mode
The read operation of the W29C040 is controlled by #CE and #OE, both Chip of which have to be low for the host to obtain data from the outputs. #CE is used for device selection. When #CE is high, the chip is de-selected and only standby power will be consumed. #OE is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either #CE or #OE is high. Refer to the read cycle timing waveforms for further details.
Page Write Mode
The W29C040 is written (erased/programmed) on a page basis. Every page contains 256 bytes of data. If a byte of data within a page is to be changed, data for the entire page must be loaded into the device. Any byte that is not loaded will be erased to "FF hex" during the write operation of the page. The write operation is initiated by forcing #CE and #WE low and #OE high. The write procedure consists of two steps. Step 1 is the byte-load cycle, in which the host writes to the page buffer of the device. Step 2 is an internal write (erase/program) cycle, during which the data in the page buffers are simultaneously written into the memory array for non-volatile storage. During the byte-load cycle, the addresses are latched by the falling edge of either #CE or #WE, whichever occurs last. The data are latched by the rising edge of either #CE or #WE, whichever occurs first. If the host loads a second byte into the page buffer within a byte-load cycle time (TBLC) of 200 S after the initial byte-load cycle, the W29C040 will stay in the page load cycle. Additional bytes can then be loaded consecutively. The page load cycle will be terminated and the internal write (erase/program) cycle will start if no additional byte is loaded into the page buffer. A8 to A18 specify the page address. All bytes that are loaded into the page buffer must have the same page address. A0 to A7 specify the byte address within the page. The bytes may be loaded in any order; sequential loading is not required. In the internal write cycle, all data in the page buffers, i.e., 256 bytes of data, are written simultaneously into the memory array. The typical write (erase/program) time is 5 mS. The entire memory array can be written in 10.4 seconds. Before the completion of the internal write cycle, the host is free to perform other tasks such as fetching data from other locations in the system to prepare to write the next page.
Software-protected Data Write
The device provides a JEDEC-approved optional software-protected data write. Once this scheme is enabled, any write operation requires a three-byte command sequence (with specific data to a specific address) to be performed before the data load operation. The three-byte load command sequence begins the page load cycle, without which the write operation will not be activated. This write scheme provides optimal protection against inadvertent write cycles, such as cycles triggered by noise during system power-up and power-down. The W29C040 is shipped with the software data protection enabled. To enable the software data protection scheme, perform the three-byte command cycle at the beginning of a page load cycle. The device will then enter the software data protection mode, and any subsequent write operation must be preceded by the three-byte command sequence cycle. Once enabled, the software data protection will remain enabled unless the disable commands are issued. A power transition will not reset the software data protection feature. To reset the device to unprotected mode, a six-byte command sequence is
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Publication Release Date: May 6, 2002 Revision A9
W29C040
required. For information about specific codes, see the Command Codes for Software Data Protection in the Table of Operating Modes. For information about timing waveforms, see the timing diagrams below.
Hardware Data Protection
The integrity of the data stored in the W29C040 is also hardware protected in the following ways: (1) Noise/Glitch Protection: A #WE pulse of less than 15 nS in duration will not initiate a write cycle. (2) VDD Power Up/Down Detection: The write and read operation are inhibited when VDD is less than 2.5V. (3) Write Inhibit Mode: Forcing #OE low, #CE high, or #WE high will inhibit the write operation. This prevents inadvertent writes during power-up or power-down periods. (4) VDD power-on delay: When VDD has reach its sense level, the device will automatically time-out 10 mS before any write (erase/program) operation.
Chip Erase Modes
The entire device can be erased by using a six-byte software command code. See the Software Chip Erase Timing Diagram.
Boot Block Operation
There are two boot blocks (16K bytes each) in this device, which can be used to store boot code. One of them is located in the first 16K bytes and the other is located in the last 16K bytes of the memory. The first 16K or last 16K of the memory can be set as a boot block by using a seven-byte command sequence. See Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set the data for the designated block cannot be erased or programmed (programming lockout); a regular programming method can change other memory locations. Once the boot block programming lockout feature is activated, the chip erase function will be disabled. In order to detect whether the boot block feature is set on the two 16K blocks, users can perform a six-byte command sequence: enter the product identification mode (see Command Codes for Identification/Boot Block Lockout Detection for specific code), and then read from address "00002 hex" (for the first 16K bytes) or "7FFF2 hex" (for the last 16K bytes). If the output data is "FF hex," the boot block programming lockout feature is activated; if the output data is "FE hex," the lockout feature is inactivated and the block can be programmed. To return to normal operation, perform a three-byte command sequence to exit the identification mode. For the specific code, see Command Codes for Identification/Boot Block Lockout Detection.
Data Polling (DQ7)- Write Status Detection
The W29C040 includes a data polling feature to indicate the end of a write cycle. When the W29C040 is in the internal write cycle, any attempt to read DQ7 of the last byte loaded during the page/byte-load cycle will receive the complement of the true data. Once the write cycle is completed. DQ7 will show the true data. See the #DATA Polling Timing Diagram.
Toggle Bit (DQ6)- Write Status Detection
In addition to data polling, the W29C040 provides another method for determining the end of a write cycle. During the internal write cycle, any consecutive attempts to read DQ6 will produce alternating 0's -4-
W29C040
and 1's. When the write cycle is completed, this toggling between 0's and 1's will stop. The device is then ready for the next operation. See Toggle Bit Timing Diagram.
Product Identification
The product ID operation outputs the manufacturer code and device code. Programming equipment automatically matches the device with its proper erase and programming algorithms. The manufacturer and device codes can be accessed by software or hardware operation. In the software access mode, a six-byte command sequence can be used to access the product ID. A read from address "00000 hex" outputs the manufacturer code "DA hex." A read from address "00001 hex" outputs the device code "46 hex." The product ID operation can be terminated by a three-byte command sequence. In the hardware access mode, access to the product ID is activated by forcing #CE and #OE low, #WE high, and raising A9 to 12 volts.
Note: The hardware SID read function is not included in all parts; please refer to Ordering Information for details.
TABLE OF OPERATING MODES
Operating Mode Selection
Operating Range: 0 to 70 C for normal products, -40 to 85 C for W29C040xxxxK, VDD = 5V 10 %, VSS = 0V, VHH = 12V
MODE #CE Read Write Standby Write Inhibit Output Disable Product ID VIL VIL VIH X X X VIL VIL #OE VIL VIH X VIL X VIH VIL VIL #WE VIH VIL X X VIH X VIH VIH AIN AIN X X X X
PINS ADDRESS Dout Din High Z High Z/DOUT High Z/DOUT High Z Manufacturer Code DA (Hex) DQ.
A0 = VIL; A1 - A18 = VIL; A9 = VHH
A0 = VIH; A1 - A18 = VIL; Device Code 46 (Hex) A9 = VHH
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Publication Release Date: May 6, 2002 Revision A9
W29C040
Command Codes for Software Data Protection
BYTE SEQUENCE 0 Write 1 Write 2 Write 3 Write 4 Write 5 Write TO ENABLE PROTECTION ADDRESS 5555H 2AAAH 5555H DATA AAH 55H A0H TO DISABLE PROTECTION ADDRESS 5555H 2AAAH 5555H 5555H 2AAAH 5555H DATA AAH 55H 80H AAH 55H 20H
Software Data Protection Acquisition Flow
Software Data Protection Enable Flow
Load data AA to address 5555
Software Data Protection Disable Flow
Load data AA to address 5555
Load data 55 to address 2AAA
Load data 55 to address 2AAA
Load data A0 to address 5555
Load data 80 to address 5555
(Optional page-load operation)
Sequentially load up to 256 bytes of page data
Load data AA to address 5555
W ait for 10 mS or toggle/polling completed
Load data 55 to address 2AAA
Exit
Load data 20 to address 5555
W ait for 10 mS
Exit
Notes for software program code: Data Format: DQ7 - DQ0 (Hex) Address Format: A14 - A0 (Hex)
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W29C040
Command Codes for Software Chip Erase
BYTE SEQUENCE 0 Write 1 Write 2 Write 3 Write 4 Write 5 Write ADDRESS 5555H 2AAAH 5555H 5555H 2AAAH 5555H DATA AAH 55H 80H AAH 55H 10H
Software Chip Erase Acquisition Flow
Load data AA to address 5555
Load data 55 to address 2AAA
Load data 80 to address 5555
Load data AA to address 5555
Load data 55 to address 2AAA
Load data 10 to address 5555
Wait for 50 mS or toggle/polling completed
Exit Notes for software chip erase: Data Format: DQ7 - DQ0 (Hex) Address Format: A14 - A0 (Hex)
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W29C040
Command Codes for Product Identification and Boot Block Lockout Detection
BYTE SEQUENCE ALTERNATE PRODUCT (7) IDENTIFICATION/BOOT BLOCK LOCKOUT DETECTION ENTRY ADDRESS 0 Write 1 Write 2 Write 3 Write 4 Write 5 Write 5555 2AAA 5555 Pause 10 S DATA AA 55 90 SOFTWARE PRODUCT IDENTIFICATION/BOOT BLOCK LOCKOUT DETECTION EXIT ADDRESS 5555H 2AAAH 5555H Pause 10 S DATA AAH 55H F0H -
Software Product Identification and Boot Block Lockout Detection Acquisition Flow
Product Identification Entry (1)
Load data AA to address 5555
Product Identification and Boot Block Lockout Detection Mode (3)
Product Identification Exit (1)
Load data 55 to address 2AAA
(2)
Read address = 00000 data = DA
Load data AA to address 5555
Load data 90 to address 5555
(2)
Read address = 00001 data = 46
Load data 55 to address 2AAA
(4)
Read address = 00002 data = FF/FE
Load data F0 to address 5555
(5)
Read address = 7FFF2 data = FF/FE
Pause 10 uS
(6) Normal Mode
Notes for software product identification/boot block lockout detection: (1) Data Format: DQ7 - DQ0 (Hex); Address Format: A14 - A0 (Hex) (2) A1 - A18 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH. (3) The device does not remain in identification and boot block (address 0002 Hex/7FFF2 Hex respond to first 16K/last 16K) lockout detection mode if power down. (4), (5) If the output data is "FF Hex," the boot block programming lockout feature is activated; if the output data "FE Hex," the lockout feature is inactivated and the block can be programmed. (6) The device returns to standard operation mode. (7) This product supports both the JEDEC standard 3 bytes command code sequence and original 6 byte command code sequence. For new designs, Winbond recommends that the 3 bytes command code sequence be used.
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W29C040
Command Codes for Boot Block Lockout Enable
BYTE SEQUENCE BOOT BLOCK LOCKOUT FEATURE SET ON FIRST 16K ADDRESS BOOT BLOCK ADDRESS 0 Write 1 Write 2 Write 3 Write 4 Write 5 Write 6 Write 5555H 2AAAH 5555H 5555H 2AAAH 5555H 00000H Pause 10 mS DATA AAH 55H 80H AAH 55H 40H 00H BOOT BLOCK LOCKOUT FEATURE SET ON LAST 16K ADDRESS BOOT BLOCK ADDRESS 5555H 2AAAH 5555H 5555H 2AAAH 5555H 7FFFFH Pause 10 mS DATA AAH 55H 80H AAH 55H 40H FFH
Boot Block Lockout Enable Acquisition Flow
Boot Block Lockout Feature Set on First 16K Address Boot Block
Load data AA to address 5555
Boot Block Lockout Feature Set on Last 16K Address Boot Block
Load data AA to address 5555
Load data 55 to address 2AAA
Load data 55 to address 2AAA
Load data 80 to address 5555
Load data 80 to address 5555
Load data AA to address 5555
Load data AA to address 5555
Load data 55 to address 2AAA
Load data 55 to address 2AAA
Load data 40 to address 5555
Load data 40 to address 5555
Load data 00 to address 00000
Load data FF to address 7FFFF
W ait for 10 m S
W ait for 10 m S
Notes for boot block lockout enable: 1. Data Format: DQ 7 - DQ0 (Hex) 2. Address Format: A14 - A0 (Hex) 3. If you have any questions about this command sequence, please contact the local distributor or Winbond Electronics Corp.
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W29C040
Data Polling Acquisition Flow
Data Polling
Byte Program Initiated
Read DQ7
No
Is DQ7= true data? Yes Write Completed
Data Toggle Acquisition Flow
Toggle Bit
Byte Program/ Sector Erase Initiated
Read byte
Read same byte
No Does DQ6 match? Yes Write Completed
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W29C040
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER Power Supply Voltage to VSS Potential Operating Temperature Storage Temperature D.C. Voltage on Any Pin to Ground Potential Except A9 Transient Voltage (<20 nS) on Any Pin to Ground Potential Voltage on A9 and #OE Pin to Ground Potential RATING -0.5 to +7.0 0 to +70 -65 to +150 -0.5 to VDD +1.0 -1.0 to VDD +1.0 -0.5 to 12.5 UNIT V C C V V V
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
Operating Characteristics
(VDD = 5.0V 10 %, VSS = 0V, TA = 0 to 70 C for normal products, -40 to 85 C for W29C040xxxxK )
PARAMETER
SYM.
TEST CONDITIONS MIN.
LIMITS TYP. MAX. 50
UNIT
Power Supply Current
ICC
#CE = #OE = VIL, #WE = VIH, all DQs open Address inputs = VIL/VIH, at f = 5 MHz
-
mA
Standby VDD Current (TTL input) Standby VDD Current (CMOS input) Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output High Voltage CMOS
ISB1 ISB2 ILI ILO VIL VIH VOL VOH1 VOH2
#CE = VIH, all DQs open Other inputs = VIL/VIH #CE = VDD -0.3V, all DQs open VIN = VSS to VDD VIN = VSS to VDD For PLCC and TSOP pkg For DIP pkg IOL = 2.0 mA IOH = -400 A IOH = -100 A; VDD = 4.5V
2.0 2.2 2.4 4.2
2 20 -
3 100 10 10 0.8 0.45 -
mA A A A V V V V V V
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W29C040
Power-up Timing
PARAMETER Power-up to Read Operation Power-up to Write Operation SYMBOL TPU. READ TPU. WRITE TYPICAL 100 10 UNIT S mS
CAPACITANCE
(VDD = 5.0V, TA = 25 C, f = 1 MHz)
PARAMETER DQ Pin Capacitance Input Pin Capacitance
SYMBOL CDQ CIN
CONDITIONS VDQ = 0V VIN = 0V
MAX. 12 6
UNIT pF pF
AC CHARACTERISTICS
AC Test Conditions
(VDD = 5.0V 10 % for 70, 90,120 nS)
PARAMETER Input Pulse Levels Input Rise/Fall Time Input/Output Timing Level Output Load 0V to 3V <5 nS 1.5V/1.5V
CONDITIONS
1 TTL Gate and CL = 100 pF for 90/120 nS CL = 30 pF for 70 nS
AC Test Load and Waveform
+5V
1.8K
DOUT
100 pF for 90/120nS 30 pF for 70nS (Including Jig and Scope)
1.3K
Input
3V 1.5V 0V Test Point
Output
1.5V
Test Point
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W29C040
AC Characteristics, continued
Read Cycle Timing Parameters
(VDD = 5.0V 10 % VSS = 0V, TA = 0 to 70 C for normal products, -40 to 85 C for W29C040xxxxK)
PARAMETER
SYM.
W29C040-70 MIN. MAX. 70 70 35 20 20 -
W29C040-90 MIN. 90 0 MAX. 90 90 40 25 25 -
W29C040-12 MIN. 120 0 MAX. 120 120 50 30 30 -
UNIT
Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time #CE High to High-Z Output #OE High to High-Z Output Output Hold from Address Change
TRC TCE TAA TOE TCHZ TOHZ TOH
70 0
nS nS nS nS nS nS nS
Byte/Page-write Cycle Timing Parameters
PARAMETER Write Cycle (erase and program) Address Setup Time Address Hold Time #WE and #CE Setup Time #WE and #CE Hold Time #OE High Setup Time #OE High Hold Time #CE Pulse Width #WE Pulse Width #WE High Width Data Setup Time Data Hold Time Byte Load Cycle Time SYM. TWC TAS TAH TCS TCH TOES TOEH TCP TWP TWPH TDS TDH TBLC MIN. 0 50 0 0 0 0 70 70 100 50 0 TYP. MAX. 10 200 UNIT mS nS nS nS nS nS nS nS nS nS nS nS S
Notes: All AC timing signals observe the following guideline for determining setup and hold times: (1) High level signal's reference level is VIH (2) Low level signal's reference level is VIL
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W29C040
AC Characteristics, continued
#DATA Polling Characteristics (1)
PARAMETER Data Hold Time #OE Hold Time #OE to Output Delay (2) Write Recovery Time SYMBOL TDH TOEH TOE TWR MIN. 10 10 0 TYP. MAX. UNIT nS nS nS nS
Notes: (1) These parameters are characterized and not 100% tested. (2) See TOE spec in A.C. Read Cycle Timing Parameters.
Toggle Bit Characteristics (1)
PARAMETER Data Hold Time #OE Hold Time #OE to Output Delay #OE High Pulse Write Recovery Time
(2)
SYMBOL TDH TOEH TOE TOEHP TWR
MIN. 10 10 150 0
TYP. -
MAX. -
UNIT nS nS nS nS nS
Notes: (1) These parameters are characterized and not 100% tested. (2) See TOE spec in A.C. Read Cycle Timing Parameters.
TIMING WAVEFORMS
Read Cycle Timing Diagram
TRC Address A18-0 #CE TCE
#OE
TOE
#WE
VIH
TOHZ
TOH DQ7-0 High-Z Data Valid TAA
T CHZ Data Valid
High-Z
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W29C040
Timing Waveforms, continued
#WE Controlled Write Cycle Timing Diagram
TWC TAS Address A18-0 TAH
TCS #CE TOES #OE TWP #WE TDS DQ7-0 Data Valid
TCH TOEH
TWPH
TDH Internal write starts
#CE Controlled Write Cycle Timing Diagram
TAS
TAH
TWC
Address A18-0 TWPH TCP #CE T OES #OE TCS TOEH TCH
#WE TDS DQ7-0 High Z Data Valid
TDH Internal Write Starts
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Timing Waveforms, continued
Page Write Cycle Timing Diagram
TWC Address A18-0
DQ7-0
#CE
#OE TWPH TBLC
TWP #WE Byte 0
Byte 1
Byte 2
Byte N-1 Internal Write Start
Byte N
#DATA Polling Timing Diagram
Address A18-0
#WE
#CE TOEH #OE TDH DQ7 TOE
HIGH-Z
TWR
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W29C040
Timing Waveforms, continued
Toggle Bit Timing Diagram
#WE
#CE #OE
TOEH TDH TOE
HIGH-Z
TWR
DQ6
Page Write Timing Diagram Software Data Protection Mode
Three-byte sequence for software data protection mode Address A18-0 5555 2AAA 5555
Byte/page load cycle starts
TWC
DQ7-0
AA
55
A0
#CE
#OE TWP #WE TWPH SW2 Byte 0 Byte N-1 Byte N (Last Byte) Internal write starts TBLC
SW0
SW1
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W29C040
Timing Waveforms, continued
Reset Software Data Protection Timing Diagram
Six-byte sequence for resetting software data protection mode Address A18-0 5555 2AAA 5555 5555 2AAA 5555
TWC
DQ7-0
AA
55
80
AA
55
20
#CE
#OE TWP #WE SW0 TWPH SW1 SW2 SW3 SW4 SW5 Internal programming starts TBLC
5 Volt-only Software Chip Erase Timing Diagram
Six-byte code for 5V-only software chip erase Address A18-0 5555 2AAA 5555 5555 2AAA 5555
TWC
DQ7-0
AA
55
80
AA
55
10
#CE
#OE TWP TWPH SW0 SW1 SW2 SW3 SW4 SW5 Internal erasing starts TBLC
#WE
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W29C040
ORDERING INFORMATION
PART NO. ACCESS TIME (nS) W29C040-90 W29C040-12 W29C040T-90 W29C040T-12 W29C040P-90 W29C040P-12 W29C040-90N W29C040-12N W29C040T-90N W29C040T-12N W29C040P-90N W29C040P-12N W29C040-90B W29C040T-70B W29C040T-90B W29C040P-70B W29C040P-90B W29C040-90BN W29C040T70BN W29C040T90BN W29C040P70BN W29C040P90BN W29C040P-70K W29C040P-90K 90 120 90 120 90 120 90 120 90 120 90 120 90 70 90 70 90 90 70 90 70 90 70 90 POWER OPERATING SUPPLY TEMP. CURRENT (C) MAX. (mA) 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 -40 to 85 -40 to 85 PACKAGE CYCLING (K) (MIN.) 600 mil DIP 600 mil DIP Type one TSOP Type one TSOP 32-pin PLCC 32-pin PLCC 600 mil DIP 600 mil DIP Type one TSOP Type one TSOP 32-pin PLCC 32-pin PLCC 600 mil DIP Type one TSOP Type one TSOP 32-pin PLCC 32-pin PLCC 600 mil DIP Type one TSOP Type one TSOP 32-pin PLCC 32-pin PLCC 32-pin PLCC 32-pin PLCC 1 1 1 1 1 1 1 1 1 1 1 1 10 10 10 10 10 10 10 10 10 10 10 10 Y Y Y Y Y Y N N N N N N Y Y Y Y Y N N N N N Y Y HARDWARE SID READ FUNCTION
W29C040T-70K W29C040T-90K
70 90
50 50
-40 to 85 -40 to 85
Type one TSOP Type one TSOP
10 10
Y Y
Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. 3. In Hardware SID Read column: Y = with SID read function; N = without SID read function.
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W29C040
HOW TO READ THE TOP MARKING
Example: The top marking of 32-pin TSOP W29C040T-90
W29C040T-90 2138977A-A12 149OBSA
st
1 line: winbond logo 2 line: the part number: W29C040T-90 3 line: the lot number 4 line: the tracking code: 149 O B SA 149: Packages made in '01, week 49 O: Assembly house ID: A means ASE, O means OSE, ...etc. B: IC revision; A means version A, B means version B, ...etc. SA: Process code
th rd nd
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W29C040
PACKAGE DIMENSIONS
32-pin P-DIP
Dimension in inches
Dimension in mm
Symbol
Min. Nom. Max. Min. Nom. Max.
0.210 0.010 0.150 0.016 0.048 0.008 0.155 0.018 0.050 0.010 1.650 0.590 0.545 0.090 0.120 0 0.630 0.650 0.600 0.550 0.100 0.130 0.160 0.022 0.054 0.014 1.660 0.610 0.555 0.110 0.140 15 0.670 0.085 14.99 13.84 2.29 3.05 0 16.00 16.51 0.25 3.81 0.41 1.22 0.20 3.94 0.46 1.27 0.25 41.91 15.24 13.97 2.54 3.30 4.06 0.56 1.37 0.36 42.16 15.49 14.10 2.79 3.56 15 17.02 2.16 5.33
D
32 17
E1
A A1 A2 B B1 c D E E1 e1 L
a
1
16
eA S Notes:
E c
S
A A2 L B B1
A1
Base Plane Seating Plane
e1
a
eA
1.Dimensions D Max. & S include mold flash or tie bar burrs. 2.Dimension E1 does not include interlead flash. 3.Dimensions D & E1 include mold mismatch and . are determined at the mold parting line. 4.Dimension B1 does not include dambar protrusion/intrusion. 5.Controlling dimension: Inches 6.General appearance spec. should be based on final visual inspection spec.
32-pin PLCC
HE E
4
1
32
30
Symbol
5 29
Dimension in Inches
Dimension in mm
Min.
0.020 0.105 0.026 0.016 0.008 0.547 0.447 0.044 0.490 0.390 0.585 0.485 0.075
Nom.
Max.
0.140
Min.
0.50
Nom.
Max.
3.56
GD D HD
13
21
14
20
c
A A1 A2 b1 b c D E e GD GE HD HE L y Notes:
0.110 0.028 0.018 0.010 0.550 0.450 0.050 0.510 0.410 0.590 0.490 0.090
0.115 0.032 0.022 0.014 0.553 0.453 0.056 0.530 0.430 0.595 0.495 0.095 0.004
2.67 0.66 0.41 0.20 13.89 11.35 1.12 12.45 9.91 14.86 12.32 1.91
2.80 0.71 0.46 0.25 13.97 11.43 1.27 12.95 10.41 14.99 12.45 2.29
2.93 0.81 0.56 0.35 14.05 11.51 1.42 13.46 10.92 15.11 12.57 2.41 0.10
0
10
0
10
L A2 A
Seating Plane
e
b b1 GE
A1 y
1. Dimensions D & E do not include interlead flash. 2. Dimension b1 does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches. 4. General appearance spec. should be based on final visual inspection sepc.
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Publication Release Date: May 6, 2002 Revision A9
W29C040
Package Dimensions, continued
32-pin TSOP
HD
Symbol
Dimension In Inches Min. Nom. Max.
0.047 0.006 0.041 0.009 0.007
Dimension In mm Min. Nom. Max.
1.20 0.15 1.05 0.23 0.17 18.50 8.10 20.20
D c
A A1 A2
__
0.002 0.037 0.007 0.005 0.720 0.311 0.780
__ __
0.039 0.008 0.006 0.724 0.315 0.787 0.020 0.020 0.031
__
0.05 0.95 0.17 0.12
__ __
1.00 0.20 0.15
M
e E
b c D E HD e L L1
A A2
0.10(0.004)
0.728 18.30 18.40 0.319 0.795 7.90 19.80 8.00 20.00 0.50 0.50 0.80
b
__
0.016
__
0.024
__
0.40
__
0.60
__
0.000 1
__
0.004 5
__
0.00 1
__
0.10 5
Y Y
__
3
__
3
L L1
A1
Note:
Controlling dimension: Millimeters
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W29C040
VERSION HISTORY
VERSION A3 A4 A5 DATE June 1998 Oct. 1998 May 1999 PAGE 4 11 20 9 1, 12, 18 1, 2, 18, 19 A6 Nov. 2000 12 1, 12, 18 1 11 1, 2, 23, 24 10 6, 7 5, 23 A7 A8 A9 April 2001 9/12/2001 May 6, 2002 11 1,19 5, 11, 13 19 4 8 DESCRIPTION Correct Power-on Delay from 5 mS to 10 mS Correct TPU.WRITE (Typ.) from 5 mS to 10 mS Correct 40-pin TSOP Package Drawing by 32-pin TSOP Correct the Address from 3FFFF to 7FFFF Modify TACC: 90/120/150 nS a 90/120 nS binning Modify Packages: PDIP/SOP/PLCC/TSOP a PLCC/TSOP Change Byte Load Cycle Time from 150 S to 200 S Modify TACC: 90/120 nS a 70/90/120 nS binning Typo Correction Modify Output Load Parameter Add DIP Package Add toggle and polling Acquisition Flow Correct the Acquisition Flow Wait Time Add in Hardware SID Read Function Note Modify VIH from 2.0V to 2.2V for DIP only (2.0V for PLCC & TSOP; 2.2V for DIP) Range page write (erase/program) cycles between 1K/10K (min.) and 5K/50K (typ.) Add operating range -40 to 85 C Add Part No of W29C040xxxxK for ordering information Correct VDD Power Up/Down Detection Description Correct Command Codes and Acquisition Flow for Software Product Identification and Boot Block Lockout Detection ADD HOW TO READ THE TOP MARKING
20
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Publication Release Date: May 6, 2002 Revision A9
W29C040
Headquarters
No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/
Winbond Electronics Corporation America
2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798
Winbond Electronics (Shanghai) Ltd.
27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998
Taipei Office
9F, No.480, Rueiguang Rd., Neihu Chiu, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579
Winbond Electronics Corporation Japan
7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
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