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PRELIMINARY TECHNICAL DATA
a
Preliminary Technical Data
FEATURES SNR = 65dB @ Fin up to 65MHz at 170Msps ENOB of 10.3 @ Fin up to 65MHz at 170 Msps (-1dBFs) SFDR = -80dBc @ Fin up to 65MHz at 170Msps (-1dBFs) Excellent Linearity: - DNL = +/- 1 lsb (typ) - INL = +/- 1.5 lsb (typ) Two Output Data options - Demultiplexed 3.3V CMOS outputs each at 85 Msps - LVDS at 170Msps 700 MHz Full Power Analog Bandwidth On-chip reference and track/hol d Power dissipation = 1.25W typical at 170Msps 1.5V Input voltage range +3.3V Supply Operation Output data format option Data Sync input and Data Clock output provided Interleaved or parallel data output option (CMOS) Clock Duty Cycle Stabilizer. APPLICATIONS Wireless and Wired Broadband Communications - Wideband carrier frequency systems - Cable Reverse Path Communications Test Equipment Radar and Satellite sub-systems Power Amplifier Linearization
12-Bit, 170 MSPS 3.3V A/D Converter
AD9430
PRODUCT DESCRIPTION The AD9430 is a 12-bit monolithic sampling analog-to- digital converter with an on-chip track-and-hold circuit and is optimized for low cost, low power, small size and ease of use. The product operates up to 170 Msps conversion rate and is optimized for outstanding dynamic performance in wideband carrier systems. The ADC requires a +3.3V power supply and a differential encode clock for full performance operation. No external reference or driver components are required for many applications. The digital outputs are TTL/CMOS or LVDS compatible. Separate output power supply pins support interfacing with 3.3V CMOS logic. An output data format select option of two's complement or offset binary is supported. In CMOS mode two output buses support demultiplexed data up to 85 Msps rates. A data sync input is supported for proper output data port alignment and a data clock output is available for proper output data timing. Fabricated on an advanced BiCMOS process, the AD9430 is available in a 100 pin surface mount plastic package (100 TQFP ePAD) specified over the industrial temperature range (-40C to +85C).
SENSE
VREF
AGND
DrGND
DrVDD AV DD
AD9430
Scaleable Reference
AIN+ AIN-
Track & Hold
ADC 12-bit Pipeline Core
LVDS Outputs
12 A port
Data(24), OR(2)
Data(12), OR(1)
CMOS Outputs
DS+ DS-
B port
Data(12), OR(1)
ENC+
Clock Management
Select CMOS or LVDS DCO+
ENC-
DCOS1 S2 S4 S5
AD9430 FUNCTIONAL BLOCK DIAGRAM
REV. PrG 4/01/2002
Information furnished by Analog Devices is believed to be accurate and reliable.However,no responsibility is assumed by Analog Devices for its use,nor for any infringements of patents or other rights of third parties that may result from its use.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way,P.O.Box 9106,Norwood,MA 02062-9106,U.S.A. Tel:781/329-4700 www.analog.com Fax:781/326-8703 (c) Analog Devices, Inc., 2002
PRELIMINARY TECHNICAL DATA AD9430
DC SPECIFICATIONS (AVDD=
reference, LVDS Output Mode) Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error POWER SUPPLY REJECTION REFERENCE OUT (VREF) ANALOG INPUTS (AIN, AIN ) Input Voltage Range (AIN- AIN )1 Input Common Mode Voltage Input Resistance Input Capacitance POWER SUPPLY Supply Voltages AVDD DrVDD Supply Current I ANALOG (AVDD= 3.3V) 2 I DIGITAL (DrVDD = 3.3V) 2 POWER CONSUMPTION3 Temp Test Level AD9430BSV-170 Min Typ Max 12 Guaranteed tbd tbd +/- .3 +/- .5 tbd tbd tbd 1.235 .768 2.8 3 5 Units Bits DrVDD = 3.3V; TMIN = -40C, TMAX = +85C, Fin = -0.5dBFS, 1.235V External
Full 25C 25C 25C 25C Full Full Full Full
I I I I I V V V V
mV % FS LSB LSB ppm/C ppm/C mV/V V
Full Full Full Full
V V V V
V V k pF
Full Full Full Full Full
V V V V V
3.0 3.0
3.3 3.3 335 55 1.29
3.6 3.6
V V mA mA W
NOTES 1 Nominal Differential Full Scale = .766 V * 2 = 1.53 Vp-p differential for S5 = 0; Nominal Differential Full Scale = .766 Vp-p d ifferential for S5 = 1 (see Fig. X) 2 IAVDD and IDrVDD are measured with an analog input of 10.3MHz, -0.5dBFs, sine wave, rated Encode rate and in LVDS output mode. See Typical Performance Characteristics and Applications section for IDrVDD. 3 Power Consumption is measured with a DC input at rated Encode rate in LVDS output mode
DIGITAL SPECIFICATIONS
Parameter (Conditions) ENCODE AND DATA SYNC INPUTS (ENC, ENC , DS, DS/ ) Differential Input Voltage 1 Encode Common Mode Voltage Input Resistance Input Capacitance LOGIC INPUTS ( S1,S2,S4,S5 ) Logic `1' Voltage Logic `0' Voltage Input Resistance Input Capacitance LOGIC OUTPUTS (Demux Mode) Logic "1" Voltage2 Logic "0" Voltage2 LOGIC OUTPUTS (LVDS Mode)2,3 VOD Differential Output Voltage VOS Output Offset Voltage Output Coding
NOTES
2
(AVDD= 3.3V, DrVDD = 3.3V; TMIN = -40C, TMAX = +85C) Test AD9430BSV-170 Temp Level Min Typ Max Units
Full Full Full Full Full Full Full Full Full Full Full Full Full
IV IV IV IV IV IV IV IV IV IV IV IV IV
0.2 1.5 5.5 4 2.0 .8 30 4 DrVDD-0.05 0.05 247 454 1.125 1.375 Two's Comp or Binary
3
V V k pF V V k pF V V mV V > 200mV 4/01/2002 REV. PrG
1All AC specifications tested by driving ENCODE and ENCODE differentially
| ENCODE - ENCODE |
Digital Output Logic Levels: DrVDD=
3.3V, CLOAD = 5pF.
LVDS Rl=100 ohms,
LVDS Output Swing Set Resistor = 3.7K
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PRELIMINARY TECHNICAL DATA AD9430
(AVDD= 3.3 V, DrVDD = 3.3V; ENCODE = Maximum Conversion Rate ; TMIN = -40C, TMAX = +85C, Internal voltage reference, LVDS Output Mode ) Test AD9430BSV-170 Parameter (Conditions) Temp Level Min Typ Max Units SNR dB 65 Analog Input 10 MHz I 25C dB 65 @ -0.5dBFS 65 MHz I 25C dB 65 100 MHz V 25C dB 64 240 MHz V 25C SINAD dB 65 Analog Input 10 MHz I 25C dB 65 @ -0.5dBFS 65 MHz I 25C dB 64.5 100 MHz V 25C dB 60 240 MHz V 25C nd rd Worst Harmonic (2 or 3 ) dBc -85 Analog Input 10 MHz I 25C dBc -80 @ -0.5dBFS 65 MHz I 25C dBc -77 100 MHz V 25C dBc -63 240 MHz V 25C th Worst Harmonic (4 or higher) dBc -87 Analog Input 10 MHz I 25C dBc -87 @ -0.5dBFS 65 MHz I 25C dBc -77 100 MHz V 25C dBc -63 240 MHz V 25C 2 Two-tone IMD F1, F2 @ -7 dBFS Full V -75 dBc Analog Input Bandwidth V 700 MHz 25C
NOTES 1 All AC specifications tested by driving ENCODE and ENCODE differentially. 2 F1 = 31.5 MHz, F2 = 32.5 MHz
AC SPECIFICATIONS1
SWITCHING SPECIFICATIONS (AVDD= 3.3 V, DrVDD = 3.3V; ENCODE = Maximum Conversion Rate ; TMIN = -40C, TMAX = +85C ) Test AD9430BSV-170 Parameter (Conditions) Temp Level Min Typ Max Units MSPS 170 I Maximum Conversion Rate1 Full MSPS 40 V Minimum Conversion Rate1 Full nS 2 V Encode Pulse Width High (tEH)1 Full nS 2 V Encode Pulse Width Low (tEL)1 Full nS .5 IV Full DS Input Setup Time (tSDS) 2 nS 1.5 IV Full DS Input Hold Time (tHDS) 2
NOTES 1 All AC specifications tested by driving ENCODE and ENCODE differentially, LVDS Mode. 2 DS inputs used in CMOS Mode only.
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PRELIMINARY TECHNICAL DATA AD9430
SWITCHING SPECIFICATIONS (cont'd) Parameter OUTPUT Parameters in Demux Mode Valid Time (tV) Propagation Delay (tPD) Rise Time (tR) (20% to 80%) Fall Time (tF) (20% to 80%) DCO Propagation Delay (tCPD) Data to DCO Skew (tPD - tCPD) Interleaved Mode (A, B Latency) Parallel Mode (A, B Latency) OUTPUT Parameters in LVDS Mode Valid Time (tV) Propagation Delay (tPD) Rise Time (tR) (20% to 80%) Fall Time (tF) (20% to 80%) DCO Propagation Delay (tCPD) Data to DCO Skew (tPD - tCPD) Pipeline Latency Aperture Delay (tA) Aperture Uncertainty (Jitter, t J) Temp Full Full 25C 25C Full Full Full Full Full Full 25C 25C Full Full Full 25C 25C Test Level IV IV V V VI IV VI VI IV I V V VI IV VI V V 2.0 3.2 .5 .5 2.7 .5 14 1.2 0.25 4.3 AD9430BSV-170 Min Typ Max tbd 3.8 1 1 3.8 0 14/14 14/15 Units ns ns ns ns ns ns Cycles Cycles ns ns ns ns ns ns Cycles ps ps rms
1.8
3.8
Measured Preliminary Performance : FFT 65MHz Ain at 170MSPS
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PRELIMINARY TECHNICAL DATA AD9430
AD9430 Timing Diagram
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PRELIMINARY TECHNICAL DATA AD9430
ABSOLUTE MAXIMUM RATINGS AVDD, DRVDD.. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 V Analog Inputs . . . . . . . . . . .. . .. . . -0.5 V to AVDD + 0.5 V Digital Inputs . . .. . . . . . . . .. . . .. -0.5 V to DRVDD + 0.5 V REFIN Inputs . . . . . . . . . . . . . . . . -0.5 V to AVDD + 0.5 V Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Operating Temperature . . . . . . . . . . ... . . . . . -55C to +125C Storage Temperature . . . . . . . . . . . . . ... . . . . -65C to +150C Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150C Maximum Case Temperature . . . . . . . . . . . . . . . . . . . ..150C JA2 . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . 25C/W, 32C/W NOTES
1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions outside of those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. 2 Typical JA = 32C/W (heat slug not soldered), Typical JA = 25C/W (heat slug soldered), for multilayer board in still air.
EXPLANATION OF TEST LEVELS Test Level I 100% production tested. II 100% production tested at 25C and sample tested at specified temperatures. III Sample tested only. IV Parameter is guaranteed by design and characterization testing. V Parameter is a typical value only. VI 100% production tested at 25C; guaranteed by design and characterization testing for industrial temperature range; 100% production tested at temperature extremes for military devices.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9430 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE
Model AD9430BSV-170 AD9430/PCB-CMOS Temperature Range -40C to +85C +25C Package Option TQFP-100 Evaluatio n Board (CMOS Mode)
S1 (Data Format Select) 1 1 0 X X X X X Notes:
1
S2 (LVDS/CMOS Output Mode Select ) X X 0 0 1 X X
Table 1. AD9430 Output Select Coding S4 S5 Mode (Select (Full Scale Interleaved or Adjust) Parallel Mode) 2 X X 2's Complement X X Offset Binary 1 X Dual Mode CMOS Interleaved 0 X Dual Mode CMOS Parallel X X LVDS Mode X 1 Full Scale -> .766 Vpp differential 1.533 Vpp Single- Ended X 0 Full Scale -> 1.533 Vpp differential
X = Don't Care S1-S5 all have 30K resistive pulldowns on chip
2
In interleaved mode output data on port A is offset from output data changes on port B by 1/2 output clock cycle. Parallel Mode
Interleaved mode
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PRELIMINARY TECHNICAL DATA AD9430
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 S5 DNC S4 AGND S2 S1
LVDSBIAS
AVDD AVDD AGND AGND AVDD AVDD AGND AGND AGND AVDD AVDD AVDD AGND AGND OR_T OR_C DRVDD DRGND D11_T D11_C D10_T D10_C D9_T D9_C AD9430 LVDS PINOUT TOP VIEW (Not to Scale) 75 DRVDD 74 DRGND 73 D8_T 72 D8_C 71 D7_T 70 D7_C 69 D6_T 68 D6_C 67 DRGND 66 D5_T 65 D5_C 64 DCO 63 DCO 62 DRVDD 61 DRGND 60 D4_T 59 D4_C 58 D3_T 57 D3_C 56 D2_T 55 D2_C 54 DRVDD 53 DRGND 52 D1_T 51 D1_C 42 43 44 45 46 47 48 49 50 DNC DB0 DB1 DNC DRVDD DRGND D0_C D0_T 75 DRVDD 74 DRGND 73 DA4 72 DA3 71 DA2 70 DA1 69 DA0 68 DNC 67 DRGND 66 DNC 65 DNC 64 DCO 63 DCO 62 DRVDD 61 DRGND 60 OR_B 59 DB11 (MSB) 58 DB10 57 DB9 56 DB8 55 DB7 54 DRVDD 53 DRGND 52 DB6 51 DB5 42 43 44 45 DB2 46 DRVDD 47 DRGND 48 DB3 49 DB4 50 DNC DNC DNC
(MSB)
AVDD AGND SENSE VREF AGND AGND AVDD AVDD AGND AGND AVDD AVDD AGND AIN AIN AGND AVDD AGND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
S5 DNC S4 AGND S2 S1
DNC
AVDD AGND SENSE VREF AGND AGND AVDD AVDD AGND AGND AVDD AVDD AGND AIN AIN AGND AVDD AGND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
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AGND AVDD AVDD AVDD AGND AGND DS DS AVDD AGND ENC ENC AGND AVDD AVDD AGND DNC
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 AD9430 CMOS PINOUT TOP VIEW (Not to Scale)
AGND AVDD AVDD AGND AGND AVDD AVDD AGND AGND AGND AVDD AVDD AVDD AGND AGND OR_A DA11 (MSB) DRVDD DRGND DA10 DA9 DA8 DA7 DA6 DA5
AGND AVDD AVDD AVDD AGND AGND GND AVDD AVDD AGND ENC ENC AGND AVDD AVDD AGND DNC
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41
AGND
AD9430 LVDS Mode Pinout
AD9430 CMOS Dual Mode Pinout -7-
PRELIMINARY TECHNICAL DATA AD9430
PIN FUNCTION DESCRIPTIONS (CMOS mode) CMOS Mode Function in CMOS Mode Name Pin Number
2,7,42,43,65,66,68 1 3 DNC S5 S4 Do not connect Full Scale Adjust pin : `1' sets FS =.766 Vpp differential,
`0' sets FS = 1.533 Vpp differential
Interlaced or parallel output mode. (only in Dual Port mode operation) HIGH = data arrives in channel A at falling edge of clock and data arrives in channel A at rising edge of clock. LOW = data arrives in channels A and B at rising edge of clock. Output Mode select. Low = Dual Port, CMOS; High = LVDS Data format select. Low = Binary, High = Two's compliment 3.3V analog supply. (3.0V to 3.6V) Analog Ground
5 6 8,14,15,18,19,24,27,28,29,34, 39,40,88,89,90,94,95,98,99 4,9,12,13,16,17,20,23,25,26,3 0,31,35,38,41,86,87,91,92,93, 96,97,100 10 11 21 22 32
S2 S1 AVDD AGND
SENSE VREF VIN+ VINDS+
33 36 37 44 45 46 49 50 51 52 55 56 57 58 59 60 48,53,61,67,74,82 47,54,62,75,83 63 64 69 70 71 72 73 76 77 78 79 80 81 84 85
DSENC+ ENCDB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 OR_B DrGND DrVDD DCODCO+ DA0 DA1 DA2 DA3 DA4 DA5 DA6 DA7 DA8 DA9 DA10 DA11 OR_A
Control Pin for Reference , Full Scale 1.235 Reference I/O - function dependent on REFSENSE Analog input - true. Analog input - compliment. Data sync (input) - true. Aligns output channels so that data from channel A represents a sample that is prior from data in channel B, taking into account the pipeline delay. (See timing diagram). Tie LOW if not used. Data sync (input) - compliment. Tie HIGH if not used. Clock input - true. Clock input - compliment. B Port Output Data Bit (LSB) B Port Output Data Bit B Port Output Data Bit B Port Output Data Bit B Port Output Data Bit B Port Output Data Bit B Port Output Data Bit B Port Output Data Bit B Port Output Data Bit B Port Output Data Bit B Port Output Data Bit B Port Output Data Bit (MSB) B Port Overrange Digital ground. 3.3V digital output supply. (3.0V to 3.6V) Data Clock output - compliment. Data Clock output - true. A port Output Data Bit (LSB) A port Output Data Bit A port Output Data Bit A port Output Data Bit A port Output Data Bit A port Output Data Bit A port Output Data Bit A port Output Data Bit A port Output Data Bit A port Output Data Bit A port Output Data Bit A port Output Data Bit (MSB) A port Overrange
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PRELIMINARY TECHNICAL DATA AD9430
PIN FUNCTION DESCRIPTIONS (LVDS mode ) Function in LVDS Mode LVDS Mode Name Pin Number
2,42,43,44,45,46 1 3 DNC S5 S4 Do not connect Full Scale Adjust pin : `1' sets FS =.766 Vpp differential,
`0' sets FS = 1.533 Vpp differential
Interlaced or parallel output mode. (only in Dual Port mode operation) HIGH = data arrives in channel A at falling edge of clock and data arrives in channel A at rising edge of clock. LOW = data arrives in channels A and B at rising edge of clock. Output Mode select. Low = Dual Port, CMOS; High = LVDS Data format select. Low = Binary, High = Two's compliment Sets LVDS Output Current = 3.5mA (Place 3.7K RSET resistor from LVDSBIAS to ground) 3.3V analog supply. (3.0V to 3.6V) Analog Ground
5 6 7 8,14,15,18,19,24,27,28,29,34, 39,40,88,89,90,94,95,98,99 4,9,12,13,16,17,20,23,25,26,3 0,31,35,38,41,86,87,91,92,93, 96,97,100 10 11 21 22 32 33 36 37 47,54,62,75,83 48,53,61,67,74,82 49 50 51 52 55 56 57 58 59 60 63 64 65 66 68 69 70 71 72 73 76 77 78 79 80 81 84 85
S2 S1 LVDSBIAS AVDD AGND
SENSE VREF VIN+ VINDS+ DSENC+ ENCDrVDD DrGND D0_C D0_T D1_C D1_T D2_C D2_T D3_C D3_T D4_C D4_T DCODCO+ D5_C D5_T D6_C D6_T D7_C D7_T D8_C D8_T D9_C D9_T D10_C D10_T D11_C D11_T OR_C OR_T
Control Pin for Reference , Full Scale 1.235 Reference I/O - function dependent on REFSENSE Analog input - true. Analog input - compliment. Data sync (input) - Not used in LVDS mode.Tie LOW . Data sync (input) - compliment. Not used in LVDS mode.Tie HIGH. Clock input - true. (LVPECL levels) Clock input - compliment. (LVPECL levels) 3.3V digital output supply. Digital ground. D0 complement output bit (LSB) (LVDS Levels) D0 true output bit (LSB) (LVDS Levels) D1 complement output bit (LVDS Levels) D1 true output bit (LVDS Levels) D2 complement output bit (LVDS Levels) D2 true output bit (LVDS Levels) D3 complement output bit (LVDS Levels) D3 true output bit (LVDS Levels) D4 complement output bit (LVDS Levels) D4 true output bit (LVDS Levels) Data Clock output - compliment. (LVDS Levels) Data Clock output - true. (LVDS Levels) D5 complement output bit (LVDS Levels) D5 true output bit (LVDS Levels) D6 complement output bit (LVDS Levels) D6 true output bit (LVDS Levels) D7 complement output bit (LVDS Levels) D7 true output bit (LVDS Levels) D8 complement output bit (LVDS Levels) D8 true output bit (LVDS Levels) D9 complement output bit (LVDS Levels) D9 true output bit (LVDS Levels) D10 complement output bit (LVDS Levels) D10 true output bit (LVDS Levels) D11 complement output bit (LVDS Levels) MSB D11 true output bit (LVDS Levels) MSB Overrange complement output bit (LVDS Levels) Overrange true output bit (LVDS Levels)
REV. PrG 4/01/2002
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PRELIMINARY TECHNICAL DATA AD9430
TERMINOLOGY Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay The delay between the 50% point of the rising edge of the ENCODE command and the instant at which the analog input is sampled. Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Crosstalk Coupling onto one channel being driven by a low level (-40 dBFS) signal when the adjacent interfering channel is driven by a full-scale signal. Differential Analog Input Resistance, Differential Analog Input Capacitance and Differential Analog Input Impedance The real and complex impedances measured at each analog input port. The resistance is measured statically and the capacitance and differential input impedances are measured with a network analyzer. Differential Analog Input Voltage Range The peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. Peak differential voltage is computed by observing the voltage on a single pin and subtracting the voltage from the other pin, which is 180 degrees out of phase. Peak-to-peak differential is computed by rotating the inputs phase 180 degrees and again taking the peak measurement. The difference is then computed between both peak measurements. Differential Nonlinearity The deviation of any code width from an ideal 1 LSB step. Effective Number of Bits The effective number of bits (ENOB) is calculated from the measured SNR based on the equation: Full-Scale Input Power Expressed in dBm. Computed using the following equation:
2 VFullscale Z Input PowerFullscale = 10 log .001
rms

Gain Error Gain error is the difference between the measured and ideal full scale input voltage range of the ADC. Harmonic Distortion, Second The ratio of the rms signal amplitude to the rms value of the second harmonic component, repo rted in dBc. Harmonic Distortion, Third The ratio of the rms signal amplitude to the rms value of the third harmonic component, reported in dBc. Integral Nonlinearity The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a "best straight line" determined by a least square curve fit. Minimum Conversion Rate The encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit. Maximum Conversion Rate The encode rate at which parametric testing is performed. Output Propagation Delay The delay between a differential crossing of ENCODE and ENCODE and the time when all output data bits are within valid logic levels. Noise (for Any Range within the ADC)
ENOB =
SNR MEASURED- 1.76 dB 6.02
V noise = Z * .001 * 10
FSdBm - SNR - Signal dBc dBFS 10
ENCODE Pulsewidth / Duty Cycle Pulsewidth high is the minimum amount of time that the ENCODE pulse should be left in Logic 1 state to achieve rated performance; pulsewidth low is the minimum time ENCODE pulse should be left in low state. See timing implications of changing tENCH in text. At a given clock rate, these specifica-tions define an acceptable ENCODE duty cycle.
Where Z is the input impedance, FS is the full scale of the device for the frequency in question, SNR is the value for the particular input level, and Signal is the signal level within the ADC reported in dB below full scale. This value includes both thermal and quantization noise. Power Supply Rejection Ratio The ratio of a change in input offset voltage to a change in power supply voltage. Signal -to-Noise-and-Distortion (SINAD) The ratio of the rms signal amplitude (set 1 dB below full scale) to the rms value of the sum of all other spectral components, including harmonics but excluding dc. -104/01/2002 REV. PrG
PRELIMINARY TECHNICAL DATA AD9430
Signal -to-Noise Ratio (without Harmonics) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. Spurious-Free Dynamic Range (SFDR) The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. May be reported in dBc (i.e., degrades as signal level is lowered), or dBFS (always related back to converter full scale). Two-Tone Intermodulation Distortion Rejection The ratio of the rms value of either input tone to the rms value of the worst third order intermodulation product; reported in dBc. Two-Tone SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. May be reported in dBc (i.e., degrades as signal level is lowered), or in dBFS (always related back to converter full scale). Worst Other Spur The ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding the second and third harmonic) reported in dBc. Transient Response Time Transient response is defined as the time it takes for the ADC to reacquire the analog input after a transient from 10% above negative full scale to 10% below positive full scale. Out-of-Range Recovery Time Out of range recovery time is the time it takes for the ADC to reacquire the analog input after a transient from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale. EQUIVALENT CIRCUITS Figure X VREF, SENSE I/O
Figure X Analog Inputs
Figure X S1-S5 Inputs
Figure X Data Outputs (CMOS Mode)
Figure X Encode and DS Inputs Figure X Data Outputs (LVDS Mode) REV. PrG 4/01/2002 -11-
PRELIMINARY TECHNICAL DATA AD9430
APPLICATION NOTES
THEORY OF OPERATION The AD9430 architecture is optimized for high speed and ease of use. The analog inputs drive an integrated high bandwidth track-and-hold circuit that samples the signal prior to quantization by the 12-bit core. For ease of use the part includes an onboard reference and input logic that accepts TTL, CMOS, or LVPECL levels. The digital outputs logic levels are user selectable as standard 3V CMOS or LVDS (ANSI-644 compatible) via pin S2. USING THE AD9430 ENCODE Input Any high speed A/D converter is extremely sensitive to the quality of the sampling clock provided by the user. A track/hold circuit is essentially a mixer, and any noise, distortion, or timing jitter on the clock will be combined with the desired signal at the A/D output. For that reason, considerable care has been taken in the design of the ENCODE input of the AD9430, and the user is advised to give commensurate thought to the clock source. The AD9430 has an internal clock duty cycle stabilization circuit that locks to the rising edge of ENCODE (falling edge of ENCODE if driven differentially), and optimizes timing internally. This allows for a wide range of input duty cycles at the input without degrading performance. Jitter in the rising edge of the input is still of paramount concern, and is not reduced by the internal stabilization circuit. This circuit is always on, and cannot be disabled by the user. The ENCODE and ENCODE inputs are internally biased to 1.5V (nominal), and support either differential or single - ended signals. For best dynamic performance, a differential signal is recommended. Good performance is obtained using an MC10EL16 in the circuit to drive the encode inputs , as illustrated in figure below. differential analog inputs for applications that require a single-ended-to-differential conversion. Both analog inputs are self-biased by an on-chip resistor divider to a nominal 2.8 V. (See Equivalent Circuits section TBD.) Special care was taken in the design of the Analog Input section of the AD9430 to prevent damage and corruption of data when the input is overdriven. The nominal input range is 1.5 V diff p-p. The nominal differential input range is 768 mV p-p x 2.
Differential Analog Input Range
Single Ended Analog Input Range Driving Encode with EL16 Analog Input The analog input to the AD9430 is a differential buffer. For
____
best dynamic performance, impedances at AIN and AIN should match. The analog input has been optimized to provide superior wideband performance and requires that the analog inputs be driven differentially. SNR and SINAD performance will degrade significantly (~6dB) if the analog input is driven with a single-ended signal. A wideband transformer such as Minicircuits ADT1 -1WT can be used to provide the -124/01/2002 REV. PrG
PRELIMINARY TECHNICAL DATA AD9430
Digital Outputs The off chip drivers on the chip can be configured by the user to provide CMOS or LVDS compatible output levels via pin S2. The CMOS digital outputs (S2=0) are TTL/CMOScompatible for lower power consumption. The outputs are biased from a separate supply (VDD), allowing easy interface to external logic. The outputs are CMOS devices which will swing from ground to VDD (with no dc load). It is recommended to minimize the capacitive load the ADC drives by keeping the output traces short (<1 inch, for a total CLOAD < 5 pF). When operating in cmos mode it is also recommended to place low value (220 ohm) series damping resistors on the data lines to reduce switching transient effects on performance. LVDS outputs are available when S2=VDD and a 3.7K RSET resistor is placed at pin 7 ( LVDSBIAS) to ground . This resistor sets the output current at each output equal to a nominal 3.5mA ( 10* IRSET ) . A 100 ohm differential termination resistor placed at the lvds receiver inputs results in a nominal 350mV voltage swing at the receiver. Note that when operating in LVDS mode the output supply must be at a dc potential greater than or equal to the analog supply level (AVDD). This can be accomplished simply by biasing the two supplies from the same power plane or by tying the two supplies on the pcb through an inductor. When operating in CMOS mode this is not required and separate supplies are recommended. Clock Outputs (DCO+, DCO-) The input ENCODE is divided by two (in CMOS mode) and available off-chip at DCO+ and DCO-. These clocks can facilitate latching off-chip, providing a low skew clocking solution (see timing diagram). The on-chip clock buffers should not drive more than 5 pF of capacitance to limit switching transient effects on performance. Note that the Outputs clocks are CMOS levels when CMOS mode is selected(S2=0) and are LVDS levels when in LVDS mode(S2=VDD). (Requiring a 100ohm differential termination at receiver in LVDS mode). The output clock in LVDS mode switches at the encode rate. Voltage Reference A stable and accurate 1.25 V voltage reference is built into the AD9430 (VREF). The analog input Full Scale Range is linearly proportional to the voltage at VREF. VREF (and in turn input full scale ) can be varied by adding an external resistor network at VREF, SENSE and GROUND. (See figure X ) . No appreciable degradation in performance occurs when VREF is adjusted 5%. Note that an external reference can be used by connecting the SENSE pin to VDD (disabling internal reference) and driving VREF with the external reference source. A .1uF capacitor to ground is recommended at VREF pin in internal and external reference applications.
Simplified Voltage Reference Equivalent Circuit
REV. PrG 4/01/2002
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PRELIMINARY TECHNICAL DATA AD9430
AD9430 EVALUATION BOARD
The AD9430 evaluation board offers an easy way to test the AD9430. It requires a clock source, an analog input signal, and a 3.3 V power supply. The clock source is buffered on the board to provide the clocks for the ADC, an on-board DAC, latches, and a data ready signal. The digital outputs and output clocks are available at two 40-pin connectors, P3 and P4. The board has several different modes of operation, and is shipped in the following configuration: * Offset Binary * Internal Voltage Reference * CMOS Parallel Timing * Full-Scale Adjust = Low
Power Connector
> 0.5 V p-p. Power to the EL16 is set at jumper E47. E47-E45 powers the buffer from AVDD, E47-E46 powers the buffer from VCLK/V_XTAL.
Voltage Reference
The AD9430 has an internal 1.23 V voltage reference. The ADC uses the internal reference as the default when jumpers E24-E27 and E25-E26 are left open. The full scale can be increased by placing optional resistor R3. The required value would vary with process and needs to be tuned for the specific application. Full scale can similarly be reduced by placing R4; tuning would be required here as well. An external reference can be used by shorting the SENSE pin to 3.3 V (place jumper E26-E25). E27-E24 jumper connects the ADC VREF pin to EXT_VREF pin at the power connector.
Data Format Select
Power is supplied to the board via a detachable 12-lead power strip (three 4-pin blocks).
Table II. Power Connector
Data Format Select sets the output data format of the ADC. Setting DFS (E1-E2) low sets the output format to be offset binary; setting DFS high (E1-E3) sets the output to two's complement.
I/P
AVDD 3.3 V DRVDD 3.3 V VDL 3.3 V EXT_VREF* VCLK/V_XTAL VAMP
Analog Supply for ADC (~ 350 mA) Output Supply for ADC (~ 28 mA) Supply for Support Logic and DAC (~350 mA) Optional External Reference Input Supply for Clock Buffer/Optional XTAL Supply for Optional Amp
Output timing is set at E11-E13. E12-E11 sets S4 low for parallel output timing mode. E11-E13 sets S4 high for interleaved timing mode.
Timing Controls
*LVEL16 clock buffer can be powered from AVDD or VCLK at E47 jumper (AVDD, DrVDD,VDL are the minimum required power connections).
Flexibility in latch clocking and output timing is accomplished by allowing for clock inversion at the timing controls section of the PCB. Each buffered clock is buffered by an XOR and can be inverted by moving the appropriate jumper for that clock.
Data Outputs
Analog Inputs
The evaluation board accepts a 1.3 V p-p analog input signal centered at ground at SMB connector J4. This signal is terminated to ground through 50 by R16. The input can be alternatively terminated at T1 transformer secondary by R13, R14. T1 is a wideband RF transformer providing the single-ended to differential conversion allowing the ADC to be driven differentially, minimizing even order harmonics. An optional second transformer T2 can be placed following T1 if desired. This would provide some performance advantage (~1-2 dB) for high analog input frequencies (>100 MHz). If T2 is placed, two shorting traces at the pads would need to be cut. The analog signal is low pass filtered by R41, C12, and R42, C13 at the ADC input.
Gain
The ADC digital outputs are latched on the board by four LVT574s; the latch outputs are available at the two 40-pin connectors at pins 11-33 on P23 (channel A) and pins 11-33 on P3 (channel B). The latch output clocks (data ready) are available at Pin 37 on P23 (channel A) and Pin 37 on P3 (channel B). The data ready clocks can be inverted at the timing controls section if needed.
: 4.6nS C1 FREQ 84.65608MHz
Full scale is set at E17-E19, E17-E18 sets S5 low, full scale = 1.5 V differential; E17-E19 sets S5 high, full scale = 0.75 V differential.
Encode
1
2
The encode clock is terminated to ground through 50 at SMB connector J5. The input is ac-coupled to a high-speed differential receiver (LVEL16) which provides the required low-jitter, fast edge rates needed for optimum performance. J5 input should be
CH1
2.00V
CH2
2.00V
M 5.00nS
CH2
Figure 13. Data Output and Clock @ 80-Pin Connector
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4/01/2002 REV. PrG
PRELIMINARY TECHNICAL DATA AD9430
DAC Outputs Optional Amplifier
Each channel is reconstructed by an on-board dual-channel DAC, an AD9753. This DAC is intended to assist in debug--it should not be used to measure the performance of the ADC. It is a current output DAC with on-board 50 termination resistors. The figure below is representative of the DAC output with a full-scale analog input. The scope setting is low bandwidth.
C1 FREQ 10.33592MHz
The footprint for transformer T2 can be modified to accept a wideband differential amplifier (AD8350) for low frequency applications where gain is required. Note that Pin 2 would need to be lifted and left floating for operation. Input transformer T1 would need to be modified to a 4:1 for impedance matching and ADC input filtering would enhance performance (see AD8350 data sheet). SNR/SINAD Performance of 61 dB/60 dB is possible and would start to degrade at about 30 MHz.
CUT TRACE
C1 PK-PK 448mV
1
AD9430
1
CH1
2.00mV
M 25.0nS CH1
248mV
Figure 14. DAC Output
Encode Xtal
CUT TRACE
An optional xtal oscillator can be placed on the board to serve as a clock source for the PCB. Power to the xtal is through the VCLK/VXTAL pin at the power connector. If an oscillator is used, ensure proper termination for best results. The board has been tested with a Valpey Fisher VF561 and a Vectron JN00158-163.84. Test results for the VF561 are shown below.
0 -10 -20 -30 -40 ENCODE 163.84MHz ANALOG 65.02MHz SNR 63.93dB SINAD 63.87dB FUND -0.45dBFS 2ND -85.62dBc 3RD -91.31dBc 4TH -90.54dBc 5TH -90.56dBc 6TH -91.12dBc THD -82.21dBc SFDR 83.93dBc SAMPLES 8k NOISEFLR -100.44dBFS WORSTSP -83.93dBc
Figure 16. Using the AD8350 on the AD9430 PCB
dB
-50 -60 -70 -80 -90 -100 0
20
40 MHz
60
80
Figure 15. FFT--Using VF561 XTAL as Clock Source
REV. PrG 4/01/2002
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PRELIMINARY TECHNICAL DATA AD9430
Table III. Evaluation Board Bill of Materials
No. Qty. 1 45
Reference Designator C1, C3-C11, C15-C17, C19-C29, C31-C48, C58-C62 C2 C12, C13 C14 C18 C30, C49, C63-C67 E3-E1-E2 E19-E17-E18 E13-E11-E12 E26-E25-E27-E24 E46-E47-E45 E35-E33-E34 E32-E30-E31 E29-E23-E28 E22-E16-E21 J1, J2, J3, J4, J5, J6 P3, P23 P4, P21, P22
Device Capacitor
Package 0603
Value 0.1 F 10 pF 20 pF 0.01 F 1 F 10 F
Comments C43, C47 Not Placed Not Placed Not Placed
2 3 4 5 6 7
0 0 1 0 7 9
8 9 10
5 2 3
Capacitor Capacitor Capacitor Capacitor Capacitor 3-Pin Header/Jumper 3-Pin Header/Jumper 3-Pin Header/Jumper 4-Pin Header 3-Pin Header/Jumper 3-Pin Header/Jumper 3-Pin Header/Jumper 3-Pin Header/Jumper 3-Pin Header/Jumper SMB 40-Pin Header 4-Pin Power Connector
0603 0603 0603 0603 CAPL
C30 Not Placed
SMB Post Detachable Connector 0603 25.531.3425.0 25.602.5453.0 50 3.9 k 100 0 510 2 k 390 1 k 742C163221JTR 742C163220JTR Minicircuits ADT1-1WT ADC Clock Buffer Xor/Buffer Latch DAC
J1 Not Placed Wieland Wieland R1, R13, R14 Not Placed R3, R4 Not Placed R15, R21-R24, R38 Not Placed
11
8
R1, R5, R13, R14, R16, R25, R27, R28, R41, R42 R2, R3, R4 R6-R8, R10, R15, R21-R24, R33-R36, R38 R12, R30, R37 R17, R18, R19, R20 R26 R29 R31, R32, R39, R40, R43, R44, R45 RZ1, RZ2, RZ3, RZ4 RZ5, RZ6, RZ7, RZ8, RZ9, RZ10, RZ11, RZ12 T1, T2 U1 U2 U3 U4, U5, U6, U7 U9
Resistor
12 13
1 8
Resistor Resistor
0603 0603
14 15 16 17 18 19 20 21 22 23 24 25 26
5 4 1 1 7 4 8 1 1 1 1 4 1
Resistor Resistor Resistor Resistor Resistor Resistor Pack 220 Resistor Pack 22 Transformer AD9430BSV MC100LVEL16D 74LCX86 74LVT574 AD9753AST
0603 0603 0603 0603 0603 SO16RES SO16RES CD542 TQFP100 SO8NB SO14NB SO20 LQFP48
CTS CTS T2 Not Placed
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4/01/2002 REV. PrG
74LCX86 U3 CLKLATA
1 16 D0 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 CLOCK CLKLATA 11 12 DM5 8 R8 9 13 DM6 7 10 R7 14 DM7 6 11 R6 DX8 DX7 DX6 DX5 15 DM8 5 12 R5 DX9 16 4 13 R4 DX10 17 3 14 R3 DX11 18 2 15 R2 DRX D1 D2 D3 D4 D5 D6 D7 GND 19 16 15 14 13 12 11 10 9 GND 10 9 8 7 6 5 4 3 2 1 2 3 R3 R4 R5 R6 R7 R8 R2 R1 GND R1 1 OUT_EN VCC 20 VDL
P1 P2 P3 P4
1 2 3 4
GND VAMP RZ1 220 RZ8 22
VCC COUTA 3 R33 100 R10 100 74LCX86 U3 DRA
4 5 6
E35 E33 E34 E32 COUTA 6 R34 100
7
1 2 U4
GND
VDL
E20
GND VCC
COUTA R9
P1 P2 P3 P4
1 2 3 4
VCLK/ V_XTAL EXT_VREF GND VDL
DRVDD
E7
H4 MTHOLES
COUT
E30 GND 74LCX86 U3 R35 100 LVT574 11 DRB
RZ2 220 1 16 D0 D1 D2 D3 D4 D5 8 9 GND 10 D6 D7 GND 15 14 13 12 11 10 9 7 6 5 4 3 2 2 R2 R3 R4 R5 R6 R7 R8 R1 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 CLOCK GND 1 OUT_EN VCC 20 19 18 17 16 15 14 13 12 11
4 5
P21 P4 P22 PTMICA04 PTMICA04 PTMICA04
GND VCC VCC GND GND VCC VCC GND GND GND VCC VCC VCC GND GND
DRVDD GND
E17 DRVDD GND
GND
E18
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
GND VCC VCC VCC GND GND
VCC GND
GND VCC
GND GND R5 50
DRVDD GND
J4 C47 0.1 F DATA SYNC J1 VCC GND GND 7 J2 R1 NOT PLACED E47 VCLK U2 2 D Q 8 VCC C5 0.15 F MC100LVEL 16 E46 C36 0.1 F E45 R1 50
C6 R13 0.1 F 25 R42 25
GND
CLK+
CLK-
REV. PrG 4/01/2002
E31 E29 COUTAB 8 CLKLATB
8
P1 P2 P3 P4
1 2 3 4
GND DRVDD GND AVDD (VCC) COUTAB R11
H3 MTHOLES
R8 100 9 10
H2 COUTB MTHOLES
VCC E23 GND 74LCX86 U3 R36 100
3 4 5 6 7 8
H2 MTHOLES
E28 E22 COUTAB U5
VDL 1 2 3 4 5 6 7 8
GND
R7 100 12 13
VCC E16 GND E21 R6 100 GROUND PAD UNDER PART PLB GND
GND DRA GND DX11 DX10 DX9 DX8 DX7 DX6 DX5 DX4 DX3 DX2 DX1 DX0 DXA DXB DRX RZ7 22 R1 R2 R3 R4 R5 R6 R7 R8 CLKLATA 16 15 14 13 12 11 10 9 DX4 DX3 DX2 DX1 DX0 DXA DXB P40 P38 P36 P34 P32 P30 P28 P26 P24 P22 P20 P18 P16 P14 P12 P10 P8 P6 P4 P2 P39 P37 P35 P33 P31 P29 P27 P25 P23 P21 P19 P17 P15 P13 P11 P9 P7 P5 P3 P1 GND
C4OMS P23
VCC
E19
E14
LVT574
VCC GND GND VCC GND R3 E29 E27 E26 R41 25 VCC GND
E13
E11
GND
E12
GND
VCC
E10
R39 1k
E8
GND EXT_VREF R4 C1 0.1 F E24 U1
E9
GND
AD9430
VCC
E6
R39 1k
E4 R3, R4 OPTIONAL
RZ3 220 1 2 3 4 5 R1 R2 R3 R4 R5 GND 16 15 14 13 12 R6 6 7 8 R7 R8
U6
1 2 3 4 5 6 OUT_EN D0 D1 D2 D3 D4 VCC Q0 Q1 Q2 Q3 Q4 20 19 18 17 16 15 VDL 1 2 3 4 5
GND RZ6 22 R1 R2 R3 R4 R5 16 15 14 13 12 R6 11 10 9 GND 7 8 9 10 D5 D6 D7 GND Q5 Q6 Q7 CLOCK 14 13 12 11 6 7 8 CLKLATA R7 R8 DRY DY11 DY10 DY9 DY8
GND VCC
E5 E3
COUT COUTB DRVDD GND
E1
GND T2 OPTIONAL C43 0.1 F GND R41 25 GND VCC GND C13 20pF GND
T2 ADT1-1WT
E2
GND GND VCC VCC GND GND GND VCC VCC C12 GND 20pF
DRVDD GND
11 10 9
T1 ADT1-1WT
C3 0.1 F C11 0.1 F
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
DY7 DY6 DY5
PRELIMINARY TECHNICAL DATA
Figure 17a. Evaluation Board Schematic -174 1 5 2 3 6 PRI SEC
RZ4 220 1 2 3 4 5 6 7 8 R1 R2 R3 R4 R5 R6 R7 R8 GND 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 9
R14 29 GND
R16 50
GND
1 4 5 2 3 6 PRI SEC
C2 10pF
LVT574 U7
OUT_EN D0 D1 D2 D3 D4 D5 D6 D7 10 VCC Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 20 19 18 17 16 15 14 13 12 VDL 1 2 3 4 5 6 7 8 R1 R2 R3 R4 R5 R6 R7 R8 GND GND CLOCK 11 CLKLATB 16 15 14 13 12 11 10 9 DY2 DY1 DY0 DYA DYB DY4 DY3 RZ5 22
GND DRB GND DY11 DY10 DY9 DY8 DY7 DY6 DY5 DY4 DY3 DY2 DY1 DY0 DYA DYB DRY P40 P38 P36 P34 P32 P30 P28 P26 P24 P22 P20 P18 P16 P14 P12 P10 P8 P6 P4 P2 P39 P37 P35 P33 P31 P29 P27 P25 P23 P21 P19 P17 P15 P13 P11 P9 P7 P5 P3 P1 GND
C6 0.1 F
ANALOG
E19
R13, R14 OPTIONAL
C4OMS P3
ENCODE R27 50 3 DN 6 QN 4 VBB VEE 5 C8 0.1 F GND GND R17 510 R10 510
J5
R20 510 GND
R19 510
E36 00 R12 VCC C4 0.1 F + C30 10 F
LVT574
AD9430
GND GND
PRELIMINARY TECHNICAL DATA AD9430
VCC + C64 10 F C16 0.1 F C17 0.1 F C19 0.1 F C21 0.1 F C20 0.1 F C23 0.1 F C22 0.1 F C25 0.1 F C24 0.1 F C27 0.1 F C26 0.1 F C29 0.1 F C28 0.1 F C31 0.1 F C32 0.1 F C35 0.1 F
GND VDL + C67 10 F C44 0.1 F C42 0.1 F C41 0.1 F C15 0.1 F C37 0.1 F
GND DRVDD + C65 10 F C61 0.1 F C62 0.1 F C60 0.1 F C59 0.1 F C58 0.1 F VCLK C66 10 F GND C14 0.01 F VREF + C63 10 F VAMP + C49 10 F C48 0.1 F
GND
GND
GND
GND R15 100 R38 100
VCLK 1 E/D 2 NC 3 GND VCC 6 5 OUTPUT B 4 OUTPUT VCLK R21 100 P1 R22 100 GND VCLK R23 100 P2 R24 100
OPIN B
OPIN B
GND GND
GND
8 AD9430 1
7
6
R38 FOR VF561 CRYSTAL
U8
OUT-
5 OPTIONAL AMP 4 U10 OPIN
GND ENBL
2
IN+
VCC
GND
3
IN-
OPTIONAL XTAL
GND
GND VAMP OPIN
J6 R25 50 GND GND J3 VOL GND C38 .1U R30 0 C18 0.1U GND R28 50
C34 VOL 0.1U GND E4Z E40 E41 R44 GND C33 GND 0.1U 1k E39 E37 E38 R45 1k GND GND RZ12 9 10 36 35 34 33 32 31 11 12 13 14 15 16 R8 R7 R6 R5 R4 R3 R2 R1 220 RZ10 30 9 10 11 12 13 14 15 16 R8 R7 R6 R5 R4 R3 R2 R1 220 8 7 6 5 4 3 2 1 29 28 27 26 25 DY4 DY5 DY6 DY7 DY8 DY9 DY10 DY11 8 7 6 5 4 3 2 1 DYB DYA DY0 DY1 DY2 DY3 VOL GND VOL
R29 392
GND
R26 2k
48
47
46
45
44
43
42
41
40
39
38
VOL GND R31 1k C40 0.1U R32 1k C45 0.1U GND DX11 DX10 DX9 DX8 DX7 DX6 DX5 DX4 1 2 3 4 5 6 7 8
R43 1k R37 DRA 0 VOL C48 0.1U GND RZ9 R1 R2 R3 R4 R5 R6 R7 R8 220 RZ11 DX3 DX2 DX1 DX0 DXA DXB 1 2 3 4 5 6 7 8 R1 R2 R3 R4 R5 R6 R7 R8 220 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 GND
1 2 3 4 5 6
GND
AD9430
7 8 9 10 11 12
13
14
15
16
17
18
19
20
21
22
23
GND C35 0.1U
VOL
Figure 17b. Evaluation Board Schematic
-18-
GND
24
37
OUT+
4/01/2002 REV. PrG
PRELIMINARY TECHNICAL DATA AD9430
Figure 18. PCB Top Side Silkscreen
Figure 21. PCB Split Power Plane
Figure 19. PCB Top Side Copper
Figure 22. PCB Bottom Side Copper
Figure 20. PCB Ground Layer
Figure 23. PCB Bottom Side Silkscreen
REV. PrG 4/01/2002
-19-
PRELIMINARY TECHNICAL DATA AD9430
Troubleshooting
If the board does not seem to be working correctly, try the following: * Verify power at IC pins. * Check that all jumpers are in the correct position for the desired mode of operation. * Verify VREF is at 1.23 V. * Try running Encode Clock and Analog Inputs at low speeds (10 MSPS/1 MHz) and monitor 574, DAC, and ADC outputs for toggling.
The AD9430 Evaluation Board is provided as a design example for customers of Analog Devices, Inc. ADI makes no warranties, express, statutory, or implied, regarding merchantability or fitness for a particular purpose.
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
100-Lead TQFP (with Exposed Heat Sink) (TQFP-100)
0.030 (0.75) 0.024 (0.60) 0.018 (0.45)
0.047 (1.20) MAX
100 1
0.630 (16.00) SQ 0.551 (14.00) SQ
76 75 75 76 100 1
SEATING PLANE
BOTTOM VIEW
TOP VIEW
(PINS DOWN)
CONDUCTIVE HEAT SINK
25 26 49 50 50 49 26 25
0.006 (0.15) 0.002 (0.05)
0.041 (1.05) 0.039 (1.00) 0.037 (0.95)
0.260 (6.00) NOM CONTROLLING DIMENSIONS ARE IN MILLIMETERS. CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED.
0.0197 (0.50) BSC
0.011 (0.27) 0.009 (0.22) 0.007 (0.17)
7 0
NOTE: THE AD9430 HAS A CONDUCTIVE HEAT SLUG TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION OF THE DEVICE OVER THE FULL INDUSTRIAL TEMPERATURE RANGE. THE SLUG IS EXPOSED ON THE BOTTOM OF THE PACKAGE AND ELECTRICALLY CONNECTED TO CHIP GROUND. IT IS RECOMMENDED THAT NO PCB SIGNAL TRACES OR VIAS BE LOCATED UNDER THE PACKAGE THAT COULD COME IN CONTACT WITH THE CONDUCTIVE SLUG. ATTACHING THE SLUG TO A GROUND PLANE WILL REDUCE THE JUNCTION TEMPERATURE OF THE DEVICE WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS.
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4/01/2002 REV. PrG

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