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NCS8353 Stereo 20W/Ch Class D Audio Power Amplifier with Programmable Power Limit and Selectable Gain
The NCS8353 is a stereo Class D audio power amplifier capable of delivering a continuous power of up to 20 W/ch into an 8 W bridge tied load (BTL). It can be powered from the existing 24 V rail in Flat Panel Television (FPTV) systems. The high efficiency of the NCS8353, 86%, reduces the requirement of an external heat sink when driving high power. The digital power limit feature can program the output power limit at 10 W, 12 W, 15 W, or 20 W/ch, allowing the NCS8353 to be a single system solution in FPTV audio applications. The NCS8353 includes a digital power limit feature. The digital power limiter quickly reduces the internal gain of the amplifier when high amplitude signals would cause excessive clipping on the output. The NCS8353 minimizes pop and click artifacts in the audio system by reducing voltage and current transients during power supply cycling, entering or recovering from shutdown, and mute. The shutdown feature reduces the quiescent current draw of the amplifier to 100 mA typical. The mute feature ensures that audio is not present at the output during audio source switching. The gain of the NCS8353 is programmed via two gain pins, G0 and G1, allowing four selectable ranges: 20 dB, 26 dB, 32 dB, and 36 dB. Auto recovery short circuit and over temperature protection circuitry are incorporated to ensure device functionality after short circuit and high temperature events occur.
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32
QFN32 MN SUFFIX CASE 488AM
MARKING DIAGRAMS
1
NCS8353 AWLYYWWG G
A WL YY WW G
= Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
(Note: Microdot may be in either location)
* Powered from 8 V to 26 V to include FPTV Backlight Supply (24 V *
ORDERING INFORMATION
Device Package Shipping
* * * * * * *
5%) NCS8353MNTXG QFN32 2500 / Tape & Reel Digital Power Limiter Controlled by Two External bits: 10 W, 12 W, (Pb-Free) 15 W, or 20 W per Channel For information on tape and reel specifications, Allows for Maximum System Flexibility including part orientation and tape sizes, please Reduces Distortion with Excessive Inputs refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Pop and Click Suppression Selectable Gain: 20 dB, 26 dB, 32 dB, 36 dB High Efficiency Eliminates the Need for External Heat * Fully Differential Architecture Sink * This is a Pb-Free Device Low Supply Current: IQ = 100 mA Typical During Typical Applications Shutdown at 12 V * Flat Panel Television (FPTV) Mute Function * Powered Speakers Auto-recovery Short-Circuit Protection Over Temperature Protection
(c) Semiconductor Components Industries, LLC, 2011
February, 2011 - Rev. 2
1
Publication Order Number: NCS8353/D
NCS8353
VCLAMPR BSRP PVDDR ROUTP RINN Modulator RINP PGNDR BSRN PVDDR ROUTN PGNDR MUTE CONTROL TO OUTPUTS EN ENABLE CIRCUITRY Ramp Oscillator VCLAMPL BSLP PVDDL LOUTP LINP Modulator LINN PGNDL BSLN PVDDL LOUTN PGNDL
MUTE
G0 G1 P0 P1 FROM OUTPUTS AVREG AVDD Gain and Power Limit Select SHORT CIRCUIT PROTECTION FAULT OVER TEMPERATURE PROTECTION AVREG
AGND THERMAL PAD
Figure 1. NCS8353 Basic Connections
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NCS8353
PVDDR VCLAMPR 25 PGNDR ROUTN ROUTP PVDDR 26
32
31
30
29
28
PVDDR
1
27
BSRN
BSRP
24
ENABLE
RINN
2
23
AVDD
RINP
3
22
MUTE
G0
4 NCS8353
21
AVREG
G1
5
20
AGND
LINP
6
19
PL0
LINN
7
18
PL1
PVDDL
8 10 12 13 14 15 16 11
17
FAULT
9
Figure 2. Package Options
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VCLAMPL
BSLN
PVDDL
PGNDL
LOUTN
PVDDL
LOUTP
BSLP
NCS8353
1 mF
1 mF
220mF
22mH
22mH
1 mF
220pF
10W
10W
220pF
0.1 mF
1 mF 0.22 mF 1 mF 0.1 mF VCLAMPR PVDDR PVDDR BSRN BSRP PGNDR ROUTN ROUTP 0.22 mF
EN
PVDDR
1 mF RINN
10W
NCS8353
AVDD 1 mF MUTE
1 mF RINP G0 G1 LINP 1 mF
AVREG 1 mF AGND
PL0
LINN 1 mF
PL1
FAULT VCLAMPL 1 mF 0.1 mF 1 mF 220mF PVDDL PGNDL LOUTN PVDDL LOUTP PVDDL BSLN 0.22 mF 220pF 22mH 1 mF BSLP 0.22 mF 1 mF 0.1 mF
220pF
10W
10W
22mH
1 mF
Figure 3. Typical Application Connection for 8 W Speaker
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NCS8353
PIN FUNCTION AND DESCRIPTION
Pin# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Name PVDDR RINN RINP G0 G1 LINP LINN PVDDL PVDDL BSLP LOUTP PGNDL LOUTN BSLN PVDDL VCLAMPL FAULT PL1 PL0 AGND AVREG MUTE AVDD ENABLE VCLAMPR PVDDR BSRN ROUTN PGNDR ROUTP BSRP PVDDR Input/output Power Input Input Input Input Input Input Power Power - Output Ground Output - Power - Output Input Input Ground Output Input Power Input - Power - Output Ground Output - Power Power supply for right channel. Right Input - Negative. Right Input - Positive. LSB Gain Setting. MSB Gain Setting. Left Input Positive. Left Input Negative. Power supply for left channel. Power supply for left channel. Bootstrap for positive left speaker output. Positive Left Speaker Output. Power ground for left channel. Negative Left Speaker Output. Bootstrap for negative left speaker output. Power supply for left channel. Internal voltage supply for left channel bootstrap capacitor. TTL compatible output. Asserts HIGH during thermal shutdown or short circuit conditions. MSB - Power Limit. LSB - Power Limit. Analog ground reference. Regulator output voltage. TTL compatible input. Mutes the device when a logic HIGH is present. Analog high voltage supply. TTL compatible input. Enable for right and left channels when logic HIGH is present. Internal voltage supply for right channel bootstrap capacitor. Power supply for right channel. Bootstrap for right negative output. Negative right speaker output. Power ground for right channel. Positive right speaker output. Bootstrap for right positive output. Power supply for right channel. Description
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NCS8353
MAXIMUM RATINGS TABLE
Parameter Power Supply Voltage (PVDDR, PVDDL) Analog Supply Voltage (AVDD) Input voltage (ENABLE, G0, G1, RINN, RINP, LINN, LINP) Input voltage Mute function (MUTE) Output Current (ROUTP, ROUTN, LOUTP LOUTN) Maximum Junction Temperature Operating Ambient Temperature Storage Temperature Junction-to-Air Thermal Resistance QFN-32 (Note 1) Symbol PVDD AVDD Vin Vin IO TJ TA TSTG RqJA Rating 30 30 -0.3 V to AVreg -0.3 V to 3.6 V 4.7 150 -40 to +85 160 31.4 Unit V V V V A C C C C/W
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Board size: 5" x 4", 4-layer, 2 oz copper.
RECOMMENDED OPERATING CONDITIONS, TA = 25C unless otherwise noted
Specification Name Operating Supply Voltage Range Analog Supply Voltage range High-level input voltage Low-level input voltage High Level Output Voltage Low Level Output Voltage Internal Oscillator Frequency G0, G1, PL0, PL1, ENABLE, MUTE G0, G1, PL0, PL1, ENABLE, MUTE Fault, IOH = +1 mA Fault, IOL = -1 mA Conditions Symbol PVDD AVDD VIH VIL VOH VOL fOSC 315 AVREG - 0.4 AGND + 0.4 Min 8 8 2 3.3 Typ Max 26 26 3.6 0.8 Unit V V V V V V kHz
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DC ELECTRICAL CHARACTERISTICS, AVDD = PVDDR = PVDDL = 12 V, RL = 8 W, TA = 25C unless otherwise noted
Specification Name Differential Output Offset Voltage 5.0 V Internal Regulator Voltage input common mode range Quiescent Current Shutdown Quiescent Current On Resistance Drain to Source Gain Conditions Inputs AC GND, CIN = 1 mF, AV = 20 dB, Measured differentially No load, Creg = 1 mF Inputs AC coupled, CIN = 1 mF, Vbias = 2.15 V No load, No filter No load, No filter, ENABLE 0.8 V Io = 500 mA G0 = G1 0.8 V G0 0.8 V, G1 2 V G0 2 V, G1 0.8 V G0 = G1 2 V Gain Matching Turn on time Turn off time ROUTN / ROUTP, LOUTN / LOUTP ENABLE 2 V ENABLE 0.8 V tON tOFF Symbol VOSDIFF AVREG VICR IQ IQSHDN RDSon AV 19 25 31 35 4.5 AGND + 0.35 28 100 360 20 26 32 36 0.5 450 150 21 27 33 37 dB ms ms Min Typ 15 5 Max 50 5.5 AVREG - 1.35 42 200 Unit mV V V mA mA mW dB
DC ELECTRICAL CHARACTERISTICS, AVDD = PVDDR = PVDDL = 24 V, RL = 8 W, TA = 25C unless otherwise noted
Specification Name Differential Output Offset Voltage 5.0V Internal Regulator Voltage input common mode range Quiescent Current Shutdown Quiescent Current On Resistance Drain to Source Gain Conditions Inputs AC GND, CIN = 1 mF, AV = 20 dB, Measured differentially No load, Creg = 1 mF Inputs AC coupled, CIN = 1 mF, Vbias = 2.15 V PVDD = 24 V, No load, No filter PVDD = 24 V, No load, No filter, ENABLE 0.8 V IO = 500 mA G0 = G1 0.8 V G0 0.8 V, G1 2 V G0 2 V, G1 0.8 V G0 = G1 2 V Gain Matching Turn on time Turn off time ROUTN / ROUTP, LOUTN / LOUTP ENABLE 2 V ENABLE 0.8 V tON tOFF Symbol VOSDIFF AVREG VICR IQ IQSHDN rDS(on) AV 19 25 31 35 4.5 AGND + 0.35 33 100 360 20 26 32 36 0.5 450 150 21 27 33 37 dB ms ms Min Typ 15 5 Max 50 5.5 AVREG - 1.35 45 200 Unit mV V V mA mA mW dB
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NCS8353
AC ELECTRICAL CHARACTERISTICS, AVDD = PVDDR = PVDDL = 12 V, RL = 8 W, TA = 25C unless otherwise noted
Specification Name AC Power Supply Rejection Ratio Common Mode Rejection Ratio IEC Output Power Total Harmonic Distortion + Noise Efficiency Voltage noise (RTI) Crosstalk Signal to Noise Ratio Thermal trip point Thermal hysteresis Conditions No supply bypass, 200 mVpp ripple, fin = 1 kHz, AV = 36 dB Inputs shorted together, VIN = 32 mVpp, fin = 1 kHz, Av = 36 dB AV = 36 dB, THD+N = 1% AV = 36 dB, POUT = 1 W, fin = 1 kHz THD+N = 0.03%, POUT = 5 W Inputs AC GND thru 100 nF, AV = 20 dB, A-weighting Po = 1 W, fin = 1 kHz, AV = 36 dB VIN = 100 mVpp, Av = 20 dB Thermal Shutdown Symbol PSRRAC CMRRIEC Pout THD+N n Ven XTALK SNR TSD THS Min Typ -69 -55 7.5 0.05 85 100 -85 90 160 30 Max Unit dB dB W % % mVrms dB dB C C
AC ELECTRICAL CHARACTERISTICS, AVDD = PVDDR = PVDDL = 24 V, RL = 8 W, TA = 25 C unless otherwise noted
Specification Name AC Power Supply Rejection Ratio Common Mode Rejection Ratio (IEC) Output Power Total Harmonic Distortion + Noise Conditions No supply bypass, 200 mVpp ripple, fin = 1 kHz, AV = 36 dB VIN = 32 mVpp, fin = 1 kHz, Av = 36 dB AV = 36 dB, THD+N = 1% AV = 20 dB, POUT = 10 W (Max value from 20 Hz to 20 kHz) THD+N = 1%, POUT = 20 W Inputs AC GND thru 100 nF, AV = 32 dB, A-Weighting Po = 1 W, fin = 1 kHz, Av = 36 dB VIN =100 mVpp, fin = 1 kHz, Av = 36 dB Thermal Shutdown Ven XTALK SNR TSD THS Symbol PSRRAC CMRRIEC Pout THD+N Min Typ -69 -55 20 0.03 Max Unit dB dB W %
Efficiency Voltage noise (RTI) Crosstalk Signal to Noise Ratio Thermal trip point Thermal hysteresis
83 100 -85 90 160 30
% mVrms dB dB C C
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NCS8353
TYPICAL CHARACTERISTICS
1 VDD = 12 V AV = 36 dB RL = 8 W THD+N (%) 1 VDD = 24 V AV = 36 dB RL = 8 W 1W
0.1 THD+N (%) 1W
0.1
10 W 0.01
0.01
5W
20 W
0.001
1
10
100
1000
10000
100000
0.001 1
10
100
1000
10000
100000
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 4. THD+N vs. Frequency (BTL)
Figure 5. THD+N vs. Frequency (BTL)
100 10 THD+N (%) 1 0.1 0.01
VDD = 12 V AV = 36 dB RL = 8 W
10
Power Limit THD+N (%)
1
VDD = 24 V AV = 36 dB RL = 8 W
Power Limit
0.1
1 kHz
1 kHz
0.01 20 Hz 20 kHz 10 100 0.001 0.01 0.1
20 Hz 20 kHz 1 OUTPUT POWER (W) 10 100
0.001 0.01
0.1
1 OUTPUT POWER (W)
Figure 6. THD+N vs. POUT
Figure 7. THD+N vs. POUT
0 -20 -40 XTALK (dB) -60 -80 -100 -120 1
VDD = 12 V AV = 36 dB RL = 8 W PO = 1 W XTALK (dB)
0 -20 -40 L-R R-L -60 -80 -100 -120 1
VDD = 24 V AV = 36 dB RL = 8 W PO = 1 W
L-R R-L
10
100
1000
10000
100000
10
100
1000
10000
100000
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 8. Crosstalk L to R and R to L (20 Hz to 20 kHz)
Figure 9. Crosstalk L to R and R to L (20 Hz to 20 kHz)
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NCS8353
TYPICAL CHARACTERISTICS
0 -10 -20 XTALK (dB) -30 -40 -50 -60 -70 -80 -90 1 10 24 V 12 V 100 90 80 70 EFFICENCY 60 50 40 30 20 10 100000 0 0 5 10 15 POWER (W) AV = 20 dB RL = 8 W 20 25 24 V 12 V
AV = 36 dB RL = 8 W Vripple = 200 mVPP fripple = 1 kHz
100 1000 10000 FREQUENCY (Hz)
Figure 10. Crosstalk vs. Frequency
Figure 11. Efficiency vs. Pout
120 ms
450 ms
Figure 12. Turn-off Time - Mute Asserted
Figure 13. Turn-on Time - Mute De-asserted
450 ms
150 ms
Figure 14. Turn-on Time - Enable Asserted
Figure 15. Turn-off Time - Enable de-asserted
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NCS8353
APPLICATIONS INFORMATION
Digital Power Limiter
The NCS8353 utilizes a Digital Power Limiter (DPL) feature that limits the output power to 10 W, 12 W, 15 W, or 20 W per channel. This is achieved by the two external power limit pins, PL0 and PL1, which are TTL level compatible. If a change in power limit is desired, the NCS8353 must first be disabled followed by setting a new power limit. Finally, when the NCS8353 is re-enabled, the new power limit will be active. Table 1 illustrates the power limit per channel of the NCS8353 depending on the logic level of the power limit pins and is based on an 8 W speaker load.
Table 1.
PL1 0 0 1 1 PL0 0 1 0 1 Power Limit 10 W 12 W 15 W 20 W
The DPL reduces the internal gain of the NCS8353 thus reduces the output voltage to ensure the programmed power limit is not exceeded. Figure 17 illustrates the output voltage waveform after the DPL is activated.
VDD
Power Limit
GND
Figure 17. DPL Activated
Figure 16 shows a typical output waveform and a desired output power for an application. If the output waveform produces a higher output power than required; e.g., due to high input amplitudes, the DPL feature of the NCS8353 activates.
VDD
The DPL monitors the input referred voltage level and is dependent on the programmed gain of the NCS8353. Table 2, page 12, is a quick reference for the system designer to verify when the DPL will activate assuming an 8 W load. If the input voltage exceeds the input reference levels illustrated in Table 2, the DPL will activate. Figure 18 highlights the output power vs. input voltage for programmed power limits.
25 20 15 10 5 VCC = 24 V RL = 8 W AV = 36 dB
Required Power Pout (W)
PL = 20 W PL = 15 W PL = 12 W PL = 10 W
GND
Figure 16. Before DPL Operation
0 0.05
0.1 0.15 0.2 Vin, INPUT VOLTAGE (V)
0.25
Figure 18. Power Limiter vs. Vin
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NCS8353
Table 2. ALL POWER LIMITS AND VOLTAGES REFERENCED TO 8 W LOAD
Plimit AV 20 dB 26 dB 32 dB 36 dB 20 W 1.789 Vin(p) 894 mVin(p) 447 mVin(p) 284 mVin(p) 15 W 1.549 Vin(p) 775 mVin(p) 387 mVin(p) 246 mVin(p) 12 W 1.386 Vin(p) 693 mVin(p) 346 mVin(p) 220 mVin(p) 10 W 1.265 Vin(p) 632 mVin(p) 316 mVin(p) 201 mVin(p)
Programmable Gain Control
The NCS8353's 2-bit gain control can be programmed either by digital control or by bootstrapping the gain control pins, G0, G1, to logic HIGH or LOW and are TTL compatible inputs for soft programming needs. Reference the electrical characteristics table for minimum and maximum levels. The logic table shown in Table 3 highlights the amplifier gain settings in dB based on gain setting.
Table 3.
G1 0 0 1 1 G0 0 1 0 1 AMPLIFIER GAIN (dB) (Typ) 20 26 32 36
during the reset time of the protection circuitry. The hiccup mode is continuous until the short is removed.
Over Temperature Protection
The thermal protection circuitry of the NCS8353 monitors the maximum junction temperature of the die. When the temperature increases to 150C, the specified maximum junction temperature, the internal gain of the device is reduced until the junction temperature is approximately 130C. If the gain reduction is unable to limit the temperature rise of the junction then the thermal protection circuitry will completely disable the output stage once the junction temperature rises above 160C. The NCS8353 will re-enable the output stage when the junction temperature falls to 130C. This provides 30 of thermal hysteresis.
Enable
Similar to the DPL, if a change in gain is desired the NCS8353 must be disabled. The gain may then be programmed to the new desired level and then re-enabled for the new gain setting to latch.
Fault Detection
The NCS8353 incorporates fault detection circuitry. If a short circuit occurs the FAULT pin asserts logic HIGH providing the system designer an error flag for monitoring. The FAULT flag also asserts HIGH when the NCS8353 enters thermal shutdown. When the NCS8353 cools to 130C or once the short circuit condition is removed the FAULT flag returns LOW.
Short-Circuit Protection
The NCS8353 incorporates a single ENABLE control for right and left audio channels. When ENABLE is asserted logic LOW, the internal circuitry completely disables each channel to reduce quiescent current draw from the power supply. Typical shutdown current for the NCS8353 will be 100 mA typical per channel and start-up time from shutdown is typically 450 ms. See the electrical specification table for conditions. The ENABLE function also serves to latch new values for gain and the DPL. When new levels are desired the NCS8353 must be disabled, the new values must be programmed, and then re-enabled for the new values to latch. See Tables 1 and 3 for power limit and gain values.
Mute Function
A short can occur to VDD, VSS, or across the load. The short circuit protection circuitry will disable the output stage from delivering current to the load when a short is present. With the short circuit protection circuitry active the internal power dissipation will be minimized. The NCS8353's short circuit protection is analogous to a power supply's hiccup mode current limiting operation. When a short is detected the NCS8353 will disable the output stage and will attempt to re-enable the output stage after 180 ms. If the short has been removed then the output stage re-enables and operates normally; however, if the short is still present the cycle begins again. Internal heat dissipation is kept to a minimum as current will only flow
The MUTE function will ensure any audio signal present at the input is inaudible at the speaker load. The right and left channels are not in shutdown during this time. During the MUTE state, the outputs will continue to switch at 50% duty cycle; however, a modulated audio signal will not be present. The MUTE function is activated with a logic HIGH signal and deactivated with a logic LOW signal.
Pop and Click Suppression
Pop and click is often a function of charge difference from input coupling and bypass capacitors, momentary differential offset voltages across the speaker, or state changes of the input source (codec) that cause an abrupt change in current to flow through the loudspeaker. In all
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NCS8353
cases these pop and click phenomena occur during the following power sequences: * Power supply power-up or power down (codec or amp). * Entering or releasing from shutdown/mute (codec or amp). * State changes in the audio codec; e.g., switching between audio sources. Due to the voltage changes in the audio signal chain a momentary current will flow through the loudspeaker. When current flows through the voice coil of a loudspeaker it causes the diaphragm to move thus causing a popping and clicking sound. The NCS8353 includes pop and click suppression circuitry that creates a slow ramp to bias the amplifier during the previously mentioned power sequences. In order to eliminate "pop and click" noises during transition, the output power in the load must not be established or cutoff suddenly. When logic high is applied to the shutdown pin, the internal biasing voltage rises quickly and once the output DC level is around the common mode voltage, the gain is established slowly. This method to turn on the device is optimized in terms of rejection of "pop and click" noises. The device has the same behavior when it is turned-off by a logic low on the shutdown pin. No power is delivered to the load 150 ms after a falling edge on the shutdown pin. Due to the fast turn on and off times, the shutdown signal can be used as a mute signal as well.
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NCS8353
PACKAGE DIMENSIONS
QFN32, 5x5x1, 0.5P CASE 488AM-01 ISSUE O
A B
NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM TERMINAL 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS MIN NOM MAX 0.800 0.900 1.000 0.000 0.025 0.050 0.200 REF 0.180 0.250 0.300 5.00 BSC 2.950 3.100 3.250 5.00 BSC 2.950 3.100 3.250 0.500 BSC 0.200 --- --- 0.300 0.400 0.500
D
PIN ONE LOCATION
2X 2X
0.15 C 0.15 C 0.10 C
32 X
0.08 C L
32 X
8
1 32 X b 0.10 C A B 32 25
0.05 C BOTTOM VIEW
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
EE EE
9
E
TOP VIEW
(A3) A SIDE VIEW A1 C
EXPOSED PAD 16 SEATING PLANE
DIM A A1 A3 b D D2 E E2 e K L
SOLDERING FOOTPRINT*
5.30 3.20 0.63
32 X
D2
K
17 32 X
E2
24
3.20
5.30
e 0.28
32 X
0.50 PITCH
28 X
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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NCS8353/D

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