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| (R) APPLICATION BULLETIN Mailing Address: PO Box 11400 * Tucson, AZ 85734 * Street Address: 6730 S. Tucson Blvd. * Tucson, AZ 85706 Tel: (602) 746-1111 * Twx: 910-952-111 * Telex: 066-6491 * FAX (602) 889-1510 * Immediate Product Info: (800) 548-6132 BURR-BROWN SPICE BASED MACROMODELS, REV. F By Hubert Biagi, R. Mark Stitt, Bonnie Baker, and Stephan Baier INTRODUCTION Computer based simulation has an importance because it can significantly reduce the development time and therefore speed up the time-to-market process. The increased use of SPICE based simulation software has created a rising demand for accurate models. Such models, or macromodels, should reflect the actual performance of the component, but without carrying the burden of too many circuit details, which can lead to convergence problems. BURR-BROWN has responded to this need and provides macromodels for a broad range of semiconductor products. This Application Bulletin, and the accompanying disk is a collection of SPICE models of BURR-BROWN op amps, difference amps, instrumentation amps, isolation amps, and analog function circuits. There are four different levels of model topologies used, which are: Level I: Standard Macromodel Level II: Enhanced Macromodel Level III: Multi-Pole/Zero Macromodel Level IV: Simplified Circuit Model * The standard op amp macromodels were derived using the MicroSim Corporation PSpice(R) PartsTM simulation software. A detailed description on this macromodel type is given in Section A. * The second level of macromodel is an enhanced version of the standard model, which is indicated by the suffix "E" in the model's name. This model type is included to offer the circuit designer a model with a higher level of accuracy. See Section B for details. * The Multiple-Pole/Zero macromodel uses the same input stage as the standard or enhanced op amp macromodel, but has multiple poles and pole/zero pairs in the mid-section. This model has the designation "M", and was used for wide bandwidth op amps and function circuits where this topology showed an advantage over the standard topology. For a detailed description see Section C. * In some instances, a fourth type of model is available, which are designated by either an "X", "X1", or an "X2" suffix. The model of this level is not a macromodel, but rather a simplified circuit model at the transistor level. The Here, the Standard macromodels (Level I) are found in the STD_MOD subdirectory. The Enhanced macromodels (Level II) are found in the ENH_MOD subdirectory. The Multi-Pole/Zero macromodels (Level III) are found in the MPZ_MOD subdirectory, and the Simplified circuit models (Level IV) are found in the CIR_MOD subdirectory. Examples of model files are shown in Table I. This application bulletin and the macromodel disk are being revised frequently. To obtain the latest revision please contact your nearest sales office. Each model net-list starts with a header containing the part number, revision information, and the license statement. It should be noted that the disk contains only the net-lists of the macromodels, and does not provide the simulation software that allows the user to run the models. The structure of the net-lists conforms to the standard SPICE format, which most SPICE based simulators will accept. Please refer to the individual software manual if conflicts are encountered. Burr-Brown also welcomes any comments, which may be sent to the Applications Department at the address given above. FILE NAME OPA111.MOD OPA111E.MOD OPA671M.MOD OPA603X.MOD DESCRIPTION OPA111 OPA111 OPA671 OPA603 Standard Op Amp Macromodel Enhanced Op Amp Macromodel Multiple Pole/Zero Macromodel Simplified Circuit Model simplified circuit models produce the most accurate simulation results, but because of the complexity, require longer simulation time. See Section D for a detailed discussion on these models. For a complete overview of all available macromodels on the disk see Table XI on the last page. DISKETTE INFORMATION The disk has four different subdirectories, in which the models are organized according to their topology level: A:\ CIR_MOD ENH_MOD MPZ_MOD STD_MOD TABLE I. Examples of Files on Macromodel Disk. PSpice(R) PartsTM, MicroSim Corp. (c) 1990 Burr-Brown Corporation AB-020F Printed in U.S.A. January, 1995 GENERAL INFORMATION Throughout this application bulletin and the net-lists of the macromodels, standard definitions and designators are used. As a reference they are listed in the following tables. Table II and Table III specifically refer to the Standard and the Enhanced macromodel only. Listed in Table IV are the definitions for all used component prefixes. COMPONENT C1 C2 CEE, CSS DP EGND FB G11,G21 GA GCM DESCRIPTION Phase-Control Capacitor Compensation Capacitor Slew-Rate Limiting Capacitor Substrate Junction Voltage-Controlled Voltage Source Output Device (Controlled by the Current Through VB, VC, VE, and VLP, VLN) Input Bias Current Correction Interstage Transconductance (Controlled by Differential Voltage at the Input Device Loads) Common-Mode Transconductance (Controlled by the Common-Mode Voltage at the Input Device Emitters or Sources) Input Stage Current Voltage-Limiting Device JFET Input Transistors Bipolar Input Transistors Interstage Resistance Input-Stage Load Resistance Input-Stage Load Resistance Input-Stage Emitter Resistance Input-Stage Current-Source Output Resistance Output Resistors Power Dissipation Resistor Independent Voltage Source Output Offset Limiter (to V+) Output Offset Limiter (to V-) Output Current Limiting Sensor Negative Supply Limit Positive Supply Limit PREFIX C D E F G H I J Q R S V DEFINITION Capacitor Diode Voltage-Controlled Voltage Source Current-Controlled Current Source Voltage-Controlled Current Source Current-Controlled Voltage Source Independent Current Source or Stimulus JFET Transistor Bipolar Transistor Resistor Voltage-Controlled Switch Independent Voltage Source or Stimulus TABLE IV. Macromodel Component Prefix Definitions. LIMITATIONS These macromodels are intended to help designers simulate typical amplifier performance. The macromodels were compiled using data sheet typical specifications. Where data sheet specifications were not available, typical measured values or design values were used. Macromodels were verified with several standard simulations such as gainphase and large- and small-signal transient response. In some cases, adjustments were made to the macromodels so simulations with the macromodel more closely agreed with actual measured typical performance. Since these macromodels only simulate the typical performance of certain selected specifications, they will not predict actual device performance under all conditions. Good design practice dictates that, in addition to simulation with macromodels, circuit verification must include: 1) worst case analysis with data sheet minimum and maximum room temperature specifications 2) worst case analysis with variation of specifications over the operating temperature range 3) thorough breadboard evaluation 4) complete prototype characterization IEE, ISS HLIM J1, J2 Q1, Q2 R2 RC1, RC2 RD1, RD2 RE1, RE2 REE, RSS RO1, RO2 RP VB VC, DC VE, DE VLIM VLN, DLN VLP, DLP TABLE II. Op Amp Macromodel Components for the Standard and Enhanced Macromodels. BURR-BROWN SYMBOL V+, V- MACROMODEL DESIGNATION +VPWR, -VPWR +VOUT, -VOUT +SR -SR Pd IB Av-dc F-0dB CMRR Phi Ro-dc Ro-ac Ios Cc DEFINITION Positive, Negative Power Supply Max Positive, Negative Output Swing Positive-Going Slew Rate Negative-Going Slew Rate Quiescent Power Dissipation Input Bias Current DC Open-Loop Voltage Gain Unity-Gain Frequency Common-Mode Rejection Ratio Phase Margin at F-0dB () DC Output Resistance AC Output Resistance Short-Circuit Output Current Compensation Capacitance SR+ SR- IB AOL UGBW CMRR oM rO zO ISC CC DUAL AND QUAD OP AMPS All op amps are modeled as single devices. To model duals or quads, use two or four models. Quiescent current for the dual or quad op amp macromodel is the dual or quad op amp quiescent current divided by two or four. INSTRUMENTATION AMPLIFIERS AND DIFFERENCE AMPLIFIERS Instrumentation amplifier and difference amplifier macromodels use standard op amp macromodels plus additional components as shown in Figures 1 and 2. There are two types of models used for difference amplifiers. They are the four-resistor difference amplifier and the five-resistor difference amplifier. FOUR-RESISTOR DIFFERENCE AMPLIFIER The four-resistor difference amplifier macromodel, used for the INA105, INA106, and the difference amplifier section in all instrumentation amplifier macromodels, is shown in 2 TABLE III. PSpice Parts Inputs for Standard and Enhanced Marcomodels. Figure 1a. The circuit uses an op amp and four matched resistors. If R2/R1 = R4/R3, GAIN = R2/R1 and CMR = . To simulate DC CMR error, R2 is set 0.01% low. CMR for a four resistor difference amplifier is: CMR = -20 LOG10 [(%/100) * R1/(R1 + R2)] Where: % = % error in any resistor. With a 0.01% resistor error, DC CMR for the INA105 unity gain difference amplifier is 86dB, and DC CMR for the INA106 gain-of-ten difference amplifier is 100.8dB. To simulate AC CMR error, a small value capacitor, C2, is placed in parallel with R2 to roll-off of CMR with increasing frequency. V+ 2 -In 3 R5 Ref B 9 A3 5 4 +In 1 R3 14 V- R4 Ref A 8 Ref C2 VO R1 13 R2 FIGURE 1b. INA117 High Voltage Difference Amplifier Macromodel and Node Assignments. V+ 2 -In 3 C2 A3 4 +In 1 R3 14 V- R4 8 Ref 5 VO R1 13 R2 9 Sense V+ 2 A1 R1 9 R FB1 11 3 -In C2 13 R2 R G1 RG C C1 C C2 A3 5 VO FIGURE 1a. Difference Amp Macromodel and Node Assignments. FIVE-RESISTOR DIFFERENCE AMPLIFIER The five-resistor difference amplifier macromodel used for the INA117 is shown in Figure 4b. The advantage of the five-resistor difference amplifier configuration is a boost in input common-mode-voltage range for a given op amp common-mode range. The circuit uses an op amp and five matched resistors. If (R2 || R5)/R1 = R4/R3, GAIN = R2/R1 and CMR = . To simulate DC CMR error, R4 is set 0.005% low. For errors in R4, the CMR for a five-resistor difference amplifier is; CMR = -20 LOG10 [(%/100) * R1/(R1 + R4)] Where: % = % error in R4 R2 || R5 = R2 * R5/(R2 + R5) With a 0.005% resistor error, DC CMR for the INA117 high common-mode-voltage unity-gain difference amplifier is 86.5dB. Note that unlike the four resistor difference amplifier, the sensitivity of DC CMR to errors in resistor value is different for different resistors. To simulate AC CMR error, a small value capacitor, C2, is placed in parallel with R2 to roll-off of CMR with increasing frequency. R G2 10 R FB2 12 R3 14 R4 8 Ref A2 +In 1 4 V- FIGURE 2. Standard Instrumentation Amplifier Macromodel and Node Assignments. FIGURE 1a 1b 2 3 4 5 6 DESCRIPTION Difference Amp Macromodel Node Assignments INA117 Difference Amplifier Macromodel Instrumentation Amp Macromodel Node Assignments INA103 Macromodel and Node Assignments INA118 Macromodel and Node Assignments INA110 Macromodel and Node Assignments INA120 Internal Gain Setting Resistor Connections TABLE V. Figure Reference. 3 V+ 3 + I1 I2 15 17 +In 2 16 CC1 Q2 9 RG 10 I3 I4 D2 12 CC2 A2 RFB2 R3 14 R4 8 Ref R FB1 11 C2 A3 5 VO D1 A1 R1 R CE Q1 R G1 13 R2 V1 1 -In R G2 4 V- FIGURE 3. INA103 Current-Feedback Instrumentation Amplifier Macromodel and Node Assignments. V+ 3 + I1 IB1 17 +In 2 16 CC1 Q2 9 RG 10 12 CC2 CG1 CG2 D2 A2 RFB2 R3 14 R4 8 Ref R FB1 11 C2 A3 5 VO I2 15 I B2 D1 A1 R1 R CE Q1 R G1 13 R2 V1 1 -In R G2 0 IBAL 4 (V-) GND FIGURE 4. INA118 Instrumentation Amplifier Macromodel and Node Assignments. 4 V+ 3 + I5 I6 I1 I2 15 21 16 +In -In 1 R G1 2 22 R CE J1 J2 Q1 Q2 9 CC1 R FB1 11 R1 13 R2 17 D1 A1 V1 C2 A3 5 VO RG R FB2 10 R G2 C G1 C G2 CC2 I3 I4 D2 A2 12 R3 14 R4 C4 8 Ref 4 V- FIGURE 5. INA110 Current-Feedback FET-Input Instrumentation Amplifier Macromodel and Node Assignments. V+ -In A1 G4 G5 INA120 INTERNAL GAIN CONNECTIONS(1) GAIN 1 10 100 1000 G4-G5 G4-G5 G4-G8 G4-G8 CONNECT G14-G15 G11-G14-G15 G11-G14 G11-G14 R FB 20k R1 R2 2k G8 G10-G15 G9-G15 44 G9 400 G10 2k 20k G14 G11 G15 A2 +In R3 R4 R FB Ref A3 VO NOTE: (1) "G" numbers are also package pin numbers. V- FIGURE 6. INA120 Internal Gain-Setting Resistor Connections. 5 SECTION A: STANDARD MACROMODELS The standard op amp macromodels were created by running the PSpice(R) PartsTM Simulation software on an IBM-compatible PC. This software uses the standard Boyle op amp model(1). The PSpice manual available from Microsim(2) contains a detailed discussion of each of the elements used in the macromodels. Op amp macromodels use the node assignments shown in Figures A1 to A6. The FET-input amplifiers using the standard PSpice Parts topology are shown in Figures A3 and A4. The node assignments for the standard PSpice Part op amp macromodels with bipolar-inputs are shown in Figures A5 and A6. Figure A1 shows the external op amp node assignments. Tables II, III and IV list component prefix designations, macromodel component descriptions, and PSpice INPUT designations used for the standard and enhanced models. The parameters that are modelled by the standard macromodels are listed in Table X. 2 -In +In 1 V+ 3 5 VO 4 V- FIGURE A1. Node Assignments for Standard and Enhanced Op Amp Macromodels. FIGURE A1 A2 A3 A4 A5 A6 DESCRIPTION Op Amp Node Assignments OPTxxx Node Assignments N-Channel JFET-Input Op Amp P-Channel JFET-Input Op Amp NPN Bipolar-Input Op Amp PNP Bipolar-Input Op Amp TABLE VI. Standard Macromodels Figure Reference. R FB 4 CFB V+ 1 2 DPHOTO 8 3 RPHOTO CPHOTO A1(1) VO V- ROUT 5 NOTE: (1) Use Boyle model illustrated in Figure A4. FIGURE A2. OPT-Standard Macromodel. 3 V+ DLN RD1 C1 11 +In 1 RO2 -In 2 J1 10 See Table II, for a more detailed description of the components. RD2 RP DP HLIM + 90 DLP 92 91 + VLN + + VC 53 12 VLP 7 VLIM + 8 RO1 6 GCM 9+ GA 5 DC VO DE 54 J2 RSS FB C2 99 R2 CSS + EGND VB + VE V- 4 ISS FIGURE A3. N-Channel JFET-Input Op Amp Standard PSpice Parts Macromodel. (1) For more information, see: G.R. Boyle, B.M. Cohn, D.O. Pederson, and J.E. Solomon, "Macromodeling of Integrated Circuit Operational Amplifiers," IEEE Journal of Solid-State Circuits, SC-9, 353 (1974). (2) MicroSim Corporation, 20 Fairbanks, Irvine, CA 92718 USA, (714) 770-3022, (800) 245-3022. 6 3 V+ ISS RP DP DLN HLIM + 10 +In 1 -In 2 J1 C1 11 See Table II, for a more detailed description of the components. 92 91 + VLN + + VC 53 90 DLP 7 VLP VLIM + 8 RO1 5 DC VO DE 54 J2 RSS CSS RO2 FB C2 6 R2 9 EGND + VB GCM GA 12 RD2 99 + + VE V- 4 RD1 FIGURE A4. N-Channel JFET-Input Op Amp Standard PSpice Parts Macromodel. 3 V+ DLN RC1 C1 11 +In 1 7 -In 2 13 RE1 Q1 Q2 14 RE2 REE RO2 99 R2 CEE + See Table II, for a more detailed description of the components. RC2 RP DP HLIM + 90 DLP 92 91 + VLN + + VC 53 12 VLP + VLIM 6 GCM 9 GA 8 RO1 5 DC VO DE 54 FB C2 + VB 10 IEE EGND + VE V- 4 FIGURE A5. NPN-Input Op Amp Standard PSpice Parts Macromodel. 3 V+ DLN RP IEE 10 RE1 +In 1 -In 2 Q1 C1 11 RC2 12 RC2 V- See Table II, for a more detailed description of the components. DP HLIM + 90 DLP 92 91 + VLN + + VC 53 DC 8 RO1 5 VO DE 54 VLP 7 VLIM + RE2 14 Q2 99 + EGND REE CEE RO2 FB R2 9 C2 6 13 GCM GA + VB + VE 4 FIGURE A6. PNP-Input Op Amp Standard PSpice Parts Macromodel. 7 SECTION B: ENHANCED MACROMODELS The enhanced version, "E", of the standard PSpice Parts model contains several additional performance features. All of the macromodels using this topology are in the ENH_MOD subdirectory on the disk. The FET-input amplifiers using the standard PSpice Parts topology plus enhancements are shown in Figures B1 and B2. The node assignments for the enhanced op amp macromodels with bipolar-inputs are shown in Figures B3 and B4. Figure A1 shows the external op amp node assignments. Tables II, III, and IV list component prefix designations, macromodel component descriptions, and PSpice INPUT designations used for the standard and enhanced models. The parameters that are modelled by the enhanced macromodels are listed in Table X. Additions and changes to the standard PSpice Parts macromodel to the enhanced version are discussed in the following text. FIGURE B1 B2 B3 B4 B5 B6 B7 DESCRIPTION N-Channel JFET-Input Op Amp P-Channel JFET-Input Op Amp NPN Bipolar-Input Op Amp PNP Bipolar-Input Op Amp OPA27/37 Input Protection OPA77/177 Input Protection INA114/118 Input Protection Circuitry Input Current Correction One feature that Burr-Brown offers with the enhanced model type is accurate simulation of input bias current for N-Channel JFET and P-Channel JFET operational amplifiers. Mathematically, the input bias current for JFET op amps should equal twice the IS of the JFET model. However, simulation will show that the gate current from J1 and J2 in Figures A3 through B2 is between 10 to 20pA larger than expected, depending on the common-mode voltage of the input stage and the magnitude of the supply voltages, if G11 and G21 are not included in the model. This additional current is generated from the drain-to-gate and source-to-gate nodes of the input FETs of the operational amplifier, which manifests itself as the bias current of the amplifier. The additional current is caused by the Spice default value, GMIN. In this case, 1/GMIN is the impedance between the drain and gate and the source and gate. This is done by Spice to keep the gate node of each FET from floating. The default value, or GMIN is 1E-12 . The voltage dependent current sources, G11 and G21 remove this error current from the model, hence the macromodel models input bias current correctly. This technique is used in all of the FET-enhanced and multiple pole/zero macromodels. To improve simulation accuracy the .OPTIONS statement should include ABSTOL = 100fA or 10fA. Noise Most of the enhanced JFET-input macromodels model device current noise and voltage noise. The current noise is modeled using RN1, RN2, RN3, RN4, RN5 and RN6 to create the noise source and the voltage-dependent current sources, G11 and G21, to model the noise on the inverting and non TABLE VII. Enhanced Macromodels Figure Reference. 3 V+ RD1 RD2 C1 11 1 CDIF -In 2 J1 10 C2CM C1CM -+ EN 64 J2 RSS RO2 99 R2 CSS + EGND 9+ VB C2 6 GCM GA 12 DP RQ FQ1 DLN HLIM + 90 DLP 7 FB + 92 91 + VLP VLIM 8 RO1 DE 54 + VE 5 VLN + + VC 53 DC VO +In G11 G21 ISS DQ2 FQ3 VQ2 FQ2 4 V- 22 + 21 + See Table II, for a more detailed description of the components. 20 DQ1 VQ1 FIGURE B1. N-Channel JFET-Input Op Amp Enhanced PSpice Parts Macromodel. 8 inverting inputs of the amplifiers. The voltage noise is modelled using DN1, DN2, VN1 and VN2 to create the noise source and EN to model the noise on the non-inverting input of the amplifiers. Input Capacitance Differential and common-mode input capacitors, CDIF, C1CM, and C2CM have been added to the enhanced macromodels. Input capacitance could also be modeled by including capacitor coefficients in the transistor models. Instead, discrete capacitors were used so the comparison to the standard model would be more obvious. Input Protection Diodes If an op amp contains input protection diodes, its enhanced op amp macromodel also contains diodes connected between the input pins as shown in Figures B5 and B6, for example. Quiescent Power RP was replaced by RQ. The value of RQ is higher. It models only the resistive portion of quiescent current. The current sources described below model the constant portion of the quiescent current. This technique provides a more accurate model of quiescent current vs power-supply voltage. 3 DLN FQ1 HLIM + 90 DLP 7 92 91 + VLP VLIM + 8 RO1 6 R2 9 + EGND FQ2 V- 4 + VB GCM GA DE 54 + VE 53 DC 5 VO VLN + V+ + VC ISS DP RQ 10 +In CDIF -In 2 C2CM C1CM 11 R J1 C1 12 RD2 99 1 - EN + 64 J2 RSS CSS RO2 FB C2 G11 G21 D1 FQ3 DQ2 20 DQ1 22 + 21 + VQ2 See Table II, for a more detailed description of the components. VQ1 FIGURE B2. P-Channel JFET-Input Op Amp Enhanced PSpice Parts Macromodel. 3 DLN RC1 11 1 +In CDIF 2 C2CM C1CM 13 Q1 Q2 14 RE2 REE RO2 99 + CEE EGND R2 9 + VB FQ2 V- DQ2 FQ3 22 + 21 + DQ1 VQ1 VQ2 4 C2 6 GCM GA RC2 C1 12 DP RQ FQ1 HLIM + 90 DLP 7 FB 92 91 + VLP VLIM + 8 RO1 DE 54 + VE 53 DC 5 VO VLN + V+ + VC -In RE1 10 IEE See Table II, for a more detailed description of the components. 20 FIGURE B3. NPN-Input Op Amp Enhanced PSpice Parts Macromodel. 9 3 DLN IEE DP RQ FQ1 HLIM + 10 RE1 +In -In C2CM 1 CDIF 2 C1CM 11 RC1 Q1 C1 12 RC2 VQ2 Q2 99 13 RE2 14 REE CEE RO2 FB R2 9 EGND FQ2 V- FQ3 20 See Table II, for a more detailed description of the components. 92 91 + VLN + V+ + VC 53 DC 8 RO1 5 VO DE 54 90 DLP VLP 7 VLIM + C2 6 GCM GA + + VB + VE DQ2 22 + 21 + 4 DQ1 VQ1 FIGURE B4. PNP-Input Op Amp Enhanced PSpice Parts Macromodel. Output Current Flowing from the Power-Supply Nodes A number of components were added so that both load and quiescent current flow from the power supply nodes. FQ3 mirrors the current flowing from VLIM. Positive current from FQ3 flows through DQ1 into VQ1. Negative current from FQ3 flows through DQ2 into VQ2. FQ1 supplies constant portion of IQ plus mirrors positive output current, which is measured by VQ1. FQ2 supplies constant portion of IQ plus mirrors negative output current, which is measured by VQ2. V+ X1.S21 NOTE: The enhanced op amp macromodels are more complicated and require more simulation time than the standard macromodels, but will provide more accuracy in simulations in some applications. 3 V+ X1.VS11 X1.FS22 X1.FS11 X1.S11 2 -In Protection circuitry for the inverting input. 2 -In D1N1 +In D1N2 3 5 VO 4 V- X1.FS12 4 V- 3 V+ X1.FS21 X1.VS21 1 FIGURE B5. Input Protection Diode Circuitry Used on OPA27/37 Enhanced Macromodels. IN N -In D1B VD1 D1A +In IN P 1 V- D2A VD2 D2B 4 R 1IN 5 VO R 2IN V+ 2 3 X2.VS11 X2.FS22 X2.FS11 X2.S11 1 +In X2.S21 X2.FS12 4 V- X2.FS21 X2.VS21 Protection circuitry for the non-inverting input. FIGURE B6. Input Protection Circuitry Used on OPA77/177 Enhanced Macromodels. 10 FIGURE B7. Input Protection Circuitry Used on INA114/118 Enhanced Macromodel. SECTION C: MULTIPLE-POLE/ZERO MACROMODELS The multiple pole/zero ("M") macromodel allows modeling of more than two poles and any additional zeros in the op amp macromodel. All of the macromodels using this topology are in the MPZ_MOD subdirectory on the disk. The input stage of this model is similar to the standard and enhanced op amp macromodels; however, after the input stage that similarity disappears. By using various circuit topologies the gain stages, pole stages, zero stages and pole/ zero stages are constructed. The number of each of these stage types is dependent on the performance characteristics of the amplifier being modelled. An effort is made to match the macromodel performance as closely as possible to the tested gain/phase of the op amp. The output stage also offers improvements in current steering from the supply voltages. This model type is typically used to model high-speed amplifiers; however, it has come in useful when modelling function circuits that require special considerations. FIGURE C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 DESCRIPTION N-Channel JFET-Input Op Amp P-Channel JFET-Input Op Amp NPN Bipolar-Input Op Amp PNP Bipolar-Input Op Amp Gain-, Pole/Zero, and Output Stages ACF2101M-Op Amp Section ACF2101M-Node Assignments OPA675M/676M-Input Stage OPA675M/676M-Package and Pad Parasitics VCA610M-Macromodel TABLE VIII. Multi Pole/Zero Macromodels Figure Reference. 7 R13 15 -In 2 J11 R11 IOS CDIFF 1 R12 +In 3 G12 ISS 4 G11 14 - + VA - R14 16 J12 + 13 V+ C12 EOS V- FIGURE C1. Input Stage to the N-Channel JFET-Input Op Amp Multiple Pole/Zero Macromodel. 7 ISS 14 R15 17 2 -In R11 IOS CDIFF 1 R13 +In G11 V- G21 3 EOS 4 - + 15 + VA R13 - J1 C12 J2 V+ R16 18 13 16 R14 FIGURE C2. Input Stage to the P-Channel JFET-Input Op Amp Multiple Pole/Zero Macromodel. 11 7 R3 V+ R4 VA +- 11 C1 Q1 R5 Q2 R6 10 -In R1 4 IOS CDIFF R2 +In EOS IEE 10 V- FIGURE C3. Input Stage to the NPN-Input Op Amp Multiple Pole/Zero Macromodel. V+ 7 ICC 12 +In 3 R1 IOS CDIFF 10 R2 -In 2 13 C1 R3 R4 4 V- Q1 VA +- 14 Q2 11 - EOS R5 + R6 15 16 FIGURE C4. Input Stage to the PNP-Input Op Amp Multiple Pole/Zero Macromodel. The accuracy of this model topology compared to the standard and enhanced model topologies is improved for high speed amplifiers primarily because of the improved gain/ phase performance. Assuming no convergence problem exists with the macromodels discussed so far, the time taken for Spice to produce the dc operating point calculation of the multiple pole/zero model is about twice the time required for the standard model. For transient analysis using this model, simulation time can be reduced by using the .OPTION statement to increase the number of transient iterations from 10 to 40. The proper Spice command is: .OPTIONS ITL4=40 The basic topology of input stages of this op amp model are shown in Figures C1, C2, C3, and C4. The input stage is the only section in the macromodels that differ between the four types of op amps (N-Channel FET, P-Channel FET, NPN Bipolar, and PNP Bipolar). The remainder of the macromodel circuit (gain stages, phase stages, CMRR stage, and output stage) is shown in a generic form in Figure C5. A summary of the parameters modelled is listed in Table X. 12 7 V1 G1 D1 VA R7 + C2 R9 23 D2 G2 V2 VA R8 + C3 9 R10 4 Gain Stage VH Reference 7 + C4 G5 (V12 - V16) R12 V12 R13 R16 V13 R17 G6 (V12 - V16) G8 (V17 - V16) R15 L1 L3 + G3 (V11 - V16) R11 G7 (V17 - V16) R19 V14 G9 (V13 - V16) R21 C6 V15 R20 G10 (V13 - V16) R22 C7 + G4 (V11 - V16) R14 + C5 R18 L2 L4 4 Pole/Zero Stage fp < fz Zero/Pole Stage fz < fp Common-Mode Gain Stage with Zero Pole Stage V+ 7 D5 D3 D6 G11 (V7 - V15) V3 VO (From Previous Stage) V15 D4 V4 R23 L5 Output Intermediate Output Node 7 D7 4 G14 (VO - V15) G13 (V15 - VO) D8 G12 (V15 - Vp) R24 4 V- Correction Current Sources Output Stage FIGURE C5. Multiple Pole/Zero Macromodel without Input Stage. Refer to Figures C1 Through C4 for Input Stage Topology. 13 V+ 7 R13 C12 15 2 -In J11 16 13 J12 D21 21 30 3 +In ISS 30 4 7 G91 R91 6 21 6 94 D92 G92 R92 D95 G95 95 G96 D96 4 D93 D94 V22 14 VOS D22 23 G22 C23 R28 R10 V- 71 V21 22 3 G22 C22 R27 30 R14 IPS RPS R9 D91 FIGURE C6. Op Amp Section of the ACF2101 Using the Multiple Pole/Zero Macromodel Topology. 37 Cap SH1 2 SH2 3 Com CINT SR 32 6 Sw Out 33 Sw Com 31 Sw In FIGURE C7. Node Assignments for ACF2101 Macromodel. The multiple pole/zero topology is used to model the op amp section of the ACF2101 switched integrator. The node assignments for this model are shown in Figure C6 and C7. The transient time of the switches (HOLD, RESET, and SELECT) should be programmed to have a slew of 6V/s. Complying with this requirement will give the user greater success in convergence during transient analysis, and a more accurate emulation of the effect of the 200ns switching speed of the actual switching transistors in the ACF2101. This is easily implemented with the PULSE command in Spice. Also, to insure proper operation, always establish the initial bias point for the transient analysis with RESET and HOLD equal to the potential of COMMON (node 3). 14 7 +V R3 C1 110 111 R4 -InA 102 Q1 114 Q2 113 115 +InA -InB 202 Q1-2 214 Q2-2 213 +InB 116 C11 216 C12 13 RSW1 997 VTTL1 CSW1 IEE -V 10 11 Q11 999 Q12 998 RSW2 996 CSW2 VTTL2 12 Cha FIGURE C8. Input Stage of the OPA675 and OPA676 Switched-Input Op Amp Using the Multiple Pole/Zero Macromodel Topology. 2 (15) -In CM1 LM CM2 108 (201) Ideal OPA 675/676 3 LOUT COUT1 8 Out COUT2 1 (16) +In CP1 LP CP2 102 (202) 19 CCPP1 LCPP CCPP2 5 Comp Cap FIGURE C9. Package and Pad Parasitics Modelled by the OPA675 and OPA676 Macromodel. The OPA675 and OPA676 are wideband op amps with two independent differential inputs (Figure C8). The multiple pole/zero topology is used to model the op amp portion of these switched-input amplifiers. Both amplifiers are identical except for the switch logic. The OPA675 is an ECLswitched device and the OPA676 is a TTL-switched device. Both files will model the device characteristics and package parasitics. If the user is using the product in its die form, the package parasitics no longer apply (Figure C9). 15 6 I1 R2 10 Gain Control 13 12 2 3 C1 E1 7 Q1 Q2 11 Q3 G3 R3 C3 6 D03 29 D01 27 R01 20 D04 24 D02 28 31 R02 21 R31 G31 R42 8 C02 26 E44 C42 G42 D42 42 E42 R41 E43 C41 G41 E41 43 D41 44 6 41 G1 G2 1 C01 Q01 Q02 45 7 Gain Stage IS Quiescent Current 7 6 Input Stage D55 D56 G51 R53 D53 51 V53 5 D54 E51 53 54 52 V54 R54 55 D57 G54 G53 D58 G52 7 Output Stage FIGURE C10. VCA610M Voltage Controlled Amplifier using the Multiple Pole/Zero Macromodel Topology. 16 SECTION D: SIMPLIFIED CIRCUIT MODELS As already mentioned the simplified circuit models provide a much different simulation approach, because they do not follow a standard model design. They are micromodels at the transistor level, therefore each model has its individual circuit schematic, which are shown on the following pages. Almost all of the devices of this model level (Level IV) are wideband/high-speed components with bandwidth capabilities of up to 1GHz. Some models have only one simplified circuit model available, and are labeled with the suffix "X". Other models offer two simplified circuit models. In general, the models with an "X1" suffix are of equivalent complexity as the "X" models. They are simpler implementations of the macromodel and will simulate faster; however, the accuracy is not as good as with the macromodels with an "X2" suffix for the same product. All of these models are found in the CIR_MOD subdirectory on the disk. These models are designed using different topologies than mentioned above and several non-linear elements. Because of the increased number of non-linear elements in these models, the simulation time is longer, but the accuracy is improved. The wideband operational amplifiers that have simplified circuit macromodels were designed using several subcircuits that allow the user to implement a variety of configurations. The OPA622 is a monolithic amplifier that can be configured as a current-feedback amplifier or a voltage-feedback amplifier. Like typical current-feedback amplifier, the OPA622 has a constant large-signal bandwidth of 280MHz. One would expect that when the OPA622 is configured in a voltage-feedback configuration the bandwidth would change with gain. This is not the case. When the OPA622 is configured as a voltage-feedback amplifier, it will again have a constant bandwidth over a wide gain and output voltage range. In the voltage-feedback mode, the OPA622 offers the speed advantages of current-feedback amplifiers and matched input impedance advantage of the voltagefeedback op amp. The OPA623 is strictly configured as a current-feedback amplifier, using the same internal design as the OPA622. The OPA660 wideband amplifier offers the user an "ideal transistor" and a buffer. The "ideal transistor" has three terminals available to the user--a high-impedance input (base), a low-impedance input/output (emitter) and the current output (collector). This "ideal transistor", otherwise called an Operational Transconductance Amplifier (OTA), is constructed using several discrete real transistors on the chip to give the user superior gain and temperature performance, hence, the comparison to an "ideal transistor". Although these transistor level models are more accurate than the other three topology levels used for macromodels on this disk, the user is cautioned that all models are an aid to circuit design and not a suggested replacement for breadboarding. Simulation should be used as a forerunner or a supplement to traditional lab testing. The parameters that are modelled by the transistor level circuit macromodels are listed in Table X. FIGURE D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 DESCRIPTION BUF600/601X1 Circuit Model BUF600/602X2 Complex Circuit Model BUF634X Circuit Model ISO120/121X Circuit Model ISO130 Circuit Model MPC100X1 Circuit Model MPC100X2 Complex Circuit Model OPA603X Circuit Model OPA620/621X Circuit Model OPA622X1 Circuit Model OPA622X2 Complex Circuit Model OPA623X1 Circuit Model OPA623X2 Complex Circuit Model OPA640X/OPA641X Circuit Model OPA642X/OPA643X Circuit Model OPA644X Circuit Model OPA646X Circuit Model OPA648X Circuit Model OPA64x Package and Pad Parasitics OPA658X Circuit Model OPA660X1 Circuit Model OPA660X2 Complex Circuit Model TABLE VIIII. Simplified Circuit Models Figure Reference. 17 VIN 4 Q21 21 Q23 1 V+ Q29 V41 41 R34 39 C39 Q41 16X C33 33 R33 Q33 Q34 C40 Q16X 42 8 C208 VOUT I21 40 Q22 12X 24 Q24 Q30 V42 RQC 22 5 V- FIGURE D1. BUF600X1 and BUF601X1 Simplified Circuit Macromodel. Compared to Figure D2, this macromodel is less complex with faster simulation times. VIN 4 Q21 21 Q27 Q23 1.4X 1 V+ Q25 Q29 1.4X 27 Q37 Q31 2X 6X 35 I21 Q33 C204 36 Q32 2X 39 Q35 Q39 6X Q41 16X Q34 Q36 34 41 Q40 6X 8 C208 Q42 6X VOUT 40 32 Q22 12X Q38 6X 24 Q24 Q26 28 Q28 1.4X Q30 1.4X RQC 22 5 V- FIGURE D2. BUF600X2 and BUF601X2 Complex Macromodel. Compared to Figure D1, this macromodel is more complex and requires more simulation time. 18 +VCC 80 D9 Q11 24 IB 22 Iss 5 Q12 R9 85 D2 86 C1 Q4 6 R24 D4 D6 7 1 VIN CP 21 Q9 20 Q10 CIN Q3 94 R6 R5 R7 VOS Q1 3 D1 4 8 D3 98 9 R8 Q5 R2 C2 10 D5 RIN D10 2 102 Q2 73 D11 11 C0 Q14 R26 18 R27 R2 17 Q7 R25 16 VOUT Q13 14 R1 R1 15 R10 13 Q6 12 Q8 D8 23 90 -VCC FIGURE D3. BUF634X Simplified Circuit Macromodel. 3(3)(1) +VS1 I1 GND1 24(40) R6 15(23) +VS2 I3 12(20) 52 C2 C2V 57 Q3 C2L 55 Q1 R3 13(21) R4 11(19) VOUT V1 I3 GND2 VOS VIN 23(39) 60 E2 R1 50 R2 51 C1 14(22) E3 R7 E1 R5 10(18) VOUT 54 COM1 21(37) E4 56 Q4 58 Q2 COM2 V2 I6 -VS2 9(17) I2 -VS1 4(4) 16(24) I4 NOTE: (1) First node number is for ISO120. Second node number is for ISO121. FIGURE D4. ISO120/121X Isolation Amplifiers Simplified-Circuit Macromodel. 19 1 VS1 VINP R1 GVS1 D1 2 VIN+ D3 D2 R3 9 R5 I1 VIN 3 VIN- R2 10 D4 R4 I2 4 GND1 V2 13 11 14 RE1 15 9 + - 10 E1 I3 Q1 Q2 16 R10 17 C3 R6 TDELAY 12 RE2 V3 C1 C2 C4 E2 E3 18 R7 19 R8 20 R9 21 22 23 R11 7 VOUT+ 6 VOUT- 5 GND2 GVS2 R12 8 VS2 FIGURE D5. ISO130X Simplified-Circuit Model. 20 In 12 R24 25 25 C23 G21 26 V22 R22 Q22 C26 R23 V28 10 V- 26 23 Q23 Q24 C24 27 Q 25 11 VOUT V27 V+ Q21 R21 14 SEL C25 Q26 28 FIGURE D6. MPC100X1 Simplified-Circuit Macromodel. Compared to Figure D7, this macromodel is less complex with faster simulation times. Shown here is only one out of four inputs of the MPC100. However, the same circuit schematic applies to the MPC102X1 and MPC104X1 model. 1 Q23 23 R23 C24 24 D26 14 SEL R24 21 Q21 22 Q22 R30 Q30 30 Q28 D25 26 Q24 Q29 27 25 Q27 R29 29 In 12 V+ R34 34 Q35 C33 Q36 34 28 Q32 32 C28 R32 Q44 46 Q46 44 R46 Q43 35 11 R45 36 Q38 Q31 45 R43 43 Q45 Q37 39 Q39 41 Q40 40 33 Q33 Q41 11 VOUT Q42 42 10 V- FIGURE D7. MPC100X2 Complex-Circuit Macromodel. Compared to Figure D6, this macromodel is more complex and requires more simulation time. Shown here is only one out of four inputs of the MPC100. 21 1 Q9A FB Q8A 34 R 8A 36 GC 10 R 0EA 8 R 0A +In 3 7 R 0B -In 9 R 0EB R 1B 11 13 37 R 8B 35 Q8B Q5B 33 R 5B 31 Q9B 27 + V6B 2 R 1EB 15 Q1B Q2B 17 R 2BT 19 Q6B C 2B 4 Q3B 25 21 Q4B Q0B 23 QSCB R 4B 6 Q0A R 1EA 22 R3 5 30 R 5A 32 Q5A 2 R 1A Q1A 14 20 Q3A QSCA Q4A 24 R 4A CB IS R PS 28 RB Q6A R 2AT 16 18 Q2A + V6A 26 V+ VO V- FIGURE D8. OPA603X High Speed Current-Feedback Op Amp Simplified-Circuit Macromodel. 22 3 V+ R7 R1 R2 5X Q5 I3 10 9 +In 1 Q1 2 2X 11 R3 13 Q2 2X 12 R4 I1 19 Q8 2X 15 Q3 4X 14 R5 16 R6 Q4 Q9 2X 22 R8 21 Q10 2X 23 R9 V- 4 C1 I2 24 18 Q6 20 20X 40X Q14 Q7 20X Q11 Q12 5 VO 25 Q13 40X 17 -In NOTE: OPA620 and OPA621 simplified-circuit macromodels are the same with the following exceptions. MODEL OPA620 OPA621 C1 (pF) 10 2 I1 (mA) 1.1 1.3 I2 (mA) 4 3.5 I3 (mA) 2 3.5 FIGURE D9. OPA620X and OPA621X High Speed Op Amp Simplified-Circuit Macromodel. 23 Biasing Circuit (BC) V+ VO+ 11 Diamond Buffer (DB) Diamond Transistor (DT) Current Buffer (CB) 12 Q27 Q61 Q21 27 Q29 C27 61 Q65 6X 6X Q121 131 Q123 21 Q25 C21 VOUT C10 23 Q23 Q24 C23 22 C22 Q26 6X 111 Q31 33 OTA Q33 10 13 Q35 37 Q37 Q39 2.2X C61 3 63 Q63 Q64 Buffer - +In C63 Q66 6X R63 8 4 R23 9 Q38 38 Q36 121 Voltage Out Q40 2.2X -In 24 62 C62 Q62 Q22 X4 Buffer + Q34 34 Q32 Q122 141 10X 28 Q28 C28 Q30 Q124 R122 V O- 6 122 R123 X2 X3 2 5 X1 IQ Adjust V- FIGURE D10. OPA622X1 Simplified Circuit Macromodel. Compared to Figure D11, this macromodel is less complex with faster simulation times. Diamond Transistor (DT) V+ 12 Q23 131 10X Current Buffer (CB) 11 VO+ Q33 Q25 10X 8X Q21 Q35 8X 23 33 111 37 111 Q43 4X 29 Q29 +In 4 Q28 6X Q31 6X Q37 5X Q39 5X 45 Q45 10 12X Q47 48X Q27 Q30 6X 28 C213 Q32 30 6X OTA 47 Q46 12X 9 C209 Q48 48X VOUT Q38 5X 38 C210 Q40 5X 46 125 125 Q44 4X 141 Q22 24 Q24 10X Q26 10X 34 Q34 8X Q36 8X V- 5 13 Buffer + X2 X3 6 VO - Diamond Buffer (DB) V+ 12 Q63 131 10X Biasing Circuit (BC) 12 Q73 Q121 Q123 C121 121 E13 Q125 11X V+ Q61 Q65 10X 4X 131 63 73 69 Q69 +In 3 Q68 Q67 Q70 Q72 70 6X Q71 6X I121 68 8 C208 Buffer - Q122 74 6X 124 Q124 R122 C124 E14 141 141 Q62 64 Q64 10X Q66 10X 122 Q74 4X 5 V- R123 C202 V- 5 X4 2 IQ Adjust X1 FIGURE D11. OPA622X2 Complex Macromodel. Compared to Figure D10, this macromodel is more complex and requires more simulation time. 25 Biasing Circuit (BC) Diamond Transistor (DT) Current Buffer (CB) Q121 131 Q123 Q21 27 Q27 Q29 C27 21 C21 Q25 6X 111 Q31 33 Q33 Q35 37 Q37 2 39 Q38 38 Q36 Q40 2.2X Q39 2.2X 3 -In R23 23 C23 Q23 Q24 C35 22 C22 Q26 6X 6 35 Q34 34 Q32 121 VOUT Q122 10X 141 Q124 RQC Q22 28 Q28 C28 Q30 122 4 X1 V- X2 X3 FIGURE D12. OPA623X1 Simplified-Circuit Macromodel. Compared to Figure D13, this macromodel is less complex with faster simulation times. 26 Diamond Transistor (DT) V+ 7 Q23 131 10X Current Buffer (CB) 7 V+ Q33 Q25 10X 10X Q21 Q35 10X 23 33 111 37 111 Q43 4X 29 Q29 +In 3 C203 Q28 6X Q31 6X Q37 5X Q39 5X 45 Q45 Q47 48X C39 28 Q27 Q30 6X 39 12X 47 Q46 Q40 5X 12X 6 C206 Q48 48X VOUT Q32 30 6X Q38 5X 38 46 123 C202 141 Q22 24 Q24 10X 123 Q44 4X Q26 10X 34 Q34 10X Q36 8X V- 4 2 -In X2 X3 4 V- Biasing Circuit (BC) 7 Q121 Q123 C121 121 E13 Q125 11X V+ 131 Q122 6X 124 Q124 RQC C124 E14 141 122 4 V- X1 FIGURE D13. OPA623X2 Complex Macromodel. Compared to Figure D12, this macromodel is less complex with faster simulation time. 27 1 21 R8 R11 R12 R14 R18 R1 R21 3 45 17 Q14 Q23 4X 4X Q18 17 44 16 Q20 Q8 16 Q29 Q33 20X 26 35 36 Q11 to C1P Q25 2X 42 10X 15 6 27 28 2X 37 Q30 Q26 24X Q21 36X 41 R20 V1 33 Q2 C2 ISOUR C3 5 Q1 28 29 Q19 4X 7 19 30 R5 4X Q15 Q20 4X 12X 12X 24X Q27 18 40 39 Q28 2X Q31 2X 36X R3 20 8X Q7 24 31 25 R9 R13 R15 C8 C6 43 38 32 Q22 20X 10X Q3 23 34 R16 Q24 Q32 Q34 2 22 R4 R19 R22 R2 4 FIGURE D14. OPA640X, OPA641X, Wide Bandwidth Op Amp Simplified-Circuit Macromodel. See Figure D19 for package parasitics. 1 R24 21 R4 R11 R8 R12 R13 R17 R19 R21 Q28 Q32 Q38 R26 3 41 28 32 Q20 3X R18 2X 3X R15 Q24 R1 40 29 33 46 47 C7 Q28 20X Q8 Q14 Q16 Q1 4X Q12 Q3 30 31 35 27 52 20X 4X 16 37 38 4X Q17 Q21 2X Q25 2X 4X Q13 17 36 16 Q15 26 34 50 Q33 Q29 20X 36X 53 R23 17 35 Q4 15 Q2 5 CA4 7 C2 ISOUR C3 12X 12X 20X 2 Q30 18 19 42 Q22 R5 4X 6 29 43 4X 4X Q18 2X Q9 R9 C1 R14 R18 Q23 51 48 Q31 Q34 2X 36X R2 20 8X 23 25 44 54 49 45 C8 C6 Q27 20X Q35 Q37 20X Q5 24 2 22 R22 R27 R25 R3 4 CA1 CA2 CA3 2 2 2 FIGURE D15. OPA642X, OPA643X, Low Distortion, High-Speed Op Amp Simplified-Circuit Macromodel. See Figure D19 for package parasitics. 1 59 34 36 CS33 IOUT1 2 V1 RB29 37 RE29 CE29 G1 38 2 C6 Q38 59 RBB34 CU34 16 52 R26 5 31 R18 39 2 ISOUR Q12 59 33 59 RB34 7 Q13 Q17 30 V3 R21 RB32 44 R32 24 V2 Q6 27 R7 R28 R10 28 46 RE31 59 59 Q14 F2 R19 C7 45 2 Q46 Q48 CE32 32 59 59 G3 R032 C032 2 50 Q09 CU32 2 43 F3 RE34 6 R6 54 Q16 29 RE30 2 R029 C029 C8PP 48 Q41 Q44 35 C8 51 CU29 F1 15 Q47 Q43 40 C4 R20 26 Q3 21 Q10 22 Q8 20 C3PP Q11 25 C3 R5 R9 RE33 CE33 G2 R033 R27 RB33 RBB33 CU33 R1 R33 17 3 R3 58 59 C1 C2 C1PP CE34 30 C4PP F1 G2 R034 C034 18 Q39 C12PP 49 Q42 Q45 C12 2 R4 C2PP 19 2 2 2 R2 18 R34 4 FIGURE 16. OPA644x, High-Speed Op Amp Simplified-Circuit Macromodel. See Figure D19 for package parasitics. 1 R1 21 R8 R11 R13 R15 R19 3 28 17 34 Q19 3X 2X Q11 Q18 3X 17 16 Q6 16 26 17 Q25 2X Q10 15 29 Q20 Q21 V1 2X 4X 6 27 35 Q28 42 Q31 Q27 36X 36 20X 40 39 Q30 2X 20X 41 R17 5 Q1 C2 ISOUR C3 Q2 31 30 Q17 7 4X 4X Q22 4X 18 19 45 Q23 Q29 43 Q32 36X R3 R5 20 Q15 Q18 32 2X 38 2X Q26 2X Q7 24 31 25 R3 R12 R14 C8 C7 Q3 33 Q24 23 37 R16 2 22 R4 R19 R2 4 FIGURE D17. OPA646X, Low Power, High-Speed Op Amp Simplified-Circuit Macromodel. See Figure D19 for package parasitics. 1 R18 12 R5 15 B12 16 B28 36 B13 27 B7 26 35 B6 B27 B37 B39 41 24 B5 25 R8 R1 R2 R22 B??? 14 B11 17 18 33 B31 I2 4 6 34 B24 CCOMP 23 32 28 B18 20 31 39 B15 B9 30 R4 22 R8 R3 29 B8 B29 B10 38 B30 B25 B2 B4 B1 3 B22 B23 B3 37 B33 R24 43 C3 5 ISOUR 32 B32 40 B35 19 42 B38 R23 B41 B42 B14 21 R7 2 R19 13 FIGURE D18. OPA648X, High-Speed Op Amp Simplified-Circuit Macromodel. L14P 15 1 C16P C17P R22P 74 C23P R27P C24P L18P 6 C2P R5P 65 7 C8P R11P 69 2 C14P 4 L9P L27P C29P R33P 79 5 L22P 76 C9P L5P C22P 3 73 C18P C1P L2P 61 C4P L6P 64 C10P L10P 68 R18P C15P C35P C38P C3P 62 R1P L1P 70 71 R17P L15P 72 R21P 8 2 60 L19P 75 R26P 10 R2P 13 R7P 63 14 77 C30P C31P L23P 78 R31P 12 FIGURE D19. Schematic to Model the Pad Parasitics Used for the OPA64X High-Speed Op Amp Series. 33 66 67 R12P 11 80 L28P R38P 81 82 R37P 9 L31P L13P 2 43 41 3 51 52 53 6 1 L2P 42 R1P L1P L7P R7P L8P R8P 8 C2P C1P C6P C7P R2P 9 4 5 54 10 55 56 R4P 46 45 R3P 44 L9P R9P L10P R10P L3P L4P C4P C8P C3P 7 50 C5P R11P R6P 49 48 2 47 L8P R5P L5P L11P 1 R16 11 1 R1 R2 20 17 37 Q7 C3 Q13 28 13 24 Q1 R7 3 25 R8 26 Q12 30 C2 31 Q10 19 Q14 R6 Q8 22 R3 12 23 Q9 21 R4 Q16 32 R10 Q2 Q4 14 C1 R5 4 Q3 Q11 29 R12 Q6 Q15 27 R9 ISOUR1 16 Q5 FIGURE D20. OPA658X, OPA2658X and OPA4658 Current-Feedback Wideband Op Amp Simplified-Circuit Macromodel. 34 C4 ISOUR2 Q17 33 Q21 Q20 34 Q19 Q22 35 36 R11 5 Q18 2 R17 2 Biasing Circuit (MBC) Diamond Transistor (MDT) 7 Q27 Q71 Q21 25 C25 71 Q75 C71 Buffer Out 6 3 23 C23 22 C22 Base Q74 C206 R23 Q23 Q24 73 Q73 C73 14 72 C72 Q72 Q76 21 C21 Diamond Buffer (MDB) V+ Q121 Q123 13 Q29 8 Q25 C208 2 Emitter C202 Collector Buffer In R73 5 35 X3 X1 Q122 Q26 Q124 R122 122 Q22 26 Q28 C26 Q30 R123 C201 X2 1 4 IQ Adjust V- FIGURE D21. OPA660X1 Simplified-Circuit Macromodel. Compared to Figure D22, this macromodel is less complex with faster simulation times. 7 Biasing Circuit (MBC) Diamond Buffer (MDB) Diamond Transistor (MDT) R33 Q73 Q21 29 27 R27 Q28 Q27 Q29 28 6 Q26 Q22 30 Q30 2 C38 C202 Q23 23 Q25 13 33 Q33 31 Q31 7 V+ Q125 13 E13 R35 35 Q35 Q121 13 Q123 79 Q81 77 Q78 78 80 Q82 74 Q76 Q74 Q124 14 Q72 Q24 Buffer Out 24 C206 14 Q80 Q79 C203 E14 14 5 Buffer In C205 Q77 Q71 Base 3 Q75 73 121 C121 I121 2 Emitter 8 Q32 32 Q34 36 34 R34 R36 4 C208 Q36 Collector Q122 124 36 X3 X1 1 R123 122 C124 IQ Adjust C201 R122 4 X2 V- FIGURE D22. OPA660X2 Complex Macromodel. Compared to Figure D21, this macromodel is more complex and requires more simulation time. OUTPUT FLOWING FROM POWER SUPPLIES QUIESCENT CURRENT vs POWER SUPPLY INPUT BIAS CURRENT CORRECTION OUTPUT VOLTAGE SWING QUIESCENT CURRENT vs TEMPERATURE DEVICE CHARACTERISTICS MODELED INPUT OFFSET CURRENT OUTPUT CURRENT LIMIT INPUT VOLTAGE NOISE INPUT CURRENT NOISE QUIESCENT CURRENT GAIN vs TEMPERATURE INPUT BIAS CURRENT OUTPUT RESISTANCE CMRR vs FREQUENCY INPUT PROTECTION GAIN vs FREQUENCY OFFSET VOLTAGE INPUT IMPEDANCE PHASE RESPONSE PSRR vs FREQUENCY SLEW RATE PAD PARASITICS NO GROUND REFERENCE COMMENTS ACF2101M BUF600X1 BUF600X2 BUF601X1 BUF601X2 BUF634X INA101 INA101E INA102 INA102E INA103 INA103E INA105 INA105E INA106 INA106E INA110 INA110E INA111 INA111E INA114 INA114E INA115 INA115E INA117 INA117E INA118 INA118E INA120 INA120E INA131 INA131E ISO120X ISO121X ISO130X MPC100X1 MPC100X2 MPC102X1 MPC104X1 OPA1013 OPA1013E OPA111 OPA111E OPA121 OPA121E OPA124 OPA124E OPA128 OPA128E OPA129 OPA129E OPA131 OPA131E OPA177 OPA177E X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X NA NA NA NA NA NA NA X X X X X X X X X X X X X NA NA NA NA X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X PSRR MODEL X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 7 10, 14 10, 14 10, 14 10, 14 1 1 1 1 1 1 1 2 2 2 2 1 1 1 1 1 1 C6,7 D1 D2 D1 D2 D3 2 2 2 2 3 3 1a 1a 1a 1a 5 5 2 2 2 2 2 2 16 16 4 4 6 6 2 2 D4 D4 D5 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 2 2 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 1 1 NA NA X X 4 4 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 14, 14, 14, 14, 10 10 10 10 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X D6 D7 D6 D6 A6 B4 A4 B2 A4 B2 A4 B2 A4 B2 A4 B2 A5 B6 TABLE X. Parameters Modeled by the Standard, Enhanced, Multiple Pole/Zero, and Simplified Circuit Macromodel. 37 FIGURE OUTPUT FLOWING FROM POWER SUPPLIES QUIESCENT CURRENT vs POWER SUPPLY INPUT BIAS CURRENT CORRECTION OUTPUT VOLTAGE SWING QUIESCENT CURRENT vs TEMPERATURE DEVICE CHARACTERISTICS MODELED INPUT OFFSET CURRENT OUTPUT CURRENT LIMIT INPUT VOLTAGE NOISE INPUT CURRENT NOISE QUIESCENT CURRENT GAIN vs TEMPERATURE INPUT BIAS CURRENT OUTPUT RESISTANCE CMRR vs FREQUENCY INPUT PROTECTION GAIN vs FREQUENCY OFFSET VOLTAGE INPUT IMPEDANCE PHASE RESPONSE PSRR vs FREQUENCY PAD PARASITICS NO GROUND REFERENCE SLEW RATE COMMENTS COMMENTS OPA2107 OPA2107E OPA2111 OPA2111E OPA2131 OPA2131E OPA2541 OPA2541E OPA2604 OPA2604E OPA2604M OPA2658X OPA27 OPA27E OPA27M OPA37 OPA37E OPA404 OPA404E OPA445 OPA445E OPA4131 OPA4131E OPA4658X OPA501 OPA501E OPA502 OPA502E OPA511 OPA511E OPA512 OPA512E OPA541 OPA541E OPA602 OPA602E OPA603X OPA604 OPA604E OPA604M OPA606 OPA606E OPA620 OPA620E OPA620X OPA621 OPA621E OPA621X OPA622X1 OPA622X2 OPA623X1 OPA623X2 OPA627 OPA627E OPA628M X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X PSRR MODEL X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 9 X X X A4 B2 A4 B2 X X X X X X X X X X X X X X X X X X X X X A4 B2 A4 B2 C2, 5 D20 A5 B4 C3, 5 A5 B4 A4 B2 A4 B2 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X D20 A5 B4 A3 B4 A4 B2 A4 B2 A4 B2 A4 B2 D8 A4 B2 C2, 5 A4 B2 A5 B4 D9 A5 B4 D9 D10 D11 D12 D13 A4 B2 C3 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 8 X X NA NA NA NA X X X X X X X X X NA NA NA NA X X X X X X X X 8 10, 14 10, 14 10, 14 10, 14 X X X X X X X X X X X TABLE X (cont). Parameters Modeled by the Standard, Enhanced, Multiple Pole/Zero, and Simplified Circuit Macromodel. 38 FIGURE OUTPUT FLOWING FROM POWER SUPPLIES QUIESCENT CURRENT vs POWER SUPPLY INPUT BIAS CURRENT CORRECTION OUTPUT VOLTAGE SWING QUIESCENT CURRENT vs TEMPERATURE DEVICE CHARACTERISTICS MODELED INPUT OFFSET CURRENT OUTPUT CURRENT LIMIT INPUT VOLTAGE NOISE INPUT CURRENT NOISE QUIESCENT CURRENT GAIN vs TEMPERATURE INPUT BIAS CURRENT OUTPUT RESISTANCE CMRR vs FREQUENCY INPUT PROTECTION GAIN vs FREQUENCY OFFSET VOLTAGE INPUT IMPEDANCE PHASE RESPONSE PSRR vs FREQUENCY PAD PARASITICS NO GROUND REFERENCE SLEW RATE COMMENTS COMMENTS OPA637 OPA637E OPA640X OPA641X OPA642X OPA643X OPA644X OPA646X OPA648X OPA660X1 OPA660X2 OPA671M OPA675M OPA676M OPA77 OPA77E OPT101 OPT201 OPT202 OPT209 UAF42 UAF42E VCA610M X X X X X X X X X X X X X X X X X X X X X X X NA NA X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X NA NA X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X PSRR MODEL X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 8, 12 8, 12 8, 12 8, 8, 8, 8, 12 12 12 12 A4 B2 D14 D14 D15 D15 D16 D17 D18 D21 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 10, 14, 5 D22 C2, 5 6 C8, C9 6, 11 C8, C9 A5 B6 A2 A2 A2 A2 3 3 13 A4 B2 C10 X X X X X X X X X X X X X X COMMENTS: 1. Instrumentation Amplifier. 2. Difference Amplifier. 3. All four op amps in the UAF42 chip are identical. This model only contains one op amp. 4. Also models isolation barrier impedance. 5. Also models enable transient response and the quiescent resistor transient response. 6. Also has the input control switch and models its transient response. 7. Model includes HOLD, RESET and SELECT switches and internal capacitor. 8. Also models total harmonic distortion. 9. Also models bias current vs power supply and bias current vs common-mode. 10. Also models group delay time. 11. Also models TTL switching times. 12. Also models output recovery time. 13. Also models gain control vs frequency. 14. Contact the factory for a more detailed description of this macromodel 800 548-6132 or FAX (602) 746-7852. TABLE X (cont). Parameters Modeled by the Standard, Enhanced, Multiple Pole/Zero, and Simplified Circuit Macromodel. 39 FIGURE PRODUCT NOTES For more information please refer to the individual data sheet. ACF2101 SWITCHED INTEGRATOR The integrator output voltage range is from +0.5V to -10V. The output voltage (VOUT) can be calculated as: RGI = One of the three internal gain-setting resistors shown in the table () RGE = external gain-setting resistor () INA103 INSTRUMENTATION AMPLIFIER The INA103 contains internal gain-setting and feedback resistors: RFB = 3k RG = 60.606 (Gain = 100) The internal gain-setting feedback resistors may be used, or external feedback resistors may be used. If the internal resistors are used: GAIN = 1 + (6k/RG) If external feedback resistors are used: GAIN = 1 + (2 * RFB/RG) Where: RG = Optional external gain-setting resistor () RFB = Optional external feedback resistor () INA110 INSTRUMENTATION AMPLIFIER INA110 INTERNAL GAIN-SETTING RESISTORS RG (w) 4.444K 404.04 201.0 80.16 GAIN (V/V) 10 100 200 500 V OUT = - 1 C INT i IN dt VOUT = the output voltage of the ACF2101 CINT = the integration capacitor (in farads) iIN = the input current (in amperes) dt = the integration time (in seconds) INA101 INSTRUMENTATION AMPLIFIER The INA101 contains internal gain-setting feedback resistors; RFB = 20k When using the metal package (TO-100), these resistors must be used. When using the ceramic or plastic packages, the internal gain-setting feedback resistors may be used, or external feedback resistors may be used. If the internal resistors are used: GAIN = 1 + (40k/RG) If external feedback resistors are used: GAIN = 1 + (2 * RFB/RG) Where: RG = external gain-setting resistor () RFB = optional external feedback resistor () INA102 INSTRUMENTATION AMPLIFIER The INA102 contains internal gain-setting and feedback resistors; RFB = 20k INA102 INTERNAL GAIN-SETTING RESISTORS RG () 4.444k 404 40.4 GAIN (V/V) 10 100 1000 The INA110 contains internal gain-setting and feedback resistors; RFB = 20k The internal resistors are ratio trimmed to high accuracy and have excellent tracking with temperature for low gain drift. If the internal resistors are used: GAIN = 1 + (40k/RG) External gain-setting resistors can be used in series with one of the internal gain-setting resistors. If external gain-setting resistors are used: GAIN = 1 + (40k/RGI + RGE]) RGI =one of the four above internal gain-setting resistors () RGE = external gain-setting resistor () INA111 INSTRUMENTATION AMPLIFIER The INA111 contains internal gain-setting feedback resistors; RFB = 25k External gain-setting resistors are used to set the gain at: GAIN = 1 + (50k/RG) RG = external gain resistor () 40 The internal resistors are ratio trimmed to high accuracy and have excellent tracking with temperature for low gain drift. If the internal resistors are used: GAIN = 1 + (40k/RG) External gain-setting resistors can be used in series with one of the internal gain-setting resistors. If external gain-setting resistors are used: GAIN = 1 + (40k/[RGI + RGE]) INA120 INSTRUMENTATION AMPLIFIER The INA120 contains an internal gain-setting and feedback resistor string; RFB = 20k INA120 INTERNAL GAIN-SETTING RESISTORS RG [] 4000 400 44 GAIN [V/V] 10 100 1000 OPA660 OPERATIONAL TRANSCONDUCTANCE AMPLIFIER AND BUFFER This device includes a voltage-controlled current source and a voltage buffer. The voltage-controlled current source or Operational Transconductance Amplifier can be viewed as an "ideal transistor". The transconductance of the OTA can be adjusted with an external resistor, allowing bandwidth, quiescent current and gain tradeoffs to be optimized. Demo boards are available. OPA675 SWITCHED-INPUT OPERATIONAL AMPLIFIER The OPA675 is a "classical" high-speed amplifier that has two differential input stages. Each stage is selectable with ECL logic. OPA676 SWITCHED-INPUT OPERATIONAL AMPLIFIER The OPA676 is a "clasical" high-speed amplifier that has two differential input stages. Each stage is selectable with TTL logic. OPA2111 DUAL OPERATIONAL AMPLIFIER The OPA2111 slew rate is asymmetric with the positivegoing slope faster than the negative-going slope (4V/s vs 2V/s). Since the PSpice macromodel only allows asymmetric slew rate in the opposite direction, a conservative symmetrical slew rate of 2V/s was used in the macromodel. The internal resistors are ratio-trimmed to high accuracy and have excellent tracking with temperature for low gain drift. If the internal gain-setting resistor string is used, it can be connected to the amplifier input terminals to give accurate gains of 1, 10, 100, and 1000. The gain equation is the same as for external gain-setting resistors, but in higher gains, part of the lower gain-setting resistor is added to the feedback resistor so the values shown for RG can not be inserted directly in the equation--see Figure 10. The internal feedback resistors can be used with external feedback resistors. If the internal feedback resistors are used with external gain-setting resistors: GAIN = 1 + (40k/RG) Where: RG = optional gain-setting resistor () connected between G5 and G14 with G11 open External gain-setting and feedback resistors can be used. If external feedback resistors are used: GAIN = 1 + (2 * RFB/RG) Where: RG = Optional external gain-setting resistor () RFB = Optional external feedback resistor () OPA111 OPERATIONAL AMPLIFIER The OPA111 slew rate is asymmetric with the positivegoing slope faster than the negative-going slope (4V/s vs 2V/s). Since the PSpice macromodel only allows asymmetric slew rate in the opposite direction, a conservative symmetrical slew rate of 2V/s was used in the macromodel. OPA121 OPERATIONAL AMPLIFIER The OPA121 slew rate is asymmetric with the positivegoing slope faster than the negative-going slope (4V/s vs 2V/s). Since the PSpice macromodel only allows asymmetric slew rate in the opposite direction, a conservative symmetrical slew rate of 2V/s was used in the macromodel. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. 41 CONTENT OF MACROMODEL DISK LEVEL II STD_MOD ACF2101M BUF600X1 BUF600X2 BUF601X1 BUF601X2 BUF634X ISO120X ISO121X ISO130X OPA646X OPA648X OPA650X OPA658X OPA2658X OPA4658X OPA660X1 OPA660X2 LEVEL I STD_MOD LEVEL III STD_MOD LEVEL IV STD_MOD OPA27M OPA604M OPA628M OPA671M OPA675M OPA676M OPA2604M VCA610M MPC100X1 MPC100X2 MPC102X1 MPC104X1 INA101 INA102 INA103 INA105 INA106 INA110 INA111 INA114 INA115 INA117 INA118 INA120 INA131 INA101E INA102E INA103E INA105E INA106E INA110E INA111E INA114E INA115E INA117E INA118E INA120E INA131E TABLE XI. Content of the Macromodel Disk, Revision F, Listed by Topology Level and Directory. New models in bold. OPA404E OPA445E OPA501E OPA502E OPA511E OPA512E OPA541E OPA602E OPA604E OPA606E OPA620E OPA621E OPA627E OPA637E OPA1013E OPA2107E OPA2111E OPA2131E OPA2541E OPA2604E OPA4131E UAF42E OPA603X OPA620X OPA621X OPA622X1 OPA622X2 OPA623X1 OPA623X2 OPA640X OPA641X OPA642X OPA643X OPA644X OPA27E OPA37E OPA77E OPA111E OPA121E OPA124E OPA128E OPA129E OPA131E OPA177E 42 OPA27 OPA37 OPA77 OPA111 OPA121 OPA124 OPA128 OPA129 OPA131 OPA177 OPA404 OPA445 OPA501 OPA502 OPA511 OPA512 OPA541 OPA602 OPA604 OPA606 OPA620 OPA621 OPA627 OPA637 OPA1013 OPA2107 OPA2111 OPA2131 OPA2541 OPA2604 OPA4131 OPT101 OPT201 OPT202 OPT209 OPT211 UAF42 |
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