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| Port Bypass Circuits for Fibre Channel Arbitrated Loop Standard and its Extensions Technical Data Features * Supports ANSI X3T11 1.0625 Gbps FC-AL Loop Configuration * Supports 802.3z 1.25 Gbps Gigabit Ethernet (GE) Rates * Single PBC, CDR, Dual Signal Detect (SD) in a Single Package * Bidirectional, Symmetric Bypass Capability * CDR in Bypass Path and Loop Path * CDR Location Determined by Wiring Configuration of Pins on PCB (Patent Pending) * Envelope Detect on Cable Input (SD) for Both Directions * Equalizers On All Inputs * High Speed PECL I/Os Referenced to VCC * Buffered Line Logic (BLL) Outputs without External Bias Resistors * 0.4 W Typical Power at VCC = 3.3 V * 5 V Tolerant LVTTL I/O * 24 Pin SSOP Package HDMP-0421 Single PBC & CDR Description The HDMP-0421 is a Single Port Bypass Circuit (PBC) with Clock and Data Recovery (CDR), and dual Signal Detect (SD) capability. This configuration will control jitter accumulation while repeating incoming signals. Port Bypass Circuits are used to provide loops that are continuously on in hard disk arrays constructed in Fibre Channel Arbitrated Loop (FC-AL) configurations. Hard disks may be pulled out or swapped while other disks in the array are available to the system. This device may also be used in multi-initiator loop configurations. A Port Bypass Circuit is a 2:1 Multiplexer array with two modes of operation: DISK IN LOOP and DISK BYPASSED. In DISK IN LOOP mode, the loop goes into and out of the disk drive. Data go from the HDMP-0421's TO_NODE[n] differential output pins to the Disk Drive Transceiver IC (for example, an HDMP-1536A) Rx differential input pins. Data from the Disk Drive Transceiver IC Tx differential output pins go to the HDMP-0421's FM_NODE[n] differential input pins. Figures 4 and 5 show connection diagrams for disk drive array applications. In DISK BYPASSED mode, the disk drive is either absent or non-functional and the loop bypasses the hard disk. DISK IN LOOP mode is enabled with a HIGH on the BYPASS[n]- pin and DISK BYPASSED mode is enabled with a LOW on the same pin. Multiple HDMP-0421s may be cascaded or connected to other members of the HDMP-04xx family through the FM_LOOP and TO_LOOP pins to create loops for arrays of disk drives. See Table 2 to identify which of the two cells (0:1) will provide FM_LOOP, TO_LOOP pins (cell connected to cable). ALL TO_NODE outputs of the HDMP-0421 are of equal strength. Combinations of HDMP-04xx may be utilized to accommodate any number of hard disks. The HDMP-0421 may also be used as a pair of 1=>1 buffers, one with a CDR and another without. For example, HDMP-0421 may be placed in front of a CMOS ASIC to clean the jitter of the outgoing signal (CDR path) and to better read the incoming signal (CDRless path). Applications * RAID, JBOD Cabinets * 1=>1 Gigabit Serial Buffer Pair (with and w/o CDR) * Multi-Initiator Loops 2 The design of the HDMP-0421 allows for placement of the CDR at one of two locations with respect to a hard disk slot. For example, if the BYPASS[0]- pin is HIGH and hard disk slot A is connected to PBC cell 1, the CDR function will be performed before entering the hard disk at slot A (Figure 4). To achieve a CDR function after slot A, the BYPASS[1]- pin must be HIGH and hard disk slot A must be connected to PBC cell 0 (Figure 5). Table 2 shows both possible connections. In both cases, a Signal Detect (SD) pin shows the status of the signal at the incoming cable. The recommended method of setting the BYPASS[i]- pins HIGH is to drive them with a highimpedence signal. Internal pullup resistors will force the BYPASS[I]- pins to VCC . FM_NODE[1] FM_NODE[0] TO_NODE[1] LOSDET TO_NODE[0] BYPASS[1]- 1 0 SD[1] 1 0 BYPASS[0]- CDR CEXT IOSDET REFCLK SD[0] Figure 1. Block Diagram of HDMP-0421. (1) FM_NODE[0] (2) FM_NODE[4] (1) TO_NODE[0] (2) TO_NODE[0] tdelav1.2 Figure 2. Timing Waveforms. 3 Table 1a. Truth Table for CDR at Entry Configurations FM_LOOP = FM_NODE[0], TO_LOOP = TO_NODE[0], BYPASS[0]- = 1 TO_LOOP FM_LOOP FM_NODE[1] TO_NODE[1] FM_LOOP FM_LOOP BYPASS[1]- 0 1 Table 1b. Truth Table for CDR at Exit Configurations FM_LOOP = FM_NODE[1], TO_LOOP = TO_NODE[1], BYPASS[1]- = 1 TO_LOOP FM_LOOP FM_NODE[0] TO_NODE[0] FM_LOOP FM_LOOP BYPASS[0]- 0 1 Table 2. Pin Connection Diagram to Achieve Desired CDR Location (see Figures 4 and 5) X Denotes CDR Position with respect to Hard Disks Hard Disk Connection to PBC Cells CDR Position (x) Cell Connected to Cable A 1 xA 0 A 0 Ax 1 FM_NODE[1]- FM_NODE[1]+ VCCHS TO_NODE[1]- TO_NODE[1]+ GND GND BYPASS[1]- SD[1] VCC GND CPLL1 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 FM_NODE[0]- FM_NODE[0]+ VCCHS TO_NODE[0]- TO_NODE[0]+ GND GND BYPASS[0]- SD[0] VCCA REFCLK CPLL0 HDMP-0421 R x.YY nnnn-nnn S YYWW COUNTRY 20 19 18 17 16 15 14 13 nnnn.nnn = WAFER LOT - BUILD NUMBER (1-3 DIGITS) Rx.yy = DIE REVISION S = SUPPLIER CODE YYWW = DATE CODE (YY = YEAR, WW = WORK WEEK) COUNTRY = COUNTRY OF MANUFACTURE Figure 3: HDMP-0421 Package Layout and Marking, Top View. 4 Table 3. Pinout Pin Name TO_NODE[0]+ TO_NODE[0]- FM_NODE[1]+ FM_NODE[1]- TO_NODE[1]+ TO_NODE[1]- FM_NODE[0]+ FM_NODE[0]- BYPASS[1]- BYPASS[0]- REFCLK CPLL1 CPLL0 SD[1] SD[0] Pin 20 21 02 01 05 04 23 24 08 17 14 12 13 09 16 Pin Type Pin Description O-PECL In CDR at entry configuration, this pin is the Serial Output (TO_LOOP+). In other configurations, this pin is wired to the hard disk. O-PECL In CDR at entry configuration, this pin is the Serial Output (TO_LOOP-). In other configurations, this pin is wired to the hard disk. I-PECL Input from Transceiver IC to Cell 1. I-PECL Input from Transceiver IC to Cell 1. O-PECL Output to Transceiver IC from Cell 1. O-PECL Output to Transceiver IC from Cell 1. I-PECL In CDR at entry configuration, this pin is the Serial Input (FM_LOOP+). In other configurations, this pin is wired to the hard disk. I-PECL In CDR at entry configuration, this pin is the Serial Input (FM_LOOP-). In other configurations, this pin is wired to the hard disk. I-LVTTL Bypass pin for cell 1. In CDR at exit configuration, float to HIGH else ground connect through a 1 K resistor. I-LVTTL Bypass pin for cell 0. In CDR at exit configuration, float to HIGH else ground connect through a 1 K resistor. I-LVTTL Reference Clock Input for Clock and Data Recovery (CDR) circuit. C PLL cap pin. Connected to pin 13 with a 0.1 microFarad capacitor. C PLL cap pin. Connected to pin 12 with a 0.1 microFarad capacitor. O-LVTTL Signal Detect via envelope detect method. In CDR at entry and at exit cases, detects signal on incoming cable respectively. Active High when signal is detected. If (FM_NODE[0]+ -FM_NODE[0]-) >= 400 mV peak-to-peak, SD = 1 If 400 mV >= (FM_NODE[0]+ -FM_NODE[0]-) >= 100 mV, SD = unpredictable If 100 mV >= (FM_NODE[0]+ -FM_NODE[0]-), SD = 0 S 6, 7, 11, 18, 19 Ground pins. S Analog Power Supply pin. S Cell 1 High Speed Output Pins Power Supply. S Cell 0 High Speed Output Pins Power Supply. S Logic Power Supply pins. GND VCCA VCCHS VCC 15 03 22 10 5 HARD DISK A SERDES FM_NODE[0] = FM_LOOP TO_NODE[0] = TO_LOOP FM_NODE[1] 1 1 0 0 0 CDR Figure 4: Connection Diagram. Case of CDR Before Entering the Hard Disk. HARD DISK B FM_NODE[1] = FM_LOOP TO_NODE[1] = TO_LOOP SERDES BYPASS[1]- = 1 FM_NODE[0] TO_NODE[0] 1 1 0 0 0 CDR Figure 5: Connection Diagram. Case of CDR After Exiting the Hard Disk. BYPASS[0]- BYPASS[0]- = 1 TO_NODE[1] BYPASS[1]- 1 1 6 Absolute Maximum Ratings TA = 25C, except as specified. Operation in excess of any one of these conditions may result in permanent damage to this device. Symbol VCC VIN,LVTTL VIN,HS_IN IO,LVTTL T stg Tj Parameter Supply Voltage LVTTL Input Voltage HS_IN Input Voltage LVTTL Output Source Current Storage Temperature Junction Temperature Units V V V mA C C Min. -0.7 -0.7 2.0 -65 0 Max. 4.0 4.0 VCC 13 +150 +125 Guaranteed Operating Rates TA = 0C to +70C, VCC = 3.15 V to 3.45 V Serial Clock Rate Serial Clock Rate FC (MBd) GE (MBd) Min. Max. Min. Max. 1040 1080 1240 1260 Clock and Data Recovery Circuit Reference Clock Requirements TA = 0C to +70C, VCC = 3.15 V to 3.45 V Symbol Parameter f Nominal Frequency Ftol Frequency Tolerance Symm Symmetry (Duty Cycle) Unit MHz ppm % Min. -100 40 Typ. 106.25 Max. +100 60 Min. -100 40 Typ. 125.00 Max. +100 60 DC Electrical Specifications TA = 0C to +70C, VCC = 3.15 V to 3.45 V Symbol Parameter VIH,LVTTL LVTTL Input High Voltage Range VIL,LVTTL LVTTL Input Low Voltage Range VOH,LVTTL LVTTL Output High Voltage Level, IOH = -400 A VOL,LVTTL LVTTL Output Low Voltage Level, IOL = 1 mA IIH,LVTTL Input High Current (Magnitude), VIN = 2.4 V, VCC = 3.45 V IIL,LVTTL Input Low Current (Magnitude), VIN = 0.4 V, VCC = 3.45 V ICC Total Supply Current, TA = 25C Unit V V V V A A mA Min. 2 0 2.2 0 Typ. Max. 4.0 0.8 3.45 0.6 40 600 0.003 300 110 7 AC Electrical Specifications TA= 0C to +70C, VCC = 3.15 V to 3.45 V Symbol Parameter Total Loop Latency from FM_NODE[0] to TO_NODE[0] Per Cell Latency from FM_NODE[4] to TO_NODE[0] Input LVTTL Rise Time Requirement, 0.8 V to 2.0 V Input LVTTL Fall Time Requirement, 2.0 V to 0.8 V Output LVTTL Rise Time Range, 0.8 V to 2.0 V, 10 pF Load Output LVTTL Fall Time Range, 2.0 V to 0.8 V, 10 pF Load HS_OUT Single-Ended Rise Time HS_OUT Single-Ended Fall Time HS_OUT Differential Rise Time HS_OUT Differential Fall Time HS_IN Input Peak-To-Peak Required Differential Voltage Range Units ns ns ns ns ns ns ps ps ps ps mV mV 200 1100 Min. Typ. 4.0 2.0 2.0 2.0 1.5 2.0 200 200 200 200 1200 1400 2.4 3.5 350 350 350 350 2000 2000 Max. t delay1 t delay2 tr,LVTTLin tf,LVTTLin t r,LVTTLout tf,LVTTLout t rs, HS_OUT tfs,HS_OUT t rd, HS_OUT t fd,HS_OUT VIP,HS_IN VOP,HS_OUT HS_OUT Output Peak-To-Peak Differential Voltage (Z0=750 , Figure 10) Power Dissipation and Thermal Resistance TA = 0C to +70C, VCC = 3.15 V to 3.45 V Symbol Parameter PD Power Dissipation jc Thermal Resistance, Junction to Case Unit mW C/W Typ. 360 14 Max. 8 Output Jitter Characteristics TA = 0C to +70C, VCC = 3.15 V to 3.45 V Symbol Parameter RJ Random Jitter at TO_NODE pins (1 sigma rms) DJ Deterministic Jitter at TO_NODE pins (pk-pk) Note: Please refer to Figures 7 and 8 for jitter measurement setup information. Unit ps ps Typ. 6 16 Max. Locking Characteristics TA = 0C to +70C, VCC = 3.15 V to 3.45 V Parameter Bit Sync Time (phase lock) Frequency Lock at Powerup Unit bits s Max. 2500 500 MARKER MODE X1 Y2 X2 manual X1, Y1 SOURCE function 1 X1 POSITION 42.006 ns Y1 POSITION -820.000 mV X2, Y2 SOURCE Y1 150.0 ps/div f1 250 ps/div 0.0 V Y 1 (f1) = -820.00 mV 2 (f1) = 797.00 mV = 1.61700 V 42.4738 ns X 42.006 ns 42.947 ns 941 ps 42.947 ns Y2 POSITION 797.000 mV function 1 X2 POSITION 1/X = 1.063 GHz Figure 6. Eye Diagram of a High Speed Differential Output. 9 RANDOM JITTER HDMP-0421 FM_NODE[0] BIAS K28.7 0011111000 CLOCK REFCLK TO_NODE[0] BYPASS-[0] BYPASS-[1] N/C 70841B PATTERN GENERATOR DATA 2 1062.5 MHz 1.4 106.25 MHz 2 70311A CLOCK SOURCE 1/10 VARIABLE DELAY CH 1/2 106.25 MHz TRIGGER 83480A DIGITAL COMMUNICATION ANALYZER Figure 7. Setup for Measurement of Random Jitter. DETERMINISTIC JITTER 70841B PATTERN GENERATOR HDMP-0421 FM_NODE[0] BIAS +K28.5 -K28.5 CLOCK REFCLK TO_NODE[0] BYPASS-[0] BYPASS-[1] N/C DATA 2 1062.5 MHz 1.4 106.25 MHz 2 70311A CLOCK SOURCE 1/10 VARIABLE DELAY CH 1/2 106.25 MHz TRIGGER 83480A DIGITAL COMMUNICATION ANALYZER Figure 8. Setup for Measurement of Deterministic Jitter. 10 O_LVTTL VCC I_LVTTL VCC VCC INTERNAL 1.4 V REFERENCE GND GND ESD PROTECTION ESD PROTECTION GND Figure 9. O-LVTTL and I-LVTTL Simplified Circuit Schematic. HS_OUT 75 VCCHS VCC VCC HS_IN + - VCC + - +TO_NODE Z0 = 75 0.01 F +FM_NODE 2*Z0 = 150 -TO_NODE Z0 = 75 GND ESD PROTECTION 0.01 F -FM_NODE GND ESD PROTECTION GND GND NOTE: 1. HS_IN INPUTS SHOULD NEVER BE CONNECTED TO GROUND AS PERMANENT DAMAGE TO THE DEVICE MAY RESULT. Figure 10. O-PECL and I-PECL Simplified Circuit Schematic. 11 D E1 E PIN 1 b A A1 e DIMENSION VALUE TOLERANCE A 2.00 A1 0.05/0.21 D 8.20 E 7.80 0.10 E1 5.30 0.10 e 0.65 b 0.30 LEAD COPLANARITY 0.10 MAX. MAX. MIN./MAX. 0.05 BASIC 0.05 ALL DIMENSIONS ARE IN MILLIMETERS Figure 11. HDMP-04221 Package Drawings. www.semiconductor.agilent.com Data subject to change. Copyright (c) 1999 Agilent Technologies, Inc. 5968-5121E (11/99) |
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