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| INTEGRATED CIRCUITS DATA SHEET TDA8779 10-bit converter interface (ADC/DAC) for quadrature transceiver Objective specification Supersedes data of 1996 Sep 05 File under Integrated Circuits, IC02 1996 Sep 18 Philips Semiconductors Objective specification 10-bit converter interface (ADC/DAC) for quadrature transceiver FEATURES * Two 10-bit ADCs with multiplexed outputs * Two 10-bit DACs with multiplexed inputs * Sampling rate for the ADCs and DACs up to 20 MHz * Digital outputs (for the ADC) and inputs (for the DAC) are TTL/CMOS compatible (2.7 to 5.5 V) * Internal reference voltage regulator * Power dissipation 520 mW * Standby mode. APPLICATIONS Wireless communication. QUICK REFERENCE DATA SYMBOL VCCA1 VCCD1 VCCA2 VCCD2 VCCO ICCA ICCD ICCO fCLK(ADC)max INLA DNLA fCLK(DAC)max INLD DNLD Ptot PARAMETER analog supply voltage for the ADC part digital supply voltage for the ADC part analog supply voltage for the DAC part digital supply voltage for the DAC part output stage supply voltage analog supply current digital supply current output stage supply current maximum clock frequency for the ADC part integral non linearity for the ADC part differential non linearity for the ADC part maximum clock frequency for the DAC part integral non linearity for the DAC part differential non linearity for the DAC part total power dissipation full-scale; ramp input; fCLK = 20 MHz full-scale; ramp input; fCLK = 20 MHz full-scale; ramp input; fCLK = 20 MHz 50% full-scale; ramp input; fCLK = 20 MHz ramp input; fCLK = 20 MHz CONDITIONS MIN. 4.75 4.75 4.75 4.75 2.7 - - - 20 - - 20 - - - TYP. 5.0 5.0 5.0 5.0 3.0 71 31 2 - 2 0.3 - 2 0.75 520 GENERAL DESCRIPTION TDA8779 The TDA8779 contains two 10-bit high speed ADCs and two 10-bit DACs for wireless communication (for use in transceiver modules). This device converts two analog input signals (channels I and Q) and digital inputs (D0 to D9) at a maximum sampling rate of 20 MHz. The input bias voltages for the analog input voltages are provided internally at the middle code. The analog input and output voltages are AC coupled. The data sampling is performed on the rising edge of the clock for ADCs and DACs. All reference voltages are generated internally. MAX. 5.5 5.5 5.5 5.5 5.5 - - - - - - - - - - UNIT V V V V V mA mA mA MHz LSB LSB MHz LSB LSB mW 1996 Sep 18 2 Philips Semiconductors Objective specification 10-bit converter interface (ADC/DAC) for quadrature transceiver ORDERING INFORMATION TYPE NUMBER TDA8779H PACKAGE NAME QFP44 DESCRIPTION plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm TDA8779 VERSION SOT307-2 BLOCK DIAGRAM handbook, full pagewidth VCCA1 7 INPUT BIAS DEC1 2 DEC2 3 DEC3 5 VCCD1 31 DGND1 28 STDBYA 29 REFERENCE REGULATOR TDA8779 32 10 10 10 34-43 44 OE INI 4 10-BIT ADC MUX INQ 6 10-BIT ADC 10 LATCHES BUFFER D0A to D9A VCCO 30 AGND1 1 26 BUFFER OUTI 9 10-BIT DAC BUFFER OUTQ 11 10-BIT DAC 10 10 LATCHES 10 10 CLKA CLKD 33 OGND 15-24 BUFFER D0D to D9D AGND2 13 REFERENCE REGULATOR 8 VCCA2 10 12 14 VCCD2 25 27 MGG075 DEC4 DEC5 DGND2 STDBYD Fig.1 Block diagram. 1996 Sep 18 3 Philips Semiconductors Objective specification 10-bit converter interface (ADC/DAC) for quadrature transceiver PINNING SYMBOL AGND1 DEC1 DEC2 INI DEC3 INQ VCCA1 VCCA2 OUTI DEC4 OUTQ DEC5 AGND2 VCCD2 D0D D1D D2D D3D D4D D5D D6D D7D D8D PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 DESCRIPTION analog ground 1 decoupling input 1 decoupling input 2 I channel ADC input decoupling input 3 Q channel ADC input analog supply voltage 1 for ADC part (+5 V) analog supply voltage 2 for DAC part (+5 V) I channel DAC analog output decoupling input 4 Q channel DAC analog output decoupling input 5 analog ground 2 digital supply voltage 2 for DAC part (+5 V) multiplexed input for the DACs; bit 0 multiplexed input for the DACs; bit 1 multiplexed input for the DACs; bit 2 multiplexed input for the DACs; bit 3 multiplexed input for the DACs; bit 4 multiplexed input for the DACs; bit 5 multiplexed input for the DACs; bit 6 multiplexed input for the DACs; bit 7 multiplexed input for the DACs; bit 8 OGND D0A D1A D2A D3A D4A D5A D6A D7A D8A D9A VCCO 33 34 35 36 37 38 39 40 41 42 43 44 OE 32 DGND1 STDBYA CLKA VCCD1 28 29 30 31 SYMBOL D9D DGND2 CLKD STDBYD PIN 24 25 26 27 TDA8779 DESCRIPTION multiplexed input for the DACs; bit 9 digital ground 2 transmission block clock power standby for the DAC part (active HIGH) digital ground 1 power standby for the ADC part (active HIGH) reception block clock digital supply voltage 1 for ADC part (+5 V) ADCs digital output enable (3-state output); (active LOW) input/output ground I and Q digital outputs; bit 0 I and Q digital outputs; bit 1 I and Q digital outputs; bit 2 I and Q digital outputs; bit 3 I and Q digital outputs; bit 4 I and Q digital outputs; bit 5 I and Q digital outputs; bit 6 I and Q digital outputs; bit 7 I and Q digital outputs; bit 8 I and Q digital outputs; bit 9 output supply voltage (2.7 to 5.5 V) 1996 Sep 18 4 Philips Semiconductors Objective specification 10-bit converter interface (ADC/DAC) for quadrature transceiver TDA8779 42 D8A 34 D0A 37 D3A 41 D7A 36 D2A 35 D1A 38 D4A 40 D6A 39 D5A 43 D9A handbook, full pagewidth 44 VCCO AGND1 DEC1 DEC2 INI DEC3 INQ VCCA1 VCCA2 OUTI 1 2 3 4 5 6 7 8 9 33 OGND 32 OE 31 VCCD1 30 CLKA 29 STDBYA TDA8779H 28 DGND1 27 STDBYD 26 CLKD 25 DGND2 24 D9D 23 D8D DEC4 10 OUTQ 11 D6D 21 DEC5 12 VCCD2 14 D0D 15 D1D 16 D2D 17 D3D 18 D4D 19 AGND2 D5D 20 D7D 22 13 MGG074 Fig.2 Pin configuration. 1996 Sep 18 5 Philips Semiconductors Objective specification 10-bit converter interface (ADC/DAC) for quadrature transceiver LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VCCA1 VCCA2 VCCD1 VCCD2 VCCO VCC PARAMETER analog supply voltage for ADC part analog supply voltage for DAC part digital supply voltage for ADC part digital supply voltage for DAC part output stage supply voltage voltage difference between: VCCA - VCCD VCCA - VCCO VCCD - VCCO Io Vi Vclk(p-p) Tstg Tamb Tj output current input voltage storage temperature operating ambient temperature junction temperature referenced to AGND AC input switching voltage (peak-to-peak value) referenced to DGND -1.0 -1.0 -1.0 - -0.3 - -55 -20 - CONDITIONS MIN. -0.3 -0.3 -0.3 -0.3 -0.3 TDA8779 MAX. +7.0 +7.0 +7.0 +7.0 +7.0 +1.0 +4.0 +4.0 10 +7.0 VCCD +150 +75 150 UNIT V V V V V V V V mA V V C C C THERMAL CHARACTERISTICS SYMBOL Rth j-a PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 75 UNIT K/W CHARACTERISTICS VCCA = V7 and V8 to V1 and V13 = 4.75 to 5.5 V; VCCD = V31 and V14 to V28 and V25 = 4.75 to 5.5 V; VCCO = V44 to V33 = 2.7 to 5.5 ; AGND1, AGND2, OGND, DGND1 and DGND2 are shorted together; Tamb = -20 to +70 C; measured typically at VCCA = VCCD = 5 V and VCCO = 3 V; CL = 15 pF; Tamb = 25C; unless otherwise specified. SYMBOL Supplies VCCA1 VCCD1 VCCA2 VCCD2 VCCO VCC analog supply voltage for ADC part digital supply voltage for ADC part analog supply voltage for DAC part digital supply voltage for DAC part output stage supply voltage voltage difference between VCCA - VCCD VCCA - VCCO VCCD - VCCO ICCA ICCD 1996 Sep 18 analog supply current digital supply current 6 -0.2 -0.2 -0.2 - - - - - 71 31 +0.2 +2.5 +2.5 - - V V V mA mA 4.75 4.75 4.75 4.75 2.7 5.0 5.0 5.0 5.0 3.0 5.5 5.5 5.5 5.5 5.5 V V V V V PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Philips Semiconductors Objective specification 10-bit converter interface (ADC/DAC) for quadrature transceiver SYMBOL ICCO ICCA1(stb) ICCA2(stb) ADC PART CLOCK INPUT VIL VIH IIL IIH VIL VIH IIL IIH IIL IIH Vi(p-p) Vi(p-p)over ZI CI VOL VOH IoZ fCLKmax tCH tCL tr tf LOW level input voltage HIGH level input voltage LOW level input current HIGH level input current 0 2.2 -10 -10 0 2.2 -1 - for code 0 for code 1023 full-scale overvoltage - - tbf - - - Io = 1 mA Io = -1 mA 0.5 V < Vo < VCCO - 0.5 V 0 -20 20 20 20 - - - - - - - - 0 - tbf tbf 1.5 - 10 3 - - - - - 4 4 PARAMETER output stage supply current analog standby current for ADC part analog standby current for DAC part CONDITIONS ramp input; fCLK = 20 MHz - - - MIN. TYP. 2 5 5 TDA8779 MAX. - - - UNIT mA mA mA 0.6 +10 +10 V A A V A A A A V V k pF VCCD1 V DIGITAL INPUTS: PINS OE AND STDBYA LOW level input voltage HIGH level input voltage LOW level input current HIGH level input current 0.6 +1 1 - - tbf 4.5 - - 0.5 VCCO +20 - - - - - VCCD1 V ANALOG INPUTS LOW level input current HIGH level input current analog input voltage (peak-to-peak value) maximum analog input over voltage (peak-to-peak value) input impedance input capacitance DIGITAL OUTPUTS: D0A TO D9A LOW level output voltage HIGH level output voltage output current in 3-state mode V V A MHz ns ns ns ns VCCO - 0.5 - SWITCHING CHARACTERISTICS (see Fig.3) maximum clock frequency clock pulse width HIGH clock pulse width LOW clock rise time clock fall time 1996 Sep 18 7 Philips Semiconductors Objective specification 10-bit converter interface (ADC/DAC) for quadrature transceiver SYMBOL PARAMETER CONDITIONS MIN. TYP. TDA8779 MAX. UNIT ANALOG SIGNAL PROCESSING Linearity INLA DNLA integral non linearity differential non linearity ramp input; fCLK = 20 MHz full-scale; ramp input; fCLK = 20 MHz 50% full-scale; ramp input; fCLK = 20 MHz - - - 2 0.5 0.3 - - - LSB LSB LSB Noise floor; note 2 NF noise floor fin = 5.1 MHz; 20 Msps fi = 5.1 MHz; 20 Msps fi = 5.1 MHz; 20 Msps fin = 5.1 MHz; fCLK = 20 MHz; Tamb = 25C fin = 5.1 MHz; fCLK = 20 MHz; Tamb = 25C full-scale sine wave; Tamb = 25C; 50% full-scale sine wave; Tamb = 25C; tds th td sampling delay time output hold time output delay time VCCO = 4.75 V VCCO = 3.15 V VCCO = 2.7 V 3-STATE OUTPUT DELAY TIMES; see Fig.4 tdZH tdZL tdHZ tdLZ output delay enable HIGH output delay enable LOW output delay disable HIGH output delay disable LOW - - - - 14 16 16 14 18 20 20 18 ns ns ns ns - - 45 - -60 -54 56 - - - - 6 dB Harmonics; note 3 THD total harmonic distortion dB Spurious free dynamic range SFDR V spurious free dynamic range dB Matching between the I and Q channels amplitude matching % phase matching - - 2 Deg Bandwidth B bandwidth maximum attenuation of -0.3 dB 5.5 tbf - - - - MHz MHz TIMING: (THE OUTPUT DATA IS AVAILABLE AFTER THE MAXIMUM DELAY TIME td); CL = 15 pF; see Fig.3 - 5 - - - - - 12 17 21 5 - 15 20 24 ns ns ns ns ns 1996 Sep 18 8 Philips Semiconductors Objective specification 10-bit converter interface (ADC/DAC) for quadrature transceiver SYMBOL PARAMETER CONDITIONS - - fCLK(DAC) = 16.384 MHz; - fCLK(ADC) = 8.192 MHz; Tamb = 25C; both DACs switching between input codes 0 and 1023; one ADC 1 V (p-p) sine wave at 4 MHz and the other ADC set at the middle code MIN. TYP. - - - TDA8779 MAX. UNIT s s dB STANDBY MODE OUTPUT DELAY TIMES; STDBYA td(stb)LH td(stb)HL ct standby (LOW-to-HIGH transition) start-up (HIGH-to-LOW transition) 100 100 -55 CROSSTALK ON THE ADC crosstalk into the ADC DAC PART DIGITAL INPUTS: D0D TO D9D AND CLKD VIL VIH IIL IIH VIL VIH IIL IIH fCLK(max) tCH tCL tr tf ts th Vo(p-p) ZoL LOW level input voltage HIGH level input voltage LOW level input current HIGH level input current 0 2.2 -200 -10 0 2.2 -1 - 20 20 20 - - 10 0 - - -120 - - - 0 - - - - 4 4 tbf tbf 0.6 0 +10 V A A V A A MHz ns ns ns ns ns ns VCCD2 V DIGITAL INPUT; STDBYD LOW level input voltage HIGH level input voltage LOW level input current HIGH level input current 0.6 +1 1 - - - - - - - tbf - - - - - VCCD2 V TIMING: see Fig.5 maximum clock frequency clock pulse width HIGH clock pulse width LOW clock rise time clock fall time input data set-up time input data hold time ANALOG OUTPUTS; note 1 output voltage (peak-to-peak value) output load impedance full-scale see Fig.6 tbf - - TRANSFER FUNCTION INLD DNLD B integral non linearity differential non linearity maximum bandwidth ramp input; fCLK = 20 MHz ramp input; fCLK = 20 MHz; full scale; Tamb = 25C - - 5.5 3 0.75 - LSB LSB MHz 1 15 0.3 V pF k 1996 Sep 18 9 Philips Semiconductors Objective specification 10-bit converter interface (ADC/DAC) for quadrature transceiver SYMBOL V PARAMETER CONDITIONS - MIN. TYP. - TDA8779 MAX. UNIT Matching between channel I and Q amplitude matching fo = 5.1 MHz; fCLK = 20 MHz; Tamb = 25C fo = 5.1 MHz; fCLK = 20 MHz; Tamb = 25C fo = 5.1 MHz; fCLK = 20 MHz fo = 5.1 MHz; fCLK = 20 MHz 6 % phase matching - - 2 Deg DYNAMIC RANGE; note 2 - -60 - dB NF noise floor SPURIOUS FREE DYNAMIC RANGE SFDR spurious free dynamic range - 50 - dB STANDBY MODE OUTPUT DELAY; STDBYD td(stb)LH td(stb)HL ct standby (LOW-to-HIGH transition) start-up (HIGH-to-LOW transition) - - fCLK(DAC) = 16.384 MHz; - fCLK(ADC) = 8.192 MHz; Tamb = 25C; one DAC switching between input codes 0 and 1023 the other DAC set at the middle code; both ADCs 1 V (p-p) sine wave at 4 MHz; incoherent - - - 100 100 -55 s s dB CROSSTALK ON THE DAC crosstalk into the DAC Notes 1. It is recommended that the DAC output voltage is AC coupled in order to achieve optimum performance. 2. The noise floor is the maximum value of the output spectrum without taking into account fundamental and harmonics of the input signal. 3. Harmonics are obtained via a Fast Fourier Transformer (FFT) treatment taking 8K acquisition points per period. 1996 Sep 18 10 Philips Semiconductors Objective specification 10-bit converter interface (ADC/DAC) for quadrature transceiver Table 1 STEP underflow 0 ... 512 ... 1023 overflow Table 2 STEP D9D 0 ... 512 ... 1023 Table 3 0 ... 1 ... 1 D8D 0 ... 0 ... 1 D7D 0 ... 0 ... 1 D6D 0 ... 0 ... 1 D5D 0 ... 0 ... 1 D4D 0 ... 0 ... 1 D3D 0 ... 0 ... 1 D2D 0 ... 0 ... 1 D1D 0 ... 0 ... 1 D0D 0 ... 0 ... 0 Output coding and input voltage (typical value, referenced to AGND) Vi - V512 (V) <-0.75 -0.75 ... 0 ... 0.75 >0.75 BINARY OUTPUT BITS D9A 0 0 ... 1 ... 1 1 D8A 0 0 ... 0 ... 1 1 D7A 0 0 ... 0 ... 1 1 D6A 0 0 ... 0 ... 1 1 D5A 0 0 ... 0 ... 1 1 D4A 0 0 ... 0 ... 1 1 D3A 0 0 ... 0 ... 1 1 D2A 0 0 ... 0 ... 1 1 TDA8779 D1A 0 0 ... 0 ... 1 1 D0A 0 0 ... 0 ... 0 1 Input coding and output voltage (typical value, referenced to DGND) BINARY INPUT BITS Vo - V512 (V) -0.5 ... 0 ... 0.5 Mode selection OE 1 0 D0A TO D9A high impedance active; binary Table 4 Standby selection D0 TO D9 - active ICCA + ICCD (typ.) 5 mA 64 mA STDBYA 1 0 Table 5 Standby selection STDBYD 1 0 OUTI AND OUTQ - active ICCA + ICCD (typ.) 5 mA 38 mA 1996 Sep 18 11 Philips Semiconductors Objective specification 10-bit converter interface (ADC/DAC) for quadrature transceiver TDA8779 handbook, full pagewidth tCH n tCL 50% CLKA I CHANNEL ADC OUTPUT In - 2 In - 1 In In + 1 Q CHANNEL ADC OUTPUT Qn - 2 Qn - 1 Qn Qn + 1 Q CHANNEL LATCHED DATA Qn - 2 Qn - 1 Qn Qn + 1 MULTIPLEXED OUTPUTS In - 2 Qn - 2 In - 1 Qn - 1 td In Qn In + 1 tds ViI or ViQ sample N th MGG078 Fig.3 Timing diagram for the ADC. 1996 Sep 18 12 Philips Semiconductors Objective specification 10-bit converter interface (ADC/DAC) for quadrature transceiver TDA8779 V handbook, full pagewidthCCD OE 50% tdHZ HIGH 90% output data tdLZ HIGH output data LOW 10% tdZL LOW tdZH 50% VCCD 50% 3.3 k TDA8779 10 pF OE MGG077 S1 tOE = 100 kHz. Fig.4 Timing diagram and test conditions of 3-state output delay time. Table 6 Test conditions for Fig.4 TEST tdLZ tdZL tdHZ tdZH SWITCH S1 VCCD VCCD DGND DGND 1996 Sep 18 13 Philips Semiconductors Objective specification 10-bit converter interface (ADC/DAC) for quadrature transceiver TDA8779 handbook, full pagewidth th tCH tCL 50% CLKD n ts MULTIPLEXED INPUTS In Qn In + 1 Qn + 1 In + 2 Qn + 2 In + 3 I CHANNEL LATCHED DATA In In + 1 In + 2 In + 3 I CHANNEL DAC OUTPUT In - 1 In In + 1 In + 2 Q CHANNEL DAC OUTPUT Qn - 1 Qn Qn + 1 Qn + 2 MGG079 Fig.5 DACs multiplexed inputs timing diagram. handbook, halfpage TDA8779 9,11 I, Q 1 F 300 15 pF MGG076 Fig.6 Equivalent DACs output load. 1996 Sep 18 14 Philips Semiconductors Objective specification 10-bit converter interface (ADC/DAC) for quadrature transceiver APPLICATION INFORMATION TDA8779 handbook, full pagewidth VCCA1 7 INPUT BIAS 100 nF 100 nF 10 nF DEC1 DEC2 2 3 47 VCCD1 nF DEC3 5 31 DGND1 28 STDBYA 29 REFERENCE REGULATOR TDA8779H 32 10 10 10 34-43 44 OE INI 4 10-BIT ADC MUX 100 nF INQ 6 10-BIT ADC 10 LATCHES BUFFER D0A to D9A VCCO 30 AGND1 1 26 BUFFER OUTI 9 10-BIT DAC BUFFER 11 10-BIT DAC 10 10 LATCHES 10 10 CLKA CLKD 1 F 15 pF 33 OGND 300 1 F 15-24 BUFFER D0D to D9D 15 pF OUTQ 300 AGND2 13 REFERENCE REGULATOR 8 VCCA2 10 nF 12 10 DEC4 DEC5 22 nF 14 VCCD2 25 27 MBH581 DGND2 STDBYD Fig.7 Application diagram. 1996 Sep 18 15 Philips Semiconductors Objective specification 10-bit converter interface (ADC/DAC) for quadrature transceiver PACKAGE OUTLINE QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm TDA8779 SOT307-2 c y X A 33 34 23 22 ZE e Q E HE wM bp pin 1 index 44 1 bp D HD wM 11 ZD B vM B vMA 12 detail X A A2 A1 (A 3) Lp L e 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.10 A1 0.25 0.05 A2 1.85 1.65 A3 0.25 bp 0.40 0.20 c 0.25 0.14 D (1) 10.1 9.9 E (1) 10.1 9.9 e 0.8 HD 12.9 12.3 HE 12.9 12.3 L 1.3 Lp 0.95 0.55 Q 0.85 0.75 v 0.15 w 0.15 y 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 10 0o o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT307-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 92-11-17 95-02-04 1996 Sep 18 16 Philips Semiconductors Objective specification 10-bit converter interface (ADC/DAC) for quadrature transceiver SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Reflow soldering Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Handbook" (order code 9397 750 00192). Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. Wave soldering TDA8779 Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering the following packages: QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. 1996 Sep 18 17 Philips Semiconductors Objective specification 10-bit converter interface (ADC/DAC) for quadrature transceiver DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values TDA8779 This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1996 Sep 18 18 Philips Semiconductors Objective specification 10-bit converter interface (ADC/DAC) for quadrature transceiver NOTES TDA8779 1996 Sep 18 19 Philips Semiconductors - a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722 Indonesia: see Singapore Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 926 5361, Fax. +7 095 564 8323 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Rua do Rocio 220, 5th floor, Suite 51, 04552-903 Sao Paulo, SAO PAULO - SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 829 1849 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 3 301 6312, Fax. +34 3 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 632 2000, Fax. +46 8 632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2686, Fax. +41 1 481 7730 Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West Road, Sec. 1, P.O. Box 22978, TAIPEI 100, Tel. +886 2 382 4443, Fax. +886 2 382 4444 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 825 344, Fax.+381 11 635 777 For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1996 Internet: http://www.semiconductors.philips.com SCA51 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 537021/1200/02/pp20 Date of release: 1996 Sep 18 Document order number: 9397 750 01181 |
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