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DATA SHEET
MOS INTEGRATED CIRCUIT
PD720113
USB 2.0 HUB CONTROLLER
The PD720113 is a USB 2.0 hub device that complies with the Universal Serial Bus (USB) Specification Revision 2.0 and works up to 480 Mbps. USB 2.0 compliant transceivers are integrated for upstream and all downstream ports. The PD720113 works backward compatible either when any one of the downstream ports is connected to a USB 1.1 compliant device, or when the upstream port is connected to a USB 1.1 compliant host. Detailed function descriptions are provided in the following user's manual. Be sure to read the manual before designing.
PD720113 User's Manual: S16619E
FEATURES
* Compliant with Universal Serial Bus Specification Revision 2.0 (Data Rate 1.5/12/480 Mbps) * Certified by USB implementers forum and granted the USB 2.0 high-speed Logo * High-speed or full-speed packet protocol sequencer for Endpoint 0/1 * 7 (Max.) downstream facing ports * All downstream facing ports can handle high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) transaction. * Supports split transaction to handle full-speed and low-speed transaction on downstream facing ports when Hub controller is working in high-speed mode. * One Transaction Translator per Hub and supports four non-periodic buffers * Support self-powered mode * Supports Over-current detection and Individual or ganged power control * Supports configurable vendor ID, product ID, string descriptors and others with external Serial ROM * Supports "non-removable" attribution on individual port * Uses 30 MHz X'tal, or clock input * 2.5 V and 3.3 V power supplies
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information.
Document No. S16618EJ3V0DS00 (3rd edition) Date Published March 2005 NS CP (N) Printed in Japan
The mark
shows major revised points.
2003
PD720113
ORDERING INFORMATION
Part Number Package 80-pin plastic TQFP (Fine pitch) (12 x 12) 80-pin plastic TQFP (Fine pitch) (12 x 12) Lead-free product Remark
PD720113GK-9EU PD720113GK-9EU-A
BLOCK DIAGRAM
To Host/Hub downstream facing port
Upstream facing port UP_PHY
CDR
SERDES
UPC
FS_REP
SIE_2H ALL_TT F_TIM EP1 EP0 External Serial ROM
CDR
DP(1)_PHY Downstream facing port #1 DP(2)_PHY
To Hub/Function upstream facing port To Hub/Function upstream facing port To Hub/Function upstream facing port To Hub/Function upstream facing port To Hub/Function upstream facing port To Hub/Function upstream facing port To Hub/Function upstream facing port
ROM I/F
Downstream facing port #2 DP(3)_PHY Downstream facing port #3
DPC
APLL
DP(4)_PHY Downstream facing port #4
X1_CLK/X2
OSB
DP(5)_PHY Downstream facing port #5 DP(6)_PHY Downstream facing port #6 DP(7)_PHY Downstream facing port #7
CSB(7:1)
PPB(7:1)
2
Data Sheet S16618EJ3V0DS
PD720113
APLL ALL_TT : Generates all clocks of Hub. : Translates the high-speed transactions (split transactions) for full/low-speed device to full/low-speed transactions. ALL_TT buffers the data transfer from either upstream or downstream direction. For OUT transaction, ALL_TT buffers data from upstream port and sends it out to the downstream facing ports after speed conversion from high-speed to full/low-speed. For IN transaction, ALL_TT buffers data from downstream ports and sends it out to the upstream facing ports after speed conversion from full/low-speed to high-speed. CDR DPC DP(n)_PHY EP0 EP1 F_TIM (Frame Timer) : Data & clock recovery circuit : Downstream Port Controller handles Port Reset, Enable, Disable, Suspend and Resume : Downstream transceiver supports high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) transaction : Endpoint 0 controller : Endpoint 1 controller : Manages hub's synchronization by using micro-SOF which is received at upstream port, and generates SOF packet when full/low-speed device is attached to downstream facing port. FS_REP OSB ROM I/F SERDES SIE_2H UP_PHY UPC : Full/low-speed repeater is enabled when the PD720113 are worked at full-speed mode : Oscillator Block : Interface block for external Serial ROM which contains user-defined descriptors : Serializer and Deserializer : Serial Interface Engine (SIE) controls USB2.0 and 1.1 protocol sequencer. : Upstream Transceiver supports high-speed (480 Mbps), full-speed (12 Mbps) transaction : Upstream Port Controller handles Suspend and Resume
Data Sheet S16618EJ3V0DS
3
PD720113
PIN CONFIGURATION (TOP VIEW)
* 80-pin plastic TQFP (Fine pitch) (12 x 12)
PD720113GK-9EU PD720113GK-9EU-A
80 VDD33 VDD25 VSS DM6 DP6 VDD33 VSS DM7 DP7 VSS VDD25 VSS TEST SCAN_MODE VSS LPWRM EXROM_EN SCL SDA/GANG_B VSS 1
DP5 DM5 VSS VDD25 DP4 DM4 VSS VDD25 VSS VDD33 DP3 DM3 VSS VDD33 DP2 DM2 VSS VDD25 DP1 DM1
75
70
65
61 60 VDD33 RPU VSS VDD25 DPU DMU VSS VDD33 VDD25 VSS AVDD AVSS AVDD AVSS(R) RREF AVSS VDD25 X2 X1_CLK VSS
5 55
10 50
15 45
20 21 25 30 35 40
41
4
VDD33 CSB7 PPB7 CSB6 PPB6 CSB5 PPB5 CSB4 VSS VDD25 PPB4 CSB3 PPB3 CSB2 PPB2 CSB1 PPB1 SYSRSTB VBUSM VDD33
Data Sheet S16618EJ3V0DS
PD720113
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pin Name VDD33 VDD25 VSS DM6 DP6 VDD33 VSS DM7 DP7 VSS VDD25 VSS TEST SCAN_MODE VSS LPWRM EXROM_EN SCL SDA/GANG_B VSS Pin No. 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Pin Name VDD33 CSB7 PPB7 CSB6 PPB6 CSB5 PPB5 CSB4 VSS VDD25 PPB4 CSB3 PPB3 CSB2 PPB2 CSB1 PPB1 SYSRSTB VBUSM VDD33 Pin No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Pin Name VSS X1_CLK X2 VDD25 AVSS RREF AVSS(R) AVDD AVSS AVDD VSS VDD25 VDD33 VSS DMU DPU VDD25 VSS RPU VDD33 Pin No. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Pin Name DM1 DP1 VDD25 VSS DM2 DP2 VDD33 VSS DM3 DP3 VDD33 VSS VDD25 VSS DM4 DP4 VDD25 VSS DM5 DP5
Remark AVSS(R) should be used to connect RREF through 1 % precision reference resistor of 2.43 k.
Data Sheet S16618EJ3V0DS
5
PD720113
1. PIN INFORMATION
Pin Name I/O Buffer Type Active Level X1_CLK X2 SYSRSTB RPU DP(7:1) DM(7:1) DPU DMU LPWRM RREF CSB(7:1) PPB(7:1) VBUSM SCL SDA/GANG_B EXROM_EN TEST SCAN_MODE VDD33 VDD25 AVDD VSS AVSS AVSS(R) I O I A (O) I/O I/O I/O I/O I A (O) I O I O I/O I I I 2.5 V Input 2.5 V Output 5 V tolerant Schmitt Input USB Pull-up control USB D+ signal I/O USB D- signal I/O USB D+ signal I/O USB D- signal I/O 3.3 V Schmitt Input Analog 5 V tolerant Input 5 V tolerant N-ch open drain 5 V tolerant Schmitt input 3.3 V Output 3.3 V Schmitt I/O 3.3 V Schmitt Input 3.3 V Input 3.3 V Input Low Low Low Crystal oscillator in or clock input Oscillator out Asynchronous chip reset External 1.5 k pull-up resistor control USB's downstream facing port D+ signal USB's downstream facing port D- signal USB's upstream facing port D+ signal USB's upstream facing port D- signal Local power monitor Reference resistor Port's over-current status input Port's power supply control output VBUS monitor External serial ROM clock out External serial ROM data IO or power management mode select External serial ROM input enable Test signal Test signal 3.3 V VDD 2.5 V VDD 2.5 V VDD for analog circuit VSS VSS for analog circuit VSS for reference resistor. Connect to AVSS. Function
Remark "5 V tolerant" means that the buffer is 3 V buffer with 5 V tolerant circuit.
6
Data Sheet S16618EJ3V0DS
PD720113
2.
2.1 * * * * * * * *
ELECTRICAL SPECIFICATIONS
Buffer List 2.5 V Oscillator interface X1_CLK, X2 5 V Schmitt input buffer SYSRSTB, CSB(7:1), VBUSM 3.3 V Schmitt input buffer LPWRM 3.3 V input buffer EXROM_EN, TEST, SCAN_MODE 3.3 V IOL = 3 mA bi-directional Schmitt input buffer with input enable (OR-type) SDA/GANG_B 3.3 V IOL = 3 mA output buffer SCL 5 V IOL = 12 mA N-ch open drain buffer PPB(7:1) USB2.0 interface RPU, DPU, DMU, DP(7:1), DM(7:1), RREF Above, "5 V" refers to a 3 V input buffer that is 5 V tolerant (has 5 V maximum input voltage). Therefore, it is
possible to have a 5 V connection for an external bus.
Data Sheet S16618EJ3V0DS
7
PD720113
2.2 Terminology
Terms Used in Absolute Maximum Ratings
Parameter Power supply voltage Symbol VDD33 VDD25 AVDD Input voltage Output voltage Output current Operating temperature Storage temperature VI VO IO TA Tstg Meaning Indicates voltage range within which damage or reduced reliability will not result when power is applied to a VDD pin. Indicates voltage range within which damage or reduced reliability will not result when power is applied to an input pin. Indicates voltage range within which damage or reduced reliability will not result when power is applied to an output pin. Indicates absolute tolerance values for DC current to prevent damage or reduced reliability when current flows out of or into an output pin. Indicates the ambient temperature range for normal logic operations. Indicates the element temperature range within which damage or reduced reliability will not result while no voltage or current are applied to the device.
Terms Used in Recommended Operating Range
Parameter Power supply voltage Symbol VDD33 VDD25 AVDD High-level input voltage VIH Meaning Indicates the voltage range for normal logic operations to occur when VSS = 0 V. Indicates the voltage, applied to the input pins of the device, which indicates the high level state for normal operation of the input buffer. * If a voltage that is equal to or greater than the "MIN." value is applied, the input voltage is guaranteed as high level voltage. Low-level input voltage VIL Indicates the voltage, applied to the input pins of the device, which indicates the low level state for normal operation of the input buffer. * If a voltage that is equal to or less than the "MAX." value is applied, the input voltage is guaranteed as low level voltage. Hysteresis voltage Input rise time Input fall time VH tri tfi Indicates the differential between the positive trigger voltage and the negative trigger voltage. Indicates allowable input signal transition time from 0.1 x VDD to 0.9 x VDD. Indicates allowable input signal transition time from 0.9 x VDD to 0.1 x VDD.
8
Data Sheet S16618EJ3V0DS
PD720113
Terms Used in DC Characteristics
Parameter Off-state output leakage current Output short circuit current Input leakage current Low-level output current High-level output current Symbol IOZ IOS II IOL IOH Meaning Indicates the current that flows into a 3-state output pin when it is in a highimpedance state and a voltage is applied to the pin. Indicates the current that flows from an output pin when it is shorted to GND while it is at high-level. Indicates the current that flows into an input pin when a voltage is applied to the pin. Indicates the current that can flow into an output pin in the low-level state without raising the output voltage above the specified VOL. Indicates the current that can flow out of an output pin in the high-level state without reducing the output voltage below the specified VOH. (A negative current indicates current flowing out of the pin.)
2.3
Electrical Specifications
Absolute Maximum Ratings
Parameter Power supply voltage Symbol VDD33 VDD25 AVDD Input/output voltage 2.5 V input/output voltage 3.3 V input/output voltage 5 V input/out voltage Output current IO VI/VO 2.3 V VDD25 2.7 V VI /VO < VDD25 + 0.9 V 3.0 V VDD33 3.6 V VI /VO < VDD33 + 1.0 V 3.0 V VDD33 3.6 V VI /VO < VDD33 + 3.0 V IOL = 3 mA IOL = 6 mA IOL = 12 mA Operating temperature Storage temperature TA Tstg 10 20 40 0 to +70 -65 to +150 mA mA mA C C -0.5 to +6.6 V -0.5 to +4.6 V -0.5 to +3.6 V Condition Rating -0.5 to +4.6 -0.5 to +3.6 -0.5 to +3.6 Unit V V V
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameters. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. The ratings and conditions indicated for DC characteristics and AC characteristics represent the quality assurance range during normal operation.
Data Sheet S16618EJ3V0DS
9
PD720113
Recommended Operating Ranges
Parameter Operating voltage Symbol VDD33 VDD25 AVDD High-level input voltage 2.5 V High-level input voltage 3.3 V High-level input voltage 5.0 V High-level input voltage Low-level input voltage 2.5 V Low-level input voltage 3.3 V Low-level input voltage 5.0 V Low-level input voltage Hysteresis voltage 5 V Hysteresis voltage 3.3 V Hysteresis voltage Input rise time for SYSRSTB Input rise time Normal buffer Schmitt buffer Input fall time Normal buffer Schmitt buffer tfi 0 0 200 10 ns ms trst tri 0 0 200 10 ns ms VH 0.3 0.2 1.5 1.0 10 V V ms VIL 0 0 0 0.7 0.8 0.8 V V V VIH 1.7 2.0 2.0 VDD25 VDD33 5.5 V V V Condition 3.3 V for VDD33 pins 2.5 V for VDD25 pins 2.5 V for AVDD pins MIN. 3.14 2.3 2.3 TYP. 3.30 2.5 2.5 MAX. 3.46 2.7 2.7 Unit V V V
Two power supply rails limitation. The PD720113 has two power supply rails (2.5 V, 3.3 V). The system will require the time when power supply rail is stable at VDD level. And, there will be difference between the time of VDD25 and VDD33. The PD720113 requires that VDD25 should be stable before VDD33 becomes stable. At any case, the system must ensure that the absolute maximum ratings for VI /VO are not exceeded. System reset signaling should be asserted more than specified time after both VDD25 and VDD33 are stable.
10
Data Sheet S16618EJ3V0DS
PD720113
DC Characteristics
Parameter Off-state output leakage current Output short circuit current Low-level output current 3.3 V low-level output current 3.3 V low-level output current 5.0 V low-level output current High-level output current 3.3 V high-level output current 3.3 V high-level output current 5.0 V high-level output current Input leakage current 3.3 V buffer 5.0 V buffer II VI = VDD or VSS VI = VDD or VSS 10 10 IOH VOH = 2.4 V VOH = 2.4 V VOH = 2.4 V -3 -6 -2 mA mA mA Symbol IOZ IOS IOL VOL = 0.4 V VOL = 0.4 V VOL = 0.4 V 3 6 12 mA mA mA
Note
Condition VO = VDD33, VDD25 or VSS
MIN.
MAX. 10 -250
Unit
A
mA
A A
Note The output short circuit time is measured at one second or less and is tested with only one pin on the LSI.
Data Sheet S16618EJ3V0DS
11
PD720113
USB Interface Block
Parameter Output pin impedance Bus pull-up resistor on upstream facing port Bus pull-up resistor on downstream facing port Termination voltage for upstream facing port pullup (full-speed) Input Levels for Low-/full-speed: High-level input voltage (drive) High-level input voltage (floating) Low-level input voltage Differential input sensitivity Differential common mode range Output Levels for Low-/full-speed: High-level output voltage Low-level output voltage SE1 Output signal crossover point voltage Input Levels for High-speed: High-speed squelch detection threshold (differential signal) High-speed disconnect detection threshold (differential signal) High-speed data signaling common mode voltage range High-speed differential input signaling levels Output Levels for High-speed: High-speed idle state High-speed data signaling high High-speed data signaling low Chirp J level (different signal) Chirp K level (different signal) VHSOI VHSOH VHSOL VCHIRPJ VCHIRPK -10.0 360 -10.0 700 -900 +10 440 +10 1100 -500 mV mV mV mV mV VHSSQ VHSDSC VHSCM See Figure 2-4. 100 525 -50 150 625 +500 mV mV mV VOH VOL VOSE1 VCRS RL of 14.25 k to GND RL of 1.425 k to 3.6 V 2.8 0.0 0.8 1.3 2.0 3.6 0.3 V V V V VIH VIHZ VIL VDI VCM (D+) - (D-) Includes VDI range 0.2 0.8 2.5 2.0 2.7 3.6 0.8 V V V V V Symbol ZHSDRV RPU RPD VTERM Conditions Includes RS resistor MIN 40.5 1.425 14.25 3.0 MAX 49.5 1.575 15.75 3.6 Unit k k V
12
Data Sheet S16618EJ3V0DS
PD720113
Figure 2-1. Differential Input Sensitivity Range for Low-/full-speed
Differential Input Voltage Range Differential Output Crossover Voltage Range
-1.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 4.6
Input Voltage Range (Volts)
Figure 2-2. Full-speed Buffer VOH/IOH Characteristics for High-speed Capable Transceiver
VDD-3.3
VDD-2.8 VDD-2.3
VDD-1.8 VDD-1.3 VDD-0.8
VDD-0.3 VDD 0
-20
IOUT (mA)
-40 Min. -60 Max. -80 VOUT (V)
Figure 2-3. Full-speed Buffer VOL/IOL Characteristics for High-speed Capable Transceiver
80 Max. 60
IOUT (mA)
Min. 40
20
0 0 0.5 1 1.5 VOUT (V) 2 2.5 3
Data Sheet S16618EJ3V0DS
13
PD720113
Figure 2-4. Receiver Sensitivity for Transceiver at DP/DM
Level 1
+400 mV Differential
Point 3
Point 4
Point 1
Point 2
0V Differential
Point 5
Point 6
Level 2
-400 mV Differential
0%
Unit Interval
100%
Figure 2-5. Receiver Measurement Fixtures
Test Supply Voltage 15.8 USB Connector Nearest Device VBUS D+ DGND 50 Coax 50 Coax + To 50 Inputs of a High Speed Differential Oscilloscope, or 50 Outputs of a High Speed Differential Data Generator -
15.8
143
143
14
Data Sheet S16618EJ3V0DS
PD720113
Power Consumption
Parameter Power Consumption Symbol PW-0 Condition The power consumption under the state without suspend. All the ports do not connect to any function.
Note
TYP.
Unit
Hub controller is operating at full-speed mode. Hub controller is operating at high-speed mode. PW-5 The power consumption under the state without suspend. The number of active ports is 5. Hub controller is operating at full-speed mode. Hub controller is operating at high-speed mode. PW-6 The power consumption under the state without suspend. The number of active ports is 6. Hub controller is operating at full-speed mode. Hub controller is operating at high-speed mode. PW-7 The power consumption under the state without suspend. The number of active ports is 7. Hub controller is operating at full-speed mode. Hub controller is operating at high-speed mode. PW_S The power consumption under suspend state. The internal clock is stopped.
44 2.2 84 23
mA (2.5 V) mA (3.3 V) mA (2.5 V) mA (3.3 V)
44 8.9 138 85
mA (2.5 V) mA (3.3 V) mA (2.5 V) mA (3.3 V)
44 10 148 98
mA (2.5 V) mA (3.3 V) mA (2.5 V) mA (3.3 V)
44 12 158 111 0.68 0.24
mA (2.5 V) mA (3.3 V) mA (2.5 V) mA (3.3 V) mA (2.5 V) mA (3.3 V)
Note
When any device is not connected to all the ports, the power consumption does not depend on the number of active ports.
Data Sheet S16618EJ3V0DS
15
PD720113
System Clock Ratings
Parameter Clock frequency Symbol fCLK X'tal Oscillator block Clock Duty cycle tDUTY Condition MIN. -500 ppm -500 ppm 40 30 50 TYP. 30 MAX. +500 ppm +500 ppm 60 MHz % Unit MHz
Remarks 1. Recommended accuracy of clock frequency is 100 ppm. 2. Required accuracy of X'tal or oscillator block is including initial frequency accuracy, the spread of X'tal capacitor loading, supply voltage, temperature, and aging, etc.
AC Characteristics (VDD = 3.14 to 3.46 V, TA = 0 to +70C) System Reset Timing
Parameter Reset active time (Figure 2-6) Symbol trst Conditions MIN. 5 MAX. Unit
s
Figure 2-6. System Reset Timing
trst
SYSRSTB
16
Data Sheet S16618EJ3V0DS
PD720113
Over-current Response Timing
Parameter Over-current response time from CSB low to PPB high (Figure 2-7) Symbol tOC Condition MIN. 500 TYP. MAX. 625 Unit
s
Figure 2-7. Over-current Response Timing
CSB(7:1) tOC PPB(7:1)
Figure 2-8. CSB/PPB Timing
500 s 500 s 500 s 500 s
Hub power supply
Bus reset
Up port D+ line
PPB pin output
Output cut-off
CSB pin input
Port power supply ON
Device connection inrush current
Overcurrent generation
CSB pin operation region
Bus power: Up port connection Self power: Power supply ON
CSB detection delay time
CSB active period
Remark
The active period of the CSB pin is in effect only when the PPB pin is ON. There is a delay time of approximately 500 s duration at the CSB pin.
Data Sheet S16618EJ3V0DS
17
PD720113
External Serial ROM Timing
Parameter Clock frequency Clock pulse width low Clock pulse width high Clock low to data out valid Time the bus must be free before a new transmission can start Start hold time Start setup time Data in hold time Data in setup time Stop setup time Data out hold time Write cycle time Symbol fSCL tLOW tHIGH tAA tBUF tHD.STA tSU.STA tHD.DTA tSU.DTA tSU.STO tDH tWR 4700 4000 100 4700 4000 4700 0 250 4700 300 15 3500 Condition MIN. TYP. 94.6 MAX. 100 Unit kHz ns ns ns ns ns ns ns ns ns ns ms
Figure 2-9. External Serial ROM Bus Timing
tHIGH tLOW SCL tSU.STA SDA (Output) tAA SDA (Input) tDH tBUF tHD.STA tHD.DAT tSU.DAT tSU.STO tLOW
Figure 2-10. External Serial ROM Write Cycle Timing
SCL
SDA Word n
8th bit
ACK
tWR Stop condition Start condition
18
Data Sheet S16618EJ3V0DS
PD720113
USB Interface Block (1/4)
Parameter Low-speed Electrical Characteristics Rise time (10% to 90%) Fall time (90% to 10%) Differential rise and fall time matching Low-speed data rate Downstream facing port source jitter total (including frequency tolerance) (Figure 2-15): To next transition For paired transitions Downstream facing port differential receiver jitter total (including frequency tolerance) (Figure 2-17): To next transition For paired transitions Source SE0 interval of EOP (Figure 2-16) Receiver SE0 interval of EOP (Figure 2-16) Width of SE0 interval during differential transition Hub differential data delay (Figure 2-13) Hub differential driver jitter (including cable) (Figure 2-13): Downstream facing port To next transition For paired transitions Upstream facing port To next transition For paired transitions Data bit width distortion after SOP (Figure 2-13) Hub EOP delay relative to tHDD (Figure 2-14) Hub EOP output width skew (Figure 2-14) Full-speed Electrical Characteristics Rise time (10% to 90%) Fall time (90% to 10%) Differential rise and fall time matching Full-speed data rate Frame interval tFR tFF tFRFM tFDRATHS tFRAME CL = 50 pF, RS = 36 CL = 50 pF, RS = 36 (tFR/tFF) Average bit rate 90 11.9940 0.9995 111.11 12.0060 1.0005 % Mbps ms 4 20 ns 4 20 ns tLHESK -300 +300 ns tLEOPD 0 200 ns tLUHJ1 tLUHJ2 tLSOP -45 -45 -60 +45 +45 +60 ns ns ns tLDHJ1 tLDHJ2 -45 -15 +45 +15 ns ns tLST tLHDD 210 300 ns ns tUJR1 tUJR2 tLEOPT tLEOPR -152 -200 1.25 670 +152 +200 1.5 ns ns tDDJ1 tDDJ2 -25 -14 +25 +14 ns ns tLR tLF tLRFM tLDRATHS CL = 200 pF to 600 pF CL = 200 pF to 600 pF (tLR/tLF)
Note
Symbol
Conditions
MIN.
MAX.
Unit
75 75 80 1.49925
300 300 125 1.50075
ns ns % Mbps
Average bit rate
s
ns
Note Excluding the first transition from the Idle state.
Data Sheet S16618EJ3V0DS
19
PD720113
(2/4)
Parameter Symbol Conditions MIN. MAX. Unit
Full-speed Electrical Characteristics (Continued) Consecutive frame interval jitter Source jitter total (including frequency tolerance) (Figure 2-15): To next transition For paired transitions Source jitter for differential transition to SE0 transition (Figure 2-16) Receiver jitter (Figure 2-17): To Next Transition For Paired Transitions Source SE0 interval of EOP (Figure 2-16) Receiver SE0 interval of EOP (Figure 2-16) Width of SE0 interval during differential transition Hub differential data delay (Figure 2-13) (with cable) (without cable) Hub differential driver jitter (including cable) (Figure 2-13): To next transition For paired transitions Data bit width distortion after SOP (Figure 2-13) Hub EOP delay relative to tHDD (Figure 2-14) Hub EOP output width skew (Figure 2-14) High-speed Electrical Characteristics Rise time (10% to 90%) Fall time (90% to 10%) Driver waveform High-speed data rate Microframe interval Consecutive microframe interval difference Data source jitter Receiver jitter tolerance Hub data delay (without cable) Hub data jitter Hub delay variation range tHSR tHSF See Figure 2-11. tHSDRAT tHSFRAM tHSRFI See Figure 2-11. See Figure 2-4. tHSHDD See Figure 2-4, Figure 2-11. tHSHDV 5 highspeed Bit times 36 highspeed+4 ns Bit times 479.760 124.9375 480.240 125.0625 4 highspeed Mbps 500 500 ps ps tHDJ1 tHDJ2 tFSOP tFEOPD tFHESK -3 -1 -5 0 -15 +3 +1 +5 15 +15 ns ns ns ns ns tHDD1 tHDD2 70 44 ns ns tJR1 tJR2 tFEOPT tFEOPR tFST -18.5 -9 160 82 14 +18.5 +9 175 ns ns ns ns ns tDJ1 tDJ2 tFDEOP -3.5 -4.0 -2 +3.5 +4.0 +5 ns ns ns tRFI No clock adjustment Note 42 ns
s
Bit times
Note Excluding the first transition from the Idle state.
20
Data Sheet S16618EJ3V0DS
PD720113
(3/4)
Parameter Hub Event Timings Time to detect a downstream facing port connect event (Figure 2-19): Awake hub Suspended hub Time to detect a disconnect event at a hub's downstream facing port (Figure 2-18) Duration of driving resume to a downstream port (only from a controlling hub) Time from detecting downstream resume to rebroadcast Duration of driving reset to a downstream facing port (Figure 2-20) Time to detect a long K from upstream Time to detect a long SE0 from upstream Duration of repeating SE0 upstream (for low-/full-speed repeater) Inter-packet delay (for high-speed) of packets traveling in same direction Inter-packet delay (for high-speed) of packets traveling in opposite direction Inter-packet delay for device/root hub response with detachable cable for highspeed Time of which a Chirp J or Chirp K must be continuously detected (filtered) by hub or device during Reset handshake Time after end of device Chirp K by which hub must start driving first Chirp K in the hub's chirp sequence Time for which each individual Chirp J or Chirp K in the chirp sequence is driven downstream by hub during reset Time before end of reset by which a hub must end its downstream chirp sequence Time from internal power good to device pulling D+ beyond VIHZ (Figure 2-20) Debounce interval provided by USB system software after attach (Figure 2-20) Maximum duration of suspend averaging interval Period of idle bus before device can initiate resume Duration of driving resume upstream tDCHSE0 tSIGATT tATTDB tSUSAVGI tWTRSM tDRSMUP 5 1 15 100 500 100 100 1 tDCHBIT 40 60 tWTDCH 100 tFILT 2.5 tURSM tDRST tURLK tURLSE0 tURPSE0 tHSIPDSD tHSIPDOD tHSRSPIPD1 88 8 192 Only for a SetPortFeature (PORT_RESET) request 10 2.5 2.5 1.0 20 100 10000 23 ms ms tDDIS tDRSMDN 2.5 2.5 2.0 20 2000 12000 2.5 tDCNN Symbol Conditions MIN. MAX. Unit
s s s
ms
s s
FS Bit times Bit times Bit times Bit times
s
s
s
s
ms ms s ms ms
Data Sheet S16618EJ3V0DS
21
PD720113
(4/4)
Parameter Hub Event Timings (Continued) Resume recovery time Time to detect a reset from upstream for non high-speed capable devices Reset recovery time (Figure 2-20) Inter-packet delay for full-speed Inter-packet delay for device response with detachable cable for full-speed SetAddress() completion time Time to complete standard request with no data Time to deliver first and subsequent (except last) data for standard request Time to deliver last data for standard request Time for which a suspended hub will see a continuous SE0 on upstream before beginning the high-speed detection handshake Time a hub operating in non-suspended full-speed will wait after start of SE0 on upstream before beginning the high-speed detection handshake Time a hub operating in high-speed will wait after start of SE0 on upstream before reverting to full-speed Time a hub will wait after reverting to fullspeed before sampling the bus state on upstream and beginning the high-speed will wait after start of SE0 on upstream before reverting to full-speed Minimum duration of a Chirp K on upstream from a hub within the reset protocol Time after start of SE0 on upstream by which a hub will complete its Chirp K within the reset protocol Time between detection of downstream chip and entering high-speed state Time after end of upstream Chirp at which hub reverts to full-speed default state if no downstream Chirp is detected tWTHS tWTFS 1.0 500 2.5 tUCHEND 7.0 ms tUCH 1.0 ms tWTRSTHS 100 875 ms tWTREV 3.0 3.125 ms tWTRSTFS 2.5 3000 ms tRSMRCY tDETRST tRSTRCY tIPD tRSPIPD1 tDSETADDR tDRQCMPLTND tDRETDATA1 tDRETDATAN tFILTSE0 2.5 2 6.5 50 50 500 50 Remote-wakeup is enabled 10 2.5 10000 10 ms Symbol Conditions MIN. MAX. Unit
s
ms Bit times Bit times ms ms ms ms
s
s
ms
22
Data Sheet S16618EJ3V0DS
PD720113
Figure 2-11. Transmit Waveform for Transceiver at DP/DM
Level 1
Point 3 Point 4
+400 mV Differential
Point 1
Point 2
0V Differential
Point 5
Point 6
Level 2 Unit Interval 0% 100%
-400 mV Differential
Figure 2-12. Transmitter Measurement Fixtures
Test Supply Voltage 15.8 USB Connector Nearest Device VBUS D+ DGND 50 Coax 50 Coax + To 50 Inputs of a High Speed Differential Oscilloscope, or 50 Outputs of a High Speed Differential Data Generator -
15.8
143
143
Data Sheet S16618EJ3V0DS
23
PD720113
Timing Diagram Figure 2-13. Hub Differential Delay, Differential Jitter, and SOP Distortion
Upstream End of Cable VSS
50% Point of Initial Swing
Upstream Port of Hub VSS
Crossover Point
Downstream Port of Hub VSS
Hub Delay Downstream tHDD1
Downstream Port of Hub VSS
Hub Delay Downstream tHDD2
50% Point of Initial Swing
A. Downstream Hub Delay with Cable
B. Downstream Hub Delay without Cable
Downstream Port of Hub VSS Upstream Port or End of Cable VSS
Crossover Point
Hub Delay Upstream tHDD1 tHDD2
Crossover Point
C. Upstream Hub Delay with or without Cable
Upstream end of cable
Upstream port
Downstream port Plug
Receptacle
Host or Hub
Hub
Function
Downstream signaling Upstream signaling
D. Measurement Points
Hub Differential Jitter: tHDJ1 = tHDDx(J) - tHDDx(K) or tHDDx(K) - tHDDx(J) Consecutive Transitions tHDJ2 = tHDDx(J) - tHDDx(J) or tHDDx(K) - tHDDx(K) Paired Transitions Bit after SOP Width Distortion (same as data jitter for SOP and next J transition): tFSOP = tHDDx(next J) - tHDDx(SOP) Low-speed timings are determined in the same way for: tLHDD, tLDHJ1, tLDJH2, tLUHJ1, tLUJH2, and tLSOP
24
Data Sheet S16618EJ3V0DS
PD720113
Figure 2-14. Hub EOP Delay and EOP Skew
Upstream End of Cable VSS
50% Point of Initial Swing Upstream Port of Hub VSS tEOP- tEOP+ tEOP- tEOP+ Downstream Port of Hub VSS Crossover Point Extended
Downstream Port of Hub VSS A. Downstream EOP Delay with Cable
B. Downstream EOP Delay without Cable
Downstream Port of Hub VSS tEOPUpstream Port or End of Cable VSS
Crossover Point Extended
tEOP+ Crossover Point Extended
C. Upstream EOP Delay with or without Cable
EOP Delay: tFEOPD = tEOPy - tHDDx (tEOPy means that this equation applies to tEOP- and tEOP+) EOP Skew: tFHESK = tEOP+ - tEOPLow-speed timings are determined in the same way for: tLEOPD and tLHESK
Data Sheet S16618EJ3V0DS
25
PD720113
Figure 2-15. USB Differential Data Jitter for Low-/full-speed
tPERIOD Differential Data Lines Crossover Points
Consecutive Transitions N x tPERIOD + txDJ1 Paired Transitions N x tPERIOD + txDJ2
Figure 2-16. USB Differential-to-EOP Transition Skew and EOP Width for Low-/full-speed
tPERIOD Differential Data Lines Crossover Point
Crossover Point Extended
Diff. Data-toSE0 Skew N x tPERIOD + txDEOP
Source EOP Width: tFEOPT tLEOPT Receiver EOP Width: tFEOPR tLEOPR
Figure 2-17. USB Receiver Jitter Tolerance for Low-/full-speed
tPERIOD Differential Data Lines
txJR
txJR1
txJR2
Consecutive Transitions N x tPERIOD + txJR1 Paired Transitions N x tPERIOD + txJR2
26
Data Sheet S16618EJ3V0DS
PD720113
Figure 2-18. Low-/full-speed Disconnect Detection
D+/D- VIHZ (min)
VIL D-/D+ VSS tDDIS Device Disconnected Disconnect Detected
Figure 2-19. Full-/high-speed Device Connect Detection
D+ VIH
D- VSS tDCNN Device Connected Connect Detected
Figure 2-20. Power-on and Connection Events Timing
Hub port power OK Hub port power-on VBUS VIH (min) VIH D+ or D- t1
Attatch detected
Reset recovery time
4.01 V
t2SUSP
tDRST
USB system software reads device speed
tSIGATT tATTDB
tRSTRCY
Data Sheet S16618EJ3V0DS
27
PD720113
3. PACKAGE DRAWING
80-PIN PLASTIC TQFP (FINE PITCH) (12x12)
HD D
60 61
41 40 A
detail of lead end
A2 A3 E HE
A1
L Lp
80 1 ZE ZD b x
M
21 20
ITEM D (UNIT:mm) DIMENSIONS 12.000.20 12.000.20 1.00 14.000.20 14.000.20 1.100.10 0.100.05 0.25 0.600.15 0.220.05 0.17 +0.03 -0.07 3 +4 -3 0.50 0.08 0.08 1.25 1.25 0.50 1.000.20 K80GK-50-9EU
e
E A2 HD HE
L1
S
y S c
A A1 A3 Lp b c
NOTE Each lead centerline is located within 0.08 mm of its true position at maximum material condition.
e x y ZD ZE L L1
28
Data Sheet S16618EJ3V0DS
PD720113
4. RECOMMENDED SOLDERING CONDITIONS
The PD720113 should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html)
PD720113GK-9EU:
Soldering Method Infrared reflow
80-pin plastic TQFP (Fine pitch) (12 x 12)
Soldering Conditions Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Three times or less Exposure limit: 3 days
Note
Symbol IR35-103-3
(after that, prebake at 125C for 10 hours) -
Partial heating
Pin temperature: 300C max., Time: 3 seconds max. (per pin row)
Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period.
PD720113GK-9EU-A:
Soldering Method Infrared reflow
80-pin plastic TQFP (Fine pitch) (12 x 12) Lead-free product
Soldering Conditions Package peak temperature: 245C, Time: 60 seconds max. (at 220C or higher), Count: Three times or less Exposure limit: 7 days
Note
Symbol IR45-107-3
(after that, prebake at 125C for 10 hours) -
Partial heating
Pin temperature: 300C max., Time: 3 seconds max. (per pin row)
Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period.
Data Sheet S16618EJ3V0DS
29
PD720113
[MEMO]
30
Data Sheet S16618EJ3V0DS
PD720113
NOTES FOR CMOS DEVICES
1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. 5 POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. 6 INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device.
Data Sheet S16618EJ3V0DS
31
PD720113
USB logo is a trademark of USB Implementers Forum, Inc.
* The information in this document is current as of March, 2005. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above).
M8E 02. 11-1

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