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KS88C6216/C6224/C6232/P6232
PRODUCT OVERVIEW
1
PRODUCT OVERVIEW
SAM8 PRODUCT FAMILY
Samsung's SAM8 family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU with a wide range of integrated peripherals, in various mask-programmable ROM sizes. Analog its major CPU features are: -- Efficient register-oriented architecture -- Selectable CPU clock sources -- Idle and Stop power-down mode release by interrupt -- Built-in basic timer with watchdog function The sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more interrupt sources and vectors. Fast interrupt processing (within a minimum of six CPU clocks) can be assigned to specific interrupt levels.
KS88C6216/C6224/C6232/P6232 MICROCONTROLLERS
KS88C6216/C6224/C6232/P6232 single-chip 8-bit microcontrollers are based on the powerful SAM8 CPU architecture. The internal register file is logically expanded to increase the on-chip register space. KS88C6216/C6224/C6232/P6232 contain 16/32 K bytes of on-chip program ROM. In line with Samsung's modular design approach, the following peripherals are integrated with the SAM8 core: -- Four programmable I/O ports (total 27 pins) -- One 8-bit basic timer for oscillation stabilization and watchdog functions -- One 8-bit general-purpose timer/counter with selectable clock sources -- One 12-bit counter with selectable clock sources, including Hsync or Csync input -- One interval timer -- PWM block with seven 8-bit PWM circuits -- Sync processor block (for Vsync and Hsync I/O, Csync input, and Clamp signal output) -- DDC and normal Multi-master IIC-bus -- 4-channel A/D converter (8-bit resolution) KS88C6216/C6224/C6232/P6232 are a versatile microcontrollers which are ideal for use in multi-sync monitors or in general-purpose applications that require sophisticated timer/counter, PWM, sync signal processing, A/D converter, and multi-master IIC-bus support with DDC. They are available in a 42pin SDIP or a 44-pin QFP package.
OTP
KS88C6216/C6224/C6232 microcontrollers are also available in OTP (One Time Programmable) version named, KS88P6232. KS88P6232 microcontroller has an on-chip 32-Kbyte one-time-programmable EPROM instead of masked ROM. KS88P6232 is comparable to KS88C6216/C6224/C6232, both in function and pin configuration except its ROM size.
1-1
PRODUCT OVERVIEW
KS88C6216/C6224/C6232/P6232
FEATURES
CPU * SAM8 CPU core Pulse Width Modulator (PWM) * 8-bit PWM: 7-CH
Memory * * 16/24/32-Kbyte internal program memory (ROM) 464-byte general-purpose register area
Sync-Processor Block * * Vsync-I, Hsync-I, Csync-I input and Vsync-O, Hsync-O, Clamp-O output pins Pseudo sync signal output Auto SOG detection Auto Hsync polarity detection
Instruction Set * * 78 instructions IDLE and STOP instructions added for power-down modes
* *
DDC Multi-Master IIC-Bus 1-Ch * * Serial Peripheral Interface Support for Display Data Channel (DDC1/DDC2B/DDC2Bi/DDC2B+)
Instruction Execution Time * Minimum 500 ns (with 12 MHz CPU clock)
Interrupts * * * * Ten interrupt sources Ten interrupt vectors Seven interrupt level Fast interrupt feature
Normal Multi-Master IIC-Bus 1-Ch * Serial Peripheral Interface
A/D Converter * 4-channel; 8-bit resolution
General I/O * Four I/O Ports (total 27pins)
Oscillator Frequency * * 8 MHz to 12 MHz crystal operation Internal Max. 12 MHz CPU clock - 40 C to + 85 C
8-Bit Basic Timer * * Programmable timer for oscillation stabilization interval control or watchdog timer function Three selective internal clock frequencies
Operating Temperature Range *
Operating Voltage Range * 4.0 V to 5.5 V
Timer/Counters * * * One 8-bit Timer/Counter with several clock sources (Capture mode) One 12-bit Counter with H-sync and several clock sources One Interval Timer
Package Types * 42-pin SDIP, 44-pin QFP
1-2
KS88C6216/C6224/C6232/P6232
PRODUCT OVERVIEW
BLOCK DIAGRAM
P0.0 -P0.7/INT0 -INT2
P2.0 -P2.7
RESET
INT0-INT2 XIN XOUT MAIN OSC
PORT 0
PORT 2
VDD , AVREF VSS1, V SS2 TEST
INTERNAL BUS PORT 1 P1.0-P1.2
PWM0 * * * * PWM6
I/O PORT and INTERRUPT CONTROL 8-BIT PWM (7-CH) PORT3 SAM8 CPU P3.0-P3.7
Vsync-I Hsync-I Csync-I Vsync-O Hsync-O Clamp-O
SyncProcessor 16/24/32Kbyte ROM 464-Byte Register File
ADC
AD0 -AD3
MT0CAP
8-Bit Counter (Timer M0)
Multi Master IIC-Bus
SCL1 SDA1
12-Blt Counter (Timer M1)
Interval Timer (Timer M2)
Multi Master IIC-Bus and DDC1/2B/2Bi/2B+
MT1CK
SCL0
SDA0
Figure 1-1. Block Diagram
1-3
PRODUCT OVERVIEW
KS88C6216/C6224/C6232/P6232
PIN ASSIGNMENTS
P0.0/INT0 P0.1/INT1 P0.2/INT2 P0.3 P0.4/TM0CAP P0.5/TM1CK P0.6 P0.7 P1.0/SDA1 P1.1/SCL1 VDD VSS1 XOUT XIN TEST SDA0 SCL0
RESET
P1.2 P2.0/PWM0 P2.1/PWM1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
KS88C6216 /C6224/C6232 42-SDIP (Top View)
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
P3.7 P3.6 P3.5 P3.4 P3.3/AD3 P3.2/AD2 P3.1/AD1 P3.0/AD0 AVREF VSS2 P2.7/Csync-I Hsync-I Vsync-I Vsync-O Hsync-O Clamp-O P2.6/PWM6 P2.5/PWM5 P2.4/PWM4 P2.3/PWM3 P2.2/PWM2
Figure 1-2. KS88C6216/C6224/C6232 42-SDIP Pin Assignment
1-4
KS88C6216/C6224/C6232/P6232
PRODUCT OVERVIEW
44 43 42 41 40 39 38 37 36 35 34
P0.4/TM0CAP P0.3 P0.2/INT2 P0.1/INT1 NC P0.0/INT0 P3.7 P3.6 P3.5 P3.4 P3.3/AD3
P0.5/TM1CK P0.6 P0.7 P1.0/SDA1 P1.1/SCL1 VDD VSS1 XOUT XIN TEST SDA0
1 2 3 4 5 6 7 8 9 10 11
KS88C6216/C6224 /C6232/P6232 44-QFP (Top View)
33 32 31 30 29 28 27 26 25 24 23
P3.2/AD2 P3.1/AD1 P3.0/AD0 AVREF VSS2 P2.7/Csync-I Hsync-I Vsync-I Vsync-O Hsync-O Clamp-O
SCL0
Figure 1-3. KS88C6224/C6232 44-QFP Pin Assignment
P1.2 P2.0/PWM0 P2.1/PWM1 P2.2/PWM2 NC P2.3/PWM3 P2.4/PWM4 P2.5/PWM5 P2.6/PWM6
RESET
12 13 14 15 16 17 18 19 20 21 22
1-5
PRODUCT OVERVIEW
KS88C6216/C6224/C6232/P6232
PIN DESCRIPTIONS
Table 1-1. KS88C6216/C6224/C6232/P6232 Pin Descriptions Pin Names P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0-P3.3 P3.4-P3.7 Pin Type I/O Pin Description General-purpose, 8-bit I/O port. Shared functions include three external interrupt inputs and I/O for timer M0 and M1. Selective configuration of port 0 pins to input or output mode is supported. Circuit Type D-1 D-1 D-1 D-1 D-1 D-1 D-1 D-1 E-1 E-1 E-1 D-1 D-1 D-1 D-1 E-1 E-1 E-1 D-1 D-1 E SDIP Pin Numbers 1 2 3 4 5 6 7 8 9 10 19 20 21 22 23 24 25 26 32 35-38, 39-42 Shared Functions INT0 INT1 INT2 TM0CAP TM1CK
I/O
General-purpose, 3-bit I/O port. Selective configuration is available for port 1 pins to input, push-pull output, n-channel opendrain mode, or IIC-bus clock and data I/O. General-purpose, 8-bit I/O port Selective configuration of port 2 pins to input or output mode is supported. The port 2 pin circuits are designed to push-pull PWM output and Csync signal input.
SDA1 SCL1
I/O
PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 Csync-I AD0-AD3
I/O
General-purpose, 8-bit I/O port Selective configuration port 3 pins to input or output mode is supported. Multiplexed for alternative use as A/D converter inputs AD0-AD3. The pins are sync processor signal I/O, IICbus clock, and data I/O.
Hsync-I Vsync-I Clamp-O Hsync-O Vsync-O SDA0 SCL0 VDD, VSS1, AVREF, VSS2
XIN, XOUT
I I O O O I/O I/O - - I I
A A A A A G-3 G-3 - - - B -
31 30 27 28 29 16 17 11, 12 34, 33 14, 13 18 15
-
Power pins ADC power pins System clock I/O pins System reset pin Factory test pin input 0V:Normal operation,5V:Factory test mode
- - - -
RESET
TEST
1-6
KS88C6216/C6224/C6232/P6232
PRODUCT OVERVIEW
PIN CIRCUITS
VDD VDD Data or Other Function Output Data Output Output Disable
VSS
VSS
Digital Input TTL Input or ADC Input
Figure 1-4. Pin Circuit Type A
Figure 1-6. Pin Circuit Type D-1
VDD 280 K
Noise Filter
RESET
Figure 1-5. Pin Circuit Type B (RESET)
1-7
PRODUCT OVERVIEW
KS88C6216/C6224/C6232/P6232
VDD Typical 47-K Pull-up Enable VDD Data
Output
Open drain
Output Disable VSS
Input
Figure 1-7. Pin Circuit Type E
VDD
Data
Output Open drain Output Disable VSS Input
Figure 1-8. Pin Circuit Type E-1
1-8
KS88C6216/C6224/C6232/P6232
PRODUCT OVERVIEW
Output Data VSS
Input
Figure 1-9. Pin Circuit Type G-3
1-9
PRODUCT OVERVIEW
KS88C6216/C6224/C6232/P6232
NOTES
1-10
KS88C6216/C6224/C6232/P6232
ELECTRICAL DATA
19
OVERVIEW
-- I/O capacitance
ELECTRICAL DATA
In this section, KS88C6216/C6224/C6232 electrical characteristics are presented in tables and graphs. The information is arranged in the following order: -- Absolute maximum ratings -- D.C. electrical characteristics -- Data retention supply voltage in stop mode -- Stop mode release timing when initiated by a reset -- A/D Converter electrical characteristics -- A.C. electrical characteristics -- Input timing measurement points for P0.0-P0.2, TM0CAP, and TM1CK -- Oscillation characteristics -- Oscillation stabilization time -- Clock timing measurement points for XIN -- Schmitt trigger characteristics
19-1
ELECTRICAL DATA
KS88C6216/C6224/C6232/P6232
Table 19-1. Absolute Maximum Ratings (TA = 25C) Parameter Supply voltage Input voltage Symbol VDD VI1 VI2 Output voltage Output current High Output current Low VO I OH Conditions - Type C (n-channel, open-drain) All port pins except VI1 All output pins One I/O pin active All I/O pins active I OL One I/O pin active Total pin current except port 3 Sync-processor I/O pins and IIC-bus clock and data pins Operating temperature Storage temperature TA TSTG - - Rating - 0.3 to + 6.5 - 0.3 to + 7.0 - 0.3 to VDD + 0.3 - 0.3 to VDD + 0.3 - 10 - 60 + 30 + 100 + 150 - 40 to + 85 - 65 to + 150
C C
Unit V V
V mA
mA
Table 19-2. D.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 4.0 V to 5.5 V) Parameter Input High voltage Symbol VIH1 VIH2 VIH3 Input Low voltage VIL1 VIL2 VIL3 Output High voltage VOH1 VOH2 VOH3 Conditions All input pins except VIH2 and VIH3 XIN TTL input (HsyncI, VsyncI, and CsyncI) All input pins except VIL2 and VIL3 XIN TTL input (HsyncI, VsyncI, and CsyncI) IOH = - 8 mA; Port 3 only IOH = - 2 mA Ports 0, 2, ClampO, H, and VsyncO IOH = - 6 mA; Port 1 VDD - 1.0 - Min 0.8 VDD 2.7 2.0 - - Typ - Max VDD VDD VDD 0.2 VDD 1.0 0.8 - V V Unit V
19-2
KS88C6216/C6224/C6232/P6232
ELECTRICAL DATA
Table 19-2. D.C. Electrical Characteristics (Continued) (TA = - 40 C to + 85 C, VDD = 4.0 V to 5.5 V) Parameter Output Low voltage Symbol VOL1 VOL2 VOL3 Input High leakage current ILIH1 ILIH2 ILIH3 Input Low leakage current ILIL1 ILIL2 ILIL3 Output High leakage current Output Low leakage current Pull-up resistor ILOH1 ILOL1 RL1 RL2 Supply current
(note)
Conditions IOL = 8 mA; port 3 only IOL = 2 mA Port 0, 2, ClampO, H, and VsyncO IOL = 6 mA Port 1; SCL and SDA VIN = VDD All input pins except XIN, XOUT VIN = VDD; XOUT only VIN = VDD; XIN only VIN = 0 V; All input pins except XIN, XOUT, and RESET VIN = 0 V; XOUT only VIN = 0 V; XIN only VOUT = VDD VOUT = 0 V VIN = 0 V Ports 3.7-3.4 VIN = 0 V RESET only Operation mode; 12 MHz crystal C1 = C2 = 22pF Idle mode; 12 MHz crystal C1 = C2 = 22pF Stop mode
Min -
Typ -
Max 0.4 0.4 0.6
Unit V
- - 2.5 - - - 2.5 - - 20 150 -
- - 6 - - -6 - - 47 280 15 5 1
3 20 20 -3 - 20 - 20 3 -3 80 480 30 10 10
A
A
A A k
IDD1 IDD2 IDD3
mA
A
NOTE: Supply current does not include drawn internal pull-up resistors and external loads of output.
19-3
ELECTRICAL DATA
KS88C6216/C6224/C6232/P6232
Table 19-3. Data Retention Supply Voltage in Stop Mode (TA = - 40 C to + 85 C) Parameter Data retention supply voltage Data retention supply current Symbol VDDDR IDDDR Conditions Stop mode Stop mode, VDDDR = 2.0 V Min 2 - Typ - - Max 5.5 5 Unit V A
NOTES: 1. During the oscillator stabilization wait time (tWAIT), all CPU operations must be stopped. 2. Supply current does not include drawn through internal pull-up resistors and external output current loads.
RESET OCCURS
OSCILLATION STABILIZATION TIME NORMAL OPERATING MODE
~ ~
STOP MODE DATA RETENTION MODE VDDDR
VDD
EXECUTION OF STOP INSTRUCTION
RESET
~ ~
NOTE: t WAIT is the same as 4,096 x x32 x 1/f OSC.
t WAIT
Figure 19-1. Stop Mode Release Timing When Initiated by a Reset
Table 19-4. Input/Output Capacitance (TA = -40 C to + 85 C, VDD = 0 V) Parameter Input capacitance Output capacitance I/O capacitance Symbol CIN COUT CIO Conditions f = 1 MHz; unmeasured pins are connected to VSS Min - Typ - Max 10 Unit pF
19-4
KS88C6216/C6224/C6232/P6232
ELECTRICAL DATA
Table 19-5. A/D Converter Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 4.0 V to 5.5 V, VSS = 0 V) Parameter Resolution Total accuracy Integral linearity error Differential linearity error Offset error of top Offset error of bottom Conversion time (1) ILE DLE EOT EOB tCON VIAN RAN AVREF AVSS (4) IADIN IADC 8 bit conversion 34 x n/fOSC (3), n=1,4,8,16 - - - - AVREF = VDD = 5V AVREF = VDD = 5V AVREF = VDD = 3V
AVREF = VDD = 5V When power down mode
Symbol
Conditions VDD = 5 V Conversion time = 5 s AVREF = 5 V AVSS = 0 V
Min - -
Typ 8 - - - 1 0.5
Max - 2 1 1 2 2 170 AVREF - VDD VSS 10 3 1.5 500
Unit bit LSB
17 AVSS 2 2.5 VSS - -
- - 1000 - - - 1 0.5 100
s V m V V A mA mA nA
Analog input voltage Analog input impedance Analog reference voltage Analog ground Analog input current Analog block Current (2)
NOTES: 1. "Conversion time" is the time required from the moment a conversion operation starts until it ends. 2. IADC is an operating current during the A/D conversion. 3. fOSC is the main oscillator clock. 4. VSS port shaves with the AVSS for KS88C6216/C6224/C6232.
19-5
ELECTRICAL DATA
KS88C6216/C6224/C6232/P6232
Table 19-6. A.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 4.0 V to 5.5V) Parameter Noise Filter Symbol tNF1H tNF1L tNF2 Conditions INT0-2, TM0CAP and TM1CK (RC delay)
RESET only (RC delay)
Min 300 800
Typ - -
Max - -
Unit ns
t NF1L t NF2
t NF1H
0.8 V DD 0.2 V DD
Figure 19-2. Input Timing Measurement Points for P0.0-P0.2, TM0CAP, and TM1CK
19-6
KS88C6216/C6224/C6232/P6232
ELECTRICAL DATA
Table 19-7. Oscillation Characteristics (TA = - 40 C + 85 C) Oscillator Main crystal or ceramic Clock Circuit
C1
Conditions VDD = 4.0 V to 5.5 V
Min 8
Typ -
Max 12
Unit MHz
XIN XOUT
C2
External clock (main)
XIN XOUT
VDD = 4.0 V to 5.5 V
8
-
12
MHz
NOTE: The maximum oscillator frequency is 12 MHz. If you use an oscillator frequency higher than 12 MHz, you cannot select a non-divided CPU clock using CLKCON settings. That is, you must select one of the divide-by values.
Table 19-8. Oscillation Stabilization Time (TA = - 40 C + 85 C, VDD = 4.0 V to 5.5 V) Oscillator Crystal Ceramic External clock Test Condition VDD = 4.0 V to 5.5 V VDD = 4.0 V to 5.5V XIN input high and low level width (tXH, tXL) Min - - 25 Typ - - - Max 20 10 500 ns Unit ms
NOTE: Oscillation stabilization time is the time required for the CPU clock to return to its normal oscillation frequency after a power-on occurs, or when Stop mode is released.
1 / fX t XL t XH
XIN
VDD - 0.5 V 0.4 V
Figure 19-3. Clock Timing Measurement Points for XIN
19-7
ELECTRICAL DATA
KS88C6216/C6224/C6232/P6232
Vout
VDD A : 0.2 V DD B : 0.4 V DD C : 0.6 V DD D : 0.8 V DD VSS
Vin A B C D
Figure 19-4. Schmitt Trigger Characteristics (Normal Port; except TTL Input)
19-8
KS88C6216/C6224/C6232/P6232
MECHANICAL DATA
20
OVERVIEW
42 14.00 0.2
MECHANICAL DATA
The KS88C6216/C6224/C6232 microcontroller is available in a 42-pin SDIP package (Samsung part number 42SDIP-600) and a 44-QFP package (Samsung part number 44-QFP-1010B).
22
0 ~ 15
42-SDIP-600
#1
21
0.25 +0.1 - 0.0 5
3.50 0.2
39.10 0.2 (1.77)
15.24 1.778 3.30 0.3 0.51MIN 5.08MAX
0.50 0.1
1.00 0.1
NOTE: Dimensions are in millimeters.
Figure 20-1. 42-Pin SDIP Package Mechanical Data (42-SDIP-600)
20-1
MECHANICAL DATA
KS88C6216/C6224/C6232/P6232
13.20 0.3 10.00 0.2
0~8
0.15
+0.10 - 0.05
13.20 0.3
10.00 0.2
44-QFP-1010B
0.10 MAX
#44 0.05 MIN 2.05 0.10 #1 0.80 0.35 - 0.05 (1.00)
+0.10
2.30 MAX
NOTE: Dimensions are in millimeters.
Figure 20-2. 44-Pin QFP Package Mechanical Data (44-QFP-1010B)
20-2
0.800.20
KS88C6216/C6224/C6232/P6232
KS88P6232 OTP
21
OVERVIEW
KS88P6232 OTP
The KS88P6232 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the KS88C6216/C6224/C6232 microcontrollers. It has an on-chip EPROM instead of masked ROM. The EPROM is accessed by serial data format. The KS88P6232 is fully compatible with the KS88C6216/C6224/C6232, both in function and in pin configuration. Because of its simple programming requirements, the KS88P6232 is ideal for use as an evaluation chip for the KS88C6216/C6224/C6232.
P0.0/INT0 P0.1/INT1 P0.2/INT2 P0.3 P0.4/TM0CAP P0.5/TM1CK P0.6 P0.7 SDAT/P1.0/SDA1 SCLK /P1.1/SCL1 VDD VSS1 XOUT XIN VPP/TEST SDA0 SCL0 RESET/RESET P1.2 P2.0/PWM0 P2.1/PWM1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
KS88P6232 42-SDIP (Top View)
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
P3.7 P3.6 P3.5 P3.4 P3.3/AD3 P3.2/AD2 P3.1/AD1 P3.0/AD0 AVREF VSS2 P2.7/Csync-I Hsync-I Vsync-I Vsync-O Hsync-O Clamp-O P2.6/PWM6 P2.5/PWM5 P2.4/PWM4 P2.3/PWM3 P2.2/PWM2
NOTE:
The bolds indicate an OTP pin name.
Figure 21-1. KS88P6232 Pin Assignments (42-SDIP Package)
21-1
KS88P6232 OTP
KS88C6216/C6224/C6232/P6232
44 43 42 41 40 39 38 37 36 35 34
P0.4/TM0CAP P0.3 P0.2/INT2 P0.1/INT1 NC P0.0/INT0 P3.7 P3.6 P3.5 P3.4 P3.3/AD3
P0.5/TM1CK P0.6 P0.7 SDAT/P1.0/SDA1 SCLK/P1.1/SCL1 VDD VSS1 XOUT XIN VPP/TEST SDA0
1 2 3 4 5 6 7 8 9 10 11
KS88C6216/C6224 /C6232/P6232 (44-QFP) Top View
33 32 31 30 29 28 27 26 25 24 23
P3.2/AD2 P3.1/AD1 P3.0/AD0 AVREF VSS2 P2.7/Csync-I Hsync-I Vsync-I Vsync-O Hsync-O Clamp-O
NOTE:
The bolds indicate an OTP pin name.
Figure 21-2. KS88P6232 Pin Assignments (44-QFP Package)
21-2
RESET /RESET
P1.2 P2.0/PWM0 P2.1/PWM1 P2.2/PWM2 NC P2.3/PWM3 P2.4/PWM4 P2.5/PWM5 P2.6/PWM6
SCL0
12 13 14 15 16 17 18 19 20 21 22
KS88C6216/C6224/C6232/P6232
KS88P6232 OTP
Table 21-1. Descriptions of Pins Used to Read/Write the EPROM Main Chip Pin Name P1.0 Pin Name SDAT Pin No. 9 (4) During Programming I/O I/O Function Serial data pin. Output port when reading and input port when writing. Can be assigned as a Input/push-pull output port. Serial clock pin. Input only pin. Power supply pin for EPROM cell writing (indicates that OTP enters into the writing mode). When 12.5 V is applied, OTP is in writing mode and when 5 V is applied, OTP is in reading mode. (Option) Chip Initialization Logic power supply pin. VDD should be tied to +5 V during programming.
P1.1 TEST
SCLK VPP (TEST)
10 (5) 15 (10)
I I
RESET
RESET
18 (13) 11/12 (6/7)
I I
VDD/VSS1
VDD/VSS1
NOTE: Parentheses indicate 44-QFP OTP pin number.
Table 21-2. Comparison of KS88P6232 and KS88C6216/C6224/C6232 Features Characteristic Program Memory Operating Voltage (VDD) OTP Programming Mode Pin Configuration EPROM Programmability 4.0 V to 5.5 V VDD = 5 V, VPP (TEST)=12.5V 42SDIP, 44QFP User Program 1 time 42SDIP, 44QFP Programmed at the factory KS88P6232 32-Kbyte EPROM KS88C6216/C6224/C6232 16/24/32-Kbyte mask ROM 4.0 V to 5.5V
OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the VPP(TEST) pin of the KS88P6232, the EPROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 16-3 below. Table 21-3. Operating Mode Selection Criteria VDD 5V VPP (TEST) 5V 12.5 V 12.5 V 12.5 V REG/ MEM 0 0 0 1 ADDRESS (A15-A0) 0000H 0000H 0000H 0E3FH R/W 1 0 1 0 EPROM read EPROM program EPROM verify EPROM read protection MODE
NOTE: "0" means Low level; "1" means High level.
21-3
KS88P6232 OTP
KS88C6216/C6224/C6232/P6232
D.C. ELECTRICAL CHARACTERISTICS
Table 21-4. D.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 4.0 V to 5.5 V) Parameter Input High leakage current Symbol ILIH1 ILIH2 ILIH3 Input Low leakage current ILIL1 ILIL2 ILIL3 Output High leakage current Output Low leakage current Pull-up resistor ILOH1 ILOL1 RL1 RL2 Supply current
(note)
Conditions VIN = VDD All input pins except XIN, XOUT VIN = VDD; XOUT only VIN = VDD; XIN only VIN = 0 V; All input pins except XIN, XOUT, and RESET VIN = 0 V; XOUT only VIN = 0 V; XIN only VOUT = VDD VOUT = 0 V VIN = 0 V Ports 3.7-3.4 VIN = 0 V
RESET only
Min - - 2.5 - - - 2.5 - - 20 150 -
Typ - - 6 - - -6 - - 47 280 15 5 1
Max 3 20 20 -3 - 20 - 20 3 -3 80 480 30 10 10
Unit A
A
A A k
IDD1 IDD2 IDD3
Operation mode; 12 MHz crystal C1 = C2 = 22pF Idle mode; 12 MHz crystal C1 = C2 = 22pF Stop mode
mA
A
NOTE: Supply current does not include drawn internal pull-up resistors and external loads of output.
21-4

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