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DATA SHEET
MOS INTEGRATED CIRCUIT
PD70320
V25TM 16/8-BIT SINGLE-CHIP MICROCONTROLLER
The PD70320 (V25) is a single-chip microcontroller on which 16-bit CPU, RAM, serial interface, timer, DMA controller, interrupt controller, etc. are all integrated. The PD70320 is compatible with the 8/16-bit microprocessor
PD70108/ 70116 (V20TM/V30TM) on the software level.
The details of the functions are described in the following User's Manuals. Be sure to read it before starting design. * V25, V35TM User's Manual -- Hardware : IEM-1220 * V25, V35 Family User's Manual -- Instructions : U12120J (Japanese version)
FEATURES
* * * * * * * *
Internal 16-bit architecture and external 8-bit data bus Compatible with PD70108/ 70116 (in native mode) on software level (some instructions added) Minimum instruction cycle : 400 ns/5 MHz (PD70320) 250 ns/8 MHz (PD70320-8) On-chip RAM : 256 words x 8 bits Input port (port T) with comparator : 8 bits I/O lines (input port : 4 bits, input/output port : 20 bits) Serial interface (internal dedicated baud rate generator) : 2 channels Asynchronous mode and I/O interface mode Interrupt controller * Programmable priority (8 levels) * Vectored interrupt function * Register bank switching function * Macro service function
* * * * * * *
DRAM and pseudo SRAM refreshing functions DMA controller : 2 channels 16-bit timer : 2 channels Time base counter On-chip clock generator Programmable wait function Standby function (STOP/HALT)
The information in this document is subject to change without notice. Document No. U10090EJ8V0DS00 (8th edition) Date Published November 1997 N Printed in Japan The mark shows major revised points.
(c)
1996 1995
PD70320
ORDERING INFORMATION
Part Number Package 84-pin plastic QFJ (1150 x 1150 mils) 84-pin plastic QFJ (1150 x 1150 mils) 94-pin plastic QFP (20 x 20 mm) 94-pin plastic QFP (20 x 20 mm) Max. Operating Frequency (MHz) 5 8 5 8
PD70320L PD70320L-8 PD70320GJ-5BG PD70320GJ-8-5BG
Remark The plastic QFJ is a new name of the PLCC.
2
PD70320
PIN CONFIGURATION (Top View)
84-Pin Plastic QFJ (1150 x 1150 mils)
PD70320L PD70320L-8
REFRQ
RESET
IOSTB
MREQ
MSTB
GND
R/W
P06
P05
P04
P03
P02
P01
P00
VDD
VTH
EA
X2
X1
IC
11 10 9 P07/CLKOUT D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
8
7
6
5
4
3
2
1 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 PT7 PT6 PT5 PT4 PT3 PT2 PT1 PT0 P17/READY P16/SCK0 P15/TOUT P14/INT/POLL P13/INTP2/INTAK P12/INTP1 P11/INTP0 P10/NMI P27/HLDRQ P26/HLDAK P25/TC1 P24/DMAAK1 P23/DMARQ1
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
P21/DMAAK0
P22/TC0
A12
A13
A14
A15
A16
A17
A18
A19
RxD0
GND
CTS0
TxD0
RxD1
CTS1
TxD1
P20/DMARQ0
IC
IC: Internally Connected
Cautions 1. Connect IC pin individually to VDD via a resistor (3 to 10 k). 2 Connect EA pin to GND via a resistor (3 to 10 k).
VDD
IC
IC
3
PD70320
94-Pin Plastic QFP (20 x 20 mm)
PD70320GJ-5BG PD70320GJ-8-5BG
P07/CLKOUT
A11
A10
94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 A12 NC A13 A14 A15 A16 A17 A18 A19 RxD0 GND CTS0 TxD0 RxD1 CTS1 TxD1 P20/DMARQ0 IC VDD VDD P21/DMAAK0 NC P22/TC0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 P05 NC IC P04 P03 P02 P01 P00 EA MREQ IOSTB MSTB R/W REFRQ RESET VDD VDD X2 X1 GND GND NC NC VTH
P25/TC1
P15/TOUT
PT0
PT1
PT2
PT3
PT4
PT5
PT6
P23/DMARQ1
P24/DMAAK1
P26/HLDAK
P10/NMI
P11/INTP0
P12/INTP1
P13/INTP2/INTAK
P14/INT/POLL
P16/SCK0
P17/READY
PT7
IC
NC
P27/HLDRQ
IC: Internally Connected NC: Non-Connection
Cautions 1. Connect IC pin individually to VDD via a resistor (3 to 10 k). 2. Connect EA pin to GND via a resistor (3 to 10 k).
4
IC
P06
NC
D7
D6
D5
D4
D3
D2
D1
D0
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
INTERNAL BLOCK DIAGRAM
STAGING LATCH STAGING LATCH
ADM
A0 to A19
P20/DMARQ0 P21/DMAAK0 P22/TC0 P23/DMARQ1 P24/DMAAK1 P25/TC1
PROGRAMMABLE DMA CONTROLLER
LC etc. PSW
ALU
PFP
INC
RESET HLDAK/P26
PC TxD0 RxD0 P16/SCK0 CTS0 TxD1 RxD1 CTS1 SERIAL INTERFACE BAUD RATE GENERATOR
TA TB TC
Note
HLDRQ/P27
BUS CONTROL LOGIC
READY/P17 MREQ MSTB R/W IOSTB POLL/INT/P14
INTERNAL RAM 256 byte * GR * MACRO SERVICE CHANNEL
INTERNAL ROM 8 Kbyte (reserved)
P10/NMI P11/INTP0 P12/INTP1 P13/INTP2/INTAK P14/INT/POLL
PROGRAMMABLE INTERRUPT CONTROLLER
INSTRUCTION DECODER MICRO SEQUENSER MICRO ROM
QUEUE (6 byte) EA D0 to D7
16-BIT TIMER
TIME BASE COUNTER
PORT
PORT with COMPARATOR
X1 CG X2 VDD
PD70320
TOUT/P15
REFRQ CLKOUT/PO7
P0
P1
P2
PT0 to 7
VTH
GND
Note Not user-accessible.
5
PD70320
CONTENTS
1. PIN FUNCTIONS .................................................................................................................................. 7
1.1 1.2 Port Pins ....................................................................................................................................................... 7 Non-port Pins ............................................................................................................................................... 8
2. INSTRUCTION SETS ........................................................................................................................... 9
2.1 2.2 2.3 Instructions Added to PD70108/70116 .................................................................................................... 9 Instruction Set Operation ......................................................................................................................... 11 Instruction Set Table ................................................................................................................................. 15
3. ELECTRICAL SPECIFICATIONS ...................................................................................................... 47 4. CHARACTERISTIC CURVES ............................................................................................................66 5. PACKAGE DRAWINGS ..................................................................................................................... 69 6. RECOMMENDED SOLDERING CONDITIONS ................................................................................ 71
6
PD70320
1.
1.1
PIN FUNCTIONS
Port Pins
Pin Name Input/Output Input & output Input & output/output Input Port Function 8-bit input/output ports, each to be specified bit-by-bit Used as non-maskable interrupt request input (input port) Used as both external interrupt request input and input port Input/input/output Input & output/input/input Input & output/output Used as both specifiable input/ output port and POLL input Input/output port specifiable bit-by-bit INT acknowledge signal output External interrupt request input Timer output Serial clock output READY input 8-bit input/output port specifiable DMA request input (CH0) bit-by-bit DMA acknowledge output (CH0) DMA end output (CH0) Input & output/input Input & output/output DMA request input (CH1) DMA acknowledge output (CH1) DMA end output (CH1) Input & output/output Input & output/input Input 8-bit input port with comparator HOLD acknowledge output HOLD input -- Control Function -- System clock output --
P00 to P06 P07/CLKOUT P10/NMI P11/INTP0 P12/INTP1 P13/INTP2/INTAK P14/POLL/INT P15/TOUT P16/SCK0 P17/READY P20/DMARQ0 P21/DMAAK0 P22/TC0 P23/DMARQ1 P24/DMAAK1 P25/TC1 P26/HLDAK P27/HLDRQ PT0 to PT7
Input & output/input Input & output/input Input & output/output
Remark All port pins become input ports after reset is released. When using P13/INTP2/INTAK as a INTAK pin, be sure to pull up the pin to avoid a malfunction of external interrupt controller after reset is released.
7
PD70320
1.2 Non-port Pins
Input/Output Output Serial data output Function
Pin Name TxD0 TxD1 RxD0 RxD1 CTS0 CTS1 REFRQ VTH RESET EA X1 X2 D0 to D7 A0 to A19 MREQ MSTB R/ W IOSTB VDD GND IC
Input
Serial data input
Input & output Input Output Input
CTS input in asynchronous mode, receive clock input/output in I/O interface mode CTS input DRAM refresh pulse output Comparator reference voltage input Reset signal input External memory access (connect to GND via a resistor (3 to 10 k))
Input
Used to connect crystal resonator/ceramic resonator for oscillating system clock. External clock is entered by entering reverse phase clock to both X1 and X2 pins. 8-bit data bus 20-bit address output Output used to indicate that memory bus cycle has been started Memory read/memory write strobe output Read cycle/write cycle ID signal output I/O read/I/O write strobe output Positive power supply pins (all pins should be connected) GND pins (all pins should be connected) Internally connected (connect individually to VDD via a resistor (3 to 10 k))
Input & output Output
8
PD70320
2. INSTRUCTION SETS
The PD70320 instruction sets are upward-compatible with those of PD70108/70116 in native mode. 2.1 Instructions Added to PD70108/70116
The following instructions are newly added to the PD70108/70116. (1) Conditional branch instruction * BTCLR ******* Bit test instruction used for special function registers If, when this BTCLR is executed, the target special function register bit status is "1", the bit is reset (0) and the program is branched to short-label described in the operand. If the target bit status is "0", the program is moved to the next instruction. PSW is not changed in this instruction. (Descriptive format)
Mnemonic Special Function Register Address sfr Operand Special Function Register Bit imm3 Branch Address short-label
BTCLR
(2) Interrupt instructions * RETRBI ****** Return instruction used for register banks This instruction is used to return the program from the interrupt service routine in which the register bank switching function is used. It cannot be used for returning from vectored interrupt servicing. (Descriptive format)
Mnemonic RETRBI Operand None
* FINT *********** This instruction is used to report the interrupt controller that interrupt servicing has ended. If an interrupt other than NMI, INT, and software interrupt is used, this instruction must be executed prior to the instruction for returning from interrupt servicing. It should not be used for NMI, INT and software interrupts. (Descriptive format)
Mnemonic FINT
Operand None
(3) CPU instruction * STOP ********* Instruction for transition to STOP state (Descriptive format)
Mnemonic STOP
Operand None
9
PD70320
(4) Register bank switch instructions * BRKCS ****** Used to switch register banks A register bank is switched to the register bank indicated by the lower 3 bits in the 16-bit register described in the operand. The program is also branched with this instruction to the address obtained from the PS stored in advance in the new register bank and the vector PC. The RETRBI instruction is used to return the program from the new register bank. (Descriptive format)
Mnemonic BRKCS
Operand reg16
* TSKSW ****** Used to switch register banks Just like the BRKCS instruction, this instruction is also executed to select a register bank. The program is branched to the address obtained from the PS stored in advance in the new register bank and the address obtained from the PC save area. (Descriptive format)
Mnemonic TSKSW
Operand reg16
(5) Data transfer instructions * MOVSPA *** Used to transfer SS and SP values This instruction is executed to transfer both SS and SP values before the register bank is switched to SS and SP of the current (post-switching) register bank. (Descriptive format)
Mnemonic MOVSPA
Operand None
* MOVSPB *** Used to transfer SS and SP values This instruction is executed to transfer the SS and SP values of the current (pre-switching) register bank to the SS and SP of the new register bank indicated by the lower 3 bits in the 16bit register described in the operand. (Descriptive format)
Mnemonic MOVSPB
Operand reg16
Some PD70108/ 70116 instructions should be much cared as shown below when used for the PD70320. * I/O instruction, primitive I/O instruction If PSW IBRK flag is reset (0), an interrupt is generated without executing this instruction. Be sure to set (1) the IBRK flag when using the I/O instruction. * FPO instruction An interrupt is generated without executing this instruction.
10
PD70320
2.2 Instruction Set Operation Table 2-1. Operand Identifier
Identifier reg reg8 reg16 dmem mem mem8 mem16 mem32 sfr imm imm3 imm4 imm8 imm16 acc sreg src-table src-block dst-block near-proc far-proc near-label short-label far-label memptr16 memptr32 regptr16 pop-value fp-op R 8-/16-bit general register 8-bit general register 16-bit general register 8-/16-bit memory location 8-/16-bit memory location 8-bit memory location 16-bit memory location 32-bit memory location 8-bit special function register location Constant within 0 to FFFFH Constant within 0 to 7 Constant within 0 to FH Constant within 0 to FFH Constant within 0 to FFFFH Register AW or AL Segment register 256-byte conversion table name Register IX-addressed block name Register IY-addressed block name Procedure in the current program segment Procedure in another program segment Label in the current program segment Label within end of instruction to -128 to +127 bytes Label in another program segment Word including location offset in the current program segment to which control is to be passed Double-word including location offset in another program segment to which control is to be passed and segment base address 16-bit general register including location offset in another program segment to which control is to be passed Number of bytes to be abandoned from stack (0 to 64K, normally even number) Immediate value to judge instruction code of external floating point operation chip Register set Description
11
PD70320
Table 2-2. Operation Code Identifier
Identifier W reg mem mod s X, XXX, YYY, ZZZ Description Byte/word specification bit (0: byte, 1: word). However, when s = 1, the sign extended byte data should be 16-bit operand even when W is 1. Register field (000 to 111) Memory field (000 to 111) Mode field (00 to 10) Sign extension specification bit (0: Sign is not extended, 1: Sign is extended) Data used to judge instruction code of external floating-point operation chip
Table 2-3. Operation Identifier (1/2)
Identifier AW AH AL BW CW CL DW SP PC PSW IX IY PS DS1 DS0 SS AC CY P S Z DIR IE V BRK MD (***) disp ext-disp8 Accumulator (16 bits) Accumulator (upper byte) Accumulator (lower byte) Register BW (16 bits) Register CW (16 bits) Register CW (lower byte) Register DW (16 bits) Stack pointer (16 bits) Program counter (16 bits) Program status word (16 bits) Index register (source) (16 bits) Index register (destination) (16 bits) Program segment register (16 bits) Data segment 1 register (16 bits) Data segment 0 register (16 bits) Stack segment register (16 bits) Auxiliary carry flag Carry flag Parity flag Sign flag Zero flag Direction flag Interrupt enable flag Overflow flag Break flag Mode flag Contents in memory shown in ( ) Displacement (8/16 bits) 16 bits obtained by extending sign of 8-bit displacement Description
12
PD70320
Table 2-3. Operation Identifier (2/2)
Identifier temp tmpcy seg offset + - x / % Temporary register (8/16/32 bits) Temporary carry flag (1 bit) Immediate segment data (16 bits) Immediate offset data (16 bits) Transfer direction Addition Subtraction Multiplication Division Modulo AND OR Exclusive OR 2-digit hexadecimal number 4-digit hexadecimal number Description

xxH xxxxH
Table 2-4. Flag Operation Identifier
Identifier (Blank) 0 1 x U R No change Cleared to 0 Set to 1 Set or cleared according to the result Not defined The previously saved value is restored. Description
Table 2-5. 8/16-Bit General Register Selection
reg 000 001 010 011 100 101 110 111 W=0 AL CL DL BL AH CH DH BH W=1 AW CW DW BW SP BP IX IY
13
PD70320
Table 2-6. Segment Register Selection
sreg 00 01 10 11 DS1 PS SS DS0
The number of clocks, for memory operand, differs among addressing modes. So, use the following values for "EA" items shown in Table 2-8 Number of Clocks. Table 2-7. Number of Clocks for Each Memory Addressing
mod mem 000 001 010 011 100 101 110 111 BW + IX BW + IY BP + IX BP + IY IX IY Direct address BW 00 Clocks 3 3 3 3 3 3 3 3 01 BW + IX + disp8 BW + IY + disp8 BP + IX + disp8 BP + IY + disp8 IX + disp8 IY + disp8 BP + disp8 BW + disp8 Clocks 3 3 3 3 3 3 3 3 10 BW + IX + disp16 BW + IY + disp16 BP + IX + disp16 BP + IY + disp16 IX + disp16 IY + disp16 BP + disp16 BW + disp16 Clocks 4 4 4 4 4 4 4 4
"T" indicates the number of wait states. Use any number of waits starting at "0" (no wait). The instruction fetch cycle is not counted as the number of clocks. There are some branch instructions for which such description as the example below is provided. The description indicates as follows: Example 15/8 *** 15: the number of clock cycles when branched 8: the number of clock cycles when not branched
14
2.3
Operation Code Group Mnemonic Operand 76543210 Data transfer MOV reg,reg mem,reg reg,mem mem,imm reg,imm acc,dmem dmem,acc sreg,reg16 sreg,mem16 reg16,sreg mem16,sreg DS0,reg16, mem32 DS1,reg16, mem32 AH,PSW PSW,AH LDEA TRANS XCH reg16,mem16 src-table reg,reg mem,reg reg,mem AW,reg16 reg16,AW MOVSPA Note MOVSPB Note reg16 1000101W 1000100W 1000101W 1100011W 1 0 1 1 W reg 1010000W 1010001W 10001110 10001110 10001100 10001100 11000101 11000100 10011111 10011110 10001101 11010111 1000011W 1000011W 1 0 0 1 0 reg 00001111 00001111 1 1 1 1 1 reg 00100101 10010101 1 1 reg reg mod reg mem mod reg mem 1 1 0 sreg reg mod 0 sreg mem 1 1 0 sreg reg mod 0 sreg mem mod reg mem mod reg mem 76543210 1 1 reg reg mod reg mem mod reg mem mod 0 0 0 mem 2 2 to 4 2 to 4 3 to 6 2 to 3 3 3 2 2 to 4 2 2 to 4 2 to 4 2 to 4 1 1 2 to 4 1 2 2 to 4 1 2 3 reg reg (mem) reg reg (mem) (mem) imm reg imm When W = 0, AL (dmem) When W = 1, AH (dmem + 1), AL (dmem) When W = 0, (dmem) AL When W = 1, (dmem + 1) AH, (dmem) AL sreg reg16 sreg (mem16) reg16 sreg (mem16) sreg reg16 (mem32) DS0 (mem32 + 2) reg16 (mem32) DS1 (mem32 + 2) AH S, Z, F1, AC, F0, P, IBRK, CY S, Z, F1, AC, F0, P, IBRK, CY AH reg16 mem16 AL (BW + AL) reg reg (mem) reg AW reg16 x x sreg : SS, DS0, DS1 sreg : SS, DS0, DS1 Bytes Operation
Flags AC CY V P S Z
Instruction Set Table
x
x
x
PD70320
New register bank SS and SP old register bank SS and SP SS and SP of reg16-indicated new register bank old register bank SS and SP
Note These instructions are newly added to the PD70108/70116.
15
16
Group Mnemonic Operand Repeat prefix REPC REPNC REP REPE REPZ REPNE REPNZ Primitive block transfer MOVBK dst-block, src-block CMPBK src-block, dst-block CMPM dst-block LDM src-block STM dst-block
Operation Code Bytes 76543210 01100101 76543210 1 Executes the primitive block transfer instruction in the continued byte while CW 0, and decrements CW by one. If any interruption is held at this time, it is processed. The program exits the loop when CY 1. Same as above. The program exits the loop when CY 0. Executes the primitive block transfer instruction in the continued byte while CW 0, and decrements CW by one. If any interruption is held at this time, it is processed. The program exits the loop when the primitive block transfer instruction is CMPBK or CMPM, and when Z 1. Same as above. The program exits the loop when Z 0. When W = 0, (IY) (IX) DIR = 0: IX IX + 1, IY IY + 1 DIR = 1: IX IX - 1, IY IY - 1 When W = 1, (IY + 1, IY) (IX + 1, IX) DIR = 0: IX IX + 2, IY IY + 2 DIR = 1: IX IX - 2, IY IY - 2 When W = 0, (IX) - (IY) DIR = 0: IX IX + 1, IY IY + 1 DIR = 1: IX IX - 1, IY IY - 1 When W = 1, (IX + 1, IX) - (IY + 1, IY) DIR = 0: IX IX + 2, IY IY + 2 DIR = 1: IX IX - 2, IY IY - 2 When W = 0, AL - (IY) DIR = 0: IY IY + 1; DIR = 1: IY IY - 1 When W = 1, AW - (IY + 1, IY) DIR = 0: IY IY + 2; DIR = 1: IY IY - 2 When W = 0, AL (IX) DIR = 0: IX IX + 1; DIR = 1: IX IX - 1 When W = 1, AW (IX + 1, IX) DIR = 0: IX + 2; DIR = 1: IX IX - 2 When W = 0, (IY) AL DIR = 0: IY IY + 1; DIR = 1: IY IY - 1 When W = 1, (IY + 1, IY) AW DIR = 0: IY IY + 2; DIR = 1: IY IY - 2 Operation
Flags AC CY V P S Z
01100100 11110011
1 1
11110010
1
1010010W
1
1010011W
1
x
x
x
x
x
x
1010111W
1
x
x
x
x
x
x
1010110W
1
1010101W
1
PD70320
Operation Code Group Mnemonic Operand 76543210 Bit field operation INS reg8,reg8 00001111 11 reg8,imm4 reg reg 00111001 4 16-bit field AW 76543210 00110001 3 16-bit field AW Bytes Operation
Flags AC CY V P S Z
00001111 11000 reg
EXT
reg8,reg8
00001111 11 reg reg
00110011
3
AW 16-bit field
reg8,imm4
00001111 11000 reg
00111011
4
AW 16-bit field
I/O
IN
Note
acc,imm8 acc,DW
1110010W 1110110W 1110011W 1110111W 0110110W
2 1 2 1 1
OUT
Note
imm8,acc DW,acc
Primitive I/O
INM
Note
dst-block,DW
OUTM
Note
DW,src-block
0110111W
1
When W = 0, AL (imm8) When W = 1, AH (imm8 + 1), AL (imm8) When W = 0, AL (DW) When W = 1, AH (DW + 1), AL (DW) When W = 0, (imm8) AL When W = 1, (imm8 + 1) AH, (imm8) AL When W = 0, (DW) AL When W = 1, (DW + 1) AH, (DW) AL When W = 0, (IY) (DW) DIR = 0: IY IY + 1; DIR = 1: IY IY - 1 When W = 1, (IY + 1, IY) (DW + 1, DW) DIR = 0: IY IY + 2; DIR = 1: IY IY - 2 When W = 0, (DW) (IX) DIR = 0: IX IX + 1; DIR = 1: IX IX - 1 When W = 1, (DW + 1, DW) (IX + 1, IX) DIR = 0: IX IX + 2; DIR = 1: IX IX - 2
Note When IBRK = 0, a software interrupt is generated automatically and the instruction is not executed.
PD70320
17
18
Group Mnemonic Operand Addition/ subtraction ADD reg,reg mem,reg reg,mem reg,imm mem,imm acc,imm ADDC reg,reg mem,reg reg,mem reg,imm mem,imm acc,imm SUB reg,reg mem,reg reg,mem reg,imm mem,imm acc,imm SUBC reg,reg mem,reg reg,mem reg,imm mem,imm acc,imm
Operation Code Bytes 76543210 0000001W 0000000W 0000001W 100000sW 100000sW 0000010W 0001001W 0001000W 0001001W 100000sW 100000sW 0001010W 0010101W 0010100W 0010101W 100000sW 100000sW 0010110W 0001101W 0001100W 0001101W 100000sW 100000sW 0001110W 11 reg reg 1 1 reg reg mod reg mem mod reg mem 1 1 1 0 1 reg mod 1 0 1 mem 11 reg reg 76543210 1 1 reg reg 2 2 to 4 2 to 4 3 to 4 3 to 6 2 to 3 2 2 to 4 2 to 4 3 to 4 3 to 6 2 to 3 2 2 to 4 2 to 4 3 to 4 3 to 6 2 to 3 2 2 to 4 2 to 4 3 to 4 3 to 6 2 to 3 reg reg + reg (mem) (mem) + reg reg reg + (mem) reg reg + imm (mem) (mem) + imm When W = 0, AL AL + imm When W = 1, AW AW + imm reg reg + reg + CY (mem) (mem) + reg + CY reg reg + (mem) + CY reg reg + imm + CY (mem) (mem) + imm + CY When W = 0, AL AL + imm + CY When W = 1, AW AW + imm + CY reg reg - reg (mem) (mem) - reg reg reg - (mem) reg reg - imm (mem) (mem) - imm When W = 0, AL AL - imm When W = 1, AW AW - imm reg reg - reg - CY (mem) (mem) - reg - CY reg reg - (mem) - CY reg reg - imm - CY (mem) (mem) - imm - CY When W = 0, AL AL - imm - CY When W = 1, AW AW - imm - CY Operation
Flags AC CY V x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x P x x x x x x x x x x x x x x x x x x x x x x x x S x x x x x x x x x x x x x x x x x x x x x x x x Z x x x x x x x x x x x x x x x x x x x x x x x x
mod reg mem mod reg mem 11000 reg
mod 0 0 0 mem
mod reg mem mod reg mem 1 1 0 1 0 reg mod 0 1 0 mem
mod reg mem mod reg mem 1 1 0 1 1 reg mod 0 1 1 mem
PD70320
Operation Code Group Mnemonic Operand 76543210 BCD operation ADD4S SUB4S CMP4S ROL4 reg8 00001111 00001111 00001111 00001111 11000 mem8 reg 00101000 3 to 5 ALL mod 0 0 0 mem ROR4 reg8 00001111 1 1 0 0 0 reg mem8 00001111 mod 0 0 0 mem Increment/ decrement INC reg8 mem reg16 DEC reg8 mem reg16 11111110 1111111W 0 1 0 0 0 reg 11111110 1111111W 0 1 0 0 1 reg 11001 reg 11000 reg 2 2 to 4 1 2 2 to 4 1 reg8 reg8 + 1 (mem) (mem) + 1 reg16 reg16 + 1 reg8 reg8 - 1 (mem) (mem) - 1 reg16 reg16 - 1 00101010 3 to 5 ALL 00101010 3 ALL 76543210 00100000 00100010 00100110 00101000 2 2 2 3 ALL dst BCD string dst BCD string + src BCD string dst BCD string dst BCD string - src BCD string dst BCD string - src BCD string reg Upper Lower Byte Byte mem Upper Lower Byte Byte reg Upper Lower Byte Byte mem Upper Lower Byte Byte x x x x x x
Note
Flags Bytes Operation AC CY V U U U x x x U U U P U U U S U U U Z x x x
Note
Note
00001111
x x x x x x
x x x x x x
x x x x x x
x x x x x x
mod 0 0 0 mem
mod 0 0 1 mem
n: 1/2 of the number of BCD digits Note The number of BCD digits is given in the CL register. The value can be set within 1 to 254.
PD70320
19
20
Group Mnemonic Operand Multiplication MULU reg8 mem8 reg16 mem16 MUL reg8 mem8 reg16 mem16 reg16, (reg16,) Note imm8 reg16, mem16, imm8 reg16, (reg16,) Note imm16 reg16, mem16, imm16
Operation Code Bytes 76543210 11110110 76543210 1 1 1 0 0 reg 2 AW AL x reg8 AH = 0: CY 0, V 0 AH 0: CY 1, V 1 AW AL x (mem8) AH = 0: CY 0, V 0 AH 0: CY 1, V 1 DW, AW AW x reg16 DW = 0: CY 0, V 0 DW = 1: CY 1, V 1 DW, AW AW x (mem16) DW = 0: CY 0, V 0 DW = 1: CY 1, V 1 AW AL x reg8 Extension of AH = AL sign: CY 0, V 0 Extension of AH AL sign: CY 1, V 1 AW AL x (mem8) Extension of AH = AL sign: CY 0, V 0 Extension of AH AL sign: CY 1, V 1 DW, AW AW x reg16 Extension of DW = AW sign: CY 0, V 0 Extension of DW AW sign: CY 1, V 1 DW, AW AW x (mem16) Extension of DW = AW sign: CY 0, V 0 Extension of DW AW sign: CY 1, V 1 reg16 reg16 x imm8 Product 16 bits: CY 0, V 0 Product > 16 bits: CY 1, V 1 reg16 (mem16) x imm8 Product 16 bits: CY 0, V 0 Product > 16 bits: CY 1, V 1 reg16 reg16 x imm16 Product 16 bits: CY 0, V 0 Product > 16 bits: CY 1, V 1 reg16 (mem16) x imm16 Product 16 bits: CY 0, V 0 Product > 16 bits: CY 1, V 1 Operation
Flags AC CY V x x P S Z
U
U
U
U
11110110
mod 1 0 0 mem
2 to 4
U
x
x
U
U
U
11110111
1 1 1 0 0 reg
2
U
x
x
U
U
U
11110111
mod 1 0 0 mem
2 to 4
U
x
x
U
U
U
11110110
1 1 1 0 1 reg
2
U
x
x
U
U
U
11110110
mod 1 0 1 mem
2 to 4
U
x
x
U
U
U
11110111
1 1 1 0 1 reg
2
U
x
x
U
U
U
11110111
mod 1 0 1 mem
2 to 4
U
x
x
U
U
U
01101011
1 1 reg
reg
3
U
x
x
U
U
U
01101011
mod reg mem
3 to 5
U
x
x
U
U
U
01101001
1 1 reg
reg
4
U
x
x
U
U
U
PD70320
01101001
mod reg mem
4 to 6
U
x
x
U
U
U
Note The 2nd operand is omissible. If omitted, the 1st operand is assumed.
Operation Code Group Mnemonic Operand 76543210 Unsigned division DIVU reg8 11110110 76543210 1 1 1 1 0 reg 2 temp AW When temp / reg8 FFH AH temp%reg8, AL temp / reg8 When temp / reg8 > FFH (SP - 1, SP - 2) PSW, (SP - 3, SP - 4) PS (SP - 5, SP - 6) PC, SP SP - 6 IE 0, BRK 0, PS (3, 2), PC (1, 0) temp AW When temp / (mem8) FFH AH temp%(mem8), AL temp / (mem8) When temp / (mem8) > FFH (SP - 1, SP - 2) PSW, (SP - 3, SP - 4) PS (SP - 5, SP - 6) PC, SP SP - 6 IE 0, BRK 0, PS (3, 2), PC (1, 0) temp DW, AW When temp / reg16 FFFFH DW temp%reg16, AW temp / reg16 When temp / reg16 > FFFFH (SP - 1, SP - 2) PSW, (SP - 3, SP - 4) PS (SP - 5, SP - 6) PC, SP SP - 6 IE 0, BRK 0, PS (3, 2), PC (1, 0) temp DW, AW When temp / (mem16) FFFFH DW temp%(mem16), AW temp / (mem16) When temp / (mem16) > FFFFH (SP - 1, SP - 2) PSW, (SP - 3, SP - 4) PS (SP - 5, SP - 6) PC, SP SP - 6 IE 0, BRK 0, PS (3, 2), PC (1, 0) Bytes Operation
Flags AC CY V U U U P U S U Z U
mem8
11110110
mod 1 1 0 mem
2 to 4
U
U
U
U
U
U
reg16
11110111
1 1 1 1 0 reg
2
U
U
U
U
U
U
mem16
11110111
mod 1 1 0 mem
2 to 4
U
U
U
U
U
U
PD70320
21
22
Group Mnemonic Operand Signed division DIV reg8 mem8 reg16 mem16
Operation Code Bytes 76543210 11110110 76543210 1 1 1 1 1 reg 2 temp AW When temp / reg8 > 0 and temp / reg8 7FH or temp / reg8 < 0 and temp / reg8 > 0 - 7FH - 1 AH temp%reg8, AL temp / reg8 When temp / reg8 > 0 and temp / reg8 > 7FH or temp / reg8 > 0 and temp / reg8 < 0 - 7FH - 1 (SP - 1, SP - 2) PSW, (SP - 3, SP - 4) PS (SP - 5, SP - 6) PC, SP SP - 6 IE 0, BRK 0, PS (3, 2), PC (1, 0) temp AW When temp / (mem8) > 0 and temp / (mem8) 7FH or temp / (mem8) < 0 and temp / (mem8) > 0 - 7FH - 1 AH temp%(mem8), AL temp / (mem8) When temp / (mem8) > 0 and temp / (mem8) > 7FH or temp / (mem8) > 0 and temp / (mem8) < 0 - 7FH - 1 (SP - 1, SP - 2) PSW, (SP - 3, SP - 4) PS (SP - 5, SP - 6) PC, SP SP - 6 IE 0, BRK 0, PS (3, 2), PC (1, 0) temp DW, AW When temp / reg16 > 0 and temp / reg16 7FFFH or temp / reg16 < 0 and temp / reg16 > 0 - 7FFFH - 1 DW temp%reg16, AW temp / reg16 When temp / reg16 > 0 and temp / reg16 > 7FFFH or temp / reg16 > 0 and temp / reg16 < 0 - 7FFFH - 1 (SP - 1, SP - 2) PSW, (SP - 3, SP - 4) PS (SP - 5, SP - 6) PC, SP SP - 6 IE 0, BRK 0, PS (3, 2), PC (1, 0) temp DW, AW When temp / (mem16) > 0 and temp / (mem16) 7FFFH or temp / (mem16) < 0 and temp / (mem16) > 0 - 7FFFH - 1 DW temp%(mem16), AW temp / (mem16) When temp / (mem16) > 0 and temp / (mem16) > 7FFFH or temp / (mem16) > 0 and temp / (mem16) < 0 - 7FFFH - 1 (SP - 1, SP - 2) PSW, (SP - 3, SP - 4) PS (SP - 5, SP - 6) PC, SP SP - 6 IE 0, BRK 0, PS (3, 2), PC (1, 0) Operation
Flags AC CY V U U U P U S U Z U
11110110
mod 1 1 1 mem
2 to 4
U
U
U
U
U
U
11110111
1 1 1 1 1 reg
2
U
U
U
U
U
U
11110111
mod 1 1 1 mem
2 to 4
U
U
U
U
U
U
PD70320
Operation Code Group Mnemonic Operand 76543210 BCD adjustment ADJBA ADJ4A 00110111 00100111 76543210 1 1 When AL 0FH > 9 or AC = 1, AL AL + 6 AH AH + 1, AC 1, CY AC, AL AL 0FH When AL 0FH > 9 or AC = 1, AL AL + 6, AC 1 When AL > 9FH or CY = 1, AL AL + 60H, CY 1 When AL 0FH > 9 or AC = 1, AL AL - 6, AH AH - 1, AC 1 CY AC, AL AL 0FH When AL 0FH > 9 or AC = 1, AL AL - 6, AC 1 When AL > 9FH or CY = 1, AL AL - 60H, CY 1 AH AL / 0AH, AL AL%0AH AL AH x 0AH + AL, AH 0 When AL < 80H, AH 0. In other cases, AH FFH. When AW < 8000H, DW 0. In other cases, DW FFFFH. reg - reg (mem) - reg reg - (mem) reg - imm (mem) - imm When W = 0, AL - imm When W = 1, AW - imm reg reg (mem) (mem) reg reg + 1 (mem) (mem) + 1 x x x x x x x x x x x x x x x x Bytes Operation
Flags AC CY V x x x x U U P U x S U x Z U x
ADJBS
00111111
1
x
x
U
U
U
U
ADJ4S
00101111
1
x
x
U
x
x
x
Data conversion
CVTBD CVTDB CVTBW CVTWL
11010100 11010101 10011000 10011001 reg,reg mem,reg reg,mem reg,imm mem,imm acc,imm 0011101W 0011100W 0011101W 100000sW 100000sW 0011110W 1111011W 1111011W 1111011W 1111011W
00001010 00001010
2 2 1 1
U U
U U
U U
x x
x x
x x
Compare
CMP
1 1 reg
reg
2 2 to 4 2 to 4 3 to 4 3 to 6 2 to 3
x x x x x x
x x x x x x
x x x x x x
x x x x x x
mod reg mem mod reg mem 1 1 1 1 1 reg mod 1 1 1 mem
Complement operation
NOT
reg mem
1 1 0 1 0 reg mod 0 1 0 mem 1 1 0 1 1 reg mod 0 1 1 mem
2 2 to 4 2 2 to 4
NEG
reg mem
x x
x x
x x
x
PD70320
x
23
24
Group Mnemonic Operand Logical operation TEST reg,reg mem,reg reg,mem reg,imm mem,imm acc,imm AND reg,reg mem,reg reg,mem reg,imm mem,imm acc,imm OR reg,reg mem,reg reg,mem reg,imm mem,imm acc,imm XOR reg,reg mem,reg reg,mem reg,imm mem,imm acc,imm
Operation Code Bytes 76543210 1000010W 1000010W 1111011W 1111011W 1010100W 0010001W 0010000W 0010001W 1000000W 1000000W 0010010W 0000101W 0000100W 0000101W 1000000W 1000000W 0000110W 0011001W 0011000W 0011001W 1000000W 1000000W 0011010W 1 1 reg reg 1 1 reg reg 1 1 reg reg 76543210 1 1 reg reg 2 2 to 4 3 to 4 3 to 6 2 to 3 2 2 to 4 2 to 4 3 to 4 3 to 6 2 to 3 2 2 to 4 2 to 4 3 to 4 3 to 6 2 to 3 2 2 to 4 2 to 4 3 to 4 3 to 6 2 to 3 reg reg (mem) reg reg imm (mem) imm When W = 0, AL imm8 When W = 1, AW imm16 reg reg reg (mem) (mem) reg reg reg (mem) reg reg imm (mem) (mem) imm When W = 0, AL AL imm8 When W = 1, AW AW imm16 reg reg reg (mem) (mem) reg reg reg (mem) reg reg imm (mem) (mem) imm When W = 0, AL AL imm8 When W = 1, AW AW imm16 reg reg reg (mem) (mem) reg reg reg (mem) reg reg imm (mem) (mem) imm When W = 0, AL AL imm8 When W = 1, AW AW imm16 Operation
Flags AC CY V U U U U U U U U U U U U U U U U U U U U U U U 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P x x x x x x x x x x x x x x x x x x x x x x x S x x x x x x x x x x x x x x x x x x x x x x x Z x x x x x x x x x x x x x x x x x x x x x x x
mod reg mem 1 1 0 0 0 reg mod 0 0 0 mem
mod reg mem mod reg mem 1 1 1 0 0 reg mod 1 0 0 mem
mod reg mem mod reg mem 1 1 0 0 1 reg mod 0 0 1 mem
mod reg mem mod reg mem 1 1 1 1 0 reg mod 1 1 0 mem
PD70320
Operation Code Group Bit manipulation Mnemonic Operand 76543210 TEST1 reg8,CL mem8,CL reg16,CL mem16,CL reg8,imm3 mem8,imm3 reg16,imm4 mem16,imm4 NOT1 reg8,CL mem8,CL reg16,CL mem16,CL reg8,imm3 mem8,imm3 reg16,imm4 mem16,imm4 00010000 0000 0001 0001 1000 1000 1001 1001 0110 0110 0111 0111 1110 1110 1111 1111 76543210 1 1 0 0 0 reg mod 0 0 0 mem 1 1 0 0 0 reg mod 0 0 0 mem 1 1 0 0 0 reg mod 0 0 0 mem 1 1 0 0 0 reg mod 0 0 0 mem 1 1 0 0 0 reg mod 0 0 0 mem 1 1 0 0 0 reg mod 0 0 0 mem 1 1 0 0 0 reg mod 0 0 0 mem 1 1 0 0 0 reg mod 0 0 0 mem 3 3 to 5 3 3 to 5 4 4 to 6 4 4 to 6 3 3 to 5 3 3 to 5 4 4 to 6 4 4 to 6 reg8 bit No. CL = 0: Z 1 reg8 bit No. CL = 1: Z 0 (mem8) bit No. CL = 0: Z 1 (mem8) bit No. CL = 1: Z 0 reg16 bit No. CL = 0: Z 1 reg16 bit No. CL = 1: Z 0 (mem16) bit No. CL = 0: Z 1 (mem16) bit No. CL = 1: Z 0 reg8 bit No. imm3 = 0: Z 1 reg8 bit No. imm3 = 1: Z 0 (mem8) bit No. imm3 = 0: Z 1 (mem8) bit No. imm3 = 1: Z 0 reg16 bit No. imm4 = 0: Z 1 reg16 bit No. imm4 = 1: Z 0 (mem16) bit No. imm4 = 0: Z 1 (mem16) bit No. imm4 = 1: Z 0 reg8 bit No. CL reg8 bit No. CL (mem8) bit No. CL (mem8) bit No. CL reg16 bit No. CL reg16 bit No. CL (mem16) bit No. CL (mem16) bit No. CL reg8 bit No. imm3 reg8 bit No. imm3 (mem8) bit No. imm3 (mem8) bit No. imm3 reg16 bit No. imm4 reg16 bit No. imm4 (mem16) bit No. imm4 (mem16) bit No. imm4 Bytes Operation
Flags AC CY V U U U U U U U U 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P U U U U U U U U S U U U U U U U U Z x x x x x x x x

2nd byte
Note
3rd byte
Note
Note 1st byte = 0FH
CY CY x
NOT1
CY
11110101
1
PD70320
25

26
Group Mnemonic Operand Bit manipulation CLR1 reg8,CL mem8,CL reg16,CL mem16,CL reg8,imm3 mem8,imm3 reg16,imm4 mem16,imm4 SET1 reg8,CL mem8,CL reg16,CL mem16,CL reg8,imm3 mem8,imm3 reg16,imm4 mem16,imm4 CLR1 CY DIR SET1 CY DIR
Operation Code Bytes 76543210 00010010 0010 0011 0011 1010 1010 1011 1011 0100 0100 0101 0101 1100 1100 1101 1101 76543210 1 1 0 0 0 reg mod 0 0 0 mem 1 1 0 0 0 reg mod 0 0 0 mem 1 1 0 0 0 reg mod 0 0 0 mem 1 1 0 0 0 reg mod 0 0 0 mem 1 1 0 0 0 reg mod 0 0 0 mem 1 1 0 0 0 reg mod 0 0 0 mem 1 1 0 0 0 reg mod 0 0 0 mem 1 1 0 0 0 reg mod 0 0 0 mem 3 3 to 5 3 3 to 5 4 4 to 6 4 4 to 6 3 3 to 5 3 3 to 5 4 4 to 6 4 4 to 6 reg8 bit No. CL 0 (mem8) bit No. CL 0 reg16 bit No. CL 0 (mem16) bit No. CL 0 reg8 bit No. imm3 0 (mem8) bit No. imm3 0 reg16 bit No. imm4 0 (mem16) bit No. imm4 0 reg8 bit No. CL 1 (mem8) bit No. CL 1 reg16 bit No. CL 1 (mem16) bit No. CL 1 reg8 bit No. imm3 1 (mem8) bit No. imm3 1 reg16 bit No. imm4 1 (mem16) bit No. imm4 1 Operation
Flags AC CY V P S Z
2nd byte Note
3rd byte Note
Note 1st byte = 0FH
CY 0 DIR 0 CY 1 DIR 1 1
11111000 11111100 11111001 11111101
1 1 1 1
0
PD70320
Operation Code Group Shift Mnemonic Operand 76543210 SHL reg,1 1101000W 76543210 1 1 1 0 0 reg 2 CY reg MSB, reg reg x 2 When reg MSB CY, V 1 When reg MSB = CY, V 0 CY (mem) MSB, (mem) (mem) x 2 When (mem) MSB CY, V 1 When (mem) MSB = CY, V 0 The following operations are repeated while temp CL and temp 0. CY reg MSB, reg reg x 2 temp temp - 1 The following operations are repeated while temp CL and temp 0. CY (mem) MSB, (mem) (mem) x 2 temp temp - 1 The following operations are repeated while temp imm8 and temp 0. CY reg MSB, reg reg x 2 temp temp - 1 The following operations are repeated while temp imm8 and temp 0. CY (mem) MSB, (mem) (mem) x 2 temp temp - 1 Bytes Operation
Flags AC CY V U x x P x S x Z x
mem,1
1101000W
mod 1 0 0 mem
2 to 4
U
x
x
x
x
x
reg,CL
1101001W
1 1 1 0 0 reg
2
U
x
U
x
x
x
mem,CL
1101001W
mod 1 0 0 mem
2 to 4
U
x
U
x
x
x
reg,imm8
1100000W
1 1 1 0 0 reg
3
U
x
U
x
x
x
mem,imm8
1100000W
mod 1 0 0 mem
3 to 5
U
x
U
x
x
x
PD70320
27
28
Group Shift Mnemonic Operand SHR reg,1 mem,1 reg,CL mem,CL reg,imm8 mem,imm8 SHRA reg,1 mem,1 reg,CL mem,CL reg,imm8 mem,imm8
Operation Code Bytes 76543210 1101000W 76543210 1 1 1 0 1 reg 2 CY reg LSB, reg reg / 2 reg MSB bit following reg MSB: V 1 reg MSB = bit following reg MSB: V 0 CY (mem) LSB, (mem) (mem) / 2 (mem) MSB bit following (mem) MSB: V 1 (mem) MSB = bit following (mem) MSB: V 0 The following operations are repeated while temp CL and temp 0. CY reg LSB, reg reg / 2 temp temp - 1 The following operations are repeated while temp CL and temp 0. CY (mem) LSB, (mem) (mem) / 2 temp temp - 1 The following operations are repeated while temp imm8 and temp 0. CY reg LSB, reg reg / 2 temp temp - 1 The following operations are repeated while temp imm8 and temp 0. CY (mem) LSB, (mem) (mem) / 2 temp temp - 1 CY reg LSB, reg reg / 2, V 0 The operand MSB remains the same status. CY (mem) LSB, (mem) (mem) / 2, V 0 The operand MSB remains the same status. The following operations are repeated while temp CL and temp 0. CY reg LSB, reg reg / 2 temp temp - 1 The operand MSB remains the same status. The following operations are repeated while temp CL and temp 0. CY (mem) LSB, (mem) (mem) / 2 temp temp - 1 The operand MSB remains the same status. The following operations are repeated while temp imm8 and temp 0. CY reg LSB, reg reg / 2 temp temp - 1 The operand MSB remains the same status. The following operations are repeated while temp imm8 and temp 0. CY (mem) LSB, (mem) (mem) / 2 temp temp - 1 The operand MSB remains the same status. Operation
Flags AC CY V U x x P x S x Z x
1101000W
mod 1 0 1 mem
2 to 4
U
x
x
x
x
x
1101001W
1 1 1 0 1 reg
2
U
x
U
x
x
x
1101001W
mod 1 0 1 mem
2 to 4
U
x
U
x
x
x
1100000W
1 1 1 0 1 reg
3
U
x
U
x
x
x
1100000W
mod 1 0 1 mem
3 to 5
U
x
U
x
x
x
1101000W 1101000W 1101001W
1 1 1 1 1 reg mod 1 1 1 mem 1 1 1 1 1 reg
2 2 to 4 2
U U U
x x x
0 0 U
x x x
x x x
x x x
1101001W
mod 1 1 1 mem
2 to 4
U
x
U
x
x
x
1100000W
1 1 1 1 1 reg
3
U
x
U
x
x
x
1100000W
mod 1 1 1 mem
3 to 5
U
x
U
x
x
x
PD70320
Operation Code Group Mnemonic Operand 76543210 Rotate ROL reg,1 1101000W 76543210 1 1 0 0 0 reg 2 CY reg MSB, reg reg x 2 + CY reg MSB CY: V 1 reg MSB = CY: V 0 CY (mem) MSB, (mem) (mem) x 2 + CY (mem) MSB CY: V 1 (mem) MSB = CY: V 0 The following operations are repeated while temp CL and temp 0. CY reg MSB, reg reg x 2 + CY temp temp - 1 The following operations are repeated while temp CL and temp 0. CY (mem) MSB, (mem) (mem) x 2 + CY temp temp - 1 The following operations are repeated while temp imm8 and temp 0. CY reg MSB, reg reg x 2 + CY temp temp - 1 The following operations are repeated while temp imm8 and temp 0. CY (mem) MSB, (mem) (mem) x 2 + CY temp temp - 1 CY reg LSB, reg reg / 2 reg MSB CY reg MSB bit following reg MSB: V 1 reg MSB = bit following reg MSB: V 0 CY (mem) LSB, (mem) (mem) / 2 (mem) MSB CY (mem) MSB bit following (mem) MSB: V 1 (mem) MSB = bit following (mem) MSB: V 0 The following operations are repeated while temp CL and temp 0. CY reg LSB, reg reg / 2 reg MSB CY temp temp - 1 The following operations are repeated while temp CL and temp 0. CY (mem) LSB, (mem) (mem) / 2 (mem) MSB CY temp temp - 1 The following operations are repeated while temp imm8 and temp 0. CY reg LSB, reg reg / 2 reg MSB CY temp temp - 1 The following operations are repeated while temp imm8 and temp 0. CY (mem) LSB, (mem) (mem) / 2 (mem) MSB CY temp temp - 1 Bytes Operation
Flags AC CY V x x P S Z
mem,1
1101000W
mod 0 0 0 mem
2 to 4
x
x
reg,CL
1101001W
1 1 0 0 0 reg
2
x
U
mem,CL
1101001W
mod 0 0 0 mem
2 to 4
x
U
reg,imm8
1100000W
1 1 0 0 0 reg
3
x
U
mem,imm8
1100000W
mod 0 0 0 mem
3 to 5
x
U
ROR
reg,1
1101000W
1 1 0 0 1 reg
2
x
x
mem,1
1101000W
mod 0 0 1 mem
2 to 4
x
x
reg,CL
1101001W
1 1 0 0 1 reg
2
x
U
mem,CL
1101001W
mod 0 0 1 mem
2 to 4
x
U
PD70320
reg,imm8
1100000W
1 1 0 0 1 reg
3
x
U
mem,imm8
1100000W
mod 0 0 1 mem
3 to 5
x
U
29
30
Group Rotate Mnemonic Operand ROLC reg,1 mem,1 reg,CL mem,CL reg,imm8 mem,imm8
Operation Code Bytes 76543210 1101000W 76543210 1 1 0 1 0 reg 2 tmpcy CY, CY reg MSB reg reg x 2 + tmpcy reg MSB CY: V 1 reg MSB = CY: V 0 tmpcy CY, CY (mem) MSB (mem) (mem) x 2 + tmpcy (mem) MSB CY: V 1 (mem) MSB = CY: V 0 The following operations are repeated while temp CL and temp 0. tmpcy CY, CY reg MSB reg reg x 2 + tmpcy temp temp - 1 The following operations are repeated while temp CL and temp 0. tmpcy CY, CY (mem) MSB (mem) (mem) x 2 + tmpcy temp temp - 1 The following operations are repeated while temp imm8 and temp 0. tmpcy CY, CY reg MSB reg reg x 2 + tmpcy temp temp - 1 The following operations are repeated while temp imm8 and temp 0. tmpcy CY, CY (mem) MSB (mem) (mem) x 2 + tmpcy temp temp - 1 Operation
Flags AC CY V x x P S Z
1101000W
mod 0 1 0 mem
2 to 4
x
x
1101001W
1 1 0 1 0 reg
2
x
U
1101001W
mod 0 1 0 mem
2 to 4
x
U
1100000W
1 1 0 1 0 reg
3
x
U
1100000W
mod 0 1 0 mem
3 to 5
x
U
PD70320
Operation Code Group Rotate Mnemonic Operand 76543210 RORC reg,1 1101000W 76543210 1 1 0 1 1 reg 2 tmpcy CY, CY reg LSB reg reg / 2 reg MSB tmpcy reg MSB bit following reg MSB: V 1 reg MSB = bit following reg MSB: V 0 tmpcy CY, CY (mem) LSB (mem) (mem) / 2 (mem) MSB tmpcy (mem) MSB bit following (mem) MSB: V 1 (mem) MSB = bit following (mem) MSB: V 0 The following operations are repeated while temp CL and temp 0. tmpcy CY, CY reg LSB reg reg / 2 reg MSB tmpcy temp temp - 1 The following operations are repeated while temp CL and temp 0. tmpcy CY, CY (mem) LSB (mem) (mem) / 2 (mem) MSB tmpcy temp temp - 1 The following operations are repeated while temp imm8 and temp 0. tmpcy CY, CY reg LSB reg reg / 2 reg MSB tmpcy temp temp - 1 The following operations are repeated while temp imm8 and temp 0. tmpcy CY, CY (mem) LSB (mem) (mem) / 2 (mem) MSB tmpcy temp temp - 1 Bytes Operation
Flags AC CY V x x P S Z
mem,1
1101000W
mod 0 1 1 mem
2 to 4
x
x
reg,CL
1101001W
1 1 0 1 1 reg
2
x
U
mem,CL
1101001W
mod 0 1 1 mem
2 to 4
x
U
reg,imm8
1100000W
1 1 0 1 1 reg
3
x
U
mem,imm8
1100000W
mod 0 1 1 mem
3 to 5
x
U
PD70320
31
32
Group Subroutine control Mnemonic Operand CALL near-proc regptr16 memptr16 far-proc memptr32 RET pop-value pop-value
Operation Code Bytes 76543210 11101000 11111111 11111111 10011010 1 1 0 1 0 reg mod 0 1 0 mem 76543210 3 2 2 to 4 5 (SP - 1, SP - 2) PC, SP SP - 2 PC PC + disp (SP - 1, SP - 2) PC, PC regptr16 SP SP - 2 (SP - 1, SP - 2) PC, SP SP - 2 PC (memptr16) (SP - 1, SP - 2) PS, (SP - 3, SP - 4) PC SP SP - 4 PS seg, PC offset (SP - 1, SP - 2) PS, (SP - 3, SP - 4) PC SP SP - 4 PS (memptr32 + 2), PC (memptr32) PC (SP + 1, SP) SP SP + 2 PC (SP + 1, SP) SP SP + 2, SP SP + pop-value PC (SP + 1, SP) PS (SP + 3, SP + 2) SP SP + 4 PC (SP + 1, SP) PS (SP + 3, SP + 2) SP SP + 4, SP SP + pop-value Operation
Flags AC CY V P S Z
11111111
mod 0 1 1 mem
2 to 4
11000011 11000010 11001011
1 3 1
11001010
3
PD70320
Operation Code Group Stack manipulation Mnemonic Operand 76543210 PUSH mem16 reg16 sreg PSW R imm8 imm16 POP mem16 reg16 sreg PSW R PREPARE DISPOSE Branch BR near-label short-label regptr16 memptr16 far-label memptr32 imm16,imm8 11111111 0 1 0 1 0 reg 0 0 0 sreg 1 1 0 10011100 01100000 01101010 01101000 10001111 01011 reg mod 0 0 0 mem 76543210 mod 1 1 0 mem 2 to 4 1 1 1 1 2 3 2 to 4 1 1 1 1 4 1 3 2 11100 reg 2 2 to 4 5 mod 1 0 1 mem 2 to 4 (SP - 1, SP - 2) (mem16) SP SP - 2 (SP - 1, SP - 2) reg16 SP SP - 2 (SP - 1, SP - 2) sreg SP SP - 2 (SP - 1, SP - 2) PSW SP SP - 2 Push registers on the stack (SP - 1, SP - 2) imm8 sign extension SP SP - 2 (SP - 1, SP - 2) imm16 SP SP - 2 SP SP + 2 (mem16) (SP - 1, SP - 2) SP SP + 2 reg16 (SP - 1, SP - 2) SP SP + 2 sreg (SP - 1, SP - 2) SP SP + 2 PSW (SP - 1, SP - 2) Pop registers from the stack Prepare New Stack Frame Dispose of Stack Frame PC PC + disp PC PC + ext-disp8 PC regptr16 PC (memptr16) PS seg PC offset PS (memptr32 + 2) PC (memptr32) Bytes Operation
Flags AC CY V P S Z
0 0 0 sreg 1 1 1 10011101 01100001 11001000 11001001 11101001 11101011 11111111 11111111 11101010 11111111
sreg: SS, DS0, DS1 R R R R R R
mod 1 0 0 mem
PD70320
33
34
Group Mnemonic Operand Conditional branch BV BNV BC BL BNC BNL BE BZ BNE BNZ BNH BH BN BP BPE BPO BLT BGE BLE BGT DBNZNE DBNZE DBNZ BCWZ BTCLR
Note
Operation Code Bytes 76543210 short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label sfr, imm3, short-label 01110000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 11100000 0001 0010 0011 00001111 10011100 76543210 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 5 if V = 1 if V = 0 if CY = 1 if CY = 0 if Z = 1 if Z = 0 if CY Z = 1 if CY Z = 0 if S = 1 if S = 0 if P = 1 if P = 0 if S V = 1 if S V = 0 if (S V) Z = 1 if (S V) Z = 0 CW = CW - 1 if Z = 0 and CW 0 CW = CW - 1 if Z = 1 and CW 0 CW = CW - 1 if CW 0 if CW = 0 PC PC + ext-disp8 PC PC + ext-disp8 PC PC + ext-disp8 PC PC + ext-disp8 PC PC + ext-disp8 PC PC + ext-disp8 PC PC + ext-disp8 PC PC + ext-disp8 PC PC + ext-disp8 PC PC + ext-disp8 PC PC + ext-disp8 PC PC + ext-disp8 PC PC + ext-disp8 PC PC + ext-disp8 PC PC + ext-disp8 PC PC + ext-disp8 PC PC + ext-disp8 PC PC + ext-disp8 PC PC + ext-disp8 PC PC + ext-disp8 Operation
Flags AC CY V P S Z
When (sfr) bit No. imm3 = 1, PC PC + ext-disp8 and (sfr) bit No. imm3 0.
PD70320
Note This instruction is newly added to the PD70108/70116.
Operation Code Group Interrupt Mnemonic Operand 76543210 BRK 3 11001100 76543210 1 (SP - 1, SP - 2) PSW, (SP - 3, SP - 4) PS, (SP - 5, SP - 6) PC, SP SP - 6 IE 0, BRK 0 PS (15, 14), PC (13, 12) (SP - 1, SP - 2) PSW, (SP - 3, SP - 4) PS, (SP - 5, SP - 6) PC, SP SP - 6 IE 0, BRK 0 PS (n x 4 + 3, n x 4 + 2), PC (n x 4 + 1, n x 4) n = imm8 When V = 1, (SP - 1, SP - 2) PSW, (SP - 3, SP - 4) PS, (SP - 5, SP - 6) PC, SP SP - 6 IE 0, BRK 0 PS (19, 18), PC (17, 16) PC (SP + 1, SP), PS (SP + 3, SP + 2), PSW (SP + 5, SP + 4), SP SP + 6 PC Save PC, PSW Save PSW Reports the CPU internal interrupt controller that interrupt service routine operation has ended. When (mem32) > reg16 or (mem32 + 2) < reg16, (SP - 1, SP - 2) PSW, (SP - 3, SP - 4) PS, (SP - 5, SP - 6) PC, SP SP - 6 IE 0, BRK 0 PS (23, 22), PC (21, 20) RB2 - 0 lower 3 bits of reg16, IE 0, BRK 0 Save PSW PSW, Save PC PC, PC Vector PC R R R R Bytes Operation
Flags AC CY V P S Z
imm8 ( 3)
11001101
2
BRKV
11001110
1
RETI RETRBI Note FINT Note CHKIND reg16,mem32
11001111 00001111 00001111 01100010 10010001 10010010 mod reg mem
1 2 2 2 to 4
R R
R R
R R
R R
Register bank switch
BRKCS Note
reg16
00001111 11000 reg
00101101
3
TSKSW Note
reg16
00001111 11111 reg
10010100
3
RB2 - 0 lower 3 bits of reg16, Old register bank Save PSW and Save PC PSW and PC, PSW and PC New register bank Save PSW and Save PC
x
x
x
x
x
x
Note These instructions are newly added to the PD70108/70116.
PD70320
35
36
Group Mnemonic Operand CPU control HALT STOP POLL DI EI BUSLOCK FPO1
Note 3 Note 2
Operation Code Bytes 76543210 11110100 00001111 10011011 11111010 11111011 11110000 fp-op fp-op,mem fp-op
Note 3
Flags Operation AC CY V 1 CPU Halt CPU Stop Poll and wait IE 0 IE 1 Bus Lock Prefix No Operation data bus (mem) No Operation data bus (mem) No Operation Segment override prefix P S Z
76543210
10011110
2 1 1 1 1
11011XXX 11011XXX 0110011X 0110011X 10010000
11YYYZZZ mod Y Y Y mem 11YYYZZZ mod Y Y Y mem
2 2 to 4 2 2 to 4 1 1
FPO2
fp-op,mem
NOP
Note 1
0 0 1 sreg 1 1 0
Notes 1. DS0:, DS1:, PS: and SS: 2. This instruction is newly added to the PD70108/70116. 3. In the PD70320, an interrupt is generated without executing these instructions.
PD70320
PD70320
Table 2-8. Number of Clocks (1/10)
Byte Processing Group Data transfer Mnemonic MOV Operands reg, reg mem, reg reg, mem mem, imm reg, imm acc, dmem dmem, acc sreg, reg16 sreg, mem16 reg16, sreg mem16, sreg DS0, reg16, mem32 DS1, reg16, mem32 AH, PSW PSW, AH LDEA TRANS XCH reg16, mem16 src-table reg, reg mem, reg/ reg, mem AW, reg16/ reg16, AW MOVSPA MOVSPB Repeat prefix REPC REPNC REP/REPE/ REPZ REPNE/ REPNZ Primitive block transfer MOVKBNote dst-block, src-block dst-block, src-block 20 + 2*T 16 + (16 + 2*T)*n 23 + 2*T 16 + (21 + 2*T)*n 16 + T 16 + (12 + T)*n 19 + T 16 + (21 + 2*T)*n 24 + 4*T 16 + (20 + 4*T)*n 27 + 4*T 16 + (25 + 4*T)*n 20 + 2*T 16 + (12 + 2*T)*n 21 + 4*T 16 + (25 + 2*T)*n reg16 On-chip RAM Access Enable 2 EA + 4 + T EA + 6 + T EA + 5 + T 5 9+T 7+T -- -- -- -- -- -- 2 3 -- 10 + T 3 EA + 10 + 2*T -- -- -- 2 2 2 2 On-chip RAM Access Disable 2 EA + 2 EA + 6 + T EA + 5 + T 5 9+T 5 -- -- -- -- -- -- 2 3 -- 10 + T 3 EA + 8 + 2*T -- -- -- 2 2 2 2 Word Processing On-chip RAM Access Enable 2 EA + 6 + 2*T EA + 8 + 2*T EA + 5 + 2*T 6 11 + 2*T 9 + 2*T 4 EA + 10 + 2*T 3 EA + 7 + 2*T EA + 19 + 4*T EA + 19 + 4*T -- -- EA + 2 -- 3 EA + 14 + 2*T 4 16 11 2 2 2 2 On-chip RAM Access Disable 2 EA + 2 EA + 8 + 2*T EA + 5 + T 6 11 + 2*T 5 4 EA + 10 + 2*T 3 EA + 3 EA + 19 + 4*T EA + 19 + 4*T -- -- EA + 2 -- 3 EA + 10 + 2*T 4 16 11 2 2 2 2
CMPKBNote
Note n 1
37
PD70320
Table 2-8. Number of Clocks (2/10)
Byte Processing Group Primitive block transfer Mnemonic CMPMNote 1 Operands dst-block src-block src-block On-chip RAM Access Enable 17 + T 16 + (15 + T)*n 12 + T 16 + (10 + T)*n STMNote 1 dst-block 12 + T 16 + (8 + T)*n Bit field manipulation INS reg8, reg8 reg8, imm4 EXT reg8, reg8 reg8, imm4 I/O INNote 2 acc, imm8 acc, DW OUT
Note 2
Word Processing On-chip RAM Access Enable 19 + 2*T 16 + (17 + 2*T)*n 14 + 2*T 16 + (12 + 2*T)*n 14 + 2*T 16 + (10 + 2*T)*n On-chip RAM Access Disable 19 + 2*T 16 + (17 + 2*T)*n 14 + 2*T 16 + (12 + 2*T)*n 10 16 + (6 + 2*T)*n
On-chip RAM Access Disable 17 + T 16 + (15 + T)*n 12 + T 16 + (10 + T)*n 10 16 + (6+ T)*n
LDM
Note 1
63 to 155 (The processing differs among bit lengths.) 64 to 156 (The processing differs among bit lengths.) 41 to 121 (The processing differs among bit lengths.) 42 to 122 (The processing differs among bit lengths.) 14 + T 13 + T 10 + T 9+T 19 + 2*T 18 + (13 + 2*T)*n 14 + T 13 + T 10 + T 9+T 17 + 2*T 18 + (11 + 2*T)*n 17 + 2*T 18 + (11 + 2*T)*n 2 EA + 6 + T EA + 6 + T 5 EA + 7 + 2*T 5 2 EA + 6 + T EA + 6 + T 5 EA + 7 + 2*T 5 16 + 2*T 15 + 2*T 10 + 2*T 9 + 2*T 21 + 4*T 18 + (15 + 4*T)*n 21 + 4*T 18 + (15 + 4*T)*n 2 EA + 12 + 4*T EA + 8 + 2*T 6 EA + 14 + 4*T 6 2 EA + 12 + 4*T EA + 8 + 2*T 6 EA + 14 + 4*T 6 16 + 2*T 15 + 2*T 10 + 2*T 9 + 2*T 17 + 4*T 18 + (11 + 4*T)*n 17 + 4*T 18 + (11 + 4*T)*n 2 EA + 8 + 2*T EA + 8 + 2*T 6 EA + 10 + 4*T 6 2 EA + 8 + 2*T EA + 8 + 2*T 6 EA + 10 + 4*T 6
imm8, acc DW, acc
Primitive I/O
INMNote 2
dst-block, DW
OUTM
Note 2
DW, src-block
19 + 2*T 18 + (13 + 2*T)*n
Addition/ ADD subtraction
reg, reg mem, reg reg, mem reg, imm mem, imm acc, imm
2 EA + 8 + 2*T EA + 6 + T 5 EA + 9 + 2*T 5 2 EA + 8 + 2*T EA + 6 + T 5 EA + 9 + 2*T 5
ADDC
reg, reg mem, reg reg, mem reg, imm mem, imm acc, imm
Notes 1. n 1 2. When IBRK = 1
38
PD70320
Table 2-8. Number of Clocks (3/10)
Byte Processing Group Mnemonic Operands reg, reg mem, reg reg, mem reg, imm mem, imm acc, imm SUBC reg, reg mem, reg reg, mem reg, imm mem, imm acc, imm BCD operation ADD4S
Note
Word Processing On-chip RAM Access Enable 2 EA + 12 + 4*T EA + 8 + 2*T 6 EA + 14 + 4*T 6 2 EA + 12 + 4*T EA + 8 + 2*T 6 EA + 14 + 4*T 6 -- -- -- -- -- -- -- -- EA + 15 + 4*T 2 -- EA + 15 + 4*T 2 -- -- 32 EA + 34 + 2*T On-chip RAM Access Disable 2 EA + 8 + 2*T EA + 8 + 2*T 6 EA + 10 + 4*T 6 2 EA + 8 + 2*T EA + 8 + 2*T 6 EA + 10 + 4*T 6 -- -- -- -- -- -- -- -- EA + 11 + 4*T 2 -- EA + 11 + 4*T 2 -- -- 32 EA + 34 + 2*T
On-chip RAM Access Enable 2 EA + 8 + 2*T EA + 6 + T 5 EA + 9 + 2*T 5 2 EA + 8 + 2*T EA + 6 + T 5 EA + 9 + 2*T 5 22 + (27 + 3*T)*n 22 + (27 + 3*T)*n 22 + (23 + 3*T)*n
On-chip RAM Access Disable 2 EA + 6 + T EA + 6 + T 5 EA + 7 + 2*T 5 2 EA + 6 + T EA + 6 + T 5 EA + 7 + 2*T 5 22 + (25 + 3*T)*n 22 + (25 + 3*T)*n 22 + (23 + 3*T)*n 17 EA + 16 + 2*T 21 EA + 22 + 2*T 5 EA + 9 + 2*T -- 5 EA + 9 + 2*T -- 24 EA + 26 + T -- --
Addition/ SUB subtraction
SUB4SNote CMP4S ROL4
Note
reg8 mem8
17 EA + 18 + 2*T 21 EA + 24 + 2*T 5 EA + 11 + 2*T -- 5 EA + 11 + 2*T -- 24 EA + 26 + T -- --
ROR4
reg8 mem8
Increment / INC decrement
reg8 mem8 reg16
DEC
reg8 mem8 reg16
Multiplication
MULU
reg8 mem8 reg16 mem16
Note n: 1/2 of the number of BCD digits.
39
PD70320
Table 2-8. Number of Clocks (4/10)
Byte Processing Group Multiplication Mnemonic MUL Operands reg8 mem8 reg16 mem16 reg16, (reg16,) imm8 reg16, mem16, imm8 reg16, (reg16,) imm16 reg16, mem16, imm16 Unsigned division DIVU reg8 mem8 reg16 mem16 Signed division DIV reg8 mem8 reg16 mem16 BCD ADJBA adjustment ADJ4A ADJBS ADJ4S Data CVTBD conversion CVTDB CVTBW CVTWL Compare CMP reg, reg mem, reg reg, mem reg, imm mem, imm acc, imm On-chip RAM Access Enable 31 to 40 EA + 33 + T to EA + 42 + T -- -- -- -- -- -- 31 EA + 33 + T -- -- 46 to 56 EA + 48 + T to EA + 58 + T -- -- 17 9 17 9 19 20 3 -- 2 EA + 6 + T EA + 6 + T 5 EA + 7 + T 5 On-chip RAM Access Disable 31 to 40 EA + 33 + T to EA + 42 + T -- -- -- -- -- -- 31 EA + 33 + T -- -- 46 to 56 EA + 48 + T to EA + 58 + T -- -- 17 9 17 9 19 20 3 -- 2 EA + 6 + T EA + 6 + T 5 EA + 7 + T 5 Word Processing On-chip RAM Access Enable -- -- 39 to 48 EA + 43 + 2*T to EA + 52 + 2*T 39 to 49 EA + 43 + 2*T to EA + 53 + 2*T 40 to 50 EA + 44 + 2*T to EA + 54 + 2*T -- -- 39 EA + 43 + 2*T -- -- 54 to 64 EA + 58 + 2*T to EA + 68 + 2*T -- -- -- -- -- -- -- 8 2 EA + 8 + 2*T EA + 8 + 2*T 6 EA + 10 + 2*T 6 On-chip RAM Access Disable -- -- 39 to 48 EA + 43 + 2*T to EA + 52 + 2*T 39 to 49 EA + 43 + 2*T to EA + 53 + 2*T 40 to 50 EA + 44 + 2*T to EA + 54 + 2*T -- -- 39 EA + 43 + 2*T -- -- 54 to 64 EA + 58 + 2*T to EA + 68 + 2*T -- -- -- -- -- -- -- 8 2 EA + 8 + 2*T EA + 8 + 2*T 6 EA + 10 + 2*T 6
40
PD70320
Table 2-8. Number of Clocks (5/10)
Byte Processing Group Comple ment operation Mnemonic NOT reg mem NEG reg mem Logical operation TEST reg, reg mem, reg/ reg, mem reg, imm mem, imm acc, imm AND reg, reg mem, reg reg, mem reg, imm mem, imm acc, imm OR reg, reg mem, reg reg, mem reg, imm mem, imm acc, imm XOR reg, reg mem, reg reg, mem reg, imm mem, imm acc, imm Bit manipulation TEST1 reg8, CL mem8, CL reg16, CL mem16, CL reg8, imm3 mem8, imm3 reg16, imm4 mem16, imm4 NOT1 reg8, CL mem8, CL reg16, CL Operands On-chip RAM Access Enable 5 EA + 11 + 2*T 5 EA + 11 + 2*T 4 EA + 8 + T 7 EA + 11 + T 5 2 EA + 8 + 2*T EA + 6 + T 5 EA + 9 + T 5 2 EA + 8 + 2*T EA + 6 + T 5 EA + 9 + T 5 2 EA + 8 + 2*T EA + 6 + T 5 EA + 9 + T 5 7 EA + 11 + T -- -- 6 EA + 8 + T -- -- 7 EA + 13 + 2*T -- On-chip RAM Access Disable 5 EA + 9 + T 5 EA + 9 + T 4 EA + 8 + T 7 EA + 11 + T 5 2 EA + 6 + T EA + 6 + T 5 EA + 7 + T 5 2 EA + 6 + T EA + 6 + T 5 EA + 7 + T 5 2 EA + 6 + T EA + 6 + T 5 EA + 7 + T 5 7 EA + 11 + T -- -- 6 EA + 8 + T -- -- 7 EA + 11 + T -- Word Processing On-chip RAM Access Enable 5 EA + 15 + 4*T 5 EA + 15 + 4*T 4 EA + 10 + 2*T 8 EA + 11 + 2*T 6 2 EA + 12 + 4*T EA + 8 + 2*T 6 EA + 14 + 4*T 6 2 EA + 12 + 4*T EA + 8 + 2*T 6 EA + 14 + 4*T 6 2 EA + 12 + 4*T EA + 8 + 2*T 6 EA + 14 + 4*T 6 -- -- 7 EA + 13 + 2*T -- -- 6 EA + 10 + 2*T -- -- 7 On-chip RAM Access Disable 5 EA + 11 + 2*T 5 EA + 11 + 2*T 4 EA + 10 + 2*T 8 EA + 11 + 2*T 6 2 EA + 8 + 2*T EA + 8 + 2*T 6 EA + 10 + 4*T 6 2 EA + 8 + 2*T EA + 8 + 2*T 6 EA + 10 + 4*T 6 2 EA + 8 + 2*T EA + 8 + 2*T 6 EA + 10 + 4*T 6 -- -- 7 EA + 13 + 2*T -- -- 6 EA + 10 + 2*T -- -- 7
41
PD70320
Table 2-8. Number of Clocks (6/10)
Byte Processing Group Bit manipulation Mnemonic NOT1 Operands mem16, CL reg8, imm3 mem8, imm3 reg16, imm4 mem16, imm4 NOT1 Bit manipulation CLR1 CY reg8, CL mem8, CL reg16, CL mem16, CL reg8, imm3 mem8, imm3 reg16, imm4 mem16, imm4 SET1 reg8, CL mem8, CL reg16, CL mem16, CL reg8, imm3 mem8, imm3 reg16, imm4 mem16, imm4 CLR1 CY DIR SET1 CY DIR Shift SHL
Note
Word Processing On-chip RAM Access Enable EA + 17 + 4*T -- -- 6 EA + 14 + 4*T 2 -- -- 8 EA + 18 + 4*T -- -- 7 EA + 15 + 4*T -- -- 7 EA + 17 + 4*T -- -- 6 EA + 14 + 4*T 2 2 2 2 8 EA + 18 + 4*T 11 + 2*n On-chip RAM Access Disable EA + 13 + 2*T -- -- 6 EA + 10 + 2*T 2 -- -- 8 EA + 14 + 2*T -- -- 7 EA + 10 + 2*T -- -- 7 EA + 13 + 2*T -- -- 6 EA + 10 + 2*T 2 2 2 2 8 EA + 14 + 2*T 11 + 2*n
On-chip RAM Access Enable -- 6 EA + 10 + 2*T -- -- 2 8 EA + 14 + 2*T -- -- 7 EA + 11 + 2*T -- -- 7 EA + 13 + 2*T -- -- 6 EA + 10 + 2*T -- -- 2 2 2 2 8 EA + 14 + 2*T 11 + 2*n
On-chip RAM Access Disable -- 6 EA + 8 + T -- -- 2 8 EA + 12 + T -- -- 7 EA + 9 + T -- -- 7 EA + 11 + T -- -- 6 EA + 8 + T -- -- 2 2 2 2 8 EA + 12 + T 11 + 2*n
reg,1 mem, 1 reg, CL mem, CL reg, imm8 mem, imm8
EA + 17 + 2*T + 2*n EA + 15 + T + 2*n EA + 21 + 4*T + 2*n EA + 17 + 2*T + 2*n 9 + 2*n 9 + 2*n 9 + 2*n 9 + 2*n
EA + 13 + 2*T + 2*n EA + 11 + T + 2*n EA + 17 + 4*T + 2*n EA + 13 + 2*T + 2*n 8 EA + 14 + 2*T 8 EA + 12 + T 8 EA + 18 + 4*T 8 EA + 14 + 2*T
SHR
reg, 1 mem, 1
Note n: Shift count
42
PD70320
Table 2-8. Number of Clocks (7/10)
Byte Processing Group Shift Mnemonic SHR
Note
Word Processing On-chip RAM Access Enable 11 + 2*n On-chip RAM Access Disable 11 + 2*n
Operands reg, CL mem, CL reg, imm8 mem, imm8
On-chip RAM Access Enable 11 + 2*n
On-chip RAM Access Disable 11 + 2*n
EA + 17 + 2*T + 2*n EA + 15 + T + 2*n EA + 21 + 4*T + 2*n EA + 17 + 2*T + 2*n 9 + 2*n 9 + 2*n 9 + 2*n 9 + 2*n
EA + 13 + 2*T + 2*n EA + 11 + T + 2*n EA + 17 + 4*T + 2*n EA + 13 + 2*T + 2*n 8 EA + 14 + 2*T 11 + 2*n 8 EA + 12 + T 11 + 2*n 8 EA + 18 + 4*T 11 + 2*n 8 EA + 14 + 2*T 11 + 2*n
SHRA
Note
reg,1 mem, 1 reg, CL mem, CL reg, imm8 mem, imm8
EA + 17 + 2*T + 2*n EA + 15 + T + 2*n EA + 21 + 4*T + 2*n EA + 17 + 2*T + 2*n 9 + 2*n 9 + 2*n 9 + 2*n 9 + 2*n
EA + 13 + 2*T + 2*n EA + 11 + T + 2*n EA + 17 + 4*T + 2*n EA + 13 + 2*T + 2*n 8 EA + 14 + 2*T 11 + 2*n 8 EA + 12 + T 11 + 2*n 8 EA + 18 + 4*T 11 + 2*n 8 EA + 14 + 2*T 11 + 2*n
Rotate
ROL
Note
reg,1 mem, 1 reg, CL mem, CL reg, imm8 mem, imm8
EA + 17 + 2*T + 2*n EA + 15 + T + 2*n EA + 21 + 4*T + 2*n EA + 17 + 2*T + 2*n 9 + 2*n 9 + 2*n 9 + 2*n 9 + 2*n
EA + 13 + 2*T + 2*n EA + 11 + T + 2*n EA + 17 + 4*T + 2*n EA + 13 + 2*T + 2*n 8 EA + 14 + 2*T 11 + 2*n 8 EA + 12 + T 11 + 2*n 8 EA + 18 + 4*T 11 + 2*n 8 EA + 14 + 2*T 11 + 2*n
ROR
Note
reg,1 mem, 1 reg, CL mem, CL reg, imm8 mem, imm8
EA + 17 + 2*T + 2*n EA + 15 + T + 2*n EA + 21 + 4*T + 2*n EA + 17 + 2*T + 2*n 9 + 2*n 9 + 2*n 9 + 2*n 9 + 2*n
EA + 13 + 2*T + 2*n EA + 11 + T + 2*n EA + 17 + 4*T + 2*n EA + 13 + 2*T + 2*n 8 EA + 14 + 2*T 11 + 2*n 8 EA + 12 + T 11 + 2*n 8 EA + 18 + 4*T 11 + 2*n 8 EA + 14 + 2*T 11 + 2*n
ROLC
Note
reg,1 mem, 1 reg, CL mem, CL reg, imm8 mem, imm8
EA + 17 + 2*T + 2*n EA + 15 + T + 2*n EA + 21 + 4*T + 2*n EA + 17 + 2*T + 2*n 9 + 2*n 9 + 2*n 9 + 2*n 9 + 2*n
EA + 13 + 2*T + 2*n EA + 11 + T + 2*n EA + 17 + 4*T + 2*n EA + 13 + 2*T + 2*n 8 EA + 14 + 2*T 8 EA + 12 + T 8 EA + 18 + 4*T 8 EA + 14 + 2*T
RORC
reg,1 mem, 1
Note n: Shift count
43
PD70320
Table 2-8. Number of Clocks (8/10)
Byte Processing Group Rotate Mnemonic RORC
Note
Word Processing On-chip RAM Access Enable 11 + 2*n On-chip RAM Access Disable 11 + 2*n
Operands reg, CL mem, CL reg, imm8 mem, imm8
On-chip RAM Access Enable 11 + 2*n
On-chip RAM Access Disable 11 + 2*n
EA + 17 + 2*T + 2*n EA + 15 + T + 2*n EA + 21 + 4*T + 2*n EA + 17 + 2*T + 2*n 9 + 2*n 9 + 2*n 9 + 2*n 9 + 2*n
EA + 13 + 2*T + 2*n EA + 11 + T + 2*n EA + 17 + 4*T + 2*n EA + 13 + 2*T + 2*n -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 22 + 2*T 22 + 2*T EA + 26 + 4*T 38 + 4*T EA + 36 + 8*T 20 + 2*T 20 + 2*T 29 + 4*T 30 + 4*T EA + 18 + 4*T 10 + 2*T 11 + 2*T 10 + 2*T 82 + 16*T 13 + 2*T 14 + 2*T EA + 16 + 4*T 12 + 2*T 13 + 2*T 14 + 2*T 82 + 16*T 18 + 2*T 18 + 2*T EA + 24 + 4*T 34 + 4*T EA + 24 + 8*T 20 + 2*T 20 + 2*T 29 + 4*T 30 + 4*T EA + 14 + 4*T 6 7 6 50 9 10 EA + 12 + 2*T 12 + 2*T 13 + 2*T 14 + 2*T 58
Subroutine CALL control
near-proc regptr16 memptr16 far-proc memptr32
RET pop-value
-- --
pop-value Stack manipulation PUSH mem16 reg16 sreg PSW R imm8 imm16 POP mem16 reg16 sreg PSW R PREPARE imm16, imm8
-- -- -- -- -- -- -- -- -- -- -- -- --
When imm8 = 0, 27 + 2*T When imm8 = 1, 39 + 4*T When imm8 = n, n > 1, 46 + 19(n - 1) + 4*T -- -- 12 + 2*T 12 + 2*T
DISPOSE
Note n: Shift count
44
PD70320
Table 2-8. Number of Clocks (9/10)
Byte Processing Group Branch Mnemonic BR Operands near-label short-label regptr16 memptr16 far-label memptr32 Conditional BV branch BNV BC/BL BNC/BNL BE/BZ BNE/BNZ BNH BH BN BP BPE BPO BLT BGE BLE BGT DBNZNE DBNZE DBNZ BCWZ BTCLR Interrupt BRK short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label sfr, imm3, short-label 3 imm8 (3) BRKV RETI RETRBI FINT CHKIND reg16, mem32 On-chip RAM Access Enable -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 29/21 -- -- -- -- -- 2 -- On-chip RAM Access Disable -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 29/21 -- -- -- -- -- 2 -- Word Processing On-chip RAM Access Enable 12 12 13 EA + 17 + 2*T 15 EA + 25 + 4*T 15/8 15/8 15/8 15/8 15/8 15/8 15/8 15/8 15/8 15/8 15/8 15/8 15/8 15/8 15/8 15/8 17/8 17/8 17/8 15/8 -- 55 + 10*T 56 + 10*T 55 + 10*T 45 + 6*T 12 2 EA + 26 + 4*T On-chip RAM Access Disable 12 12 13 EA + 17 + 2*T 15 EA + 25 + 4*T 15/8 15/8 15/8 15/8 15/8 15/8 15/8 15/8 15/8 15/8 15/8 15/8 15/8 15/8 15/8 15/8 17/8 17/8 17/8 15/8 -- 43 + 10*T 44 + 10*T 43 + 10*T 37 + 2*T 12 2 EA + 26 + 4*T
45
PD70320
Table 2-8. Number of Clocks (10/10)
Byte Processing Group Mnemonic Operands reg16 reg16 On-chip RAM Access Enable -- -- -- -- -- 4 12 2 fp-op fp-op, mem FPO2 fp-op fp-op, mem NOP Segment override prefix (DS0:, DS1:, PS: and SS:) -- -- -- -- 4 2 On-chip RAM Access Disable -- -- -- -- -- 4 12 2 -- -- -- -- 4 2 Word Processing On-chip RAM Access Enable 15 20 -- -- -- 4 12 2 60 + 10*T 60 + 10*T 60 + 10*T 60 + 10*T 4 2 On-chip RAM Access Disable 15 20 -- -- -- 4 12 2 48 + 10*T 48 + 10*T 48 + 10*T 48 + 10*T 4 2
Register BRKCS bank switch TSKSW CPU control HALT STOP POLL DI EI BUSLOCK FPO1
46
PD70320
3. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (TA = 25C)
Parameter Supply Voltage Input Voltage Symbol VDD VTH VI Output Voltage Output Current Low VO IOL Each output pin Total Output Current High IOH Each output pin Total Operating Ambient Temperature Storage Temperature TA Tstg Test Conditions Rating - 0.5 to +7.0 - 0.5 to VDD + 0.5 - 0.5 to VDD + 0.5 - 0.5 to VDD + 0.5 4.0 50 -2.0 -20 -40 to +85 - 65 to +150 Unit V V V V mA mA mA mA C C
Cautions 1. Do not make direct connections of the output (or input/output) pins of the IC product with each other, and also avoid direct connections to VDD, VCC or GND. However, the open drain pins or the open collector pins can be directly connected with each other. For the external circuit designed with the timing specifications so that any collision of the outputs from the pins subject to high-impedance state may be prevented, direct connection can be also made. 2. Product quality may suffer if the absolute maximum ratings are exceeded for even a single parameter, or even momentarily. In other words, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded. The normal operation and reliability of the product can be only assured with the specifications and the conditions indicated as the DC and AC characteristics.
47
PD70320
OSCILLATOR CHARACTERISTICS (TA = -40 to +85C, VDD = +5.0 V 10%, VSS = 0 V, 0 V VTH VDD + 0.1 V)
PD70320
MIN. Ceramic or Crystal Resonator X1 X2 Oscillation frequency (fXX) 4 MAX. 10
Resonator
Recommended Circuit
Parameter
PD70320-8
MIN. 4 MAX. 16
Unit MHz
C1
C2
External Clock
1
X1
X2
X1 input frequency (fX)
4
10
4
16
MHz
HCMOS Inverter
X1 rise/fall time (tXR, tXF)
0
20
0
20
ns
or 2 X1 X2 Open HCMOS Inverter X1 input high-/ low-level width (tWXH, tWXL) 35 250 20 250 ns
Cautions 1. Mount the oscillation circuit as close to pins X1 and X2 as possible. 2. Do not route other signal lines through the area within the dotted line.
48
PD70320
RECOMMENDED OSCILLATOR CONSTANT Ceramic resonator
Manufacturer Kyocera Corp. Murata Mfg. Co., Ltd. Part Number KBR-10.0M
Note 1
Recommended Constants C1 [pF] 33 100 47 C2 [pF] 33 100 47
CSA7.37MT040Note 2 CSA10.0MTNote 1 CSA11.0MT
Note 2
CSA16.0MX040Note 1 TDK FCR10.0M2SNote 2 FCR16.0M2S
Note 2 Note 2
30 30 15 22
30 30 6 10
FCR16.0M2G
Notes 1. The operating ambient temperature (TA) is -10C to +70C when this resonator is used. 2. The operating ambient temperature (TA) is -20C to +80C when this resonator is used. Crystal resonator
Manufacturer Kinseki Co., Ltd. Part Number HC-49/U(KR-100) HC-49/U(KR-160) Recommended Constants C1 [pF] 22 22 C2 [pF] 22 22
Remark For more details on the characteristics of the resonators, please contact the manufacturer.
49
PD70320
CAPACITANCE (TA = 25C, VDD = 0 V)
Parameter Input Capacitance Output Capacitance Input/output Capacitance Symbol CI CO CIO Test Conditions fC = 1 MHz Unmeasured pins returned to 0 V. MIN. TYP. MAX. 10 20 20 Unit pF pF pF
DC CHARACTERISTICS (TA = -40C to +85C, VDD = +5.0 V 10%)
Parameter Input Voltage Low Input Voltage High Symbol VIL VIH1 VIH2 Output Voltage Low Output Voltage High Input Current Input Leakage Current Output Leakage Current VTH Current VDD Supply Current VOL VOH II ILI ILO ITH IDD1 Except RESET, P10/NMI, X1, X2 RESET, P10/NMI, X1, X2 IOL = 1.6 mA IOH = -0.4 mA EA, P10/NMI; 0 VI VDD Except EA, P10/NMI; 0 VI VDD 0 VO VDD 0 V VTH VDD Operating mode 0.5 VDD - 1.0 20 10 10 1.0 100 120 40 50 30 Test Conditions MIN. 0 2.2 0.8VDD TYP. MAX. 0.8 VDD VDD 0.45 Unit V V V V V
A A A
mA mA mA mA mA
PD70320 PD70320-8 PD70320 PD70320-8
50 65 20 25 10
IDD2
HALT mode
IDD3
STOP mode
A
AC CHARACTERISTICS (TA = -40 to +85C, VDD = +5.0 V 10%)
Parameter X1 Input Cycle Time X1 Input High-/Low-Level Width X1 Input Rise/Fall Time CLKOUT Output Cycle Time CLKOUT Output High-/Low-Level Width CLKOUT Output Rise/Fall Time Input Rise/Fall Time Symbol tCYX tWXH, tWXL tXR, tXF tCYK tWKH, tWKL tKR, tKF tIR, tIF tIRS, tIFS Output Rise/Fall Time tOR, tOF Except RESET, NMI, X1 and X2 RESET, NMI Except CLKOUT fX /2, T = tCYK 200 0.5T - 15 15 20 30 20 Test Conditions
PD70320
MIN. 98 35 20 2000 MAX. 250
PD70320-8
MIN. 62 20 20 125 0.5T - 15 15 20 30 20 2000 MAX. 250
Unit ns ns ns ns ns ns ns ns ns
50
PD70320
Parameter Address Delay Time from CLKOUT Data Input Delay Time from Address Data Delay Time from MREQ Data Delay Time from MSTB MSTB Delay Time from MREQ MREQ Low-Level Width Address Hold Time (from MREQ ) Data Input Hold Time (from MREQ ) Control Signal Recovery Time Data Output Delay Time from Address Address Setup Time (to MREQ ) Address Setup Time (to MSTB ) MSTB Low-Level Width Data Output Setup Time (to MSTB ) Data Output Hold Time (from MSTB ) Address Setup Time (to IOSTB ) Data Delay Time from IOSTB IOSTB Low-Level Width Address Hold Time (from IOSTB ) Data Input Hold Time (from IOREQ ) Data Output Setup Time (to IOSTB ) Data Output Hold Time (from IOSTB ) DMARQ Setup Time (to MREQ ) DMARQ Hold Time (from DMAAK ) DMAAK Output Low-Level Width TC Delay Time from DMAAK TC Low-Level Width DMAAK Output Low-Level Width Address Setup Time (to REFRQ ) REFRQ Low-Level Width Address Hold Time (from REFRQ ) RESET Low-Level Width Symbol tDKA tDADR tDMRD tDMSD tDMRMS tWMRL tHMA tHMDR tRVC tDADW tDAMR tDAMS tWMSL tSDM tHMDW tDAIS tDISD tWISL tHISA tHISDR tSDIS tHISDW tSDADQ tHDADQ tWDMRL tDDATC tWTCL tWDMWL tDARF tWRFL tHRFA tWRSL1 tWRSL2 READY Setup Time (to MREQ , IOSTB ) tSCRY0 tSCRY STOP mode release/ power-ON reset System reset n2 n3 Write mode 2T - 30 (n + 1)T - 30 0.5T - 30 (n + 1)T - 30 0.5T - 30 30 5 T - 100 (n - 1)T - 100 Demand release mode Demand release mode Read mode 0 (n + 1.5)T - 30 0.5T + 50 (n + 1)T - 30 0.5T - 30 0 (n + 1)T - 50 0.5T - 30 1T 0.5T - 30 T - 30 (n + 0.5)T - 30 (n + 1)T - 50 0.5T - 30 0.5T - 30 (n + 1)T - 90 (n + 0.5)T + 30 0.5T - 35 (n + 1)T - 30 0.5T - 30 0 T - 25 0.5T + 50 Test Conditions MIN. MAX. 90 (n + 1.5)T - 90 (n + 1)T - 75 (n+ 0.5)T - 75 0.5T + 35 (n + 1)T + 30 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms
s
ns ns
51
PD70320
Parameter READY Hold Time (from MREQ , IOSTB ) Symbol tHCRY0 tHCRY tHCRY1 HLDRQ Setup Time (to CLKOUT ) HLDAK Delay Time from CLKOUT HLDAK Delay Time from Bus Float Bus Output Delay Time from HLDAK HLDAK Delay Time from HLDRQ Bus Output Delay Time from HLDRQ HLDRQ Low-Level Width HLDAK Low-Level Width tSHQK tDKHA tCFHA tDHAC tDHQHA tDHQC tWHQL tWHAL 3T + 30 1.5T 1T 30 8T 30 5 2T 30 80 0 2T - 30 1T - 30 2T - 130 0 1000 450 210 20 1000 420 80 0.5T 1T - 50 1T - 50 3T + 160 Test Conditions n=2 n3 n3 MIN. 1T (n - 1)T (n - 2)T 30 80 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
INT, DMARQ Setup Time (to CLKOUT ) tSIQK INT, DMARQ High-/Low-Level Width POLL Setup Time (to CLKOUT ) NMI High-/Low-Level Width CTS Low-Level Width INT Setup Time (to CLKOUT ) INTAK Delay Time from CLKOUT INT Hold Time (from INTAK ) INTAK Low-Level Width INTAK High-Level Width Data Delay Time from INTAK Data Hold Time (from INTAK ) SCK0 Cycle Time SCK0 High-/Low-Level Width TxD Delay Time from SCK0 TxD Hold Time (from SCK0 ) CTS0 Cycle Time CTS0 High-/Low-Level Width RxD Setup/Hold Time (to/from CTS0 ) tWIQH, tWIQL tSPLK tWNIH, tWNIL tWCTL tSIRK tDKIA tHIAIQ tWIAL tWIAH tDIAD tHIAD tCYTK tWSTH, tWSTL tDTKD tHTKD tCYRK tWSRH, tWSRL tSRDK, tHKRD
s
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Remark n indicates the number of wait states. No wait is "n = 0".
52
PD70320
COMPARATOR CHARACTERISTICS
Parameter Comparator Accuracy Threshold Voltage Compare Time PT Input Voltage Symbol VACOMP VTH tCOMP VIPT 0 64 0
(TA = -40C to +85C, VDD = +5.0 V 10%)
Test Conditions MIN. TYP. MAX. 100 VDD + 0.1 65 VDD Unit mV V tCYK V
DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA HOLDING CHARACTERISTICS (TA = -40 to +85C)
Parameter Data Hold Supply Voltage VDD Rise/Fall Time Symbol VDDDR tRVD, tFVD Test Conditions MIN. 2.5 200 MAX. 5.5 Unit V
s
DATA HOLDING TIMING
90% 10% VDDDR
tFVD
tRVD
AC TEST INPUT WAVEFORM (Except RESET, NMI, X1 and X2)
2.2 V Test Points 0.8 V tIF 0.8 V tIR 2.2 V
AC TEST INPUT WAVEFORM (RESET, NMI, X1 and X2)
0.8 VDD Test Points 0.8 V tIFS 0.8 V tIRS 0.8 VDD
AC TEST OUTPUT TEST POINTS Output load condition: 100 pF
2.2 V Test Points 0.8 V 0.8 V 2.2 V
53
PD70320
CLOCK TIMING
tCYX
0.8 VDD X1 0.8 V tWXH tXR tXF tWXL
tCYK
2.2 V CLKOUT 0.8 V tWKH tKR tKF tWKL
POLL INPUT TIMING
CLKOUT tSPLK tSPLK
POLL
CTS0 AND CTS1 INPUT TIMING
tWCTL
CTS0 and CTS1
54
PD70320
INTERRUPT INPUT/DMA INPUT TIMING
CLKOUT tWNIH tWNIL
NMI tSIQK tSIQK
Note tWIQH tWIQL
Note INTP0 to INTP2, DMARQ0 to DMARQ1 RESET INPUT TIMING When STOP mode is released/at power-on reset:
CLKOUTNote
tWRSL1
RESET
Note CLKOUT signal is output after CLKOUT output is set. When system is reset:
CLKOUTNote
tWRSL2
RESET
Note CLKOUT output is set to input port by RESET input.
55
PD70320
READY TIMING When 2 wait states are inserted:
T1
TAW
TAW
T2
MREQNote 1, IOSTBNote 2
tHCRY0 tSCRY0
READY
When (n - 2) extra wait states are inserted [n 3]:
T1
TAW
TAW
TW x (n - 2)
T2
MREQNote 1, IOSTBNote 2 tHCRY tHCRY1
tSCRY tSCRY0
READY
Notes 1. In case of memory cycle 2. In case of I/O cycle
56
PD70320
SERIAL OPERATION When transmitting data in I/O interface mode
tCYTK tWSTL tWSTH
SCK0 tDTKD tHTKD
TxD
When receiving data in I/O interface mode
tCYRK tWSRL tWSRH
CTS0
RxD
tSRDK tHKRD
57
PD70320
READ OPERATION
tCYK CLKOUT tDKA A19 to A0 tDADR D7 to D0 tDMRD R/ W tDAMR MREQ tWMRL tRVC tHMDR tHMA
tDMRMS MSTB
tDMSD
tDAMS IOSTB
tWMSL
REFRQ
DMAAK1 to DMAAK0
58
PD70320
WRITE OPERATION
tCYK CLKOUT tDKA A19 to A0 tDADW D7 to D0 tSDM R/ W tDAMR MREQ tWMRL tRVC tHMDW tHMA
tDMRMS MSTB
tDAMS IOSTB
tWMSL
REFRQ
DMAAK1 to DMAAK0
59
PD70320
I/O READ TIMING
tCYK CLKOUT tDKA A19 to A0 tDADR D7 to D0 tDISD R/W tHISDR tHISA
MREQ
MSTB
tDAIS IOSTB
tWISL
tRVC
REFRQ
DMAAK1 to DMAAK0
60
PD70320
I/O WRITE TIMING
tCYK CLKOUT tDKA A19 to A0 tDADW D7 to D0 tSDIS R/ W tHISDW tHISA
MREQ
MSTB
tDAIS IOSTB
tWISL
tRVC
REFRQ
DMAAK1 to DMAAK0
61
PD70320
DMA (I/O MEMORY) TIMING
tCYK CLKOUT tDKA A19 to A0
D7 to D0
R/ W tDAMR MREQ tWMRL tHMA
tDMRMS MSTB
tRVC
tDAMS IOSTB
tWMSL
tSDADQ DMARQ1 to DMARQ0 tHDADQ DMAAK1 to DMAAK0 tWDMRL TC1 to TC0
tDDATC
tWTCL
62
PD70320
DMA (MEMORY I/O) TIMING
tCYK CLKOUT tDKA A19 to A0
D7 to D0
R/W tDAMR MREQ tWMRL tHMA
tRVC MSTB
tDAMS IOSTB
tWMSL
tSDADQ DMARQ1 to DMARQ0 tHDADQ DMAAK1 to DMAAK0 tWDMWL TC1 to TC0
tDDATC
tWTCL
63
PD70320
REFRESH TIMING
tCYK CLKOUT tDKA A19 to A0
D7 to D0
R/W
MREQ
MSTB
IOSTB
tDARF REFRQ
tWRFL
tHRFA
tRVC DMAAK1 to DMAAK0
64
PD70320
HOLD REQUEST/ACKNOWLEDGE TIMING Normal mode
CLKOUT tSHQK HLDRQ tDKHA tWHQL tDHAC tCFHA HLDAK tWHAL tDHQHA tSHQK
Note
Releasing HOLD mode at refreshing time
CLKOUT tSHQK HLDRQ tWHQL Note tDKHA HLDAK tDHQC
Note A19 to A0, D7 to D0, MREQ, MSTB, IOSTB, R/W EXTERNAL INTERRUPT REQUEST/ACKNOWLEDGE TIMING
CLKOUT tSIRK INT tDKIA INTAK tWIAL D0 to D7 tRVC MREQ IOSTB tRVC tWIAH tDIAD tHIAD tHIAIQ
65
PD70320
4. CHARACTERISTIC CURVES
IDD1 vs fCLK (TA = 25C, VDD = 5 V) 140
120
Supply Current IDD1 (mA)
100
80
60
40
20
0
0
2
4
6
8
10
12
System Clock Frequency fCLK (MHz)
IDD2 vs fCLK (TA = 25C, VDD = 5 V) 70
60
Supply Current IDD2 (mA)
50
40
30
20
10
0
0
2
4
6
8
10
12
System Clock Frequency fCLK (MHz)
66
PD70320
IDD1 vs VDD 120 (TA = 25C)
100
Supply Current IDD1 (mA)
80
60
fCLK = 8 MHz fCLK = 5 MHz
40 fCLK = 2 MHz fCLK = 1 MHz 20 fCLK = 0.5 MHz 0 0 4 5 6
Supply Voltage VDD (V)
IDD2 vs VDD 50
(TA = 25C)
Supply Current IDD2 (mA)
40
30 fCLK = 8 MHz fCLK = 5 MHz fCLK = 1 MHz fCLK = 2 MHz fCLK = 0.5 MHz
20
10
0
0
4
5
6
Supply Voltage VDD (V)
67
PD70320
IOH vs VOH (TA = 25C, VDD = 5 V)
-3
Output Current IOH (mA)
-2
-1
0
0
0.2 0.4 Output Voltage VDD - VOH (V)
0.6
6
IOL vs VOL (TA = 25C, VDD = 5 V)
Output Current IOL (mA)
4
2
0
0
0.2 0.4 Output Voltage VOL (V)
0.6
68
PD70320
5. PACKAGE DRAWINGS
84 PIN PLASTIC QFJ ( 1150 mil)
A B
C F E U T K M N Q
M
G H
I
J
P84L-50A3-2 NOTE Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D E F G H I J K M N P Q T U MILLIMETERS 30.2 0.2 29.28 29.28 30.2 0.2 1.94 0.15 0.6 4.4 0.2 2.8 0.2 0.9 MIN. 3.4 1.27 (T.P.) 0.40 0.10 0.12 28.20 0.20 0.15 R 0.8 0.20+0.10 -0.05 INCHES 1.189 0.008 1.153 1.153 1.189 0.008 0.076+0.007 -0.006 0.024 0.173+0.009 -0.008 0.110 -0.008 0.035 MIN. 0.134 0.050 (T.P.) 0.016+0.004 -0.005 0.005 1.110 +0.009 -0.008 0.006 R 0.031 0.008+0.004 -0.002
+0.009
D
84 1
69
PD70320
94 PIN PLASTIC QFP ( 20)
A B
F2
71 72
48 47
detail of lead end
C D
S
94 1
24 23
F1
G1
G2 H I
M
J K
P
N
NOTE
L
ITEM A B C D F1 F2 G1 G2 H I J K L M N P Q R S MILLIMETERS 23.20.4 20.00.2 20.00.2 23.20.4 1.6 0.8 1.6 0.8 0.350.10 0.15 0.8 (T.P.) 1.60.2 0.80.2 0.15 +0.10 -0.05 0.10 3.7 0.10.1 55 4.0 MAX. INCHES 0.913 +0.017 -0.016 0.787 +0.009 -0.008 0.787 +0.009 -0.008 0.913 +0.017 -0.016 0.063 0.031 0.063 0.031 0.014 +0.004 -0.005 0.006 0.031 (T.P.) 0.0630.008 0.031 +0.009 -0.008 0.006 +0.004 -0.003 0.004 0.146 0.0040.004 55 0.158 MAX. S94GJ-80-5BG-3
Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition.
70
M
Q
R
PD70320
6. RECOMMENDED SOLDERING CONDITIONS
The following conditions must be met when soldering this product. For more details, refer to our document "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL" (C10535E). Please consult with our sales office when using other soldering process or under different soldering conditions. Table 6-1. Surface Mount Type Soldering Conditions (1) PD70320L : 84-pin plastic QFJ (1150 x 1150 mils)
PD70320L-8 : 84-pin plastic QFJ (1150 x 1150 mils)
Soldering Process VPS Soldering Conditions Package peak temperature: 215C, Reflow time: 40 seconds or less, Number of reflow processes: 1 Exposure limit: 2 daysNote (16 hours pre-baking is required at 125C afterwards) Pin temperature: 300C or below, Flow time: 3 seconds or less (per side of device) Symbol VP15-162-1
Partial heating method
--
Note Exposure limit before soldering after dry-pack package is opened. Storage conditions: 25C and relative humidity at 65% or less. (2) PD70320GJ-5BG : 94-pin plastic QFP (20 x 20 mm)
PD70320GJ-8-5BG : 94-pin plastic QFP (20 x 20 mm)
Soldering Process Infrared ray reflow Soldering Conditions Package peak temperature: 235C, Reflow time: 30 seconds or less, Number of reflow processes: 3 or less Exposure limit: 7 daysNote (36 hours pre-baking is required at 125C afterwards) Package peak temperature: 215C, Reflow time: 40 seconds or less, Number of reflow processes: 3 or less Exposure limit: 7 daysNote (36 hours pre-baking is required at 125C afterwards) Wave soldering Package peak temperature: 260C, Reflow time: 10 seconds or less, Number of reflow processes: 1 Pre-heating temperature: 120C max. (package surface temperature) Exposure limit: 7 daysNote (36 hours pre-baking is required at 125C afterwards) Pin temperature: 300C or below, Flow time: 3 seconds or less (per side of device) WS60-367-1 Symbol IR35-367-3
VPS
VP15-367-3
Partial heating method
--
Note Exposure limit before soldering after dry-pack package is opened. Storage conditions: 25C and relative humidity at 65% or less. Caution Use of more than one soldering process should be avoided (except for partial heating method).
71
PD70320
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
72
PD70320
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics (France) S.A. NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583
NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.1.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388
Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951
NEC do Brasil S.A.
Cumbica-Guarulhos-SP, Brasil Tel: 011-6465-6810 Fax: 011-6465-6829
J97. 8
73
PD70320
Related documents
V25, V35 User's Manual -- Hardware V25, V35 Family User's Manual -- Instructions
IEM-1220 U12120J (Japanese version)
The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. V20, V25, V30, and V35 are trademarks of NEC Corporation. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.
M4 96.5
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