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1M x 16-Bit Dynamic RAM 1k & 4k Refresh (Hyper Page Mode- EDO)
Advanced Information
* * *
HYB5116165BSJ -50/-60/-70 HYB5118165BSJ -50/-60/-70
1 048 576 words by 16-bit organization 0 to 70 C operating temperature Performance: -50 tRAC tCAC tAA tRC tHPC RAS access time CAS access time Access time from address Read/Write cycle time Hyper page mode (EDO) cycle time 50 13 25 84 20 -60 60 15 30 104 25 -70 70 20 35 124 30 ns ns ns ns ns
* *
* * * * * * *
Single + 5 V ( 10 %) supply Low power dissipation max. 1100 active mW ( HYB5118165BSJ-50) max. 990 active mW ( HYB5118165BSJ-60) max. 880 active mW ( HYB5118165BSJ-70) max. 550 active mW ( HYB5116165BSJ-50) max. 495 active mW ( HYB5116165BSJ-60) max. 440 active mW ( HYB5116165BSJ-70) 11 mW standby (TTL) 5.5. mW standby (MOS) Output unlatched at cycle end allows two-dimensional chip selection Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh and Self Refresh Hyper page mode (EDO) capability All inputs, outputs and clocks fully TTL-compatible 1024 refresh cycles / 16 ms for HYB5118165BSJ (1k-Refresh) 4096 refresh cycles / 64 ms for HYB5116165BSJ (4k-Refresh) Plastic Package: P-SOJ-42-1 400 mil
Semiconductor Group
1
1.96
HYB 5116(8)165BSJ-50/-60/-70 1M x 16-EDO DRAM
The HYB 5116(8)165BSJ is a 16 MBit dynamic RAM organized as 1 048 576 words by 16-bits. The HYB 5116(8)165BSJ utilizes a submicron CMOS silicon gate process technology, as well as advanced circuit techniques to provide wide operating margins, both internally and for the system user. Multiplexed address inputs permit the HYB 5116(8)165BSJ to be packaged in a standard SOJ 42 plastic package with 400 mil width. These packages provide high system bit densities and are compatible with commonly used automatic testing and insertion equipment. System-oriented features include single + 5 V ( 10 %) power supply, direct interfacing with high-performance logic device families such as Schottky TTL. Ordering Information Type HYB 5116165BJ-50 HYB 5116165BJ-60 HYB 5116165BJ-70 HYB 5118165BJ-50 HYB 5118165BJ-60 HYB 5118165BJ-70 Pin Names A0-A9 A0-A9 A0-A11 A0 to A7 RAS OE I/O1-I/O16 UCAS LCAS WE Row Address Inputs for HYB5118165BSJ Column Address Inputs for HYB5118165BSJ Row Address Inputs for HYB5116165BSJ Column Address Inputs for HYB5116165BSJ Row Address Strobe Output Enable Data Input/Output Upper Column Address Strobe Lower Column Address Strobe Read/Write Input Power Supply (+ 5 V) Ground (0 V) not connected Ordering Code on request on request on request Q67100-Q1107 Q67100-Q1108 Q67100-Q1109 Package P-SOJ-42-1 400 mil P-SOJ-42-1 400 mil P-SOJ-42-1 400 mill P-SOJ-42-1 400 mil P-SOJ-42-1 400 mil P-SOJ-42-1 400 mil Descriptions DRAM (access time 50 ns) DRAM (access time 60 ns) DRAM (access time 70 ns) DRAM (access time 50 ns) DRAM (access time 60 ns) DRAM (access time 70 ns)
VCC VSS
N.C.
Semiconductor Group
2
HYB 5116(8)165BSJ-50/-60/-70 1M x 16-EDO DRAM
P-SOJ-42-1
400 mil
Vcc I/O1 I/O2 I/O3 I/O4 Vcc I/O5 I/O6 I/O7 I/O8 N.C. N.C. WE RAS N.C. N.C. A0 A1 A2 A3 Vcc
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 HYB3118165BSJ
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
Vss I/O16 I/O15 I/O14 I/O13 Vss I/O12 I/O11 I/O10 I/O9 N.C. LCAS UCAS OE A9 A8 A7 A6 A5 A4 Vss
Vcc I/O1 I/O2 I/O3 I/O4 Vcc I/O5 I/O6 I/O7 I/O8 N.C. N.C. WE RAS A11 A10 A0 A1 A2 A3 Vcc
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 HYB3116165BSJ
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
Vss I/O16 I/O15 I/O14 I/O13 Vss I/O12 I/O11 I/O10 I/O9 N.C. LCAS UCAS OE A9 A8 A7 A6 A5 A4 Vss
Pin Configuration
Semiconductor Group
3
HYB 5116(8)165BSJ-50/-60/-70 1M x 16-EDO DRAM
I/O1 I/O2
I/O16
WE UCAS LCAS
. .
&
Data in Buffer
No. 2 Clock Generator 16
Data out Buffer
16
OE
8
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11
12
Column Address Buffer(8)
8
Column Decoder
Refresh Controller
Sense Amplifier I/O Gating
16
Refresh Counter (12) 12 Row
256 x16
Address Buffers(12)
12
Decoder 4096
Row
Memory Array 4096x256x16
RAS
No. 1 Clock
Generator
Voltage Down Generator
VCC VCC (internal)
Block Diagram for HYB 5116165BSJ
Semiconductor Group
4
HYB 5116(8)165BSJ-50/-60/-70 1M x 16-EDO DRAM
I/O1 I/O2
I/O16
WE UCAS LCAS
. .
&
Data in Buffer
No. 2 Clock Generator 16
Data out Buffer
16
OE
10
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
Column Address Buffer(10)
10
Column Decoder
Refresh Controller
Sense Amplifier I/O Gating
16
Refresh Counter (10) 10 Row 10
1024 x16
Address Buffers(10)
10
Decoder 1024
Row
Memory Array 1024x1024x16
RAS
No. 1 Clock
Generator
Voltage Down Generator
VCC VCC (internal)
Block Diagram for HYB 5118165BSJ
Semiconductor Group
5
HYB 5116(8)165BSJ-50/-60/-70 1M x 16-EDO DRAM
Absolute Maximum Ratings Operating temperature range ............................................................................................0 to 70 C Storage temperature range.........................................................................................- 55 to 150 C Input/output voltage ................................................................................-0.5 to min (Vcc+0.5,7.0) V Power supply voltage...................................................................................................-1.0V to 7.0 V Power dissipation..................................................................................................................... 1.0 W Data out current (short circuit) ................................................................................................ 50 mA Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC Characteristics( note : values in brackets for HYB5118165BSJ) TA = 0 to 70 C, VSS = 0 V, VCC = 5 V 10 %; tT = 2 ns Parameter Input high voltage Input low voltage Output high voltage (IOUT = - 5 mA) Output low voltage (IOUT = 4.2 mA) Input leakage current (0 V VIH Vcc + 0.3V, all other pins = 0 V) Output leakage current (DO is disabled, 0 V VOUT Vcc + 0.3V) Average VCC supply current: -50 ns version -60 ns version -70 ns version (RAS, CAS, address cycling: tRC = tRC min.) Symbol Limit Values min. max. Vcc+0.5 0.8 - 0.4 10 10 2.4 - 0.5 2.4 - - 10 - 10 Unit Test Condition V V V V A A 1) 1) 1) 1) 1) 1)
VIH VIL VOH VOL II(L) IO(L) ICC1
- - - - - - -
100(200) mA 90 (180) mA 80 (160) mA 2 mA
2) 3) 4)
Standby VCC supply current (RAS = CAS = VIH) ICC2
Average VCC supply current, during RAS-only refresh cycles: -50 ns version -60 ns version -70 ns version (RAS cycling, CAS = VIH, tRC = tRC min.)
-
2) 4)
ICC3
100(200) mA 90 (180) mA 80 (160) mA
Semiconductor Group
6
HYB 5116(8)165BSJ-50/-60/-70 1M x 16-EDO DRAM
DC Characteristics( note : values in brackets for HYB5118165BSJ) TA = 0 to 70 C, VSS = 0 V, VCC = 5 V 10 %; tT = 2 ns Parameter Symbol Limit Values min. Average VCC supply current, ICC4 during hyper page mode: -50 ns version -60 ns version -70 ns version (RAS = VIL, CAS, address cycling:tPC = tPC min.) - - - - max. 70 (90) 55 (75) 45 (60) 1 Unit Test Condition mA mA mA mA
2) 3) 4)
Standby VCC supply current (RAS = CAS = VCC - 0.2 V)
Average VCC supply current, during CASbefore-RAS refresh mode: -50 ns version -60 ns version -70 ns version (RAS, CAS cycling: tRC = tRC min.)
ICC5 ICC6
1)
- - -
100(200) mA 90 (180) mA 80 (160) mA 1 mA
2) 4)
Average Self Refresh Current
(CBR cycle with tRAS>TRASSmin., CAS held low, WE=Vcc-0.2V, Address and Din=Vcc - 0.2V or 0.2V)
ICC7
_
Capacitance TA = 0 to 70 C,VCC = 5 V 10 %, f = 1 MHz Parameter Input capacitance (A0 to A11) Input capacitance (RAS, UCAS, LCAS, WE, OE) I/O capacitance (I/O1-I/O16) Symbol Limit Values min. max. 5 7 7 pF pF pF - - - Unit
CI1 CI2 CIO
Semiconductor Group
7
HYB 5116(8)165BSJ-50/-60/-70 1M x 16-EDO DRAM
AC Characteristics 5)6) TA = 0 to 70 C,VCC = 5 V 10 %, tT = 2 ns Parameter
Symbol
16E
Limit Values -50 min. -60 -70 max. - - 10k 10k - - - - 53 35 - - - 50 64 16 max. min. - - 10k 10k - - - - 37 25 104 40 60 10 0 10 0 10 14 12 15 50 - 50 64 16 5 1 - - max. min. - - 10k 10k - - - - 45 30 - - - 50 64 16 124 50 70 12 0 10 0 12 14 12 17 60 5 1 - -
Unit Note
common parameters
Random read or write cycle time RAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay RAS hold time CAS hold time CAS to RAS precharge time Transition time (rise and fall) Refresh period for HYB5116165 Refresh period for HYB5118165 tRC tRP tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tT tREF tREF 84 30 50 8 0 8 0 8 12 10 13 40 5 1 - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms 7
Read Cycle
Access time from RAS Access time from CAS OE access time Read command setup time Read command hold time Read command hold time referenced to RAS CAS to output in low-Z Output buffer turn-off delay tRAC tCAC tOEA tRCS tRCH tRRH tCLZ tOFF - - - - 25 0 0 0 0 0 50 13 25 13 - - - - - 13 - - - - 30 0 0 0 0 0 60 15 30 15 - - - - - 15 - - - - 35 0 0 0 0 0 70 17 35 17 - - - - - 17 ns ns ns ns ns ns ns ns ns ns 11 11 8 12 8, 9 8, 9 8,10
Access time from column address tAA Column address to RAS lead time tRAL
Semiconductor Group
8
HYB 5116(8)165BSJ-50/-60/-70 1M x 16-EDO DRAM
AC Characteristics (cont'd) 5)6) TA = 0 to 70 C,VCC = 5 V 10 %, tT = 2 ns Parameter
Symbol
16E
Limit Values -50 min. -60 0 0 0 13 13 15 - - - - 0 0 0 15 15 -70 max. 17 - - - - max. min. 13 - - - - max. min.
Unit Note
Output turn-off delay from OE Data to CAS low delay Data to OE low delay CAS high to data delay OE high to data delay
tOEZ tDZC tDZO tCDD tODD
0 0 0 10 10
ns ns ns ns ns
12 13 13 14 14
Write Cycle
Write command hold time Write command pulse width Write command setup time tWCH tWP tWCS 8 8 0 13 13 0 8 - - - - - - - 10 10 0 15 15 0 10 - - - - - - - 10 10 0 17 17 0 12 - - - - - - - ns ns ns ns ns ns ns 16 16 15
Write command to RAS lead time tRWL Write command to CAS lead time tCWL Data setup time Data hold time tDS tDH
Read-modify-Write Cycle
Read-write cycle time RAS to WE delay time CAS to WE delay time OE command hold time tRWC tRWD tCWD tOEH 113 64 27 39 10 - - - - - 138 77 32 47 13 - - - - - 162 89 36 54 15 - - - - - ns ns ns ns ns 15 15 15
Column address to WE delay time tAWD
Hyper Page Mode (EDO) Cycle
Hyper page mode (EDO) cycle time CAS precharge time Access time from CAS precharge Output data hold time RAS pulse width in EDO mode CAS precharge to RAS Delay tHPC tCP tCPA tCOH tRAS tRHPC 20 8 - 5 50 27 - - 27 - - 25 10 - 5 32 - - 32 - - 30 10 - 5 37 - - 37 - - ns ns ns ns ns 7
200k 60
200k 70
200k ns
Semiconductor Group
9
HYB 5116(8)165BSJ-50/-60/-70 1M x 16-EDO DRAM
AC Characteristics (cont'd) 5)6) TA = 0 to 70 C,VCC = 5 V 10 %, tT = 2 ns Parameter
Symbol
16E
Limit Values -50 min. -60 -70 max. max. min. max. min.
Unit Note
Hyper Page Mode (EDO) Read-modify-Write Cycle
Hyper page mode (EDO) readwrite cycle time CAS precharge to WE tPRWC tCPWD 58 41 - - 68 49 - - 77 56 - - ns ns
CAS-before-RAS Refresh Cycle
CAS setup time CAS hold time RAS to CAS precharge time Write to RAS precharge time tCSR tCHR tRPC tWRP 10 10 5 10 10 - - - - - 10 10 5 10 10 - - - - - 10 10 5 10 10 - - - - - ns ns ns ns ns
Write hold time referenced to RAS tWRH
CAS-before-RAS Counter Test Cycle
CAS precharge time tCPT 35 - 40 - 40 - ns
Self Refresh Cycle
RAS pulse width RAS precharge CAS hold time tRASS tRPS tCHS 100k _ 95 -50 _ _ 100k _ 110 -50 _ _ 100k _ 130 -50 _ _ ns ns ns 17 17 17
Semiconductor Group
10
HYB 5116(8)165BSJ-50/-60/-70 1M x 16-EDO DRAM
Notes:
1) All voltages are referenced to VSS. 2) ICC1, ICC3, ICC4 and ICC6 depend on cycle rate. 3) ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open. 4) Address can be changed once or less while RAS = Vil. In case of ICC4 it can be changed once or less during a hyper page mode (EDO) cycle 5) An initial pause of 200 s is required after power-up followed by 8 RAS cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using the internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 6) AC measurements assume tT = 2 ns. 7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also measured between VIH and VIL. 8) Measured with the specified current load and 100 pF at Vol = 0.8 V and Voh = 2.0 V. Access time is determined by the latter of tRAC, tCAC, tAA,tCPA, tOEA . tCAC is measured from tristate. 9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC. 10) Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA. 11) Either tRCH or tRRH must be satisfied for a read cycle. 12) tOFF (max.), tOEZ (max.) define the time at which the output achieves the open-circuit conditions and are not referenced to output voltage levels. tOFF is referenced from the rising edge of RAS or CAS, whichever occurs last. 13) Either tDZC or tDZO must be satisfied. 14) Either tCDD or tODD must be satisfied. 15) tWCS, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and data out pin will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD (min.) and tAWD > tAWD (min.), the cycle is a read-write cycle and I/O will contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition of I/O (at access time) is indeterminate. 16) These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge in read-write cycles. 17)When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM operation: If row addresses are being refreshed on an evenly distributed manner over the refresh interval using CBR refresh cycles, then only one CBR cycle must be performed immediately after exit from Self Refresh. If row addresses are being refreshed in any other manner (ROR - Distributed/Burst; or CBR-Burst) over the refresh interval, then a full set of row refreshes must be performed immediately before entry to and immediately after exit from Self Refresh
Semiconductor Group
11
HYB 5116(8)165BSJ-50/-60/-70 1M x 16-EDO DRAM
Semiconductor Group
12
HYB 5116(8)165BSJ-50/-60/-70 1M x 16-EDO DRAM
tRC tRAS
V
tRP
RAS
IH
VIL
tCSH tRCD tRSH tCAS tRAL
tCRP
V
IH
UCAS LCAS
VIL
tRAD tASR tASC tCAH
Column
tASR
Row
V
Address
IH
VIL
Row
tRCH tRAH tRCS tRRH tAA tOEA
V
WE
IH
VIL
V
OE
IH
VIL
tDZC tDZO tODD tCAC tCLZ
Hi Z
tCDD
I/O (Inputs)
V
IH
VIL
tOFF tOEZ
Valid Data Out Hi Z
I/O (Outputs) V
V OH OL
tRAC
"H" or "L"
WL1
Read Cycle
Semiconductor Group
13
HYB 5116(8)165BSJ-50/-60/-70 1M x 16-EDO DRAM
tRC tRAS
V
tRP
RAS
IH
VIL
tCSH tRCD tRSH tCAS tRAL tCAH
Column
tCRP
V IH
UCAS LCAS
VIL
tRAD tASR tASC
tASR
Row
Address
V IH VIL
.
Row
tRAH
V
tWCS t WP
tCWL
WE
IH
VIL
tWCH tRWL
OE
V IH VIL
tDS
I/O (Inputs)
V IH VIL
tDH
Valid Data In
OH I/O (Outputs) V OL
V
Hi Z
"H" or "L"
WL2
Write Cycle (Early Write)
Semiconductor Group
14
HYB 5116(8)165BSJ-50/-60/-70 1M x 16-EDO DRAM
tRC tRAS
V
tRP
RAS
IH
VIL
tCSH tRCD tRSH tCAS tRAL
tCRP
V
IH
UCAS LCAS
VIL
tRAD tASR tASC tCAH
Column
tASR
. Row
V
IH
Address V IL
Row
tRAH
V
WE
IH
tCWL tRWL tWP
VIL
tOEH
V
OE
IH
VIL
tDZO tDZC
I/O (Inputs)
V IH VIL
tODD tDS tOEZ tCLZ tOEA
tDH
Valid Data
OH I/O (Outputs) V OL
V
Hi-Z
Hi-Z
"H" or "L"
WL3
Write Cycle (OE Controlled Write)
Semiconductor Group
15
HYB 5116(8)165BSJ-50/-60/-70 1M x 16-EDO DRAM
tRWC tRAS
V IH VIL V IH
tRP
RAS
tCSH tRCD tRSH tCAS tCRP
CAS
VIL
tRAH tASR
V
tCAH tASC
Column
tASR
Row
Address
IH
VIL
Row
tRAD
V
tAWD tCWD tRWD
tCWL tRWL tWP
IH
WE
VIL
tAA tRCS
V IH
tOEA
tOEH
OE
VIL
tDZO tDZC
I/O (Inputs)
V IH VIL
tDS tDH
Valid Data in
tCLZ tCAC
tODD tOEZ
Data Out
I/O (Outputs) V OL
V OH
tRAC
"H" or "L"
WL4
Read-Write (Read-Modify-Write) Cycle
Semiconductor Group
16
HYB 5116(8)165BSJ-50/-60/-70 1M x 16-EDO DRAM
tRAS
V
tRP tRHCP tRSH tCRP
RAS
IH
tRCD
VIL
tHPC tCRP
V IH
tCAS
tCP
tCAS
tCAS
UCAS LCAS
VIL
tCSH tASR tRAH tASC
Row
tRAL tCAH tASC tCAH
Column 2
tASC tCAH
Column N
Address
V IH VIL Column 1
tRAD tRRH tRCH
tRCS
WE
VIH VIL
tOES
V
tCAC tAA tCPA
tCAC tAA tCPA
tOFF
OE
OH OL
tOEA tRAC tAA tCAC
V
tOEZ tCOH tCOH
Data Out 2 Data Out N
I/O IH (Output) V IL
V
tCLZ
Data Out 1
"H" or "L"
WL5
Hyper Page Mode (EDO) Read Cycle
Semiconductor Group
17
HYB 5116(8)165BSJ-50/-60/-70 1M x 16-EDO DRAM
tRAS
V IH
tRP tRHCP tRSH tCRP
tRCD
RAS
VIL
tHPC tCRP
V IH
tCAS
tCP
tCAS
tCAS
UCAS LCAS
VIL
tCSH tASR tRAH tASC
Row Addr
tRAL tCAH tASC tCAH
Column 2
tASC tCAH
Column N
V
Address
IH
VIL
Column 1
tRAD tCWL tWCS
VIH VIL
tCWL tWCH tWP tWCS
tRWL tCWL tWCH tWP
tWCH tWCS tWP
WE
V
OE
OH OL
V
tDS
V IH
tDH
tDS
tDH
tDS
tDH
I/O (Input) V IL
Data In 1
Data In 2
Data In N
"H" or "L"
WL8
Hyper Page Mode (EDO) Early Write Cycle
Semiconductor Group
18
tRASP tRP tPRWC tCP tCAS tCAS tCAH tASC tASC
Column Row Column
V
RAS
IH
V IL
tCSH tRCD tCAS tRAL tCRP tRSH
Semiconductor Group
V
UCAS LCAS
IH
V IL
tRAD tCAH tASC
Column
tASR
tRAH
tCAH
tASR
V
Address
IH
V IL
Row
V
tRCS tAWD tOEA tOEA tWP tWP tOEA tAWD tAWD
tRWD tCWD tCWL tCWL
tCPWD tCWD
tCPWD tCWD
tRWL tCWL
WE
IH
Hyper Page Mode (EDO) Late Write and Read-Modify Write Cycle
19
V IL
tAA
tWP
V
IH
OE
V IL
tCPA tDZC
Data In
tCPA tODD
Data In
V
IH
tDZC tCLZ tDZO tCLZ tCAC tRAC tOEZ tDH tDS
Data Out Data Out
tDZC tCLZ tOEH
tODD
Data In
I/O (Inputs) V IL
tODD tAA
tOEH tOEZ tDS tDH
tOEH tCAC tAA tDS
Data Out
tDH
OH I/O (Outputs) V
V
OL
HYB 5116(8)165BSJ-50/-60/-70 1M x 16-EDO DRAM
WL17
HYB 5116(8)165BSJ-50/-60/-70 1M x 16-EDO DRAM
tRC tRAS
RAS
V IH VIL
tRP
tCRP tRPC
UCAS LCAS
V IH VIL
tRAH tASR
tASR
Row
V
Address
IH
VIL
Row
OH I/O (Outputs) V OL
V
HI-Z
"H" or "L"
WL9
RAS-Only Refresh Cycle
Semiconductor Group
20
HYB 5116(8)165BSJ-50/-60/-70 1M x 16-EDO DRAM
tRC tRP
V
tRAS
tRP
RAS
IH
VIL
tRPC tCP
tCSR tCHR tRPC
tCRP
UCAS LCAS
V IH VIL
tWRP tWRH
V IH
WE
VIL
tOEZ
V
OE
IH
VIL
tCDD
I/O (Inputs)
V IH
VIL
tODD
OH I/O (Outputs)VOL V
HI-Z
tOFF
"H" or "L"
WL10
CAS-Before-RAS Refresh Cycle
Semiconductor Group
21
HYB 5116(8)165BSJ-50/-60/-70 1M x 16-EDO DRAM
tRC
V
tRC tRP tRAS tRP
tRAS
IH
RAS
VIL
tRCD
V
tRSH tCHR tCRP
UCAS LCAS
IH
VIL
tRAD tASC tASR tRAH
Row
tWRP tCAH tWRH tASR
Row
V
Address
IH
VIL
Column
tRCS
V
tRRH
WE
IH
VIL
tAA tOEA
V
OE
IH
VIL
tDZC tDZO
tCDD tODD tCAC tCLZ
V
I/O (Inputs)
IH
VIL
tOFF tOEZ
Valid Data Out HI-Z
tRAC
OH I/O (Outputs) V OL V
"H" or "L"
WL11
Hidden Refresh Cycle (Read)
Semiconductor Group
22
HYB 5116(8)165BSJ-50/-60/-70 1M x 16-EDO DRAM
tRC tRP
V IH
tRC tRP tRAS
tRAS
RAS
VIL
tRCD
V IH
tRSH
tCHR
tCRP
UCAS LCAS
VIL
tRAD tRAH tASR tASC tCAH
Column
tASR
Row
V
Address
IH
VIL
Row
tWCS
tWCH tWP
tWRP
tWRH
V
WE
IH
VIL
tDS
V
tDH
Valid Data
I/O (Input)
IH
V IL
OH I/O (Output) V OL
V
HI-Z
"H" or "L"
WL12
Hidden Refresh Cycle (Early Write)
Semiconductor Group
23
HYB 5116(8)165BSJ-50/-60/-70 1M x 16-EDO DRAM
tRP
RAS
V IH VIL
tRASS
tRPS
tRPC tCSR
V
tCHS
tCRP
tCP
IH
UCAS LCAS
VIL
tWRP tWRH
V
WE
IH
VIL
OE
V IH VIL
tCDD
I/O (Inputs)
V IH
VIL
tODD tOEZ
OH I/O (Outputs) V OL
V
HI-Z
tOFF
"H" or "L"
WL13
CAS before RAS Self Refresh Cycle
Semiconductor Group
24
HYB 5116(8)165BSJ-50/-60/-70 1M x 16-EDO DRAM
tRAS
Read Cycle:
RAS
V IH V IL
tRP
tCSR
UCAS LCAS
V IH V IL
tCHR
tCP
tRSH tCAS tRAL
tASC
Address
V IH V IL
tCAH tAA tCAC
tASR
Row
Column
tWRP
WE
V IH V IL V IH V IL V IH V IL VOH VOL
tRRH tOEA tCDD tOFF tOEZ
Data Out
tRCH
tWRH
tRCS tDZC tDZO tCLZ
OE I/O (Inputs)
tODD
I/O (Outputs)
tWRP
Write Cycle:
WE
V IH V IL
tWCS
tRWL tCWL tWCH
tWRH
OE
V IH V IL
tDS
I/O (Inputs) I/O (Outputs)
V IH V IL V IH V IL
tDH
Data In
HI-Z
CAS-Before-RAS Refresh Counter Test Cycle
Semiconductor Group
25
HYB 5116(8)165BSJ-50/-60/-70 1M x 16-EDO DRAM
Plastic Package P-SOJ-42 (400 mil) (Small Outline J-lead, SMD)
1)
10.3
-0.3
B
1.27 0.43
0.81 max. 9.4 0.18 A 42x 0.08 11.2
+ 0.1 -
+ - 0.25
+ 0.15 -
0.18
B
25.4
42
22
GPJ05853
1
1)
21
27.43
-0.25
A
Index marking
1) does not include plastic or metal protusion of 0.15 max per side
Semiconductor Group
26

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