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256k x 16-Bit EDO-DRAM
HYB 514175BJ-50/-55/-60
Advanced Information * * * * 262 144 words by 16-bit organization 0 to 70 C operating temperature Fast access and cycle time RAS access time: 50 ns (-50 version) 55 ns (-55 version) 60 ns (-60 version) CAS access time: 13 ns (-50 & -55 version) 15 ns (-60 version) Cycle time: 89 ns (-50 version) 94 ns (-55 version) 104 ns (-60 version) Hyper page mode (EDO) cycle time 20 ns (-50 & -55 version) 25 ns (-60 version) High data rate 50 MHz (-50 & -55 version) 40 MHz (-60 version) Single + 5 V ( 10 %) supply with a built-in VBB generator * Low Power dissipation max. 1100 mW active (-50 version) max. 1045 mW active (-55 version) max. 935 mW active (-60 version) * Standby power dissipation 11 mW standby (TTL) 5.5 mW max. standby (CMOS) * Output unlatched at cycle end allows two-dimensional chip selection * Read, write, read-modify write, CAS-before-RAS refresh, RAS-only refresh, hidden-refresh and hyper page (EDO) mode capability * 2 CAS/1 WE control * All inputs and outputs TTL-compatible * 512 refresh cycles/16 ms * Plastic Packages: P-SOJ-40-1 400 mil width
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Semiconductor Group
1
1998-10-01
HYB 514175BJ/BJL-50/-55/-60 256k x 16 EDO-DRAM
The HYB 514175BJ is the new generation dynamic RAM organized as 262 144 words by 16-bit. The HYB 514175BJ utilizes CMOS silicon gate process as well as advanced circuit techniques to provide wide operation margins, both internally and for the system user. Multiplexed address inputs permit the HYB 514175BJ to be packed in a standard plastic 400 mil wide P-SOJ-40-1 package. This package size provides high system bit densities and is compatible with commonly used automatic testing and insertion equipment. System oriented features include single + 5 V ( 10 %) power supply, direct interfacing with high performance logic device families such as Schottky TTL. Ordering Information Type HYB 514175BJ-50 HYB 514175BJ-55 HYB 514175BJ-60 Truth Table RAS H L L L L L L L L LCAS H H L H L L H L L UCAS H H H L L H L L L WE H H H H H L L L H OE H H L L L H H H H I/O1 - I/O8 High-Z High-Z Dout High-Z Dout Din Don't care Din High-Z I/O9 - I/O16 High-Z High-Z High-Z Dout Dout Don't care Din Din High-Z Operation Standby Refresh Lower byte read Upper byte read Word read Lower byte write Upper byte write Word write - Ordering Code Q67100-Q2072 Q67100-Q2100 Q67100-Q2073 Package P-SOJ-40-1 400 mil P-SOJ-40-1 400 mil P-SOJ-40-1 400 mil Description 50 ns 256k x 16 EDO-DRAM 55 ns 256k x 16 EDO-DRAM 60 ns 256k x 16 EDO-DRAM
Pin Names A0 - A8 RAS UCAS, LCAS WE OE I/O1 -I/O16 Address Inputs Row Address Strobe Column Address Strobe Read/Write Input Output Enable Data Input/Output Power Supply (+ 5 V) Ground (0 V) No Connection
VCC VSS
N.C.
Semiconductor Group
2
1998-10-01
HYB 514175BJ-50/-55/-60 256k x 16 EDO-DRAM
P-SOJ-40-1
V CC I/O1 I/O2 I/O3 I/O4 V CC I/O5 I/O6 I/O7 I/O8 N.C. N.C. WE RAS N.C. A0 A1 A2 A3 V CC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 V SS 39 I/O16 38 I/O15 37 I/O14 36 I/O13 35 V SS 34 I/O12 33 I/O11 32 I/O10 31 I/O9 30 N.C. 29 LCAS 28 UCAS 27 OE 26 A8 25 A7 24 A6 23 A5 22 A4 21 V SS
SPP02811
Pin Configuration (top view)
Semiconductor Group
3
1998-10-01
HYB 514175BJ/BJL-50/-55/-60 256k x 16 EDO-DRAM
I/O1 I/O2 . . . I/O16 . . ..
Data In Buffer WE UCAS LCAS & 16
Data Out Buffer 16
OE
No.2 Clock Generator
9
Column Address Buffers (9)
9
A0 A1 A2 A3 A4 A5 A6 A7 A8 9 Refresh Counter (9) 9 Row Address Buffers (9) 9 Row Decoder . . . 512 . . . Refresh Controller
Column Decoder
Sense Amplifier I/O Gating 512 x 16
16
Memory Array 512 x 512 x 16
. . .
. . .
RAS
No.1 Clock Generator Substrate Bias Generator
V CC V SS
SPB02827
Block Diagram
Semiconductor Group
4
1998-10-01
HYB 514175BJ-50/-55/-60 256k x 16 EDO-DRAM
Absolute Maximum Ratings Operating temperature range ....................................................................................... 0 to + 70 C Storage temperature range.................................................................................... - 55 to + 150 C Input/output voltage ....................................................................................................... - 1 to + 6 V Power supply voltage..................................................................................................... - 1 to + 6 V Data out current (short circuit) ............................................................................................... 50 mA
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC Characteristics TA = 0 to 70 C; VSS = 0 V; VCC = 5 V 10 %, tT = 2 ns Parameter Input high voltage Input low voltage Output high voltage (IOUT = - 5.0 mA) Output low voltage (IOUT = 4.2 mA) Input leakage current, any input (0 V < VIN < 7 V, all other inputs = 0 V) Output leakage current (DO is disabled, 0 V < VOUT < VCC) Average VCC supply current -50 version -55 version -60 version Standby VCC supply current (RAS = LCAS = UCAS = WE = VIH) Average VCC supply current during RAS-only refresh cycles -50 version -55 version -60 version Average VCC supply current during hyper page mode (EDO) operation -50 version -55 version -60 version Symbol Limit Values min. max. 0.8 - 0.4 10 10 2.4 - 1.0 2.4 - - 10 - 10 - 200 190 170 mA
2, 3, 4
Unit Test Condition
1 1 1 1 1
VIH VIL VOH VOL II(L) IO(L) ICC1
VCC + 0.5 V
V V V A A
1
ICC2 ICC3
- -
2
mA
200 190 170
mA
2, 4
ICC4
- 190 180 170 mA
2, 3, 4
Semiconductor Group
5
1998-10-01
HYB 514175BJ/BJL-50/-55/-60 256k x 16 EDO-DRAM
DC Characteristics (cont'd) TA = 0 to 70 C; VSS = 0 V; VCC = 5 V 10 %, tT = 2 ns Parameter Standby VCC supply current (RAS = LCAS = UCAS = WE = VCC - 0.2 V) Average VCC supply current during CAS-before-RAS refresh mode -50 version -55 version -60 version Capacitance TA = 0 to 70 C; VCC = 5 V 10 %, f = 1 MHz Parameter Input capacitance (A0 to A8) Input capacitance (RAS, UCAS, LCAS, WE, OE) Output capacitance (l/O1 to l/O16) Symbol Limit Values min. max. 5 7 7 pF pF pF - - - Unit Symbol Limit Values min. max. 1 - - 200 190 170 mA Unit Test Condition mA
1
ICC5 ICC6
2, 4
CI1 CI2 CIO
AC Characteristics 5, 6 TA = 0 to 70 C; VSS = 0 V; VCC = 5 V 10 %, tT = 2 ns Parameter Symbol -50 Limit Values -55 -60 min. max. min. max. min. max. Common Parameters Random read or write cycle time RAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time Unit Note
tRC tRP tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD
89 35 50 8 0 8 0 8 12 10
- - 10k 10k - - - - 37 25
94 35 55 8 0 8 0 8 12 10
- - 10k 10k - - - - 43 30
104 40 60 10 0 10 0 10 14 12
- - 10k 10k - - - - 45 30
ns ns ns ns ns ns ns ns ns ns
Semiconductor Group
6
1998-10-01
HYB 514175BJ-50/-55/-60 256k x 16 EDO-DRAM
AC Characteristics (cont'd)5, 6 TA = 0 to 70 C; VSS = 0 V; VCC = 5 V 10 %, tT = 2 ns Parameter Symbol -50 RAS hold time CAS hold time CAS to RAS precharge time Transition time (rise and fall) Refresh period Read Cycle Access time from RAS Access time from CAS Access time from column address OE access time Column address to RAS lead time Read command setup time Read command hold time CAS to output in low-Z Output buffer turn-off delay from OE Data to OE low delay CAS high to data delay OE high to data delay Write Cycle Write command hold time Write command pulse width Write command setup time Write command to RAS lead time Write command to CAS lead time Data setup time Data hold time Data to CAS low delay Limit Values -55 13 45 5 1 - - - - 50 16 15 50 5 1 - -60 - - - 50 16 ns ns ns ns ms
7
Unit Note
min. max. min. max. min. max.
tRSH tCSH tCRP tT tREF
13 40 5 1 -
- - - 50 16
tRAC tCAC tAA tOEA tRAL tRCS tRCH tCLZ tOEZ tDZO tCDD tODD
- - - - 25 0 0 0 0 0 0 0 10 10
50 13 25 13 - - - - - 13 13 - - -
- - - - 25 0 0 0 0 0 0 0 10 10
55 13 25 13 - - - - - 13 13 - - -
- - - - 30 0 0 0 0 0 0 0 13 13
60 15 30 15 - - - - - 15 15 - - -
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
8, 9 8, 9 8, 10
11 11 8 12 12 13 14 14
Read command hold time ref. to RAS tRRH Output buffer turn-off delay from CAS tOFF
tWCH tWP tWCS tRWL tCWL tDS tDH tDZC
8 8 0 13 13 0 8 0
- - - - - - - -
8 8 0 13 13 0 8 0
- - - - - - - -
10 10 0 15 15 0 10 0
- - - - - - - -
ns ns ns ns ns ns ns ns
16 16 13 15
Semiconductor Group
7
1998-10-01
HYB 514175BJ/BJL-50/-55/-60 256k x 16 EDO-DRAM
AC Characteristics (cont'd)5, 6 TA = 0 to 70 C; VSS = 0 V; VCC = 5 V 10 %, tT = 2 ns Parameter Symbol -50 Limit Values -55 -60 min. max. min. max. min. max. Read-Modify-Write Cycle Read-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time OE command hold time Hyper Page Mode (EDO) Cycle Hyper page mode cycle time CAS precharge time Access time from CAS precharge Output data hold time RAS hold time from CAS precharge Unit Note
tRWC tRWD tCWD tAWD tOEH
118 64 27 39 10
- - - - -
122 69 27 39 10
- - - - -
138 77 32 47 13
- - - - -
ns ns ns ns ns
15 15 15
tHPC tCP tCPA tCOH tRHCP
20 8 - 5 50 27
- - 27 - -
20 8 - 5 27
- - 27 - -
25 10 - 5 32
- - 32 - -
ns ns ns ns ns
7
RAS pulse width in hyper page mode tRAS
200k 55
200k 60
200k ns
Hyper Page Mode (EDO) Read-Modify-Write Cycle Hyper page mode read/write cycle time CAS precharge to WE delay time CAS-before-RAS Refresh Cycle CAS setup time CAS hold time RAS to CAS precharge time Write to RAS precharge time Write to RAS hold time
tPRWC tCPWD
58 41
- -
58 41
- -
68 49
- -
ns ns
tCSR tCHR tRPC tWRP tWRH
5 10 5 10 10
- - - - -
5 10 5 10 10
- - - - -
5 10 5 10 10
- - - - -
ns ns ns ns ns
CAS-before-RAS Counter Test Cycle CAS precharge time
tCPT
35
-
35
-
40
-
ns
Semiconductor Group
8
1998-10-01
HYB 514175BJ-50/-55/-60 256k x 16 EDO-DRAM
Notes All voltages are referenced to VSS. ICC1, ICC3, ICC4 and ICC6 depend on cycle rate. ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open. Address can be changed once or less while RAS = VIL. In case of ICC4 it can be changed once or less during a hyper page mode (EDO) cycle 5. An initial pause of 200 s is required after power-up followed by 8 RAS cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using the internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 6. AC measurements assume tT = 2 ns. 7. VIH (MIN.) and VIL (MAX.) are reference levels for measuring timing of input signals. Transition times are also measured between VIH and VIL. 8. Measured with the specified current load and 100 pF at VOL = 0.8 V and VOH = 2.0 V. Access time is determined by the latter of tRAC, tCAC, tAA , tCPA , tOEA. tCAC is measured from tristate. 9. Operation within the tRCD (MAX.) limit ensures that tRAC (MAX.) can be met. tRCD (MAX.) is specified as a reference point only. If tRCD is greater than the specified tRCD (MAX.) limit, then access time is controlled by tCAC. 10.Operation within the tRAD (MAX.) limit ensures that tRAC (MAX.) can be met. tRAD (MAX.) is specified as a reference point only. If tRAD is greater than the specified tRAD (MAX.) limit, then access time is controlled by tAA. 11.Either tRCH or tRRH must be satisfied for a read cycle. 12.tOFF (MAX.), tOEZ (MAX.) define the time at which the output achieves the open-circuit conditions and are not referenced to output voltage levels. tOFF is referenced from the rising edge of RAS or CAS, whichever occurs last. 13.Either tDZC or tDZO must be satisfied. 14.Either tCDD or tODD must be satisfied. 15.tWCS, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS > tWCS (MIN.), the cycle is an early write cycle and data out pin will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (MIN.), tCWD > tCWD (MIN.) and tAWD > tAWD (MIN.), the cycle is a read-write cycle and I/O will contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition of I/O (at access time) is indeterminated. 16.These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge in read-write cycles. 1. 2. 3. 4.
Semiconductor Group
9
1998-10-01
HYB 514175BJ/BJL-50/-55/-60 256k x 16 EDO-DRAM
t RC t RAS VIH
RAS
t RP
VIL t CSH t RCD
UCAS LCAS
VIH VIL t RAD t ASR VIH t ASC t CAH
t RSH t CAS t RAL
t CRP
t ASR
Column Row
Address
Row
VIL
t RAH t RCS t RRH t AA t OEA
t RCH
VIH
WE
VIL VIH
OE
VIL
t DZC t DZO t ODD
t CDD
I/O (Inputs)
VIH VIL t CAC t CLZ t OEZ
Valid Data OUT Hi Z
t OFF
VOH I/O (Outputs) V OL
Hi Z
t RAC
"H" or "L"
SPT03043
Read Cycle
Semiconductor Group
10
1998-10-01
HYB 514175BJ-50/-55/-60 256k x 16 EDO-DRAM
t RC t RAS VIH
RAS
t RP
VIL t CSH t RCD
UCAS LCAS
VIH VIL t RAD t ASR VIH t ASC t CAH
t RSH t CAS t RAL
t CRP
t ASR
Column Row
Address
Row
VIL
t RAH t WCS
t CWL t WP t WCH t RWL
VIH
WE
VIL
VIH
OE
VIL t DS
I/O (Inputs)
t DH
VIH
Valid Data IN
VIL
Hi Z
VOH I/O (Outputs) V OL
"H" or "L"
SPT03044
Write Cycle (Early Write)
Semiconductor Group
11
1998-10-01
HYB 514175BJ/BJL-50/-55/-60 256k x 16 EDO-DRAM
t RC t RAS VIH
RAS
t RP
VIL t CSH t RCD
UCAS LCAS
VIH VIL t RAD t ASR VIH t ASC t CAH
t RSH t CAS t RAL
t CRP
t ASR
Column Row
Address
Row
VIL
t RAH
t CWL t RWL t WP
VIH
WE
VIL t OEH VIH
OE
VIL t DZO t DZC
I/O (Inputs)
t ODD t DS
t DH
VIH
Valid Data
VIL t CLZ t OEA t OEZ
VOH I/O (Outputs) V OL
Hi Z
Hi Z
"H" or "L"
SPT03045
Write Cycle (OE Controlled Write)
Semiconductor Group
12
1998-10-01
HYB 514175BJ-50/-55/-60 256k x 16 EDO-DRAM
t RWC t RAS VIH
RAS
VIL t CSH t RSH t RCD
UCAS LCAS
t RP t CAS t CRP
VIH VIL t ASR VIH t RAH t ASC
Column
t CAH t ASR
Row
Address
Row
VIL t RAD t AWD t CWD t RWD VIH
WE
t CWL t RWL t WP
VIL t RCS
t AA t OEA t OEH
VIH
OE
VIL
t DZC t DZO
t DS t DH
Valid Data IN
I/O (Inputs)
VIH VIL t CAC t CLZ t ODD t OEZ
Data OUT
VOH I/O (Outputs) V OL t RAC
"H" or "L"
SPT03046
Read-Write (Read-Modify-Write) Cycle
Semiconductor Group
13
1998-10-01
HYB 514175BJ/BJL-50/-55/-60 256k x 16 EDO-DRAM
t RAS t RCD VIH
RAS
t RHCP
VIL t HPC t CRP
UCAS LCAS
t RP t CP t CAS t RSH t CAS t CRP
t CAS
VIH VIL t CSH t ASR VIH t RAH t ASC
Column 1
t CAH t ASC
t RAL t CAH t CAH t ASC
Column N
Address
Row
Column 2
VIL t RAD t RCS VIH
WE
t RRH
t RCH
VIL t OES t OEA VIH
OE
t CAC t AA t CPA
t CAC t AA t CPA t OFF
VIL t RAC t AA t CAC t CLZ
I/O (Output) V OL
t COH
Data OUT 1
t COH
Data OUT 2
t OEZ
Data OUT N
VOH
"H" or "L"
SPT03056
Hyper Page Mode (EDO) Read Cycle
Semiconductor Group
14
1998-10-01
HYB 514175BJ-50/-55/-60 256k x 16 EDO-DRAM
t RAS t RCD VIH
RAS
t RHCP
VIL t HPC t CRP
UCAS LCAS
t RP t CP t CAS t RSH t CAS t CRP
t CAS
VIH VIL t CSH t ASR VIH t RAH t ASC t CAH t ASC t CAH t ASC t RAL t CAH
Address
VIL
Row Address
Column 1
Column 2
Column N
t RAD t WCS t CWL t WCH t WP VIH
WE
t RWL t WCS t CWL t WCH t WP t WCS t CWL t WCH t WP
VIL VIH
OE
VIL t DH t DS
I/O (Input)
t DH t DS
Data IN 2
t DH t DS
Data IN N
VIH
Data IN 1
VIL
"H" or "L"
SPT03057
Hyper Page Mode (EDO) Early Write Cycle
Semiconductor Group
15
1998-10-01
HYB 514175BJ/BJL-50/-55/-60 256k x 16 EDO-DRAM
t RASP VIH
RAS
VIL t CSH t CP t RCD
UCAS LCAS
t RP t PRWC t CAS t CAS t RSH t CRP t CAS
VIH VIL t ASR VIH t RAD t RAH t ASC
Row
t CAH
t CAH t ASC
Column
t RAL t CAH t ASC
Column
t ASR
Row
Address
Column
VIL t RWD t CWD t RCS VIH
WE
t CWL
t CPWD t CWD
t CWL
t CPWD t CWD
t RWL t CWL
VIL t AA
t AWD t OEA t OEH t WP
t AWD t OEA t OEH t WP
t AWD t OEA t WP t OEH
VIH
OE
VIL t DZC t DZO VIH I/O (Inputs) V IL t CAC t RAC VOH I/O (Outputs) V
OL
t CLZ
t CLZ t ODD t DZC
Data IN
t CLZ t CPA
t CPA
t ODD
Data IN
t DZC
t ODD
Data IN
t DH t DS t OEZ
Data OUT
t DH t AA t DS t OEZ
Data OUT
t CAC t AA t OEZ
Data OUT
t DH t DS
"H" or "L"
SPT03131
Hyper Page Mode (EDO) Late Write and Read-Modify-Write Cycles
Semiconductor Group
16
1998-10-01
HYB 514175BJ-50/-55/-60 256k x 16 EDO-DRAM
t RC t RAS VIH
RAS
t RP
VIL t CRP t RPC
UCAS LCAS
VIH VIL VIH t ASR t RAH t ASR
Row Row
Address
VIL VOH I/O (Outputs) V OL
Hi Z
"H" or "L"
SPT03050
RAS-Only Refresh Cycle
Semiconductor Group
17
1998-10-01
HYB 514175BJ/BJL-50/-55/-60 256k x 16 EDO-DRAM
t RC t RP VIH
RAS
t RAS
t RP
VIL t RPC t CP t CSR
UCAS LCAS
t CHR
t RPC
t CRP
VIH VIL t WRH t WRP VIH
WE
VIL VIH
OE
VIL t ODD
I/O (Inputs)
VIH VIL t CDD t OEZ
I/O (Outputs) V OL
VOH t OFF
Hi Z
"H" or "L"
SPT03051
CAS-Before-RAS Refresh Cycle
Semiconductor Group
18
1998-10-01
HYB 514175BJ-50/-55/-60 256k x 16 EDO-DRAM
t RC t RP t RAS t RAS
t RC t RP
VIH
RAS
VIL
t RCD t RSH t CHR t CRP VIH VIL t RAD t ASC t RAH t ASR VIH t CAH
Row Column
UCAS LCAS
t WRP t WRH t ASR
Row
Address
VIL VIH
WE
t RCS
t RRH
VIL t AA t OEA VIH
OE
VIL
t DZC t DZO
t CDD t ODD
I/O (Inputs)
VIH VIL t CLZ t RAC VOH
Valid Data OUT
t CAC t OEZ
t OFF
I/O (Outputs) V OL
Hi Z
"H" or "L"
SPT03053
Hidden Refresh Cycle (Read)
Semiconductor Group
19
1998-10-01
HYB 514175BJ/BJL-50/-55/-60 256k x 16 EDO-DRAM
t RC t RAS VIH
RAS
t RC t RP t RAS t RP
VIL t RCD
UCAS LCAS
t RSH
t CHR
t CRP
VIH VIL t RAD t ASC t RAH t ASR VIH t CAH
Row Column
t ASR
Row
Address
VIL
t WCS t WCH t WP t WRP t WRH
VIH
WE
VIL t DS t DH
I/O (Input)
VIN
Valid Data
VIL
Hi Z
VOH I/O (Output) V OL
"H" or "L"
SPT03054
Hidden Refresh Cycle (Early Write)
Semiconductor Group
20
1998-10-01
HYB 514175BJ-50/-55/-60 256k x 16 EDO-DRAM
Read Cycle
VIH
RAS
t RAS
t RP
VIL t CHR t CSR
UCAS LCAS
t RSH t CP t CAS t RAL t CAH t ASC t ASR
Row
VIH VIL
VIH
Address Column
VIL VIH
t WRP
t AA t CAC t OEA
t RRH
WE
VIL VIH
OE
t WRH
t RCS
t RCH
VIL t DZC
I/O (Inputs)
t CDD t ODD t DZO t CLZ t OFF t OEZ
Data OUT
VIH VIL
I/O (Outputs) V OL
VOH t WCS t WRP t RWL t CWL t WCH t WRH VIH t DH
Write Cycle
VIH
WE
VIL
OE
VIL t DS
I/O (Inputs)
VIH
Data IN
VIL
Hi Z
VOH I/O (Outputs) V OL
"H" or "L"
SPT03055
CAS-Before-RAS Refresh Counter Test Cycle
Semiconductor Group
21
1998-10-01
HYB 514175BJ/BJL-50/-55/-60 256k x 16 EDO-DRAM
Package Outlines Plastic Package, P-SOJ-40-1 (SMD) (Plastic small outline J-leaded)
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Semiconductor Group 22
Dimensions in mm 1998-10-01
GPJ09018

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