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64Mx64bits PC133 SDRAM Unbuffered DIMM
based on 32Mx8 SDRAM with LVTTL, 4 banks & 8K Refresh
HYM72V64636T8 Series
DESCRIPTION
The HYM72V64636T8 Series are 64Mx64bits Synchronous DRAM Modules. The modules are composed of sixteen 32Mx8bits CMOS Synchronous DRAMs in 400mil 54pin TSOP-II package, one 2Kbit EEPROM in 8pin TSSOP package on a 168pin glass-epoxy printed circuit board. One 0.22uF and one 0.0022uF decoupling capacitors per each SDRAM are mounted on the PCB. The HYM72V64636T8 Series are Dual In-line Memory Modules suitable for easy interchange and addition of 512Mbytes memory. The HYM72V64636T8 Series are fully synchronous operation referenced to the positive edge of the clock . All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth.
FEATURES
* * * * PC133/PC100MHz support 168pin SDRAM Unbuffered DIMM Serial Presence Detect with EEPROM 1.25" (31.75mm) Height PCB with double sided components Single 3.30.3V power supply - 1, 2, 4 or 8 or Full page for Sequential Burst * * All device pins are compatible with LVTTL interface - 1, 2, 4 or 8 for Interleave Burst Data mask function by DQM * Programmable CAS Latency ; 2, 3 Clocks * * * * * * SDRAM internal banks : four banks Module bank : two physical bank Auto refresh and self refresh 8192 refresh cycles / 64ms Programmable Burst Length and Burst Type
ORDERING INFORMATION
Part No.
HYM72V64636T8-H
Clock Frequency
133MHz
Internal Bank
4 Banks
Ref.
8K
Power
Normal
SDRAM Package
TSOP-II
Plating
Gold
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.3/Apr.01
PC133 SDRAM Unbuffered DIMM
HYM72V64636T8 Series
PIN DESCRIPTION
PIN CK0~CK3 CKE0, CKE1 /S0 ~ /S3 BA0, BA1 A0 ~ A12 /RAS, /CAS, /WE DQM0~DQM7 DQ0 ~ DQ63 VCC VSS SCL SDA SA0~2 WP NC PIN NAME Clock Inputs Clock Enable Chip Select SDRAM Bank Address Address Row Address Strobe, Column Address Strobe, Write Enable Data Input/Output Mask Data Input/Output Power Supply (3.3V) Ground SPD Clock Input SPD Data Input/Output SPD Address Input Write Protect for SPD No Connection DESCRIPTION The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh Enables or disables all inputs except CK, CKE and DQM Selects bank to be activated during /RAS activity Selects bank to be read/written during /CAS activity Row Address : RA0 ~ RA12, Column Address : CA0 ~ CA9 Auto-precharge flag : A10 /RAS, /CAS and /WE define the operation Refer function truth table for details Controls output buffers in read mode and masks input data in write mode Multiplexed data input / output pin Power supply for internal circuits and input buffers Ground Serial Presence Detect Clock input Serial Presence Detect Data input/output Serial Presence Detect Address Input Write Protect for Serial Presence Detect on DIMM No connection
Rev. 1.3/Apr.01
2
PC133 SDRAM Unbuffered DIMM
HYM72V64636T8 Series
PIN ASSIGNMENTS
FRONT SIDE PIN NO.
1 2 3 4 5 6 7 8 9 10
BACK SIDE PIN NO.
85 86 87 88 89 90 91 92 93 94
FRONT SIDE PIN NO.
41 42 43 44 45 46 47 48 49 50 51 52
BACK SIDE PIN NO.
125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168
NAME
VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7
NAME
VSS DQ32 DQ33 DQ34 DQ35 VCC DQ36 DQ37 DQ38 DQ39
NAME
VCC CK0 VSS NC /S2 DQM2 DQM3 NC VCC NC NC NC NC VSS DQ16 DQ17 DQ18 DQ19 VCC DQ20 NC NC CKE1 VSS DQ21 DQ22 DQ23 VCC DQ24 DQ25 DQ26 DQ27 VCC DQ28 DQ29 DQ30 DQ31 VSS CK2 NC WP SDA SCL VCC
NAME
CK1 A12 VSS CKE0 /S3 DQM6 DQM7 NC VCC NC NC NC NC VSS DQ48 DQ49 DQ50 DQ51 VCC DQ52 NC NC NC VSS DQ53 DQ54 DQ55 VCC DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63 VSS CK3 NC SA0 SA1 SA2 VCC
Architecture Key
11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 NC NC VSS NC NC VCC /WE DQM0 DQM1 /S0 NC VSS A0 A2 A4 A6 A8 A10/AP BA1 VCC 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VCC DQ46 DQ47 NC NC VSS NC NC VCC /CAS DQM4 DQM5 /S1 /RAS VSS A1 A3 A5 A7 A9 BA0 A11 VCC
53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84
Voltage Key
Rev. 1.3/Apr.01
3
PC133 SDRAM Unbuffered DIMM
HYM72V64636T8 Series
BLOCK DIAGRAM
Note : 1. The serial resistor values of DQs are 10ohms
Rev. 1.3/Apr.01
4
PC133 SDRAM Unbuffered DIMM
HYM72V64636T8 Series
SERIAL PRESENCE DETECT
BYTE NUMBER BYTE0 BYTE1 BYTE2 BYTE3 BYTE4 BYTE5 BYTE6 BYTE7 BYTE8 BYTE9 BYTE10 BYTE11 BYTE12 BYTE13 BYTE14 BYTE15 BYTE16 BYTE17 BYTE18 BYTE19 BYTE20 BYTE21 BYTE22 BYTE23 BYTE24 BYTE25 BYTE26 BYTE27 BYTE28 BYTE29 BYTE30 BYTE31 BYTE32 BYTE33 BYTE34 BYTE35 BYTE36 ~61 BYTE62 BYTE63 BYTE64 BYTE65 ~71 FUNCTION DESCRIPTION # of Bytes Written into Serial Memory at Module Manufacturer Total # of Bytes of SPD Memory Device Fundamental Memory Type # of Row Addresses on This Assembly # of Column Addresses on This Assembly # of Module Banks on This Assembly Data Width of This Assembly Data Width of This Assembly (Continued) Voltage Interface Standard of This Assembly SDRAM Cycle Time @/CAS Latency=3 Access Time from Clock @/CAS Latency=3 DIMM Configuration Type Refresh Rate/Type Primary SDRAM Width Error Checking SDRAM Width Minimum Clock Delay Back to Back Random Column Address Burst Lenth Supported # of Banks on Each SDRAM Device SDRAM Device Attributes, /CAS Lataency SDRAM Device Attributes, /CS Lataency SDRAM Device Attributes, /WE Lataency SDRAM Module Attributes SDRAM Device Attributes, General SDRAM Cycle Time @/CAS Latency=2 Access Time from Clock @/CAS Latency=2 SDRAM Cycle Time @/CAS Latency=1 Access Time from Clock @/CAS Latency=1 Minimum Row Precharge Time (tRP) Minimum Row Active to Row Active Delay (tRRD) Minimum /RAS to /CAS Delay (tRCD) Minimum /RAS Pulse Width (tRAS) Module Bank Density Command and Address Signal Input Setup Time Command and Address Signal Input Hold Time Data Signal Input Setup Time Data Signal Input Hold Time Superset Information (may be used in future) SPD Revision Checksum for Byte 0~62 Manufacturer JEDEC ID Code ....Manufacturer JEDEC ID Code FUNCTION -H 128 Bytes 256 Bytes SDRAM 13 10 2 Bank 64 Bits LVTTL 7.5ns 5.4ns None 7.8125us / Self Refresh Supported x8 None tCCD = 1 CLK 1,2,4,8,Full Page 4 Banks 3 /CS Latency=0 /WE Latency=0 Neither Buffered nor Registered +/- 10% voltage tolerence, Burst Read Single Bit Write, Precharge All, Auto Precharge, Early RAS Precharge 20ns 15ns 20ns 45ns 256MB 1.5ns 0.8ns 1.5ns 0.8ns Intel SPC1.2B Hynix JEDED ID Unused Hynix (Korea Area) HSA (United States Area) HSE (Europe Area) HSJ (Japan Area) ASIA Area VALUE NOTE -H 80h 08h 04h 0Dh 0Ah 02h 40h 00h 01h 75h 54h 00h 82h 08h 00h 01h 8Fh 04h 04h 01h 01h 00h 0Eh 00h 00h 00h 00h 14h 0Fh 14h 2Dh 40h 15h 08h 15h 08h 00h 12h D1h A0h FFh 0*h 1*h 2*h 3*h 4*h 3, 8 2 1
BYTE72
Manufacturing Location
11
Rev. 1.3/Apr.01
5
PC133 SDRAM Unbuffered DIMM
HYM72V64636T8 Series
Continued
BYTE NUMBER
BYTE73 BYTE74 BYTE75 BYTE76 BYTE77 BYTE78 BYTE79 BYTE80 BYTE81 BYTE82 BYTE83 BYTE84 BYTE85 ~90 BYTE91 BYTE92 BYTE93 BYTE94 BYTE95 ~98 BYTE99 ~125 BYTE126 BYTE127 BYTE128 ~256
FUNCTION DESCRIPTION
Manufacturer' Part Number (Component) s Manufacturer' Part Number (256Mb based) s Manufacturer' Part Number (Voltage Interface) s Manufacturer' Part Number (Memory Width) s ....Manufacturer' Part Number (Memory Width) s Manufacturer' Part Number (Data Width) s ....Manufacturer' Part Number (Data Width) s Manufacturer' Part Number (Refresh, SDRAM Bank) s Manufacturer' Part Number (Package Type) s Manufacturer' Part Number (Component Configuration) s Manufacturer' Part Number (Hyphent) s Manufacturer' Part Number (Min. Cycle Time) s Manufacturer' Part Number s Revision Code (for Component) ....Revision Code (for PCB) Manufacturing Date ....Manufacturing Date Assembly Serial Number Manufacturer Specific Data (may be used in future) Reserved Intel Specification Details for 100MHz Support Unused Storage Locations
FUNCTION
-H 7 (SDRAM) 2 V (3.3V, LVTTL) 6 4 6 3 6 (8K Refresh, 4Banks) T 8 (x8 based) - (Hyphen) H Blanks Process Code Process Code Work Week Year None Refer to Note9 Refer to Note7 -
VALUE
-H 37h 31h 56h 33h 32h 36h 33h 36h 54h 48h 2Dh 48h 20h 00h 64h F5h 00h
NOTE
4, 5 4, 5 4, 5 4, 5 4, 5 4, 5 4, 5 4, 5 4, 5 4, 5 4, 5 4, 5 4, 5 4, 6 4, 6 3, 6 3, 6 6
7, 8, 9 7, 8, 9
Note : 1. The bank address is excluded 2. 1, 2, 4, 8 for Interleave Burst Type 3. BCD adopted 4. ASCII adopted 5. Basically Hynix writes Part No. except for HYM'in Byte 73~90 to use the limited 18 bytes from byte 73 to byte 90 ` 6. Not fixed but dependent 7. CK0~CK3 connected to DIMM, TBD junction temp, CL2(3) support, Intel defined Concurrent Auto Precharge suport 8. Refer to the most recent Intel and JEDEC SPD Specification 9. These values are applied to PC100 applications only per Intel PC SDRAM specification 10. In the case of L-Part, character L' will be added between byte 81 and byte 82 ` 11. Refer to Hynix web site
Rev. 1.3/Apr.01
6
PC133 SDRAM Unbuffered DIMM
HYM72V64636T8 Series
ABSOLUTE MAXIMUM RATINGS
Parameter Ambient Temperature Storage Temperature Voltage on Any Pin relative to VSS Voltage on VDD relative to VSS Short Circuit Output Current Power Dissipation Soldering Temperature Time TA TSTG VIN, VOUT VDD, VDDQ IOS PD TSOLDER Symbol 0 ~ 70 -55 ~ 125 -1.0 ~ 4.6 -1.0 ~ 4.6 50 1 260 10 Rating C C V V mA W C Sec Unit
Note : Operation at above absolute maximum rating can adversely affect device reliability.
DC OPERATING CONDITION (TA=0 to 70C)
Parameter Power Supply Voltage Input High voltage Input Low voltage Symbol VDD, VDDQ VIH VIL Min 3.0 2.0 -0.3 Typ 3.3 3.0 0 Max 3.6 VDDQ + 0.3 0.8 Unit V V V Note 1 1,2 1,3
Note : 1.All voltages are referenced to VSS = 0V 2.VIH(max) is acceptable 5.6V AC pulse width with <=3ns of duration. 3.VIL(min) is acceptable -2.0V AC pulse width with <=3ns of duration.
AC OPERATING TEST CONDITION (TA=0 to 70C, VDD=3.30.3V, VSS=0V)
Parameter AC Input High / Low Level Voltage Input Timing Measurement Reference Level Voltage Input Rise / Fall Time Output Timing Measurement Reference Level Voltage Output Load Capacitance for Access Time Measurement Symbol VIH / VIL Vtrip tR / tF Voutref CL Value 2.4/0.4 1.4 1 1.4 50 Unit V V ns V pF 1 Note
Note : 1.Output load to measure access times is equivalent to two TTL gates and one capacitor (50pF). For details, refer to AC/DC output load circuit
Rev. 1.3/Apr.01
7
PC133 SDRAM Unbuffered DIMM
HYM72V64636T8 Series
CAPACITANCE (TA=25C, f=1MHz)
-H Parameter CK0~ CK3 CKE0, CKE1 Input Capacitance /S0~/S3 A0~12, BA0, BA1 /RAS, /CAS, /WE DQM0~DQM7 Data Input / Output Capacitance DQ0 ~ DQ63 Pin Symbol Min CI1 CI2 CI3 CI4 CI5 CI6 CI/O 35 45 25 70 70 15 10 Max 40 50 35 95 95 20 20 pF pF pF pF pF pF pF Unit
OUTPUT LOAD CIRCUIT
Vtt=1.4V
RT=250
Output
Output 50pF
50pF
DC Output Load Circuit
AC Output Load Circuit
Rev. 1.3/Apr.01
8
PC133 SDRAM Unbuffered DIMM
HYM72V64636T8 Series
DC CHARACTERISTICS I (TA=0 to 70C, VDD=3.30.3V)
Parameter Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage ILI ILO VOH VOL Symbol Min. -16 -1 2.4 Max 16 1 0.4 Unit uA uA V V Note 1 2 IOH = -4mA IOL = +4mA
Note : 1.VIN = 0 to 3.6V, All other pins are not tested under VIN =0V 2.DOUT is disabled, VOUT=0 to 3.6
DC CHARACTERISTICS II
Speed Parameter Symbol Test Condition -H Operating Current IDD1 Burst length=1, One bank active tRC tRC(min), IOL=0mA CKE VIL(max), tCK = min CKE VIL(max), tCK = CKE VIH(min), CS VIH(min), tCK = min Input signals are changed one time during 2clks. All other pins VDD-0.2V or 0.2V CKE VIH(min), tCK = Input signals are stable. CKE VIL(max), tCK = min CKE VIL(max), tCK = CKE VIH(min), CS VIH(min), tCK = min Input signals are changed one time during 2clks. All other pins VDD-0.2V or 0.2V CKE VIH(min), tCK = Input signals are stable. tCK tCK(min), IOL=0mA All banks active tRRC tRRC(min), All banks active CKE 0.2V CL=3
1200 32 mA 32 mA 1
Unit
Note
Precharge Standby Current IDD2P in Power Down Mode IDD2PS
IDD2N Precharge Standby Current in Non Power Down Mode IDD2NS Active Standby Current in Power Down Mode IDD3P IDD3PS
320 mA 224 112 mA 112
IDD3N Active Standby Current in Non Power Down Mode IDD3NS Burst Mode Operating Current Auto Refresh Current Self Refresh Current
640 mA 640
IDD4 IDD5 IDD6
1600 1920 64
mA mA mA
1 2
Note : 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open 2. Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II
Rev. 1.3/Apr.01
9
PC133 SDRAM Unbuffered DIMM
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
-H Parameter Symbol Min System Clock Cycle Time CAS Latency = 3 tCK3 tCHW tCLW tAC3 tOH tDS tDH tAS tAH tCKS tCKH tCS tCH tOLZ 7.5 2.5 2.5 2.7 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.8 1 Max 1000 5.4 ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1 1 1 1 1 1 1 1 1 1 2 Unit Note
HYM72V64636T8 Series
Clock High Pulse Width Clock Low Pulse Width Access Time From Clock CAS Latency = 3
Data-Out Hold Time Data-Input Setup Time Data-Input Hold Time Address Setup Time Address Hold Time CKE Setup Time CKE Hold Time Command Setup Time Command Hold Time CLK to Data Output in Low-Z Time CLK to Data Output in High-Z Time
CAS Latency = 3
tOHZ3
2.7
5.4
ns
Note : 1.Assume tR / tF (input rise and fall time ) is 1ns If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter 2.Access times to be measured with input signals of 1v/ns edge rate, from 0.8v to 2.0v If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter
Rev. 1.3/Apr.01
10
PC133 SDRAM Unbuffered DIMM
HYM72V64636T8 Series
AC CHARACTERISTICS II
-H Parameter Symbol Min Operation RAS Cycle Time Auto Refresh RAS to CAS Delay RAS Active Time RAS Precharge Time RAS to RAS Bank Active Delay CAS to CAS Delay Write Command to Data-In Delay Data-In to Precharge Command Data-In to Active Command DQM to Data-Out Hi-Z DQM to Data-In Mask MRS to New Command Precharge to Data CAS Latency = 3 Output Hi-Z Power Down Exit Time Self Refresh Exit Time Refresh Time tRRC tRCD tRAS tRP tRRD tCCD tWTL tDPL tDAL tDQZ tDQM tMRD tPROZ3 tPDE tSRE tREF 65 20 45 20 15 1 0 2 5 2 0 2 3 1 1 100K 64 ns ns ns ns ns CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK ms 1 tRC 65 Max ns Unit Note
Note : 1. A new command can be given tRRC after self refresh exit
Rev. 1.3/Apr.01
11
PC133 SDRAM Unbuffered DIMM
HYM72V64636T8 Series
DEVICE OPERATING OPTION TABLE
HYM72V64636T8-H
CAS Latency 133MHz(7.5ns) 125MHz(8ns) 100MHz(10ns) 3CLKs 3CLKs 3CLKs tRCD 3CLKs 3CLKs 2CLKs tRAS 6CLKs 6CLKs 5CLKs tRC 9CLKs 9CLKs 7CLKs tRP 3CLKs 3CLKs 2CLKs tAC 5.4ns 6ns 6ns tOH 2.7ns 3ns 3ns
COMMAND TRUTH TABLE
Command Mode Register Set No Operation Bank Active Read H Read with Autoprecharge Write H Write with Autoprecharge Precharge All Banks H Precharge selected Bank Burst Stop DQM Auto Refresh Burst-Read-SingleWRITE Entry Self Refresh1 Exit H H H H H L H X L H L H Entry Precharge power down Exit L H L H Clock Suspend Entry Exit H L L L H V X V V X H X H X H X X X H L L H H X H X H X X X H X H X H X X L L L H X L H X L L L X L L L X H H H X X H L X V X X X X X L L H L X X L X X X A9 Pin High (Other Pins OP code) V X L H L L X CA H H X X L H L H X CA H L V CKEn-1 H H H CKEn X X L X L H L H H H H X RA L V V CS L H RAS L X CAS L X WE L X X X DQM X
ADDR
A10/ AP OP code
BA
Note
Note : 1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high 2. X = Dont care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address, Opcode = Operand Code, NOP = No Operation
Rev. 1.3/Apr.01
12
PC133 SDRAM Unbuffered DIMM
HYM72V64636T8 Series
PACKAGE DEMENSION
Rev. 1.3/Apr.01
13

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