View BU-61705_377233.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

PRELIMINARY DATA SHEET
BU-64703
Make sure the next Card you purchase has...
(R)
SIMPLE SYSTEM RT Mark3 (SSRT Mark3)
FEATURES
* Complete Integrated Remote Terminal Including: *All 3.3Volt Terminal (No Other Power Supplies Are Required) *Dual Low-Power 3.3V Only Transceivers *Complete RT Protocol Logic * Supports MIL-STD-1553A/B Notice 2, STANAG-3838 RT, and MIL-STD-1760 Stores Management * 0.88" X 0.88", 0.130", Max Height CQFP * 80-Pin Ceramic Flatpack or Gullwing Package
DESCRIPTION
The BU-64703 Simple System RT Mark3 (SSRT Mark3) MIL-STD1553 terminals provide a complete interface between a simple system and a MIL-STD-1553 bus. The SSRT Mark3 is powered entirely by 3.3 volts, thus eliminating the need for a 5V power supply. This terminal integrates dual transceiver, protocol logic, and a FIFO memory for received messages in a 0.88 inch square ceramic package. The gull wing package with a "toe-to-toe" maximum dimension of 1.13 inches enables its use in applications where PC board space is at a premium. The SSRT Mark3 provides multi-protocol support of MILSTD-1553A/B, MIL-STD-1760, McAir, and STANAG-3838. The SSRT Mark3's transceivers are completely monolithic, require only a +3.3V supply, and consume low power. The internal architecture is identical to that of the original BU-61703/61705 Simple System RT (SSRT). There are versions of the Simple System RT Mark3 available with transceivers trimmed for MIL-STD-1760 compliance, or compatible to McAir standards. The SSRT Mark3 can operate with a choice of clock frequencies of 10, 12, 16, or 20 MHz. The SSRT Mark3 incorporates a built-in self-test (BIT). This BIT, which is processed following power turn-on or after receipt of an Initiate Self-Test Mode command, provides a comprehensive test of the SSRT Mark3's encoders, decoders, protocol, transmitter watchdog timer, and protocol section. The SSRT Mark3 also includes an auto-configuration feature. The SSRT Mark3 is ideal for stores and other simple systems that do not require a microprocessor. To streamline the interface to simple systems, the SSRT Mark3 includes an internal 32-word FIFO for received data words. This serves to ensure that only complete, consistent blocks of validated data words are transferred to a system.
* 3.3V Logic Power * Meets 1553A/McAir Response Time Requirements * Internal FIFO for Burst Mode Capability on Receive Data * 16-bit DMA Interface * Auto Configuration Capability * Comprehensive Built-In Self-Test * Direct Interface to Simple (Processorless) Systems * Available with Full Military Temperature Range and Screening * Selectable Input Clock: 10, 12, 16, or 20 MHz
This Preliminary data sheet provides detailed functional capabilities for product currently in prototype production. These specifications are being provided to allow for electrical design, layout and operation.
FOR MORE INFORMATION CONTACT:
Data Device Corporation 105 Wilbur Place Bohemia, New York 11716 631-567-5600 Fax: 631-567-7358 www.ddc-web.com
Technical Support: 1-800-DDC-5757 ext. 7234
(c)
2003 Data Device Corporation
Data Device Corporation www.ddc-web.com
TX_INH MSTCLR
+3.3V
TX/RX A TRANSCEIVER A DATA BUFFERS DMA HANDSAKE AND TRANDFER CONTROL LOGIC D15-D0 DTREQ DTGRT DTACK HS FAIL MEMOE MEMWR
SYSTEM DATA
TX/RX A
TX/RX B TRANSCEIVER B
DMA HANDSAKE CONTROL
TX/RX B
DATA TRANSFER CONTROL
CONTROL INPUTS 2
AUTO_CFG BRO_ENA
DUAL ENCODER DECODER AND RT STATE LOGIC
L_BRO, T/R, SA4-SA0 WC/MC/CWC4-0
COMMAND ADDRESS BUS
ILLEGAL
RTAD4-RTAD0
SRV_RQST SSFLAG BUSY RTACTIVE INCMD
RT ADDRESS
RTADP RT_AD_LAT RT_AD_ERR
RT WORD INPUTS
CLK_IN
GBR MSG_ERR RTFAIL
CLOCK FREQUENCY SELECTION
CLK_SEL1 CLK_SEL0
RT MESSAGE STATUS
BU-64703 Pre-01-03/03
FIGURE 1. SSRT Mark3 BLOCK DIAGRAM
TABLE 1. SSRT Mark3 SPECIFICATIONS
PARAMETER ABSOLUTE MAXIMUM RATING Supply Voltage (Note 10) * Logic (Voltage Input Range) * Transceivers (not during transmit) * Transceiver (during transmit) RECEIVER Differential Input Resistance (Notes 1-6) Differential Input Capacitance (Notes 1-6) Threshold Voltage, Transformer Coupled, Measured on Stub Common Mode Voltage (Note 7) TRANSMITTER Differential Output Voltage (Note 8) * Direct Coupled Across 35 , Measured on Bus * Transformer Coupled Across 70 , Measured on Bus BU-64703XX-XX0 BU-64703X8-XX2 (Note 9) Output Noise, Differential (Direct Coupled) Output Offset Voltage, Transformer Coupled Across 70 ohms Rise/Fall Time BU-64703X8 BU-64703X9 LOGIC VIH All signals except CLOCK_IN CLOCK_IN VIL All signals except CLOCK_IN CLOCK_IN Schmidt Hysteresis All signals except CLOCK_IN CLOCK_IN IIH, IIL All signals except CLOCK_IN IIH (Vcc=3.6V, VIN=Vcc) IIH (Vcc=3.6V, VIH=2.7V) IIL (Vcc=3.6V, VIH=0.4V) CLOCK_IN IIH IIL VOH (Vcc=3.0V, VIH=2.7V, VIL=0.2V, IOH=max) VOL (Vcc=3.0V, VIH=2.7V, VIL=0.2V, IOL=max) IOL IOH CI (Input Capacitance) CIO (Bi-directional signal input capacitance) MIN TYP MAX UNITS
TABLE 1. SSRT Mark3 SPECIFICATIONS (Cont'd)
PARAMETER POWER SUPPLY REQUIREMENTS Voltages/Tolerances (Note 10) * +3.3V Logic * +3.3V Transceivers Current Drain(Total Hybrid)(Notes 8,14) * BU-64703X8/9-XX0,(1553 & McAir) * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle * BU-64703X8-XX2, (1760) * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle POWER DISSIPATION Total Hybrid (Notes 8, 11 and 14) * BU-64703X8/9-XX0, (1553 & McAir) * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle * BU-64703X8-XX2, (1760) * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle Hottest Die * BU-64703X8/9-XX0 (1553 &McAir) * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle * BU-64703X8-XX2 (1760) * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle CLOCK INPUT Frequency * Nominal Value * Default * Option * Option * Option
* Long Term Tolerance
MIN
TYP
MAX
UNITS
-0.3 -0.3 -0.3 2.5
6.0 6.0 4.5
V V V k
3.14 3.14
3.3 3.3
3.46 3.46
V V
5 0.200 0.860 10
pF Vp-p Vpeak
95 310 525 955 95 332 583
1.041
mA mA mA mA mA mA mA A
6
7
9
Vp-p
18 20
20 22
27 27 10 250
Vp-p Vp-p mVp-p mVpeak
0.31 0.67 1.02 1.72 0.31 0.74 1.16 2.01
W W W W W W W W
-250
100 200
150 250
300 300
nsec nsec
2.1 0.8*Vcc 0.7 0.2*Vcc 0.4 1.0
V V V V V V A A A A A V 0.4 V mA mA pF pF
0.09 0.45 0.80 1.51 0.09 0.54 0.95 1.80
W W W W W W W W
-10 -350 -350 -10 -10 2.4
10 -33 -33 10 10
16.0 12.0 10.0 20.0
MHz MHz MHz MHz
* 1553A Compliance * 1553B Compliance
* Short Term Tolerance, 1 second
0.01 0.10
-0.01 -0.10
% %
3.4 -3.4 50 50
* 1553A Compliance * 1553B Compliance
* Duty Cycle
-0.001 -0.01 40
0.001 0.01 60
% % %
Data Device Corporation www.ddc-web.com
3
BU-64703 Pre-01-03/03
TABLE 1. SSRT Mark3 SPECIFICATIONS (Cont'd)
PARAMETER 1553 MESSAGE TIMING RT-to-RT Response Timeout (Note 12) RT Response Time (mid-parity to mid-sync) (Note 12) Transmitter Watchdog Timeout THERMAL Thermal Resistance (Notes 8, 13) Ceramic Flatpack / Gull Lead Junction-to-Case, Hottest Die (JC) Operating Case Temperature -1XX, -4XX -2XX, -5XX -3XX, -8XX Operating Junction Temperature Storage Temperature Lead Temperature (soldering, 10 sec.) PHYSICAL CHARACTERISTICS Size 80-pin Ceramic Flatpack / Gull Lead Lead Toe-Toe Distance 80-pin Gull Wing MIN TYP MAX UNITS
17.5 4
18.5
19.5 7
s s s
660.5
9
11
C/W
-55 -40 0 -55 -65
+125 +85 +70 155 155 +300
C C C C C C
0.88 X 0.88 X 0.13 (22.3 x 22.3 x 3.3) 1.13 (28.7)
in. (mm) in. (mm)
Weight 80-pin Ceramic Flatpack/Gull Wing Package
0.353 (10)
oz (g)
NOTES: Notes 1 through 6 are applicable to the Receiver Differential Resistance and Differential Capacitance Specifications: (8) (1) Specifications include both transmitter and receiver (tied together internally). (9) (2) Impedance parameters are specified directly between pins TX/RX A(B) and TX/RX A(B) of the SSRT Mark3 hybrid. It is assumed that all power and ground inputs to the hybrid are connected. The specifications are applicable for both unpowered and powered conditions. The specifications assume a 2 volt rms balanced, differential, sinusoidal input. The applicable frequency range is 75 kHz to 1 MHz. Minimum resistance and maximum capacitance parameters are guaranteed over the operating range, but are not tested. Assumes a common mode voltage within the frequency range of dc to 2 MHz, applied to the pins of the isolation transformer on the stub side (either direct or transformer coupled), and referenced to hybrid ground. Transformer must be a DDC recommended transformer or other transformer that provides an equivalent minimum CMRR. An "X" in one or more of the product type fields indicates that the reference is applicable to all available product options. MIL-STD-1760 requires a 20 Vp-p minimum output on the stub connection.
(3)
(10) External 10 F tantalum and 0.1 F capacitors to ground should be located as close as possible to +3.3 Vdc input pins. (11) Power dissipation specifications assume a transformer coupled configuration, with external dissipation (while transmitting) of 0.14 watts for the active isolation transformer, 0.08 watts for the active bus coupling transformer, 0.45 watts for each of the two bus isolation resistors, and 0.15 watts for each of the two bus termination resistors. (12) Measured from mid-parity crossing of command word to mid-sync crossing of RT's status word. (13) JC is measured to bottom of ceramic case.
(4)
(5)
(6)
(7)
(14) Current drain and power dissipation specs are preliminary and subject to change.
Data Device Corporation www.ddc-web.com
4
BU-64703 Pre-01-03/03
INTRODUCTION
GENERAL
The BU-64703 Simple System RT Mark3 (SSRT Mark3) is a complete MIL-STD-1553 Remote Terminal (RT) bus interface unit. Contained in this hybrid are a dual transceiver and Manchester II encoder/decoder, and MIL-STD-1553 Remote Terminal (RT) protocol logic. Also included are built-in self-test capability and a parallel subsystem interface. The subsystem interface includes a 12-bit address bus and a 16-bit data bus that operates in a 16-bit DMA handshake transfer configuration. The local bus and associated control signals are optimized for +3.3 volt logic but are +5 volt tolerant. The transceiver front end of the SSRT Mark3 is implemented by means of low-power monolithic technology. The transceiver requires only a single +3.3 V voltage source. The voltage source transmitters provide superior line driving capability for long cables and heavy amounts of bus loading. In addition, the monolithic transceivers can provide a minimum stub voltage level of 20 volts peak-to-peak transformer coupled, making the SSRT Mark3 suitable for MIL-STD-1760 applications. To provide compatability to McAir specs, the SSRT Mark3 is available with an option for transmitters with increased rise and fall times. Besides eliminating the demand for an additional power supply, the use of a +3.3V only transceiver requires the use of a step-up, rather than a step-down, isolation transformer. This provides the advantage of a higher terminal input impedance than is possible for a 15V, 12V or 5V transmitter. As a result, there is a greater margin for the input impedance test, mandated for the 1553 validation test. This allows for longer cable lengths between a system connector and the isolation transformers of an embedded 1553 terminal. The receiver sections of the SSRT Mark3 are fully compliant with MIL-STD-1553B in terms of front-end overvoltage protection, threshold, and bit-error rate. The SSRT Mark3 implements all MIL-STD-1553 message formats, including all 13 MIL-STD 1553 dual redundant mode codes. Any subset of the possible 1553 commands (broadcast, T/R bit, subaddress, word count/mode code) may be optionally illegalized by means of an external PROM, PLD, or RAM. An extensive amount of message validation is performed for each message received. Each word received is validated for correct sync type and sync encoding, Manchester II encoding, parity, and bit count. All messages are verified to contain a legal, defined command word and correct word count. If the SSRT Mark3 is the receiving RT in an RT-to-RT transfer, it verifies that the T/R bit of the transmit command word is logic "1" and that the transmitting RT responds in time and contains the correct RT address in its Status Word. The SSRT Mark3 may be operated from a 10, 12, 16, or 20 MHz clock input. For any clock frequency, the decoder samples incoming data on both edges of the clock input. This oversampling, in effect, provides for a sampling rate of twice the input clocks' frequency. Benefits of the higher sampling rate include a wider tolerance for zero-crossing distortion and improved bit error rate performance. Data Device Corporation www.ddc-web.com 5
The SSRT Mark3 includes a hardwired RT address input. This includes 5 address lines, an address parity input, and an address parity error output. The RT address can also be latched by means of a latching input signal. The SSRT Mark3 supports command illegalization. Commands may be illegalized by asserting the input signal ILLEGAL active low within approximately 2 s after the mid-parity bit zero-crossing of the received command word. Command words may be illegalized as a function of broadcast, T/R bit, subaddress, word count, and/or mode code. An internal Built-in-Test (BIT) Word register is updated at the end of each message. The contents of the BIT Word Register are transmitted in response to a Transmit BIT Word Mode Command. The SSRT Mark3 provides a number of real-time output signals. These various signals provide indications of message in progress, valid received message, message error, handshake fail, loop-test fail or transmitter timeout. The SSRT Mark3 includes standard DMA handshake signals (Request, Grant, and Acknowledge) as well as transfer control outputs (MEMOE and MEMWR). The DMA interface operates in a 16-bit mode, supporting word-wide transfers. The SSRT Mark3's system interface allows the SSRT Mark3 to be interfaced directly to a simple system that doesn't include a microprocessor. This provides a low-cost 1553 interface for A/D and D/A converters, switch closures, actuators, and other discrete I/O signals. The SSRT Mark3 has an internal FIFO for received data words. This 32-word deep FIFO may be used to allow the SSRT Mark3 to transfer its data words to the local system in burst mode. Burst mode utilizes the FIFO by transferring data to the local bus at a rate of one data word every three clock cycles. Burst mode negotiates only once for use of the subsystem bus. Negotiation is performed only after all 1553 data words have been received and validated. In non-burst mode, the SSRT Mark3 will negotiate for the local bus after every received data word. The data word transfer period is three clock cycles for each received 1553 data word. The SSRT Mark3 may also be used in a shared RAM interface configuration. By means of tri-state buffers and a small amount of "glue" logic, the SSRT Mark3 will store Command Words and access Data Words to/from dedicated "mailbox" areas in a shared RAM for each broadcast / T/R bit / subaddress / mode code.
ADDRESS MAPPING
A typical addressing scheme for the SSRT Mark3 12-bit address bus could be as follows: A11: A10: A9-A5: A4-A0: BROADCAST/OWNADDRESS TRANSMIT/RECEIVE SUBADDRESS 4-0 WORD COUNT/MODE CODE 4-0 BU-64703 Pre-01-03/03
This method of address mapping provides for a "mailbox" allocation scheme for the storage of data words. The 12 address outputs may be used to map into 4K words of processor address space. The SSRT Mark3's addressing scheme maps messages in terms of broadcast/ownaddress, transmit/receive, subaddress, and word/count mode code. A 32-word message block is allocated for each T/R-subaddress. For non-mode code messages, the Data Words to be transmitted or received are accessed from (to) relative locations 0 through 31 within the respective message block. For the MIL-STD-1553B Synchronize with data, Selected transmitter shutdown, Override selected transmitter shutdown, and Transmit vector word mode commands which involve a single data word transfer, the address for the data word is offset from location 0 of the message block for subaddresses 0 and 31 by the value of the mode code field of the received command word. The data words transmitted in response to the Transmit last command or Transmit BIT word mode commands are accessed from a pair of internal registers.
this, the burst mode and the non-burst mode. In burst mode, all received data words are transferred from the SSRT Mark3 to the subsystem in a contiguous burst, only following the reception of the correct number of valid data words. In the non-burst mode, single data words are written to the external subsystem immediately following the reception of each individual data word. To initiate a DMA write cycle, the SSRT Mark3 asserts DTREQ low. The subsystem must then respond with DTGRT low. Assuming that DTGRT was asserted in time, the SSRT Mark3 will then assert DTACK low. The SSRT Mark3 will then assert the appropriate value of L_BRO, T/R, SA4-0, and MC/CWC4-0, MEMOE high, and MEMWR low. MEMWR will be asserted low for one clock cycle. The subsystem may then use either the falling or rising edge of MEMWR to latch the data. Similar to the DMA read operation, the address outputs CWC4 through CWC0 are incremented after the completion of a DMA write operation.
HANDSHAKE FAIL
Following the assertion of DTREQ low by the SSRT Mark3, the external subsystem has 10 s to respond by asserting DTACK to logic "0". If the SSRT Mark3 (SSRT Mark3) asserts DTREQ and the subsystem does not respond with DTGRT in time for the SSRT Mark3 to complete a data word transfer, the HSFAIL output will be asserted low to inform the subsystem of the handshake failure, and bit 12 in the internal Built-In-Test (BIT) word will be set to logic "1". If the handshake failure occurs on a data word read transfer (for a transmit command), the SSRT Mark3 will abort the current message transmission. In the case of a handshake failure on a write transfer (received command) the SSRT Mark3 will set the handshake failure output and BIT word bit, and abort processing the current message.
DMA INTERFACE
A 16-bit data bus, a 12-bit address bus, and six control signals are provided to facilitate communication with the parallel subsystem. The data bus D15-D0 consists of bi-directional tri-state signals. The address bus L_BRO, T/R, SA4-SA0, and WC/MC/CWC4-0; along with the data transfer control signals MEMOE and MEMWR are two-state output signals. The control signals include the standard DMA handshake signals DTREQ, DTGRT, DTACK, as well as the transfer control outputs MEMOE and MEMWR. HS_FAIL provides an indication to the subsystem of a handshake failure condition. Data transfers between the subsystem and the SSRT Mark3 are performed by means of a DMA handshake, initiated by the SSRT Mark3. A data read operation is defined to be the transfer of data from the subsystem to the SSRT Mark3. Conversely, a data write operation transfers data from the SSRT Mark3 to the subsystem. Data is transferred as a single 16-bit word.
MESSAGE PROCESSING OPERATION
Following the receipt and transfer of a valid Command Word, the SSRT Mark3 will attempt to perform one of the following operations: (1) transfer received 1553 data to the subsystem, (2) read data from the subsystem for transmission on the 1553 bus, (3) transmit status (and possibly the last command word or RT BIT word) on the 1553 bus, and/or (4) set status word conditions. The SSRT Mark3 responds to all non-broadcast messages to its RT address with a 1553 Status Word.
DMA READ OPERATION
In response to a transmit command, the SSRT Mark3 needs to read data words from the external subsystem. To initiate a data word read transfer, the SSRT Mark3 asserts the signal DTREQ low. Assuming that the subsystem asserts DTGRT in time, the SSRT Mark3 will then assert the appropriate values of L_BRO (logic "0"), T/R (high), SA4-0, and MC/CWC4-0; MEMWR high, along with DTACK low and MEMOE low to enable data to be read from the subsystem. After the transfer of each Data Word has been completed, the value of the address bus outputs CWC4 through CWC0 is incremented.
RT ADDRESS
RT Address 4-0 (RT_AD_4 = MSB) and RT Address Parity (RT_AD_P) should be programmed for a unique RT address and reflect an odd parity sum. The SSRT Mark3 will not respond to any MIL-STD-1553 commands or transfer received data from any non-broadcast messages if an odd parity sum is not presented by RT_AD_4-0 and RT_AD_P. An address parity error will be indicated by a low output on the RT_AD_ERR pin. The input signal RT_AD_LAT operates a transparent latch for RTAD4RTAD0 and RTADP. If RT_AD_LAT is low, the output of the latch tracks the value presented on the input pins. If RT_AD_LAT is high, the output of the internal latch becomes latched to the val6 BU-64703 Pre-01-03/03
DMA WRITE OPERATION
In response to a receive command, the SSRT Mark3 will need to transfer data to the subsystem. There are two options for doing Data Device Corporation www.ddc-web.com
ues presented at the time of a low-to-high transition of RT_AD_LAT. RT address and RT Address Parity must be presented valid before the mid-parity crossing of the 1553 command and held, at least, until following the first received data word.
Mark3 samples BUSY approximately 2 s following the mid-parity bit zero crossing of the received Command Word. If BUSY is sampled low for a particular message, the value of the busy bit transmitted in the SSRT Mark3's status word will be logic "1". If BUSY is sampled high for a particular message, the value of the busy bit transmitted in the SSRT Mark3's status word will be logic "0". If the RT responds to a transmit command with a busy bit of logic "1", the status word will be transmitted, but no data words will be transmitted by the SSRT Mark3. If the SSRT Mark3 responds to a receive command with a busy bit of logic "1", data words will be transferred to the external subsystem (although these may be blocked by means of external logic). Similar to ILLEGAL, it is possible to cause the SSRT Mark3 to respond with Busy for specific command words (only), by means of an external PROM, RAM, or PLD device.
COMMAND ILLEGALIZATION
The SSRT Mark3 includes a provision for command illegalization. If a command is illegalized, the SSRT Mark3 will set the Message error bit and transmit its status word to the Bus Controller. No data words will be transmitted in response to an illegalized transmit command. However, data words associated with an illegalized receive command will be written to the external subsystem (although these transfers may be blocked using external logic). ILLEGAL is sampled approximately 2 s following the mid-parity bit zero crossing of the received command word. A low on ILLEGAL will illegalize a particular command word and cause the SSRT Mark3 to respond with its Message error bit set in its status word. Command illegalization based on broadcast, T/R bit, subaddress, and/or word count/mode code may be implemented by means of an external PROM, PLD, or RAM device, as shown in Figure 2. The external device may be used to define the legality of specific commands. Any subset of the possible 1553 commands may be illegalized as a function of broadcast, T/R bit, subaddress, word count, and/or mode code. The output of the illegalization device should be tied directly to the SSRT Mark3's ILLEGAL signal input. The maximum access time of the external illegalizing device is 400 ns. If illegalization is not used, ILLEGAL should be hardwired to logic "1".
TRANSMIT COMMAND (RT-TO-BC TRANSFER)
If the SSRT Mark3 receives a valid Transmit command word that the subsystem determines is legal (input signal ILLEGAL is high) and the subsystem is not BUSY (input signal BUSY is high), the SSRT Mark3 will initiate a transmit data response following transmission of its status word. This entails a handshake/read cycle for each data word transmitted, with the number of data words to be transmitted specified by the word count field of the transmit command word. If ILLEGAL is sampled low, the Message Error bit will be set in the SSRT Mark3's status word. No data words will be transmitted following transmission of the status word to an illegalized transmit command. A low on the BUSY input will set the busy bit in the Status Word; in this instance, only the status word will be transmitted, with no data words.
BUSY
The external subsystem may control the SSRT Mark3's Busy RT status word bit by means of the BUSY input signal. The SSRT
RECEIVE COMMAND (BC-TO-RT TRANSFER)
In non-burst mode, a DMA handshake will be initiated for each data word received from the 1553 data bus. If successful, the
L-BRO
A 11
T/R
A 10
SA4 SA3 SA2 SA1 SA0
A9 A8 A7 A6 A5
PROM / RAM / PLD (4Kx1) (400ns max)
BU - 64703
WC/MC/CWC4 A4 A3 A2 A1 A0 D0
"SSRT Mark3"
WC/MC/CWC3 WC/MC/CWC2 WC/MC/CWC1 WC/MC/CWC0
IL L E G A L
FIGURE 2. SSRT Mark3 ILLEGALIZATION
Data Device Corporation www.ddc-web.com 7 BU-64703 Pre-01-03/03
respective handshake will be followed by a corresponding write cycle. A handshake timeout will not terminate transfer attempts for the remaining data words, error flagging or Status Word transmission. After the reception of a valid non-mode code receive Command Word followed by the correct number of valid Data Words and assuming that all words are successfully transferred to the subsystem, a negative pulse will be asserted on the Good Block Received (GBR) output. The width of this pulse is two clock cycles. In burst mode, a DMA handshake will not be initiated until after all data words have been received over the 1553 data bus and stored into the SSRT Mark3's internal FIFO. After the handshake has been negotiated, the SSRT Mark3 will burst the contents of the FIFO to the local bus (D0-D15). After the reception of a valid non-mode code receive command word followed by the correct number of valid data words and assuming that all words are successfully transferred to the subsystem, a negative pulse will be asserted on the output Good Block Received (GBR). The width of this pulse is two clock cycles.
Following the last data word transfer for a valid non-mode code receive message (for either non-burst mode or burst mode), GBR will be asserted low for two clock cycles. MSG_ERR is asserted as a low output level following any detected error in a received message, except for an error in the command word. If an error is detected in a received command word, the rest of the message will be ignored. If MSG_ERR and/or HS_FAIL have been asserted (low), they will be cleared to logic "1" following receipt of a subsequent valid command word.
LOOPBACK TEST
The SSRT Mark3 performs a loopback self-test at the end of each non-broadcast message processed. The loopback test consists of the following verifications: (1) The received version of every transmitted word is verified for validity (encoding, bit count, parity) and correct sync type; and (2) The received version of the last transmitted word is verified by means of a bit-by-bit comparison to the transmitted version of this word. If there is a transmitter timeout (660.5 s) and/or if the loopback test fails for one or more transmitted words, the Terminal flag status word bit will be set in response to the next non-broadcast message. Note that the setting of the Terminal flag status bit following a loop test failure may be disabled by means of the Auto-Config feature; i.e., by setting Auto-Config bit 4 to logic "0".
RT-TO-RT TRANSFER ERRORS
For the case where the SSRT Mark3 is the receiving RT of an RT-to-RT transfer, if the transmitting RT does not respond within the specified time period, the SSRT Mark3 will determine that a timeout condition has occurred. The value of the SSRT Mark3's RT-to-RT timeout timer is in the range from 17.5 to 18.5 s, and is specified from the mid-parity bit crossing of the transmit command word to the mid-sync crossing of the transmitting RT's status word. In the case of an RT-to-RT timeout, the SSRT Mark3 will not respond and the RT-to-RT NO TRANSFER TIMEOUT bit (bit 2) of the SSRT Mark3's BIT Word will be set to logic "1". Also, if the SSRT Mark3 is the receiving RT for an RT-to-RT transfer, and the T/R bit of the second command word is logic "0", or the RT address field for the transmit command is the same as for the receive command, or the subaddress for the transmit command is 00000 or 11111, the SSRT Mark3 will not respond, and will set the RT-to-RT SECOND COMMAND ERROR bit (bit 1) of the RT BIT word to logic "1".
STATUS WORD
The Broadcast Command Received bit is formulated internally by the SSRT Mark3. The Message Error Status bit will be set if the current command is a Transmit Status Word or Transmit Last Command mode command if there was an error in the data portion of the previous receive message. Message Error will also be set if ILLEGAL has been sampled low by the SSRT Mark3 for the current message. ILLEGAL, SRV_RQST, BUSY, and SSFLAG (Subsystem Flag) will be sampled from their respective Status input pins approximately 2 s following the mid-parity bit zero crossing of the received Command Word. This time is 400 ns maximum following after the L_BRO, T/R, SA4-0, and WC/MC/CWC4-0 outputs have been presented valid.
RT STATUS, ERROR HANDLING, AND MESSAGE TIMING SIGNALS
Message transfers and transfer errors are indicated by means of the INCMD, HS_FAIL, MSG_ERR, and RTFAIL error indication outputs. Additional error detection and indication mechanisms include updating of the internal command, RT status and BIT word registers. The SSRT Mark3 provides a number of timing signals during the processing of 1553 messages. INCMD is asserted low when a new command is received. At the end of a message (either valid or invalid), INCMD transitions from low to high. As discussed above, HS_FAIL will be asserted low if the subsystem fails to respond to DTREQ within the maximum amount of time (10 s). Data Device Corporation www.ddc-web.com
PROTOCOL SELF-TEST
The SSRT Mark3 includes a comprehensive, autonomous offline self-test of its internal protocol logic. The test includes a comprehensive test of all registers, Manchester encoder and decoders, transmitter failsafe timer, protocol logic, and the internal FIFO. This test is completed in approximately 32,000 clock cycles. That is, about 1.6 ms with a 20 MHz clock, 2.0 ms at 16 MHz, 2.7 ms at 12 MHz, and 3.2 ms at 10 MHz. While the SSRT Mark3 is performing its off-line self-test, it will ignore (and therefore not respond to) all messages received from the 1553 bus. Unless disabled by means of the SSRT Mark3's Auto-Config feature, the protocol self-test will be performed following the SSRT 8 BU-64703 Pre-01-03/03
Mark3's power turn-on (i.e., when MSTCLR is released high). If the Auto-Config feature is used and Auto-Config bit 5 is set to logic "0", then a failure of the protocol self-test following power turn-on will result in the SSRT Mark3 not going online. If bit 5 is set to logic "0" and the protocol self-test passes following power turn-on, the SSRT Mark3 will go online. The protocol self-test will also be performed following receipt of an Initiate self-test mode command from the 1553 bus. If an Initiate self-test mode command is received by the SSRT Mark3, and Auto-Config bit 5 is set to logic "0", then a failure of the protocol self-test following will result in the SSRT Mark3 going offline. If the protocol self-test fails: (1) the Terminal Flag bit will be set to logic "1" in the SSRT Mark3 status word; (2) bit 8 in the SSRT Mark3's BIT word, BIT Test Fail, will be set to logic "1"; (3) the SSRT Mark3's RTFAIL output will be asserted to logic "0".
TABLE 2. AUTO-CONFIGURATION PARAMETERS
BIT FUNCTION DESCRIPTION If logic "0", the RT will become enabled only if the self-test passes. If auto-config is not used, or if this bit is logic "1", or if the power-up self-test passes, then the RT will go online following self-test. If the loop test fails for a particular message, the Terminal flag bit will be set in the SSRT Mark3's status response for the subsequent non-broadcast message. In MIL-STD-1553B mode, subaddress 31 is a mode code subaddress, and mode codes are implemented in full accordance with MIL-STD-1553B. In MIL-STD-1553A mode, subaddress 31 is a non-mode code subaddress, and no data words are transmitted or anticipated to be received for mode code messages. Subaddress 30 wraparound is enabled. That is, the data words for a receive message to subaddress 30 are stored in the internal FIFO, and not transferred to the external system. For a subsequent transmit message to subaddress 30, the transmitted data words are read from the internal FIFO, rather than from the external system. Enables burst mode (using the internal FIFO) for received data words. In burst mode, for a receive message, all data words are transferred to the external system in a contiguous burst following reception of the last data word. If enabled, the SSRT Mark3 will perform self-test following the rising edge of MSTCLR.
5
RT GOES ONLINE IF SELF-TEST FAILS
4
RTFAIL-to-TERMINAL FLAG AUTO-WRAP
3
MIL-STD-1553A/B (-B is logic "1", or the default).
AUTO-CONFIGURATION
The SSRT Mark3 includes an auto-configuration feature, which allows various optional features to be enabled or disabled. Autoconfiguration may be enabled or disabled by means of the input signal AUTO_CFG. If AUTO_CFG is connected to logic "1", then the auto-configure option is disabled, and the six configuration parameters revert to their default values. Note that the default condition for each configuration parameter is enabled (for the MIL-STD-1553A/B protocol selection, 1553B is the default). If AUTO_CFG is connected to logic "0", then the configuration parameters are transferred over D5-D0 by means of a DMA read data transfer. The transfer occurs during the time that the RTACTIVE and DTACK outputs are logic "0", following MSTCLR transitioning from logic "0" to logic "1" and a successful DT_REQ-to-DTGRT handshake. Note that if DTGRT is hardwired to logic "0", the handshake process is not necessary (i.e., DTACK and RTACTIVE will both be asserted to logic "0" one clock cycle following DT_REQ). Each of the configuration parameters is enabled if the SSRT Mark3 reads a value of logic "1" for the respective data bit. The auto-configuration parameters are defined by TABLE 2. The timing signals pertaining to Auto-Configuration mode are illustrated in Figure 12.
2
SUBADDRESS 30 WRAPAROUND
1
BURST MODE
0
POWER-UP SELFTEST ENABLE
TABLE 3. CLOCK FREQUENCY SELECTION
CLK_SEL_1 0 0 1 1 CLK_SEL_0 0 1 0 1 CLOCK FREQUENCY 10 MHz 20 MHz 12 MHz 16 MHz
CLOCK INPUT
The SSRT Mark3 may be operated from one of four clock frequencies: 10, 12, 16, or 20 MHz. The selected clock frequency must be designated by means of the input signals CLK_SEL_1 and CLK_SEL_0, as shown in TABLE 3.
Data Device Corporation www.ddc-web.com
9
BU-64703 Pre-01-03/03
MID-PARITY
MID-PARITY DATA #1
MID-PARITY
MID-SYNC
MID-PARITY STATUS
t9 1553 BUS
RX COMMAND DATA #2
t1 L-BRO, T/R, SA4-SA0 t7 WC/MC/CWC
PREVIOUS MSG WC / MC 1F CWC = 0
t10
CWC = 1
ILLEGAL, SRV_RQST SSFLAG, BUSY
t4
VALID
t8
t6
cwc t13
WC / MC
t5
INCMD GBR DTREQ DTGRT DTACK D15-D0 MEMWR MEMOE t2
t15
NOTE 1
t14 t11
BURST DATA WRITE TRANSFER
(Refer to FIGURE 9)
t12 RT_FAIL
t3
MSG_ERR HS_FAIL
RT RECEIVE COMMAND (BURST MODE) NOTE 1 : If the RX message is a Broadcast message then the rising edge of INCMD is referenced from the rising edge of GBR.
FIGURE 3. RT RECEIVE COMMAND (BURST MODE) TIMING
Data Device Corporation www.ddc-web.com BU-64703 Pre-01-03/03
10
TABLE FOR FIGURE 3. RT RECEIVE COMMAND TIMING (BURST MODE)
REF t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 DESCRIPTION Mid-parity crossing of received command word delay to SA4-SA0, L-BRO, T/R Bit, and WC/MC valid Mid-parity crossing of received command word delay to falling edge of INCMD Mid-parity crossing of received command word delay to MSG_ERR and HS_FAIL rising ILLEGAL, SRV_RQST, SSFLAG, BUSY input access time from SA4-SA0, L-BRO, T/R, and CWC/MC valid L_BRO, T/R, SA4-0, and WC/MC4-0 valid prior to INCMD low. ILLEGAL, SRV_RQST, SSFLAG, BUSY hold time following falling edge of INCMD Mid-parity crossing of first data word to WC/CWC valid data of 1Fh Duration of WC/CWC data value of 1Fh RT Response time. CWC transition to next word following mid-parity of subsequent received data words. Mid-parity crossing of last data word to DTREQ falling edge (requesting data word burst write transfer) Mid-Sync crossing of Status response to RT_FAIL rising CWC valid following falling edge of DTREQ CLOCK FREQUENCY ALL ALL ALL ALL ALL ALL ALL ALL ALL ALL ALL ALL ALL 20 16 12 10 MHz MHz MHz MHz 100 125 167 200 3 4 4 500 300 1 200 6.5 1 4.5 1.5 30 5.25 7 RESPONSE TIME MIN TYP 1.5 2 1.5 400 MAX UNITS s s s ns ns ns s ns s s s s ns ns ns ns ns s
t14
GBR pulse width (see Note 1)
t15
Mid-parity crossing of status word to INCMD rising
ALL
NOTE: (1) If the RX message is a Broadcast message then the rising edge of INCMD is referenced from the rising edge of GBR.
Data Device Corporation www.ddc-web.com
11
BU-64703 Pre-01-03/03
MID-PARITY
MID-PARITY DATA #1
MID-PARITY
MID-SYNC
MID-PARITY STATUS
t11 1553 BUS
RX COMMAND DATA #2
t1 L-BRO, T/R, SA4-SA0 t7 WC/MC/CWC
PREVIOUS MSG WC / MC 1F CWC = 0 CWC = 1
t15
WC / MC
ILLEGAL, SRV_RQST SSFLAG, BUSY
t4
VALID
t9
t6 t2 t8 t17 t12 t13 t14
t5
INCMD GBR DTREQ DTGRT DTACK D15-D0 MEMWR MEMOE RT_FAIL
t10
SINGLE WORD WRITE DATA WORD #1
SINGLE WORD WRITE DATA WORD #2
(Refer to FIGURE 10)
t3
MSG_ERR HS_FAIL
t16
RT RECEIVE COMMAND (NON-BURST MODE)
FIGURE 4. RT RECEIVE COMMAND (NON-BURST MODE) TIMING
Data Device Corporation www.ddc-web.com BU-64703 Pre-01-03/03
12
TABLE FOR FIGURE 4. RT RECEIVE COMMAND TIMING (NON-BURST MODE)
REF t1 t2 t3 t4 t5 t6 t7 DESCRIPTION Mid-parity crossing of received command word delay to SA4-SA0, L-BRO, T/R Bit, and WC/MC valid Mid-parity crossing of received command word delay to falling edge of INCMD Mid-parity crossing of received command word delay to MSG_ERR and HS_FAIL rising ILLEGAL, SRV_RQST, SSFLAG, BUSY input access time from SA4-SA0, L-BRO, T/R, and CWC/MC valid RT Sub-Address, L-BRO, and T/R Bit setup time prior to INCMD low ILLEGAL, SRV_RQST, SSFLAG, BUSY valid time following falling edge of INCMD Mid-parity crossing to WC/CWC value of 1Fh CLOCK FREQUENCY ALL ALL ALL ALL ALL ALL ALL 20 16 12 10 20 16 12 10 MHz MHz MHz MHz MHz MHz MHz MHz 500 300 1 1.2 1.25 1.33 1.4 200 250 333 400 30 4 4 1 100 125 167 200 75 94 125 150 1.5 3.0 6.5 7 RESPONSE TIME MIN TYP 1.5 2 1.5 400 MAX UNITS s s s ns ns ns s s s s s ns ns ns ns ns s s s ns ns ns ns ns ns ns ns s s
t8
Mid-parity crossing of first data word to DTREQ falling edge
t9
WC/CWC data value of 1Fh held
t10 t11 t12 t13
CWC valid following falling edge of DTREQ RT Response time. Delay from following mid-parity of last received data word to GBR low. (see Notes 1, 2) Mid-parity crossing of all data words, except first data word, to DTREQ falling edge GBR pulse width
ALL ALL ALL ALL 20 16 12 10 20 16 12 10 MHz MHz MHz MHz MHz MHz MHz MHz
t14
t15
CWC transition to WC prior to Mid-Sync crossing of Status response.
t16 t17
Mid-Sync crossing of status response to RT_FAIL rising Mid-parity crossing of status word to INCMD rising
ALL ALL
NOTES: (1) Assumes that DTGRT is tied to logic "0". If DTGRT is not connected to logic "0", the minimum time to drive GBR active low will increase by the amount of the DTGRT (low) - to - DTGRT (low) delay. The transceiver delays are measured at a range of 150ns to 450ns for the receiver and 100ns to 250ns for the transmitter.
(2)
Data Device Corporation www.ddc-web.com
13
BU-64703 Pre-01-03/03
MID-PARITY
MID-SYNC
MID-SYNC STATUS DATA #1
MID-SYNC
MID-PARITY DATA #2
t1 1553 BUS
TX COMMAND
t2 L-BRO, T/R, SA4-SA0 t8 WC/MC/CWC
PREVIOUS MSG WC 1F CWC = 0
t14 cwc = 1
WC
t5
ILLEGAL, SRV_RQST SSFLAG, BUSY
VALID
t11 t7
t6 INCMD GBR DTREQ t3
t12
t15
t9 DTGRT DTACK D15-D0 MEMWR MEMOE t10 RT_FAIL MSG_ERR t4 HS_FAIL
SINGLE WORD READ
t13
SINGLE WORD READ
(Refer to FIGURE 11)
DATA WORD #1 DATA WORD #2
RT TRANSMIT COMMAND
FIGURE 5. RT TRANSMIT COMMAND TIMING
Data Device Corporation www.ddc-web.com BU-64703 Pre-01-03/03
14
TABLE FOR FIGURE 5. RT TRANSMIT COMMAND TIMING
REF t1 t2 t3 t4 t5 t6 t7 t8 RT Response time. Mid-parity crossing of received command word delay to L-BRO, T/R Bit, SA4-SA0, and WC/MC valid Mid-parity crossing of received command word delay to falling edge of INCMD Mid-Parity crossing of receive command word delay to MSG_ERR and HS_FAIL rising ILLEGAL, SRV_RQST, SSFLAG, BUSY input access time from SA4-SA0, L-BRO, T/R Bit, and CWC/MC valid L-BRO, T/R, SA4-0, and WC/MC4-0 setup time prior to INCMD low ILLEGAL, SRV_RQST, SSFLAG, BUSY hold time following falling edge of INCMD Mid-Sync crossing of status word to WC/CWC valid data of 1Fh DESCRIPTION CLOCK FREQUENCY ALL ALL ALL ALL ALL ALL ALL ALL 20 16 12 10 MHz MHz MHz MHz 500 300 6.5 6.75 6.81 6.92 7 1.5 200 250 333 400 30 1.75 1.81 1.92 2 1.55 1.56 1.59 1.6 3 VALUE MIN 4 TYP 6.5 1.5 2 1.5 400 MAX 7 UNITS s s s s ns ns ns s s s s s s ns ns ns ns ns s s s s s s s s s
t9
Mid-Sync crossing of status word to DTREQ falling edge
t10
Mid-Sync crossing of Status response to RT_FAIL rising (see Note 1)
ALL 20 16 12 10 MHz MHz MHz MHz
t11
Duration of WC/CWC value of 1Fh
t12
CWC valid following falling edge of DTREQ
ALL 20 16 12 10 20 16 12 10 MHz MHz MHz MHz MHz MHz MHz MHz
t13
Mid-Sync crossing of received data word to DTREQ falling edge
t14
Mid-Sync crossing of last received data word for CWC to transition to WC
t15
Mid-Parity crossing of status word to INCMD rising
ALL
NOTE: (1) Assuming that RTFAIL was previously low.
Data Device Corporation www.ddc-web.com
15
BU-64703 Pre-01-03/03
MID-PARITY
MID-SYNC
MID-SYNC
MID-SYNC
MID-PARITY STATUS
t1 1553 BUS
RX COMMAND TX COMMAND STATUS DATA #1 DATA #2
t2 L-BRO, T/R, SA4-SA0 t8 WC/MC/CWC
ILLEGAL, SRV_RQST SSFLAG, BUSY
PREVIOUS MSG WC 1F CWC = 0
t14 cwc = 1
WC
t5
VALID
t11 t7
t6 INCMD GBR DTREQ t3
t12
t15
t9 DTGRT DTACK D15-D0 MEMWR MEMOE t10 RT_FAIL MSG_ERR t4 HS_FAIL
SINGLE WORD READ
t13
SINGLE WORD READ DATA WORD #2
DATA WORD #1
(Refer to FIGURE 11)
RT - RT TRANSMIT COMMAND
FIGURE 6. RT - RT TRANSMIT TIMING
Data Device Corporation www.ddc-web.com BU-64703 Pre-01-03/03
16
TABLE FOR FIGURE 6. RT-RT TRANSMIT COMMAND TIMING
REF t1 t2 t3 t4 t5 t6 t7 t8 DESCRIPTION RT - RT response timeout for transmitting RT. Mid-parity crossing of received command word delay to L-BRO, T/R Bit, SA4-SA0, and WC/MC valid Mid-parity crossing of received command word delay to falling edge of INCMD Mid-Parity crossing of received command word delay to MSG_ERR and HS_FAIL rising ILLEGAL, SRV_RQST, SSFLAG, BUSY input access time from SA4-SA0, L-BRO, T/R, and CWC/MC valid L-BRO, T/R, SA4-0, and WC/MC4-0 setup time prior to INCMD low ILLEGAL, SRV_RQST, SSFLAG, BUSY hold time following falling edge of INCMD Mid-Sync crossing of status word to WC/CWC valid data of 1Fh CLOCK FREQUENCY ALL ALL ALL ALL ALL ALL ALL ALL 20 16 12 10 MHz MHz MHz MHz 500 300 6.5 6.75 6.81 6.92 7 1.5 200 250 333 400 30 1.75 1.81 1.92 2 1.55 1.56 1.59 1.6 3 VALUE MIN 17.5 TYP 18.5 1.5 2 1.5 400 MAX 19.5 UNITS s s s s ns ns ns s s s s s s ns ns ns ns ns s s s s s s s s s
t9
Mid-Sync crossing of status word to DTREQ falling edge
t10
Mid-Sync crossing of Status response to RT_FAIL rising
ALL 20 16 12 10 MHz MHz MHz MHz
t11
Duration of WC/CWC value of 1Fh
t12
CWC valid following falling edge of DTREQ
ALL 20 16 12 10 20 16 12 10 MHz MHz MHz MHz MHz MHz MHz MHz
t13
Mid-Sync crossing of received data word to DTREQ falling edge
t14
Mid-Sync crossing of last received data word for CWC to transition to WC
t15
Mid-Parity crossing of status word to INCMD rising
ALL
Data Device Corporation www.ddc-web.com
17
BU-64703 Pre-01-03/03
MID-PARITY
MID-PARITY
MID-SYNC
MID-PARITY DATA #1
MID-PARITY
MID-SYNC
MID-PARITY STATUS
t7 1553 BUS L-BRO, T/R, SA4-SA0 WC/MC/CWC
PREVIOUS MSG WC / MC
t10
STATUS DATA #2
RX COMMAND
TX COMMAND
t1
t8
1F CWC = 0
t11
CWC = 1
ILLEGAL, SRV_RQST SSFLAG, BUSY
t4
VALID
t9 t6
cwc t14
WC / MC
t5 INCMD GBR DTREQ DTGRT DTACK D15-D0 MEMWR t2
t16
NOTE 1
t15 t12
BURST DATA WRITE TRANSFER
(Refer to FIGURE 9)
MEMOE t13 RT_FAIL t3 MSG_ERR HS_FAIL
RT - RT RECEIVE COMMAND (BURST MODE) NOTE 1 : If the RX message is a Broadcast message then the rising edge of INCMD is referenced from the rising edge of GBR.
FIGURE 7. RT - RT RECEIVE (BURST-MODE) TIMING
Data Device Corporation www.ddc-web.com BU-64703 Pre-01-03/03
18
TABLE FOR FIGURE 7. RT-RT RECEIVE COMMAND TIMING (BURST MODE)
REF t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 DESCRIPTION Mid-parity crossing of received command word delay to SA4-SA0, L-BRO, T/R Bit, and WC/MC valid Mid-parity crossing of received command word delay to falling edge of INCMD Mid-parity crossing of received command word delay to MSG_ERR and HS_FAIL rising ILLEGAL, SRV_RQST, SSFLAG, BUSY input access time from SA4-SA0, L-BRO, T/R, and CWC/MC valid L_BRO, T/R, SA4-0, and WC/MC4-0 valid prior to INCMD low. ILLEGAL, SRV_RQST, SSFLAG, BUSY hold time following falling edge of INCMD RT - RT response timeout for transmitting RT. Mid-parity crossing of first data word to WC/CWC valid data of 1Fh Duration of WC/CWC data value of 1Fh RT Response time. CWC transition to next word following mid-parity of subsequent received data words. Mid-parity crossing of last data word to DTREQ falling edge (requesting data word burst write transfer) Mid-Sync crossing of Status response to RT_FAIL rising CWC valid following falling edge of DTREQ CLOCK FREQUENCY ALL ALL ALL ALL ALL ALL ALL ALL ALL ALL ALL ALL ALL ALL 20 16 12 10 MHz MHz MHz MHz 100 125 167 200 3 4 4 500 300 17.5 18.5 1 200 6.5 1 4.5 1.5 30 5.25 7 19.5 RESPONSE TIME MIN TYP 1.5 2 1.5 400 MAX UNITS s s s ns ns ns s s ns s s s s ns ns ns ns ns s
t15
GBR pulse width (see Note 1)
t16
Mid-parity crossing of status word to INCMD rising
ALL
NOTE: (1) If the RX message is a Broadcast message then the rising edge of INCMD is referenced from the rising edge of GBR.
Data Device Corporation www.ddc-web.com
19
BU-64703 Pre-01-03/03
MID-PARITY
MID-PARITY
MID-SYNC
MID-PARITY DATA #1
MID-PARITY
MID-SYNC
MID-PARITY STATUS
t7
t12
STATUS DATA #2
1553 BUS
RX COMMAND
TX COMMAND
t1 L-BRO, T/R, SA4-SA0 WC/MC/CWC
PREVIOUS MSG WC / MC
t8
1F CWC = 0 CWC = 1
t16
WC / MC
ILLEGAL, SRV_RQST SSFLAG, BUSY
t4
VALID
t10
t6 t2 t18 t13 t9 t14 t15
t5
INCMD GBR DTREQ DTGRT DTACK D15-D0 MEMWR
t11
SINGLE WORD WRITE DATA WORD #1
SINGLE WORD WRITE DATA WORD #2
(Refer to FIGURE 10)
MEMOE RT_FAIL
t3
MSG_ERR HS_FAIL
t17
RT - RT RECEIVE COMMAND (NON-BURST MODE)
FIGURE 8. RT - RT RECEIVE (NON-BURST-MODE) TIMING
Data Device Corporation www.ddc-web.com BU-64703 Pre-01-03/03
20
TABLE FOR FIGURE 8. RT-RT RECEIVE COMMAND TIMING (NON-BURST MODE)
REF t1 t2 t3 t4 t5 t6 t7 t8 DESCRIPTION Mid-parity crossing of received command word delay to SA4-SA0, L-BRO, T/R Bit, and WC/MC valid Mid-parity crossing of received command word delay to falling edge of INCMD Mid-parity crossing of receive command word delay to MSG_ERR and HS_FAIL rising ILLEGAL, SRV_RQST, SSFLAG, BUSY input access time from SA4-SA0, L-BRO, T/R, and CWC/MC valid RT Sub-Address, L-BRO, and T/R Bit setup time prior to INCMD low ILLEGAL, SRV_RQST, SSFLAG, BUSY valid time following falling edge of INCMD RT - RT response timeout for transmitting RT. Mid-parity crossing to WC/CWC value of 1Fh CLOCK FREQUENCY ALL ALL ALL ALL ALL ALL ALL ALL 20 16 12 10 20 16 12 10 MHz MHz MHz MHz MHz MHz MHz MHz 500 300 17.5 18.5 1 1.2 1.25 1.33 1.4 200 250 333 400 30 4 4 1 100 125 167 200 75 94 125 150 1.5 3.0 6.5 7 19.5 RESPONSE TIME MIN TYP 1.5 2 1.5 400 MAX UNITS s s s ns ns ns s s s s s s ns ns ns ns ns s s s ns ns ns ns ns ns ns ns s s
t9
Mid-parity crossing of first data word to DTREQ falling edge
t10
WC/CWC data value of 1Fh held
t11 t12 t13 t14
CWC valid following falling edge of DTREQ RT Response time. Delay from following mid-parity of last received data word to GBR low. (see Notes 1, 2) Mid-parity crossing of all data words, except first data word, to DTREQ falling edge GBR pulse width
ALL ALL ALL ALL 20 16 12 10 20 16 12 10 MHz MHz MHz MHz MHz MHz MHz MHz
t15
t16
CWC transition to WC prior to Mid-Sync crossing of Status response.
t17 t18
Mid-Sync crossing of status response to RT_FAIL rising Mid-parity crossing of status word to INCMD rising
ALL ALL
NOTES: (1) Assumes that DTGRT is tied to logic "0". If DTGRT is not connected to logic "0", the minimum time to drive GBR active low will increase by the amount of the DTGRT (low) - to - DTGRT (low) delay. The transceiver delays are measured at a range of 150ns to 450ns for the receiver and 100ns to 250ns for the transmitter.
(2)
Data Device Corporation www.ddc-web.com
21
BU-64703 Pre-01-03/03
CLOCK IN t1 t2 DTREQ DTGRT t6 DTACK t5 MEMWR MEMOE L-BRO, T/R, SA4-SA0 t3 WC/MC/CWC t7 D15-D0 t10 GBR
1
t17 t4 t8 t9 t11 t12 t13 t11 t12 t13
VALID
t15
CWC = 0
t7
CWC = 1 WC
t14
DATA VALID
t16
DATA VALID
t14 t18 t19 t20 t21
t10
INCMD
DMA WRITE - BURST MODE (SHOWN FOR TWO DATA WORDS)
1
INCMD rising edge is shown for the case of a RX Broadcast command message. For the non-Broadcast case, INCMD rising edge is after the Mid-Parity crossing of the RT STATUS response.
FIGURE 9. DMA WRITE TRANSFER (BURST-MODE) TIMING
Data Device Corporation www.ddc-web.com BU-64703 Pre-01-03/03
22
TABLE FOR FIGURE 9. SSRT Mark3 DMA WRITE (BURST MODE) TIMING
REF t1 t2 DESCRIPTION CLOCK IN rising to DTREQ low DTREQ falling to DTGRT low CWC setup time prior to MEMWR falling for first word of burst transfer (see Note 1) DTGRT low setup prior to CLOCK IN rising edge CLOCK FREQUENCY ALL ALL 20 16 12 10 20 16 12 10 MHz MHz MHz MHz MHz MHz MHz MHz 60 85 127 160 15 105 118 138 155 40 40 30 290 365 490 590 10 22 43 60 40 52.5 73.3 90 10 23 43 60 15 10 23 43 60 40 40 40 90 115 157 190 100 125 167 200 40 300 375 500 600 VALUE @3.3 VOLTS MIN TYP MAX 40 10 UNITS ns s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 40 50 62.5 83.3 100 40 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
t3
t4
ALL
t5
DTGRT falling to DTACK low
t6 t7 t8
CLOCK IN rising to DTACK low Data output valid following CLOCK IN DTGRT hold time following DTACK falling DTACK low pulse width (based on a two data word transfer) (see Note 2)
ALL ALL ALL 20 16 12 10 20 16 12 10 20 16 12 10 20 16 12 10 20 16 12 10 MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz
t9
t10
Data output setup time prior to MEMWR low
t11
CLOCK IN rising to MEMWR low
ALL
t12
MEMWR low pulse width
t13
CLOCK IN rising to MEMWR high
ALL
t14
Data output and CWC hold time following MEMWR high
t15
Data output hold time following CLOCK IN rising
ALL
t16
CWC (all but first data word) setup time prior to MEMWR low
t17 t18 t19
CLOCK IN rising to DTREQ and DTACK high Data output signal Tri-State following CLOCK IN rising CLOCK IN rising to GBR falling edge
ALL ALL ALL 20 16 12 10 MHz MHz MHz MHz
t20
GBR low pulse width
t21
INCMD rising following CLOCK IN rising (see Note 3)
ALL
NOTES: (1) Assumes DTGRT is low at the time that DTREQ is asserted low. If not, then this time will increase by the amount of the DTREQ (low) - to - DTGRT (low) delay. (2) (3) DTACK pulse width is 3 clock cycles per data word transfer. Rising edge of INCMD will immediately follow the rising edge of GBR only for a broadcast message. For a non-broadcast message, the rising edge of INCMD will occur after the mid-parity crossing of the RT status response. This additional delay time is approximately 96 clock cycles: 9.6 s at 10 MHz, 8 s at 12 MHz, 6.0 s at 16 MHz, or 4.8 s at 20 MHz.
Data Device Corporation www.ddc-web.com
23
BU-64703 Pre-01-03/03
CLOCK IN t1 t2 DTREQ DTGRT t6 DTACK t5 MEMWR MEMOE L-BRO, T/R, SA4-SA0 WC/MC/CWC t7 D15-D0 t10
DATA VALID VALID
t15 t4 t8 t9 t11 t12 t13
t3
CWC = 0
t16 t14
t17
NON-BURST DMA WRITE NOTE: With the DTGRT pin tied to GND, the time from DTREQ to DTACK is 1 clock cycle.
FIGURE 10. DMA WRITE TRANSFER (NON-BURST-MODE) TIMING
Data Device Corporation www.ddc-web.com BU-64703 Pre-01-03/03
24
TABLE FOR FIGURE 10. SSRT Mark3 DMA WRITE TIMING (NON-BURST)
REF t1 t2 DESCRIPTION CLOCK IN rising to DTREQ low DTREQ (low) - to - DTGRT (low) delay time CWC setup time prior to MEMWR falling (see Note) DTGRT low setup prior to CLOCK IN rising CLOCK FREQUENCY ALL ALL 20 16 12 10 20 16 12 10 MHz MHz MHz MHz MHz MHz MHz MHz 110 148 210 260 15 105 118 138 155 40 40 30 200 250 333 400 60 85 127 160 40 40 52.5 73.3 90 10 23 43 60 40 15 40 50 62.5 83.3 100 40 VALUE @3.3 VOLTS MIN TYP MAX 40 10 UNITS ns s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
t3
t4
ALL
t5
DTGRT falling to DTACK low
t6 t7 t8
CLOCK IN rising to DTACK low Data output valid following CLOCK IN rising DTGRT hold time following DTACK falling
ALL ALL ALL 20 16 12 10 20 16 12 10 20 16 12 10 20 16 12 10 MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz
t9
DTACK low pulse width
t10
Data output setup time prior to MEMWR low
t11
CLOCK IN rising to MEMWR low
ALL
t12
MEMWR low pulse width
t13
CLOCK IN rising to MEMWR high
ALL
t14
Data output hold time following MEMWR high
t15 t16 t17 NOTES: (1)
CLOCK IN rising to DTREQ and DTACK high Data output hold time following CLOCK IN rising Data output signal Tri-State following CLOCK IN rising
ALL ALL ALL
Assumes that DTGRT is low at the time DTREQ is asserted low. If not, these values can increase by the delay time from DTREQ (low) - to - DTGRT (low).
Data Device Corporation www.ddc-web.com
25
BU-64703 Pre-01-03/03
CLOCK IN t1 t2 DTREQ t4 DTGRT t6 DTACK t5 MEMWR t9 MEMOE L-BRO, T/R, SA4-SA0 WC/CWC
VALID
t13 t7 t8
t10
t3
CWC = 0
t11 D15-D0
t12
DATA VALID
DMA SINGLE WORD READ
FIGURE 11. DMA READ TRANSFER TIMING
Data Device Corporation www.ddc-web.com BU-64703 Pre-01-03/03
26
TABLE FOR FIGURE 11. SSRT Mark3 DMA READ TIMING
REF t1 t2 DESCRIPTION CLOCK IN rising to DTREQ low DTREQ (low) - to - DTGRT delay time CLOCK FREQUENCY ALL ALL 20 16 12 10 MHz MHz MHz MHz 60 85 127 160 10 105 118 138 155 40 30 200 250 333 400 40 150 188 250 300 70 95 136 170 30 40 VALUE @3.3 VOLTS MIN TYP MAX 40 10 UNITS ns s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
t3
CWC setup time prior to MEMOE falling
t4
DTGRT low setup prior to CLOCK IN rising
ALL 20 16 12 10 MHz MHz MHz MHz
t5
DTGRT falling to DTACK low
t6 t7
CLOCK IN rising to DTACK low DTGRT hold time following DTACK falling
ALL ALL 20 16 12 10 MHz MHz MHz MHz
t8
DTACK low pulse width
t9
CLOCK IN rising to MEMOE low
ALL 20 16 12 10 20 16 12 10 MHz MHz MHz MHz MHz MHz MHz MHz
t10
MEMOE low pulse width
t11
Time for input data to become valid following falling edge of MEMOE
t12 t13
Data input hold time following CLOCK IN rising (see Note) CLOCK IN rising to DTREQ, DTACK, and MEMOE high
ALL ALL
NOTE: (1) The SSRT Mark3's data sampling time occurs one clock cycle prior to the rising edge of MEMOE.
Data Device Corporation www.ddc-web.com
27
BU-64703 Pre-01-03/03
CLOCK IN MSTCLR DTREQ DTGRT t6 DTACK t5 RTACTIVE MEMWR MEMOE t9 D15-D0 t10
DATA VALID
t2 t3 t1 t4 t7 t8
t11
t13 t12 note1
AUTO-CONFIGURATION - DMA SINGLE WORD READ Note1: RTACTIVE asserted high 1 clock following DTACK high assuming self-test is not enabled. When self-test is enabled RTACTIVE is delayed in the amount of 't12'. See the table reference for details.
FIGURE 12. AUTO-CONFIGURATION - DMA READ TRANSFER TIMING
Data Device Corporation www.ddc-web.com BU-64703 Pre-01-03/03
28
TABLE FOR FIGURE 12. AUTO-CONFIGURATION - DMA READ TIMING
REF DESCRIPTION CLOCK FREQUENCY 20 16 12 10 MHz MHz MHz MHz VALUE @3.3 VOLTS MIN 35 47.5 68.3 85 TYP 50 62.5 83.3 100 MAX 65 77.5 98.3 115 40 10 10 105 118 138 155 40 30 185 235 318 385 200 250 333 400 215 265 348 415 120 157 220 270 UNITS ns ns ns ns ns s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 40 1.6 2.0 2.7 3.2 40 ns ms ms ms ms ns
t1
MSTCLR high delay to DTREQ low
t2 t3 t4
CLOCK IN rising to DTREQ low DTREQ (low) - to - DTGRT delay time DTGRT low setup prior to CLOCK IN rising
ALL ALL ALL 20 16 12 10 MHz MHz MHz MHz
t5
DTGRT falling to DTACK low
t6 t7
CLOCK IN rising to DTACK low DTGRT hold time following DTACK falling
ALL ALL 20 16 12 10 20 16 12 10 MHz MHz MHz MHz MHz MHz MHz MHz
t8
DTACK low pulse width
t9
Time for input data to become valid following falling edge of DTACK
t10 t11
Data input hold time following sampling time (see Note 1) CLOCK IN rising to DTREQ, DTACK, and MEMOE high
ALL ALL 20 16 12 10 MHz MHz MHz MHz
30
t12
RTACTIVE high delayed from DTACK high (see Note 2)
t13
CLOCK IN rising to RTACTIVE high
ALL
NOTES: (1) (2) During Auto-Configuration the SSRT Mark3 samples data three clock cycles following the falling edge of DTACK. If self-test mode is not enabled, then RTACTIVE will go active high 1 clock cycle following the rising edge of DTACK. If self-test is enabled then RTACTIVE will be delayed from going active high in accordance with `t12'.
Data Device Corporation www.ddc-web.com
29
BU-64703 Pre-01-03/03
CLOCK IN t1 SIGNAL IN t2 SIGNAL OUT HIGH TO LOW t3 SIGNAL OUT LOW TO HIGH
CLOCK EDGE TO SIGNAL IN / OUT TIMING
FIGURE 13. CLOCK EDGE SIGNAL TIMING
TABLE FOR FIGURE 13. SSRT Mark3 CLOCK EDGE TO SIGNAL IN / OUT VALID TIMING
REF t1 t2 t3 DESCRIPTION SIGNAL INPUT setup time prior to CLOCK IN rising edge CLOCK IN rising edge to SIGNAL OUTPUT driven low (see Note) CLOCK IN rising edge to SIGNAL OUTPUT driven high (see Note) VALUE @3.3 VOLTS MIN 15 40 40 TYP MAX UNITS ns ns ns
NOTE: (1) Assumes a 50 pf external load. For loading above 50pf, the validity of output signals is delayed by an additional 0.14 ns/pf typ, 0.28ns/pf max.
Data Device Corporation www.ddc-web.com
30
BU-64703 Pre-01-03/03
INTERFACE TO MIL-STD-1553 BUS
The SSRT Mark3 is the world's first MIL-STD-1553 terminal powered entirely by 3.3 volts. Unique isolation transformer turns ratios, single output winding transformers and new interconnection methods are required in order to meet mandated MIL-STD1553 differential voltage levels. FIGURE 14 illustrates the two possible interface methods between the SSRT Mark3 series and a MIL-STD-1553 bus. Connections for both direct (short stub, 1:3.75) and transformer (long stub, 1:2.7) coupling, as well as nominal peak-to-peak voltage levels at various points (when transmitting), are indicated in the diagram. The new isolation transformers for the SSRT Mark3 series now contain only one set of output windings. Different isolation transformers are now required for a direct or transformer coupled, MIL-STD-1553 Bus implementation. The center tap of the primary winding (the side of the transformer that connects to the SSRT Mark3) must be directly connected to the +3.3 volt plane. Additionally a 10uf, low inductance tantalum capacitor and a 0.01uf ceramic capacitor must be mounted as close as possible and with the shortest leads to the center tap of the transformer(s) and the ground plane.
3.3V 10F + .01F TX/RX (7.4 Vpp) SSRT Mark3 TX/RX 55 DIRECT-COUPLED ISOLATION TRANSFORMER BETA LVB-4103 3.3V (1:3.75) 55 28 Vpp 1 FT MAX 7 Vpp SHORT STUB (DIRECT COUPLED)
DATA BUS Z0
OR
10F + .01F TX/RX (7.4 Vpp)
(1:2.7)
LONG STUB (TRANSFORMER COUPLED) 20 FT MAX 20 Vpp
(1:1.41) 0.75 Z0 28 Vpp 7 Vpp
SSRT Mark3
TX/RX TRANSFORMER-COUPLED ISOLATION TRANSFORMER BETA LVB-4203 COUPLING TRANSFORMER
0.75 Z0
Z0
NOTES: 1. Transformer center tap capacitors: use a 10F tantalum for low inductance, and a 0.01F ceramic. Both must be mounted as close as possible, and with the shortest leads to the center tap of the transformer(s) and ground. 2. Connect the Mark3 hybrid grounds as directly as possible to the 3.3V ground plane. 3. Z0 = 70 to 85 Ohms.
FIGURE 14. SSRT Mark3 INTERFACE TO MIL-STD-1553 BUS
Data Device Corporation www.ddc-web.com 31 BU-64703 Pre-01-03/03
PULSE TRANSFORMERS
In selecting isolation transformers to be used with the SSRT Mark3 , there is a limitation on the maximum amount of leakage inductance. If this limit is exceeded, the transmitter rise and fall times may increase, possibly causing the bus amplitude to fall below the minimum level required by MIL-STD-1553. In addition, an excessive leakage imbalance may result in a transformer dynamic offset that exceeds 1553 specifications. The maximum allowable leakage inductance is a function of the coupling method. For Transformer Coupled applications, it is a maximum of 5.0 H. For Direct it is a maximum of 10.0 H, and is measured as follows: The side of the transformer that connects to the SSRT Mark3 is defined as the "primary" winding. If one side of the primary is shorted to the primary center-tap, the inductance should be measured across the "secondary" (stub side) winding. This inductance must be less than 5.0 H (Transformer Coupled) and 10.0 H (Direct Coupled). Similarly, if the other side of the primary is shorted to the primary center-tap, the inductance measured across the "secondary" (stub side) winding must also be less than 5.0 H (Transformer Coupled) and 10.0 H (Direct Coupled). The difference between these two measurements is the "differential" leakage inductance. This value must be less than 1.0 H (Transformer Coupled) and 2.0 H (Direct Coupled). Beta Transformer Technology Corporation (BTTC), a subsidiary of DDC, manufactures transformers in a variety of mechanical configurations with the required turns ratios of 1:3.75 direct coupled, and 1:2.7 transformer coupled. TABLE 4 provides a listing of many of these transformers. For further information, contact BTTC at 631-244-7393 or at www.bttc-beta.com.
TABLE 4. BTTC TRANSFORMERS FOR USE WITH SSRT Mark3
TRANSFORMER CONFIGURATION Single epoxy transformer, through-hole, transformer coupled, 0.625" X 0.630", 0.300" max height, +130 C max Single epoxy transformer, through-hole, direct coupled, 0.625" X 0.630", 0.300" max height, +130 C max Single epoxy transformer, surface mount, transformer coupled, 0.625" X 0.625", 0.130" max height, +85 C max Single epoxy transformer, surface mount, direct coupled, 0.625" X 0.625", 0.130" max height, +85 C max Single epoxy transformer, surface mount, transformer coupled, 0.625" X 0.630", 0.300" max height, +130 C max Single epoxy transformer, surface mount, direct coupled, 0.625" X 0.630", 0.300" max height, +130 C max (BTTC LEGACY PART NO.) (B-3372) (B-3383) (B-3389) (B-3390) (B-3391) (B-3392) BTTC PART NO. LVB-4203 LVB-4103 LVB-4213 LVB-4113 LVB-4223 LVB-4123
Notes: 1. SMT (Surface Mount) body package size (a" x b") does not include leads.
The list of approved transformers for use with SSRT Mark3 is constantly being updated. Please contact Beta Transformer Technology Corporation for the latest transformer configuration information.
Data Device Corporation www.ddc-web.com
32
BU-64703 Pre-01-03/03
1553 BUS CONNECTIONS
The isolation transformers should be placed as physically close as possible to the respective TX/RX pins on the SSRT Mark3. In addition, the distance from the isolation transformers to any connectors or cables leaving the board should be as short as possible. In addition to limiting the voltage drops in the analog signal traces when transmitting, reducing the hybrid-to-transformer and transformer-to-connector spacing serves to minimize crosstalk from other signals on the board. The general practice in connecting the stub side of a transformer (or direct) coupled terminal to an external system connector is to make use of 78 ohm twisted-pair shielded cable. This minimizes impedance discontinuities. The decision of whether to isolate or make connections between the center tap of the isolation transformer's secondary, the stub shield, the bus shield, and/or chassis ground must be made on a system basis, as determined by an analysis of EMI/RFI and lightning considerations. In most systems, it is specified that the 1553 terminal's input impedance must be measured at the system connector. This is despite the fact that the MIL-STD-1553B requirement is for it to
ISOLATION TRANSFORMER STUB COUPLING 10F + SSRT Mark3 HYBRID .01F 3.3V 78 1.5W TEST/ SIMULATION EQUIPMENT STUB COUPLING
be measured looking directly in from the bus side of the isolation transformer. The effect of a relatively long stub cable will be to reduce the measured impedance (looking in from the bus). In order to keep the impedance above the required level of 1000 ohms (for transformer-coupled stubs), the length of any cable between the 1553 RT and the system connector should be minimized.
"SIMULATED BUS" (LAB BENCH) INTERCONNECTIONS
For purposes of software development and system integration, it is generally not necessary to integrate the required couplers, terminators, etc., that comprise a complete MIL-STD-1553B bus. In most instances, a simplified electrical configuration will suffice. The three connection methods illustrated in FIGURE 15 allow the SSRT Mark3 to be interfaced over a "simulated bus" to simulation and test equipment. It is important to note that the termination resistors indicated are necessary in order to ensure reliable communications between the SSRT Mark3 and the simulation/test equipment.
(A)
ISOLATION TRANSFORMER DIRECT COUPLING 10F + SSRT Mark3 HYBRID .01F 55 1W 3.3V 55 1W 39 0.5W 55 DIRECT COUPLING 55 TEST/ SIMULATION EQUIPMENT
(B)
ISOLATION TRANSFORMER DIRECT COUPLING 10F + SSRT Mark3 HYBRID 3.3V 55 1W 39 0.5W 55 1W 20 0.5W 20 0.5W TEST/ SIMULATION EQUIPMENT STUB COUPLING
.01F
(C) (A) TRANSFORMER COUPLED TO TRANSFORMER COUPLED (B) DIRECT COUPLED TO DIRECT COUPLED (C) DIRECT COUPLED TO TRANSFORMER COUPLED
FIGURE 15. "SIMULATED BUS" (LAB BENCH) INTERCONNECTIONS
Data Device Corporation www.ddc-web.com 33 BU-64703 Pre-01-03/03
SIMPLE SYSTEM INTERFACE
FIGURE 16 illustrates the capability of the SSRT Mark3 to interface to a system with no host processor in burst mode. In this example, only one set of external latches is needed to buffer the data words written by the SSRT Mark3 to the external system. In burst mode, all received data words are stored in the internal FIFO until the last word is received. At this point, the SSRT Mark3 will transfer the entire contents of the FIFO to the system if the message is validated. In this case, GBR_L will be driven low for two clock cycles following the burst transfer cycle. If the received message is not valid, the FIFO data will not be transferred to the external system and GBR_L will remain high.
3.3V + 10F .01F
BUS A
LATCH
D15-D0 DISCRETE DIGITAL OUTPUTS
3.3V + 10F .01F
Write Address Decoder
LATCH
BUS B
EN MEMWR BU-64703 SSRT Mark3 RT ADDRESS L-BRO, T/R, SA4-0, WC/CWC4-0 Read Address Decoder TRI-STATE BUFFER EN
RTAD4-0, RTADP
DISCRETE DIGITAL INPUTS TRI-STATE BUFFER EN +V TRI-STATE BUFFER EN
Clock Oscillator
CLK-IN MEMOE +3.3V
EN
+3.3V AUTO_CFG MSTCLR AUTOCONFIGURATION (OPTIONAL)
DTGRT
RTACTIVE DTACK
FIGURE 16. SSRT Mark3-TO-SIMPLE SYSTEM INTERFACE (Shown for BURST MODE)
Data Device Corporation www.ddc-web.com BU-64703 Pre-01-03/03
34
BIT WORD
The SSRT Mark3 provides an internally formulated Built-In-Test word (BIT word). This word is transmitted to the BC in response to a Transmit BIT Word Mode Code Command. The BIT word bit functions and descriptions are provided in TABLE 5.
TABLE 5. INTERNAL BUILT-IN-TEST (BIT) WORD DEFINITION
BIT 15 (MSB) 14 13 FUNCTION TRANSMITTER TIMEOUT CH. B LOOP TEST FAILURE CH. A LOOP TEST FAILURE DESCRIPTION Set if the SSRT Mark3's failsafe timer detected a fault condition. The transmitter timeout circuit will automatically shut down the CH. A or CH. B transmitter if it transmits for longer than 660.5 s. A loopback test is performed on the transmitted portion of every non-broadcast message. A validity check is performed on the received version of every word transmitted by the SSRT Mark3. In addition, a bit-by-bit comparison is performed on the last word transmitted by the RT for each message. If either the received version of the last word does not match the transmitted version and/or the received version of any transmitted word is determined to be invalid (sync, encoding, bit count, parity), or a failsafe timeout occurs on the respective channel, the LOOP TEST FAILURE bit for the respective bus channel will be set. If this bit is set, it indicates that the subsystem had failed to respond with the DMA handshake input DTGRT asserted within 10 s after the SSRT Mark3 has asserted DTREQ.
12 11 10 9
HANDSHAKE FAILURE
TRANSMITTER SHUTDOWN B If either of these bits are logic "1", this indicates that the respective 1553 transmitter has been shut TRANSMITTER SHUTDOWN A down by means of a Transmitter shutdown mode command. TERMINAL FLAG INHIBITED Set to logic "1" if the SSRT Mark3's Terminal flag RT status bit has been disabled by an Inhibit terminal flag mode code command. Will revert to logic "0" if an Override inhibit terminal flag mode code command is received. Set to logic "1" to denote that the SSRT Mark3 has failed its off-line protocol self-test. This bit will be logic "0" if the self-test passed or had not been performed. Set to logic "1" if the previous message had a high word count error. Set to logic "1" if the previous message had a low word count error. If set, indicates that the SSRT Mark3 detected a Command sync in a received Data Word. Indicates that the SSRT Mark3 received one or more words containing one or more of the following error types: sync field error, Manchester encoding error, parity error, and/or bit count error.
8 7 6 5 4
BIT TEST FAIL HIGH WORD COUNT LOW WORD COUNT INCORRECT SYNC TYPE RECEIVED INVALID WORD MANCHESTER/PARITY ERROR RECEIVED
3
RT-RT TRANSFER RESPONSE This bit is set if the SSRT Mark3 is the receiving RT for an RT-to-RT transfer and one or more of the ERROR (no gap, data, sync, following errors occurs: (1) If the transmitting RT responds with a response time of less than 4 s, per address mismatch) MIL-STD-1553B (mid-parity bit to mid-sync); i.e., less than 2 s dead time; and/or (2) There is an incorrect sync type or format error (encoding, bit count, and/or parity error) in the transmitting RT Status Word; and/or (3) The RT address field of the transmitting RT Status Word does not match the RT address in the transmit Command Word. RT-RT TRANSFER NO RESPONSE TIMEOUT If set, indicates that, for the previous message, the SSRT Mark3 was the receiving RT for an RT-toRT transfer and that the transmitting RT either did not respond or responded later than the SSRT Mark3 RT-to-RT timeout time. The SSRT Mark3's RT-to-RT response timeout time is defined as the time from the mid-bit crossing of the parity bit of the transmit Command Word to the mid-sync crossing of the transmitting RT status word. The value of the SSRT Mark3's RT-to-RT response timeout time is in the range from 17.5 to 19.5 s. If the SSRT Mark3 is the receiving RT for an RT-to-RT transfer, if this bit is set, it indicates one or more of the following error conditions in the transmit Command Word: (1) T/R bit = logic "0"; (2) subaddress = 00000 or 11111; (3) same RT Address field as the receive Command Word.
2
1
RT-RT TRANSFER T/R ERROR ON SECOND COMMAND OR INVALID ADDRESS COMMAND WORD CONTENTS ERROR
0 (LSB)
Indicates that a received command word is not defined in accordance with MIL-STD-1553B. This includes the following undefined Command Words: (1) The Command Word is a non-mode code, broadcast, transmit command; (2) a message with a T/R bit of "0", a subaddress/mode field of 00000 or 11111, and a mode code field with a value between 00000 and 01111; (3) a mode code command that is not permitted to be broadcast (e.g., Transmit Status) is sent to the broadcast address 11111.
Note: Bits 15 through 9 are cleared only following a RESET input or receipt of a Reset Remote Terminal mode command. Bits 8 through 0 are updated as a result of every message processed.
Data Device Corporation www.ddc-web.com
35
BU-64703 Pre-01-03/03
MODE CODES
The SSRT Mark3 fully implements all 13 of the dual redundant MIL-STD-1553B mode codes. Four of the mode codes, Transmit vector word, Synchronize (with data), Selected transmitter shutdown, and Override transmitter shutdown, involve data transfers with the subsystem. For the Transmit last command mode command, the data word transmitted is from the SSRT Mark3's last command internal register. For the Transmit BIT word mode command, the SSRT Mark3's internally formulated BIT Word is transmitted. TABLE 6 provides a summary of the 1553B mode codes supported by the SSRT Mark3.
SUMMARY OF RESPONSES TO MODE CODE MESSAGES
The SSRT Mark3's responses to mode codes, including responses to various error conditions, are summarized in TABLE 6.
TABLE 6. MODE CODE SUMMARY
T/R BIT 0 1 1 1 1 1 1 1 1 1 1 1 0 1 1 0 0 1 0 Note:
For the Selected transmitter shutdown and Override transmitter shutdown mode commands, the SSRT Mark3 responds with Clear Status but no action is taken.
MODE CODE 00000-01111 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001-01111 10000 10001 10010 10011 10100 10101 10110-11111 10110-11111
FUNCTION Undefined Dynamic Bus Control Synchronize Transmit Status Word Initiate Self Test Transmitter Shutdown Override Transmitter Shutdown Inhibit Terminal Flag Override Inhibit Terminal Flag Reset Remote Terminal RESERVED Transmit Vector Word Synchronize with Data Transmit Last Command Transmit BIT Word Selected Transmitter Shutdown (see Note) Override Selected Transmitter Shutdown (see Note) RESERVED RESERVED
DATA WORD No No No No No No No No No No No From Subsystem To Subsystem From Internal Register From Internal Register To Subsystem To Subsystem From Subsystem To Subsystem
BROADCAST ALLOWED No No Yes No Yes Yes Yes Yes Yes Yes TBD No Yes No No Yes Yes TBD TBD
Data Device Corporation www.ddc-web.com
36
BU-64703 Pre-01-03/03
DETAILED MODE CODES FUNCTIONAL DESCRIPTION
The applicable Mode Codes for the SSRT Mark3 are described below:
DYNAMIC BUS CONTROL ( T/R = 1; 00000) MESSAGE SEQUENCE = DBC + STATUS The SSRT Mark3 responds with Status showing non-acceptance of the mode code command. ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Command Followed by Data Word. No Status response. Set Message error bit (Status Word), High Word Count (BIT Word). 3. T/R bit Set to Zero. No Status response. Set Message Error bit (Status Word), Command Word Contents Error (BIT Word). 4. Zero T/R bit and Broadcast Address. No Status response. Set Message Error and Broadcast Received bits (Status Word), Command Word Contents Error (BIT Word). 5. Broadcast Address. No Status response. Set Message Error and Broadcast Received bits (Status Word), Command Word Contents Error (BIT Word).
SYNCHRONIZE WITHOUT DATA WORD ( T/R = 1; 00001) MESSAGE SEQUENCE = SYNC + STATUS The SSRT Mark3 responds with Status. ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word), High Word Count (BIT Word). 3. T/R bit Set to Zero. No Status response. Set Message Error bit (Status Word), Command Word Contents Error (BIT Word). 4. Zero T/R bit and Broadcast Address. No Status response. Set Message Error and Broadcast Received bits (Status Word), Command Word Contents Error (BIT Word).
TRANSMIT STATUS WORD ( T/R = 1; 00010) MESSAGE SEQUENCE = TRANSMIT STATUS + STATUS The Status register is not updated before it is transmitted and contains the resulting status from the previous command (assuming that it was not a Transmit status or Transmit last command mode command). ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word) 3. T/R bit Set to Zero. No Status response. Set Message Error bit (Status Word), Command Word Contents Error (BIT Word). 4. Zero T/R bit and Broadcast Address. No Status response. Set Message Error and Broadcast Received bits (Status Word), Command Word Contents Error (BIT Word). 5. Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits (Status Word), Command Contents Error (BIT Word).
INITIATE SELF-TEST ( T/R = 1; 00011) MESSAGE SEQUENCE = SELF TEST + STATUS If the command was non-broadcast, the SSRT Mark3 responds with Status. If the command was either non-broadcast or broadcast, the SSRT Mark3 will go offline and perform its internal off-line protocol self-test. The self-test exercises the SSRT Mark3's encoder and decoders, registers, transmitter watchdog timer, and protocol logic. This test is completed in approximately 32,000 clock cycles. That is, about 1.6 ms with a 20 MHz clock, 2.0 ms at 16 MHz, 2.7 ms at 12 MHz, and 3.2 ms at 10 MHz. While the SSRT Mark3 is performing its off-line self-test, it will ignore (and therefore not respond to) all messages received from the 1553 bus. The bus controller may determine the result of the self-test by means of a Transmit BIT word mode command. If the self-test passes, bit 8 of the SSRT Mark3's BIT word (BIT Test Fail) will be logic "0"; if the self-test fails, this bit will be logic "1". In addition, if self-test fails, the terminal flag status word bit will be set to logic "1" in response to the next non-broadcast message. ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word), High Word Count (BIT Word). 3. T/R bit Set to Zero. No status response. Set Message Error bit (Status Word), Command Word Contents Error (BIT Word). 4. Zero T/R bit and Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits (Status word), Command Word Contents Error (BIT Word). 5. Loopback Test Failure. Set Terminal Flag bit in internal Status register (Status Word for next non-broadcast command), Current Channel (A or B) Loop Test Failure and CH A/B Loop Test Failure (BIT Word), assert RTFAIL output.
Data Device Corporation www.ddc-web.com
37
BU-64703 Pre-01-03/03
TRANSMITTER SHUTDOWN ( T/R = 1; 00100) MESSAGE SEQUENCE =SHUTDOWN + STATUS This command is only used with dual redundant bus systems. The SSRT Mark3 responds with Status. Following the Status transmission, the SSRT Mark3 inhibits any further transmission from the alternate redundant channel. Once shutdown, the transmitter can only be reactivated by an Override Transmitter Shutdown or Reset RT mode command, or Hardware Reset (MSTRCLR input). Note that the receivers on both channels are always active, even when the transmitters are inhibited. ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word), High Word Count (BIT Word). 3. T/R bit Set to Zero. No status response. Set Message Error bit (Status Word), Command Word Contents Error (BIT Word). 4. Zero T/R bit and Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits (Status word), Command Word Contents Error (BIT Word).
OVERRIDE TRANSMITTER SHUTDOWN ( T/R = 1; 00101) MESSAGE SEQUENCE = OVERRIDE SHUTDOWN + STATUS This command is only used with dual redundant bus systems. The SSRT Mark3 responds with Status. At the end of the Status transmission, the SSRT Mark3 reactivates the transmitter of the alternate redundant bus. If the command was broadcast, the Broadcast Command Received Status Word bit is set and status transmission is suppressed. ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word), High Word Count (BIT Word). 3. T/R bit Set to Zero. No status response. Set Message Error bit (Status Word), Command Word Contents Error (BIT Word). 4. Zero T/R bit and Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits (Status word), Command Word Contents Error (BIT Word).
INHIBIT TERMINAL FLAG BIT ( T/R = 1; 00110) MESSAGE SEQUENCE = INHIBIT TERMINAL FLAG + STATUS The SSRT Mark3 responds with Status and inhibits further setting of the Terminal Flag bit in its internal Status Word register. Once the Terminal Flag has been inhibited, it can only be reactivated by an Override Inhibit Terminal Flag or Reset RT mode code commands, or by Reset. If the command was broadcast, the Broadcast Received bit is set, the state of the Terminal Flag bit in the internal Status Word register remains unchanged and Status transmission is suppressed. ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word), High Word Count (BIT Word). 3. T/R bit Set to Zero. No status response. Set Message Error bit (Status Word), Command Word Contents Error (BIT Word). 4. Zero T/R bit and Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits (Status word), Command Word Contents Error (BIT Word).
OVERRIDE INHIBIT TERMINAL FLAG BIT ( T/R = 1; 00111) MESSAGE SEQUENCE = OVERRIDE INHIBIT TERMINAL FLAG + STATUS The SSRT Mark3 responds with Status and re-enables the Terminal Flag bit in its internal Status register. If the command was a broadcast, the Broadcast Command Received bit is set and status transmission is suppressed. ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word), High Word Count (BIT Word). 3. T/R bit Set to Zero. No status response. Set Message Error bit (Status Word), Command Word Contents Error (BIT Word). 4. Zero T/R bit and Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits (Status word), Command Word Contents Error (BIT Word).
Data Device Corporation www.ddc-web.com
38
BU-64703 Pre-01-03/03
RESET REMOTE TERMINAL ( T/R = 1; 01000) MESSAGE SEQUENCE = RESET REMOTE TERMINAL + STATUS The SSRT Mark3 responds with Status and internally resets. The Message Error and Broadcast Command Received bits of the internal Status register are reset to 0. The internal BIT Word Register is reset to 0. If either of the 1553 transmitters has been shut down, the shutdown condition is overridden. If the Terminal Flag bit has been inhibited, the inhibit is overridden. If the command is received as a broadcast, the Broadcast Command Received bit is set and the Status Word is suppressed. Also, if the command is received as a broadcast and the Terminal Flag bit had been set as a result of the Loopback test of the previous message, the Terminal Flag bit is not reset to zero. ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word), High Word Count (BIT Word). 3. T/R bit Set to Zero. No status response. Set Message Error bit (Status Word), Command Word Contents Error (BIT Word). 4. Zero T/R bit and Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits (Status word), Command Word Contents Error (BIT Word).
RESERVED MODE CODES ( T/R = 1; 01001 - 01111) MESSAGE SEQUENCE = RESERVED MODE COMMAND + STATUS The SSRT Mark3 responds with status. If the command has been illegalized by means of the illegalization table, the Message Error Status Word bit will be set. ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word), High Word Count (BIT Word). 3. T/R bit Set to Zero. No status response. Set Message Error bit (Status Word), Command Word Contents Error (BIT Word). 4. Zero T/R bit and Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits (Status word), Command Word Contents Error (BIT Word).
TRANSMIT VECTOR WORD ( T/R = 1; 10000) MESSAGE SEQUENCE = TRANSMIT VECTOR WORD + STATUS VECTOR WORD The SSRT Mark3 transmits a Status Word followed by a vector word. The vector word is read from the external subsystem. ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word), High Word Count (BIT Word). 3. T/R bit Set to Zero. No Status response. Set Message Error bit (Status Word), and Low Word Count (BIT Word). 4. T/R bit Set to Zero plus one Data Word. The SSRT Mark3 will respond with Status 5. Zero T/R bit and Broadcast Address, no Data Word. No Status response. Set Message Error and Broadcast Command Received bits (Status Word), and Low Word Count (BIT word). 6. Zero T/R bit and Broadcast Address, plus one Data Word. No Status response. Set Broadcast Command Received bits (Status Word) 7. Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits (Status Word), Command Word Contents Error (BIT word).
SYNCHRONIZE WITH DATA WORD ( T/R = 0; 10001) MESSAGE SEQUENCE = SYNCHRONIZE COMMAND/DATA WORD + STATUS The SSRT Mark3 will write the received 16 bit data word to the external subsystem. ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Correct Command Not Followed by Data Word. No Status response. Set Message Error bit (Status Word), Low Word Count (BIT Word) 3. Command Followed by too many Data Words. No Status response. Set Message Error bit (Status Word), High Word Count (BIT word). 4. Command T/R bit set to One followed by Data Word. No Status response. Set Message Error bit (Status Word), and High Word Count (BIT Word). 5. Command T/R bit set to One not followed by Data Word. The SSRT Mark3 replies with Status plus one Data Word. The Data Word is read from the subsystem (or single-word data block for subaddress 0000 or 1111). 6. Command T/R bit Set to One and Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits (Status Word); Set Command Word Contents Error (BIT word).
Data Device Corporation www.ddc-web.com
39
BU-64703 Pre-01-03/03
TRANSMIT LAST COMMAND ( T/R = 1; 10010) MESSAGE SEQUENCE = TRANSMIT LAST COMMAND + STATUS/LAST COMMAND The Status register is not updated before transmission. It contains the Status from the previous command. The Data Word transmitted contains the previous valid command (providing it was not another TRANSMIT LAST COMMAND or TRANSMIT STATUS WORD mode command). ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word), High Word Count Error (Bit Word). 3. T/R bit Set to Zero, no Data Word. No Status response. Set Message Error bit (Status Word), Low Word Count (BIT Word). 4. T/R bit Set to Zero, plus one Data Word. The SSRT Mark3 will respond with Status. The Data Word is transferred to the internal register. 5. Zero T/R bit and Broadcast Address, no Data Word. No Status response. Set Message Error and Broadcast Received bits (Status Word), Low Word Count Error(BIT Word). 6. Zero T/R bit and Broadcast Address, one Data Word. No Status response. Set Broadcast Received Bit (status word). The Data Word is transferred to the internal register. 7. Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits (Status Word), Command Word Contents Error (BIT Word).
TRANSMIT BIT WORD ( T/R = 1; 10011) MESSAGE SEQUENCE = TRANSMIT BIT WORD + STATUS/BIT WORD The SSRT Mark3 responds with Status followed by the Built-in Test (BIT) word. ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word), High Word Count Error (Bit Word). 3. T/R bit Set to Zero, no Data Word. No Status response. Set Message Error bit (Status Word), Low Word Count (BIT Word). 4. T/R bit Set to Zero, plus one Data Word. The SSRT Mark3 will respond with Status. The Data Word is transferred to internal registers. 5. Zero T/R bit and Broadcast Address, no Data Word. No Status response. Set Message Error and Broadcast Received bits (Status Word), Low Word Count Error (BIT Word). 6. Zero T/R bit and Broadcast Address, one Data Word. No Status response. Set Broadcast Received Bit (status word). The Data Word is transferred to internal registers. 7. Broadcast Address. No Status response. Set Message Error and Broadcast Command received bits (Status Word), Command Word contents Error (BIT Word).
SELECTED TRANSMITTER SHUTDOWN ( T/R = 0; 10100) MESSAGE SEQUENCE = TRANSMITTER SHUTDOWN/DATA + STATUS The Data Word received is transferred to the subsystem and Status is transmitted. No other action is taken by the SSRT Mark3. No transmitters are shut down as a result of this mode command. This command is intended for use with RTs with more than one dual redundant channel. If the command was a broadcast, the Broadcast Command Received bit is set and Status transmission is suppressed. ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Command Not Followed by Data Word. No Status response. Set Message Error bit (Status Word), and Low Word Count Bit (BIT Word). No status response. Bits Set: message error (SW), High Word Count, Illegal Mode Code (BIT Word) 3. Command Followed by too many Data Words. No Status response. Set Message Error bit (Status Word), and High Word Count Bit (BIT Word). 4. Command T/R bit Set to One followed by one Data Word. No Status response. Set Message Error bit (Status Word), and High Word Count (BIT Word). 5. Command T/R bit Set to One not followed by Data Word. The SSRT Mark3 replies with Status plus one Data Word. The Data Word is read from the subsystem. 6. Command T/R bit Set to One and Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits (Status Word), and Command Contents Error (BIT Word).
Data Device Corporation www.ddc-web.com
40
BU-64703 Pre-01-03/03
OVERRIDE SELECTED TRANSMITTER SHUTDOWN ( T/R = 0; 10101) MESSAGE SEQUENCE = TRANSMITTER SHUTDOWN/DATA + STATUS The Data Word received is transferred to the subsystem. No transmitters that have been previously shut down are reactivated as a result of this command. No other action is taken by the SSRT Mark3. This command is intended for use with RTs with more than one dual redundant channel. If the command was a broadcast, the Broadcast Command Received bit is set and Status transmission is suppressed. ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Command Not Followed by Data Word. No Status response. Set Message Error bit (Status Word), and Low Word Count (BIT Word). 3. Command Followed by too many Data Words. No Status response. Set Message Error bit (Status Word), and High Word Count bit (BIT Word). 4. Command T/R bit Set to One followed by Data Word. No Status response. Set Message Error bit (Status Word), and High Word Count (BIT Word). 5. Command T/R bit Set to One not followed by Data Word. The SSRT Mark3 replies with Status plus one Data Word. The Data Word is read from the subsystem. 6. Command T/R bit Set to One and Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits (Status Word), and Command Contents Error (BIT Word).
RESERVED MODE CODES ( T/R = 1; 11111) MESSAGE SEQUENCE (when T/R = 1) = RESERVED MODE CODE STATUS/DATA (when T/R = 0) = RESERVED MODE CODE DATA + STATUS For a RESERVED receive Command, the SSRT Mark3 stores the Data Word to the subsystem. If the command was a broadcast, the Broadcast Command Received bit is set and Status transmission is suppressed. For a RESERVED transmit Command Word, the SSRT Mark3 responds with Status plus a single Data Word. The Data Word is read from the subsystem. ERROR CONDITIONS (T/R = 1) 1. Invalid Command. No response, command ignored. 2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word), High Word Count (BIT Word). 3. Broadcast Command. No Status response. Set Message Error bit (status word), and Command Word Contents Error (BIT Word). ERROR CONDITIONS (T/R = 0) 1. Invalid Command. No response, command ignored. 2. Command not followed by Contiguous Data Word. No Status response. Set Message Error bit (Status Word), and Low Word Count (BIT Word). 3. Command followed by too many Data Words. No Status response. Set Message Error bit (Status Word), and High Word Count (BIT word).
Data Device Corporation www.ddc-web.com
41
BU-64703 Pre-01-03/03
SIGNAL DESCRIPTIONS BY FUNCTIONAL GROUPS TABLE 7. POWER AND GROUND
SIGNAL NAME +3.3V_Xcvr PIN 10 30 +3.3V_Logic 51 69 Gnd_Xcvr 22 79 14 31 Gnd_Logic 50 70 77 Logic Ground. Transceiver Ground. Logic power. Transceiver power. DESCRIPTION
TABLE 8. MIL-STD-1553 ISOLATION TRANSFORMER INTERFACE
SIGNAL NAME TX/RX-A (I/O) TX/RX-A (I/O) TX/RX-B (I/O) TX/RX-B (I/O) PIN 3 5 15 17 Analog transmit/receive input/output signals. Connect directly to 1553 isolation transformers. DESCRIPTION
TABLE 9. DATA BUS (16)
SIGNAL NAME D15 (I/O) (MSB) D14 (I/O) D13 (I/O) D12 (I/O) D11 (I/O) D10 (I/O) D09 (I/O) D08 (I/O) D07 (I/O) D06 (I/O) D05 (I/O) D04 (I/O) D03 (I/O) D02 (I/O) D01 (I/O) D00 (I/O) (LSB) PIN 59 56 54 55 58 60 57 52 53 41 49 43 48 47 42 46 16-bit bi-directional data bus. When the SSRT Mark3 is writing data to the external system, these signals are active outputs. At all other times, these signals are high impedance inputs. DESCRIPTION
Data Device Corporation www.ddc-web.com
42
BU-64703 Pre-01-03/03
TABLE 10. COMMAND / ADDRESS BUS
SIGNAL L_BRO (O) PIN 1 DESCRIPTION Latched Broadcast. This two-state output signal is latched following receipt of a new command word. For a broadcast command, this signal outputs a value of logic "1". For a non-broadcast message, this signal will output logic "0". Transmit/Receive. This two-state output signal is latched following receipt of a new command word. For a transmit message, this signal will output a value of logic "1". For a receive message, this signal will output logic "0". Subaddress. These five two-state output signals are latched following receipt of a new command word. They provide the subaddress field of the received command word.
T/R
2
SA4 (O) SA3 (O) SA2 (O) SA1 (O) SA0 (O) WC / MC / CWC4 (O) (MSB) WC / MC / CWC3 (O) WC / MC / CWC2 (O) WC / MC / CWC1 (O) WC / MC / CWC0 (O) (LSB)
75 7 12 27 74 78
13
19
33
Word Count/Mode Code/Current Word Count. Following receipt of a new command word, these five two-state output signals provide the contents of the command word's Word Count/Mode Code field. For a non-mode code receive message, the contents of WC/CWC are updated and incremented to reflect the value of the current data word being transferred to the system (in non-burst mode), or to the internal FIFO (in burst mode). CWC increments from 0 to the value of the Word Count field - 1 during the message. At the end of a non-mode code receive message in burst mode, the contents of CWC will then increment from 0 to the value of the word count field -1, as each word is transferred from the internal FIFO to the external system over D15-D0. In burst mode, it takes three clock cycles to transfer each word to the external system. For a non-mode code transmit command, the value of CWC starts from 0 and increments to the value of Word Count - 1, as each word is read from the external system and transferred to the SSRT Mark3. For a mode code command, the WC/CWC outputs the command word mode code field, which remains latched through the end of the message (until receipt of a subsequent command word).
18
TABLE 11. DMA HANDSHAKE AND TRANSFER CONTROL SIGNALS
SIGNAL DTREQ (O) DTGRT (I) PIN 29 72 DESCRIPTION Data Transfer Request. Active low level output signal used to request use of the external system data bus (D15-D0). Data Transfer Grant. Input from the external subsystem that must be asserted low in response to the SSRT Mark3 asserting DTREQ low in order to enable the SSRT Mark3 to read data from or write data to the external subsystem. The maximum allowable time from DTREQ to DTGRT is 10 s. If the SSRT Mark3's DMA handshake isn't required, DTGRT may be hardwired to logic "0". DTACK (O) 35 Data Transfer Acknowledge. Active low output signal used to indicate the SSRT Mark3's acceptance of the system data bus (D15-D0), in response to a data transfer grant (DTGRT). The SSRT Mark3's data transfers over D15-D0 will be framed by the time that DTACK is asserted low. If AUTO_CFG is strapped to logic "0", there will be a DTREQ/DTGRT handshake cycle after the rising edge of MSTCLR, following power turn-on. After DTGRT is sampled low, DTACK and RTACTIVE will then be asserted low to enable configuration data to be read from an external tri-state buffer. For transmit messages, or receive messages in non-burst mode, or for receive messages to subaddress 30 assuming that Subaddress 30 Autowrap is disabled, DTACK will be asserted low to indicate the transfer of individual words between the external system and the SSRT Mark3. For receive messages in burst mode assuming a valid received message, DTACK will be asserted low after the DTREQto-DTGRT handshake following the receipt of the last received data word. It will remain low for the duration of the DMA burst write transfer from the SSRT Mark3 to the external system. The total time for a burst write transfer is three clock cycles times the number of data words. HS_FAIL (O) MEMOE (O) 63 20 Handshake Fail. If this signal is asserted low, this indicates a handshake timeout condition. That is, the system did not respond with a DTGRT in time, following the SSRT Mark3's assertion of DTREQ. Memory Output Enable. MEMOE two-state output signal is used to enable data inputs from the external system to be enabled on to D15-D0. MEMOE pulses low for three clock cycles for each data word read from the external system. The SSRT Mark3 latches the data one clock cycle prior to the rising edge of MEMOE. Memory Write. Active low two-state output signal (one clock cycle wide) asserted low during SSRT Mark3 write cycles. Used to transfer data from the SSRT Mark3 to the external system. The external system may latch data on either the falling or rising edge of MEMWR.
MEMWR (O)
28
Data Device Corporation www.ddc-web.com
43
BU-64703 Pre-01-03/03
TABLE 12. RT ADDRESS
SIGNAL RTAD4 (I) (MSB) RTAD3 (I) RTAD2 (I) RTAD1 (I) RTAD0 (I) (LSB) RTADP (I) PIN 40 39 24 45 38 44 Remote Terminal Address Parity. This input signal must provide an odd parity sum with RTAD4-RTAD0 in order for the RT to respond to non-broadcast commands. That is, there must be an odd number of logic "1"s from among RTAD4RTAD0 and RTADP. RT Address Latch. If RT_AD_LAT is connected to logic "0", then the SSRT Mark3 is configured to accept a hardwired RT address from RTAD4-RTAD0 and RTADP. If RT_AD_LAT is initially logic "0", and then transitions to logic "1", the values presented on RTAD4-RTAD0 and RTADP will be latched internally by the SSRT Mark3 on the rising edge of RT_AD_LAT. RT_AD_ERR (O) 6 Remote Terminal Address Error. Output Signal that reflects the parity combination of the RTAD[4:0] inputs and RTADP input. A high level indicates odd (correct) parity. A low level indicates even (incorrect) parity. Note, if RT_AD_ERR is low, then the SSRT Mark3 will not recognize any valid Command Word received to its own RT address. RT Address inputs. DESCRIPTION
RT_AD_LAT (I)
36
TABLE 13. RT STATUS WORD INPUTS
SIGNAL ILLEGAL (I) PIN 68 DESCRIPTION Illegal. Input to the SSRT Mark3 that is sampled after the Command Word transfer. A logic "0" will cause the Message Error bit in the status response to be set (logic "1"), while a logic "1" on this input will have no effect on the Message Error bit. Service Request. When this input is logic "0", the Service request bit in the SSRT Mark3's status word will be logic "1". When this input is logic "1", the Service request bit in the SSRT Mark3's status word will be logic "0". Subsystem Flag. If this input is asserted low, the Subsystem Flag bit will be set in the SSRT Mark3's Status Word. Busy. If this input is asserted low, the Busy bit will be set to logic "1" in the SSRT Mark3's Status Word. If the Busy bit in the status word is logic "1", the SSRT Mark3 will not transmit any data words, except for a Transmit last command or Transmit BIT word mode command. For a receive command, if the SSRT Mark3 is Busy, it will still transfer data words to the external system (although these transfers may be blocked by means of external logic).
SRV_RQST (I) SSFLAG (I) BUSY (I)
66 37 61
Data Device Corporation www.ddc-web.com
44
BU-64703 Pre-01-03/03
TABLE 14. RT ACTIVITY AND MESSAGE STATUS INDICATORS
SIGNAL RTACTIVE (O) PIN 62 DESCRIPTION RT Active. This signal will be low (logic "0") following power turn-on, and when the SSRT Mark3 is reading its Auto-configure word or is performing its internal self-test. After the self-test passes, or if the Auto-configure option is not used, or if Auto-configure is used but bit 5 of the Auto-configure word is logic "1" (meaning for the RT to always go online), RTACTIVE will then transition to logic "1". When this occurs, the SSRT Mark3 will begin processing messages over the 1553 bus. If Auto-configure is enabled, and bit 5 of the Auto-configure word is logic "0" and the self-test fails, then RTACTIVE will remain at logic "0". In this case, the SSRT Mark3 will remain offline and not process any 1553 messages. A failed self test will cause RTFAIL_L to be asserted low (logic "0"). If the auto-configure option is used, the external system should enable the configuration bits on D5-D0 when RTACTIVE and DTACK are both outputting logic "0". INCMD GBR (O) 32 67 In-command. This two-state output is asserted low whenever a message is being processed by the SSRT Mark3. Good Block Received. Low level two-state output pulse (2 clock cycles wide) that is used to indicate to the external system that a valid, legal, non-mode receive command with the correct number of valid data words has been received and transferred to the external system. For non-burst mode, this pulse will occur after the last data word is transferred. Assuming a DTREQ-to-DTGRT time of 0, this will be approximately 4 s following the mid-parity bit crossing of the last received data word. For burst mode, the GBR pulse will begin synchronous with the rising edge of DTACK at the end of the burst write transfer.
MSG_ERR (O)
34
Message Error. Active low level two-state output signal used to flag to the external system that there was a message error on the 1553 bus communication (word, gap, or word count error) for a particular message. This output goes low upon detecting the error and is reset following the receipt of the next valid command word (to the RT) from the 1553 bus, or if MSTCLR is asserted low. If this output goes low, all further servicing of the current message is aborted. Remote Terminal Fail. This two-state output signal will be asserted low following a failure of the built-in self-test performed following power turn-on or as the result of the receipt of an Initiate self-test mode command. The built-in off-line self-test includes tests of the Manchester encoder and decoders, transmitter failsafe timer, and RT protocol logic. In addition, RTFAIL will be asserted low following a failure of the on-line loop test for any non-broadcast message. The online loop test verifies the validity of the received version of all transmitted words (sync, Manchester encoding, bit count, parity), and includes a bit-by-bit comparison and verification of the last transmitted word. If asserted to logic "0", RTFAIL will clear to logic "1" when the SSRT Mark3 begins transmission of its status word in response to a subsequent valid non-broadcast message.
RTFAIL (O)
64
TABLE 15. CONTROL INPUTS
SIGNAL MSTCLR (I) AUTO_CFG (I) PIN 25 76 DESCRIPTION Master Clear. Negative true Reset input, asserted low following power turn-on. When coming out of a "reset" condition, note that the risetime of MSTCLR must be less than 10 s. Auto-configure input. If connected to logic "1", then the auto-configure option is disabled, and the six configuration parameters revert to their default values as listed in TABLE 2. Note that the default condition for each configuration parameter is enabled (for the MIL-STD-1553A/B protocol selection, -1553B is the default). If AUTO_CFG is connected to logic "0", then the configuration parameters are transferred over D5-D0 during a DMA read data transfer, when RTACTIVE and DTACK are logic "0", following MSTCLR transitioning from logic "0" to logic "1". Each of the configuration parameters is enabled if the SSRT Mark3 reads a value of logic "1" for the respective data bit.
BRO_ENA (I)
71
Broadcast Enable. If this input is logic "1", the SSRT Mark3 will recognize RT address 31 as the broadcast address. If this input is logic "0", the SSRT Mark3 will not recognize RT address 31 as the broadcast address; however, in this configuration, RT address 31 may be used as a standard RT address. Transmitter inhibit input for the MIL-STD-1553 transmitters. For normal operation, this input should be connected to logic "0". To force a shutdown of the Channel A and Channel B transmitters, a value of logic "1" should be applied to this input.
TX_INH (I)
65
Data Device Corporation www.ddc-web.com
45
BU-64703 Pre-01-03/03
TABLE 16. CLOCK INPUT
SIGNAL CLK_IN (I) CLK_SEL_1 (I) PIN 26 73 DESCRIPTION Clock Input. The clock frequency must be designated by means of the CLK_SEL_1 and CLK_SEL_0 inputs. These two inputs are used to designate the SSRT Mark3's clock frequency, as follows: CLK_SEL_1 0 CLK_SEL_0 (I) 80 0 1 1 CLK_SEL_0 0 1 0 1 Clock Frequency 10 MHz 20 MHz 12 MHz 16 MHz
TABLE 17. FACTORY TEST (NO USER CONNECTIONS)
SIGNAL NC PIN 4 8 9 11 16 21 23 DESCRIPTION For factory test only. Do not connect for normal operation.
Data Device Corporation www.ddc-web.com
46
BU-64703 Pre-01-03/03
PIN FUNCTIONS TABLE 18. "GULL WING" AND FLAT PACKAGE PIN FUNCTIONS
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 FUNCTION L_BRO T/R TX/RX_A N/C TX/RX_A RT_AD_ERR SA3 N/C N/C +3.3 V_XCVR N/C SA2 WC3 GROUND_LOGIC TX/RX_B N/C TX/RX_B WC0 WC2 MEMOE PIN 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 FUNCTION N/C GROUND_XCVR N/C RTAD2 MSTCLR CLOCK_IN SA1 MEMWR DTREQ +3.3V_LOGIC GROUND_LOGIC INCMD WC1 MSG_ERR DTACK RT_AD_LAT SSFLAG RTAD0 RTAD3 RTAD4 PIN 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 FUNCTION D6 D1 D4 RTADP RTAD1 D0 D2 D3 D5 GROUND_LOGIC +3.3V_LOGIC D8 D7 D13 D12 D14 D9 D11 D15 D10 PIN 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 FUNCTION BUSY RTACTIVE HS_FAIL RT_FAIL TX_INH SRV_RQST GBR ILLEGAL +3.3V_LOGIC GROUND_LOGIC BRO_ENA DTGRT CLK_SEL_1 SA0 SA4 AUTO_CFG GROUND_LOGIC WC4 GROUND_XCVR CLK_SEL_0
Data Device Corporation www.ddc-web.com
47
BU-64703 Pre-01-03/03
2.360 MAX (59.94) 1.880 MAX (47.75) 0.890 MAX (22.606) 0.500 TYP (12.70)
0.130 (3.302)
60 61
41 40
0.040 TYP. (1.016)
TOP VIEW
19 EQUAL SPACES 0.760 (19.304) (TOL. NON-CUMM.)
80 1 20
21
PIN NUMBERS FOR REFERENCE ONLY
0.200 (05.08)
0.015 TYP. (0.381)
0.008 (0.2032) 0.025 (0.635)
0.880 (23.352)
INDEX DENOTES PIN NO. 1
0.050 (1.27) 0.040 (1.016)
Notes: 1) Dimensions are in inches (mm).
SIDE VIEW
FIGURE 17. BU-64703FX FLAT PACKAGE MECHANICAL OUTLINE
Data Device Corporation www.ddc-web.com
48
BU-64703 Pre-01-03/03
1.130 MAX (28.702) 0.890 MAX (22.606)
60 41
61
40
0.890 MAX (22.606)
0.015 TYP. (0.381)
19 EQUAL SPACES 0.760 (19.304) (TOL. NON-CUMM.)
80 PIN 1 DENOTED BY INDEX MARK 0.040 TYP. (1.016) 19 EQUAL SPACES 0.760 (19.304) (TOL. NON-CUMM.) 1 20
21
0.040 TYP. (1.016)
PIN NUMBERS FOR REFERENCE ONLY
TOP VIEW
R 0.012 TYP (R 0.305)
INDEX DENOTES PIN NO. 1
0.006
+0.010 - 0.004 +0.254
0.130 MAX. (3.302) 0.008 MAX. (0.2032) 0.910 MAX. (23.114)
1.020 MAX. (25.908) 1.130 MAX. (28.702)
(0.152 - 0.102 )
0.055 MAX. (1.397) 0.055 (1.397)
SIDE VIEW
Notes: 1) Dimensions are in inches (mm).
FIGURE 18. BU-64703GX GULL WING PACKAGE MECHANICAL OUTLINE
Data Device Corporation www.ddc-web.com
49
BU-64703 Pre-01-03/03
ORDERING INFORMATION
BU-64703XX-XXXX Supplemental Process Requirements: S = Pre-Cap Source Inspection L = Pull Test Q = Pull Test and Pre-Cap Inspection K = One Lot Date Code W = One Lot Date Code and PreCap Source Y = One Lot Date Code and 100% Pull Test Z = One Lot Date Code, PreCap Source and 100% Pull Test Blank = None of the Above Test Criteria: 0 = Standard Testing 2 = MIL-STD-1760 Amplitude Compliant (Not available with Voltage/Transceiver Option 9) Process Requirements: 0 = Standard DDC practices, no Burn-In (See table below.) 1 = MIL-PRF-38534 Compliant 2 = B* 3 = MIL-PRF-38534 Compliant with PIND Testing 4 = MIL-PRF-38534 Compliant with Solder Dip 5 = MIL-PRF-38534 Compliant with PIND Testing and Solder Dip 6 = B* with PIND Testing 7 = B* with Solder Dip 8 = B* with PIND Testing and Solder Dip 9 = Standard DDC Processing with Solder Dip, no Burn-In Temperature Range**/Data Requirements: 1 = -55C to +125C 2 = -40C to +85C 3 = 0C to +70C 4 = -55C to +125C with Variables Test Data 5 = -40C to +85C with Variables Test Data 6 = Custom Part (Reserved) 7 = Custom Part (Reserved) 8 = 0C to +70C with Variables Test Data Voltage/Transceiver Option: 8 = +3.3 Volts rise/fall times = 100 to 300 ns (-1553B) 9 = +3.3 Volts rise/fall times = 200 to 300 ns (-1553B and McAir compatible) (Not available with Test Criteria Option "2" MIL-STD-1760 Amplitude Compliant) Package Type: F = Flat Pack G = "Gull Wing" (Formed Lead) B = 324-ball BGA Package (Consult factory) Logic Voltage 3 = 3.3 Volt Product Type: BU-6470 = RT only with simple (non-processor) interface
*Standard DDC Processing with burn-in and full temperature test--see TABLE below. ** Temperature range refers to "Case Temperature".
STANDARD DDC PROCESSING
TEST INSPECTION SEAL TEMPERATURE CYCLE CONSTANT ACCELERATION BURN-IN MIL-STD-883 METHOD(S) CONDITION(S) 2009, 2010, 2017, and 2032 -- 1014 A and C 1010 C 2001 A 1015, TABLE 1 --
Data Device Corporation www.ddc-web.com
50
BU-64703 Pre-01-03/03
NOTES
Data Device Corporation www.ddc-web.com
51
BU-64703 Pre-01-03/03
The information in this Preliminary data sheet is believed to be accurate; however, no responsibility is assumed by Data Device Corporation for its use, and no license or rights are granted by implication or otherwise in connection therewith. Specifications are subject to change without notice. Please visit our web site at www.ddc-web.com for the latest information.
105 Wilbur Place, Bohemia, New York, U.S.A. 11716-2482 For Technical Support - 1-800-DDC-5757 ext. 7234 Headquarters, N.Y., U.S.A. - Tel: (631) 567-5600, Fax: (631) 567-7358 Southeast, U.S.A. - Tel: (703) 450-7900, Fax: (703) 450-6610 West Coast, U.S.A. - Tel: (714) 895-9777, Fax: (714) 895-4988 United Kingdom - Tel: +44-(0)1635-811140, Fax: +44-(0)1635-32264 Ireland - Tel: +353-21-341065, Fax: +353-21-341568 France - Tel: +33-(0)1-41-16-3424, Fax: +33-(0)1-41-16-3425 Germany - Tel: +49-(0)8141-349-087, Fax: +49-(0)8141-349-089 Japan - Tel: +81-(0)3-3814-7688, Fax: +81-(0)3-3814-7689 World Wide Web - http://www.ddc-web.com
(R)
ST
ERED
DATA DEVICE CORPORATION REGISTERED TO ISO 9001 FILE NO. A5976
Pre-01-03/03
52
PRINTED IN THE U.S.A.
FI
RM
U
REG
I

▲Up To Search▲

Price & Availability of BU-61705

	To Download BU-61705 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .