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| User's Manual V850 FAMILY TM 32-bit Single-Chip Microcontroller Architecture Document No. U10243EJ7V0UM00 (7th edition) Date Published March 2001 J CP(K) (c) Printed in Japan 1994 [MEMO] 2 User's Manual U10243EJ7V0UM SUMMARY OF CONTENTS CHAPTER 1 INTRODUCTION ........................................................................................................... CHAPTER 2 REGISTER SET ........................................................................................................... CHAPTER 3 DATA TYPE ................................................................................................................. CHAPTER 4 ADDRESS SPACE ....................................................................................................... CHAPTER 5 INSTRUCTIONS ............................................................................................................ 16 20 27 30 38 CHAPTER 6 INTERRUPTS AND EXCEPTIONS ............................................................................. 106 CHAPTER 7 RESET ........................................................................................................................... 113 CHAPTER 8 PIPELINE ...................................................................................................................... 114 APPENDIX A INSTRUCTION MNEMONIC (IN ALPHABETICAL ORDER) .................................. 127 APPENDIX B INSTRUCTION LIST ................................................................................................... 135 APPENDIX C INSTRUCTION OP CODE MAP ............................................................................... 137 APPENDIX D INDEX .......................................................................................................................... 139 User's Manual U10243EJ7V0UM 3 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Purchase of NEC I 2C components conveys a license under the Philips I 2C Patent Rights to use these components in an I 2 C system, provided that the system conforms to the I 2C Standard Specification as defined by Philips. V800 Series, V850 Family, V850/SA1, V850/SB1, V850/SB2, V850/SF1, V850/SV1, V850E/MA1, V850E/MA2, V850E/IA1, V850E/IA2, V850E/MS1, V850E/MS2, V851, V852, V853, and V854 are trademarks of NEC Corporation. Windows is a trademark or a registered trademark of Microsoft Corporation in the United States and/or other countries. 4 User's Manual U10243EJ7V0UM The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. * The information in this document is current as of March, 2001. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. * NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. * NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00. 4 User's Manual U10243EJ7V0UM 5 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * * * * * Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements * In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 NEC Electronics (Germany) GmbH Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A. Velizy-Villacoublay, France Tel: 01-3067-5800 Fax: 01-3067-5899 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (France) S.A. NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Madrid Office Madrid, Spain Tel: 091-504-2787 Fax: 091-504-2860 NEC Electronics Singapore Pte. Ltd. Novena Square, Singapore Tel: 253-8311 Fax: 250-3583 NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics (Germany) GmbH Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Guarulhos-SP, Brasil Tel: 11-6462-6810 Fax: 11-6462-6829 J01.2 6 User's Manual U10243EJ7V0UM Major Revisions in this Edition Page Throughout p. 18 p. 20 p. 21 p. 22 p. 103 p. 106 p. 111 p. 111 Change of target device Change of Figure 1-1 V850 Family Product Development Modification of description in 2.1.1 (1) General registers Modification of Figure 2-1 Program Register List Modification of Figure 2-2 List of Program Register Operations Modification of Table 5-10 List of Number of Instruction Execution Clock Cycles Modification of description in CHAPTER 6 INTERRUPTS AND EXCEPTIONS Modification of description in 6.2.2 Exception trap Modification of Figure 6-5 Exception Trap Processing Format The mark shows major revised points. Description User's Manual U10243EJ7V0UM 7 INTRODUCTION Target Readers This manual is intended for users who wish to understand the functions of the V850 CPU core in the V850 Family in designing systems using the products of the V850 Family. * V850 CPU Core Products * V851 TM Note 1 * V852 TM Note 2 * V853 TM : PD703000, 703001, 70P3000 : PD703002, 70P3002 : PD703003A, 70F3003A, 703003A(A) Note 3, 70F3003A(A) Note 3, 703004A, 703025A, 703025A(A), 70F3025A * V854 TM Note 2 * V850/SA1 TM : PD703006 Note 1, 703008, 70F3008, 703008Y, 70F3008Y : PD703014A, 703014AY, 703014B, 703014BY, 703015 Note 2, 703015Y Note 2, 703015A, 703015AY, 703015B, 703015BY, 70F3015BNote 3, 70F3015BY Note 3, 703017A, 70F3017A, 703017AY, 70F3017AY * V850/SB1 TM : PD703030A Note 3, 703030AY Note 3, 703031A, 703031AY, 703032A, 70F3032A, 703032AY, 70F3032AY, 703033A, 70F3033A, 703033AY, 70F3033AY * V850/SB2 TM : PD703034A, 703034AY, 703035A, 70F3035A, 703035AY, 70F3035AY, 703036A Note 3, 703036AY Note 3, 703037A, 70F3037A, 703037AY, 70F3037AY * V850/SF1 TM : PD703078Y, 703079Y, 70F3079Y : PD703038 Note 3, 703038Y Note 3, 70F3038 Note 3, 70F3038YNote 3, 703039, 703039Y, 703040, 703040Y, 703041, 703041Y, 70F3040, 70F3040Y * V850/SV1 TM Notes 1. Maintenance parts 2. Discontinued 3. Under development Purpose This manual is intended for users to understand the functions of the V850 Family Architecture described in the Organization below. Organization This manual contains the following information: * * * * * Register set Data type Instruction format and instruction set Interrupts and exceptions Pipeline operation 8 User's Manual U10243EJ7V0UM How to read this manual It is assumed that the readers of this manual have general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. To know about the hardware functions: Read the User's Manual Hardware of each device. To learn about the functions of a specific instruction in detail: Read CHAPTER 5 INSTRUCTIONS. To know about the electrical specifications: Read the DATA SHEET of each device. To understand the overall functions of the V850 Family: Read this manual in the order of CONTENTS. With the V850 Family, data consisting of 2 bytes is called a half-word, and data consisting of 4 bytes is called a word. Conventions Data significance: Active low representation: Memory map address: Note: Caution: Remark: Numeric representation: Higher digits on the left and lower digits on the right xxx (overscore over pin or signal name) Higher address on the top and lower address on the bottom Footnote for item marked with Note in the text Information requiring particular attention Supplementaly information Binary ... xxxx or xxxxB Decimal ... xxxx Hexadecimal ... xxxxH Prefixes indicating the power of 2 (address space, memory capacity): K (kilo) ... 210 = 1,024 M (mega) ... 220 = 1,0242 G (giga) ... 230 = 1,0243 Data type: Word ... 32 bits Halfword ... 16 bits Byte ... 8 bits User's Manual U10243EJ7V0UM 9 Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. * Documents related to devices Document Name Product Name V851 Data Sheet User's Manual Hardware U10987E U10988E U11826E U11827E U13188E U13189E U12756E U12755E -- U14526E U12768E U11969E U10913E U10038E U10935E Architecture This manual PD703000, 703001 PD70P3000 V852 PD703002 PD70P3002 V853 PD703003A, 703004A, 703025A PD70F3003A, 70F3025A V854 PD70F3008 PD70F3008Y PD703006, 703008, 703008Y V850/SA1 PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY PD70F3017A, 70F3017AY U14527E U14734E U13850E V850/SB1 PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY PD703032A, 703032AY, 70F3032A, 70F3032AY U14893E V850/SB2 PD703034A, 703034AY, 703035A, 703035AY, 70F3035A, 70F3035AY PD703037A, 703037AY, 70F3037A, 70F3037AY U14780E U14894E V850/SF1 V850/SV1 PD703078Y, 703079Y, 70F3079Y PD703039, 703039Y, 703040, 703040Y, 703041, 703041Y PD70F3040, 70F3040Y U15183E U13953E U14665E U14462E U14662E 10 User's Manual U10243EJ7V0UM * Documents related to development tools (user's manuals) Document Name IE-703002-MC (In-circuit Emulator for V852, V853, V854, V850/SA1, V850/SB1, V850/SB2, V850/SF1, V850/SV1) IE-703003-MC-EM1 (V853 Peripheral I/O Board) IE-703008-MC-EM1 (V854 Peripheral I/O Board) IE-703017-MC-EM1 (V850/SA1 Peripheral I/O Board) IE-703037-MC-EM1 (V850/SB1, V850/SB2 Peripheral I/O Board) IE-703040-MC-EM1 (V850/SV1 Peripheral I/O Board) CA850 (Ver. 2.30 or Later) (C Compiler Package) Operation C Language Project Manager Assembly Language ID850 (Ver.2.20 or Later) (Integrated Debugger) SM850 (Ver.2.20 or Later) (System Simulator) SM850 (Ver. 2.00 or Later) (System Simulator) RX850 (Ver. 3.13 or Later) (Real-Time OS) Operation Windows TM Document Number U11595E U11596E U12420E U12898E U14151E U14337E U14568E U14566E U14569E U14567E Based U14580E U14782E U14873E U13430E U13410E U13431E U13773E U13774E U13772E U13737E U13916E U14410E U13502E Operation Windows Based External Part User Open Interface Specifications Fundamental Installation Technical RX850 Pro (Ver. 3.13) (Real-Time OS) Fundamental Installation Technical RD850 (Ver. 3.01) (Task Debugger) RD850 Pro (Ver.3.01) (Task Debugger) AZ850 (Ver. 3.0) (System Performance Analyzer) PG-FP3 (Flash Memory Programmer) User's Manual U10243EJ7V0UM 11 CONTENTS CHAPTER 1 INTRODUCTION ........................................................................................................... 1.1 General ................................................................................................................................... 1.2 Architecture Features ........................................................................................................... 1.3 Product Development ........................................................................................................... 1.4 CPU Internal Configuration .................................................................................................. CHAPTER 2 REGISTER SET ........................................................................................................... 2.1 Program Registers ................................................................................................................ 2.1.1 Program register set .................................................................................................................... Interrupt status saving registers .................................................................................................. NMI status saving registers ......................................................................................................... Exception cause register ............................................................................................................. Program status word ................................................................................................................... System register number .............................................................................................................. 16 16 17 18 19 20 20 20 2.2 System Registers .................................................................................................................. 2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 23 23 24 24 25 26 CHAPTER 3 DATA TYPE ................................................................................................................. 3.1 Data Format ........................................................................................................................... 3.1.1 Data type and addressing ........................................................................................................... Integer ......................................................................................................................................... Unsigned integer ......................................................................................................................... Bit ................................................................................................................................................ 27 27 27 3.2 Data Representation ............................................................................................................. 3.2.1 3.2.2 3.2.3 28 28 29 29 3.3 Data Alignment ...................................................................................................................... 29 30 31 32 32 35 CHAPTER 4 ADDRESS SPACE ....................................................................................................... 4.1 Memory Map .......................................................................................................................... 4.2 Addressing Modes ................................................................................................................ 4.2.1 4.2.2 Instruction address ...................................................................................................................... Operand address ........................................................................................................................ CHAPTER 5 INSTRUCTIONS ............................................................................................................ 38 5.1 Instruction Format .................................................................................................................. 38 5.2 Outline of Instructions ........................................................................................................... 41 5.3 Instruction Set ........................................................................................................................ 45 5.4 Number of Instruction Execution Clock Cycles .................................................................. 103 CHAPTER 6 INTERRUPTS AND EXCEPTIONS ............................................................................. 106 6.1 Interrupt Processing ............................................................................................................. 107 6.1.1 6.1.2 Maskable interrupts ..................................................................................................................... 107 Non-maskable interrupts ............................................................................................................. 109 Software exceptions .................................................................................................................... 110 Exception trap ............................................................................................................................. 111 6.2 Exception Processing .......................................................................................................... 110 6.2.1 6.2.2 6.3 Restoring from Interrupt/Exception .................................................................................... 112 12 User's Manual U10243EJ7V0UM CHAPTER 7 RESET ........................................................................................................................... 113 7.1 Initialization ........................................................................................................................... 113 7.2 Start Up ................................................................................................................................. 113 CHAPTER 8 PIPELINE ...................................................................................................................... 114 8.1 Outline of Operation ............................................................................................................. 114 8.2 Pipeline Flow During Execution of Instructions ................................................................ 115 8.2.1 8.2.2 8.2.3 8.2.4 8.2.5 8.2.6 8.2.7 8.2.8 8.2.9 Load instructions ......................................................................................................................... 115 Store instructions ........................................................................................................................ 115 Arithmetic operation instructions (excluding multiply and divide instructions) ............................. 115 Multiply instructions ..................................................................................................................... 116 Divide instructions ....................................................................................................................... 116 Logical operation instructions ...................................................................................................... 116 Saturation operation instructions ................................................................................................. 117 Branch instructions ...................................................................................................................... 117 Bit manipulation instructions ....................................................................................................... 118 8.2.10 Special instructions ..................................................................................................................... 119 8.3 Pipeline Disorder .................................................................................................................. 121 8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 Alignment hazard ........................................................................................................................ 121 Referencing execution result of load instruction ......................................................................... 122 Referencing execution result of multiply instruction .................................................................... 122 Referencing execution result of LDSR instruction for EIPC and FEPC ...................................... 123 Cautions when creating programs .............................................................................................. 123 Harvard architecture .................................................................................................................... 124 Short path .................................................................................................................................... 125 8.4 Additional Items Related to Pipeline ................................................................................... 124 8.4.1 8.4.2 APPENDIX A INSTRUCTION MNEMONIC (IN ALPHABETICAL ORDER) .................................. 127 APPENDIX B INSTRUCTION LIST ................................................................................................... 135 APPENDIX C INSTRUCTION OP CODE MAP ............................................................................... 137 APPENDIX D INDEX .......................................................................................................................... 139 User's Manual U10243EJ7V0UM 13 LIST OF FIGURES Figure No. 1-1 1-2 2-1 2-2 2-3 4-1 4-2 4-3 4-4 4-5 4-6 4-7 6-1 6-2 6-3 6-4 6-5 6-6 8-1 8-2 8-3 8-4 8-5 Title V850 Family Product Development ....................................................................................... Internal Configuration ............................................................................................................ Program Register List ........................................................................................................... List of Program Register Operations ..................................................................................... System Registers .................................................................................................................. Memory Map ......................................................................................................................... Relative Addressing (JR disp22/JARL disp22, reg2) ............................................................ Relative Addressing (Bcond disp9) ....................................................................................... Register Addressing (JMP [reg1]) ......................................................................................... Based Addressing (Type 1) ................................................................................................... Based Addressing (Type 2) ................................................................................................... Bit Addressing ....................................................................................................................... Maskable Interrupt Processing Format ................................................................................. Non-maskable Interrupt Processing Format ......................................................................... Software Exception Processing Format ................................................................................ Illegal Instruction Code .......................................................................................................... Exception Trap Processing Format ....................................................................................... Restoring from Interrupt/Exception ....................................................................................... Example of Executing Nine Standard Instructions ................................................................ Align Hazard Example ........................................................................................................... Example of Execution Result of Load Instruction .................................................................. Example of Execution Result of Multiply Instruction ............................................................. Example of Execution Result of LDSR Instruction for EIPC and FEPC ................................ Page 18 19 21 22 23 31 32 33 34 35 36 37 108 109 110 111 111 112 114 121 122 122 123 14 User's Manual U10243EJ7V0UM LIST OF TABLES Table No. 2-1 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 6-1 7-1 8-1 A-1 B-1 B-2 Title System Register Number ...................................................................................................... Load/Store Instructions ......................................................................................................... Arithmetic Operation Instructions .......................................................................................... Saturated Operation Instructions .......................................................................................... Logical Operation Instructions ............................................................................................... Branch Instructions ............................................................................................................... Bit Manipulation Instructions ................................................................................................. Special Instructions ............................................................................................................... List of Conditional Branch Instructions .................................................................................. Condition Codes .................................................................................................................... List of Number of Instruction Execution Clock Cycles ........................................................... List of Interrupt/Exception Codes .......................................................................................... Register Status after Reset ................................................................................................... Access Times (in Clocks) ...................................................................................................... Instruction Mnemonic (In Alphabetical Order) ....................................................................... Mnemonic List ....................................................................................................................... Instruction Set ....................................................................................................................... Page 26 41 41 42 42 43 44 44 54 85 103 107 113 115 128 135 136 User's Manual U10243EJ7V0UM 15 CHAPTER 1 INTRODUCTION The V850 Family is a collection of NEC's single-chip microcontrollers that have a CPU core using the RISC microprocessor technology of the V800 SeriesTM, with on-chip ROM/RAM and peripheral I/Os, etc. The V850 Family of microcontrollers provides a migration path to the existing NEC-original single-chip microcontroller "78K Series", and boasts higher cost-performance. The V850 Family has products that incorporate the V850 and V850E CPUs, however this manual targets products that incorporate the V850 CPU. This chapter briefly outlines the V850 Family. 1.1 General Real-time control systems are used in a wide range of applications, including: * Office equipment such as HDDs (Hard Disk Drives), PPCs (Plain Paper Copiers), printers, and facsimiles * Automobile electronics such as engine control systems and ABSs (Antilock Braking Systems) * Factory automation equipment such as NC (Numerical Control) machine tools and various controllers The great majority of these systems hitherto employed 8-bit or 16-bit microcontrollers. However, the performance level of these microcontrollers has become inadequate in recent years as control operations have risen in complexity, leading to the development of increasingly complicated instruction sets and hardware design. As a result, the need has arisen for a new generation of microcontrollers operable at much higher frequencies to achieve an acceptable level of performance under today's more demanding requirements. The V850 Family of microcontrollers was developed to satisfy this need. This family uses RISC architecture that can provide maximum performance with simpler hardware, allowing users to obtain a performance approximately 15 times higher than that of the existing 78K/III Series and 78K/IV Series CISC single-chip microcontrollers at a lower total cost. In addition to the basic instructions of conventional RISC CPUs, the V850 Family is provided with special instructions such as saturation, bit manipulation, and multiply/divide (executed by a hardware multiplier) instructions, which are especially suited to digital servo control systems. Moreover, instruction formats are designed for maximum compiler coding efficiency, allowing the reduction of object code sizes. 16 User's Manual U10243EJ7V0UM CHAPTER 1 INTRODUCTION 1.2 Architecture Features * High-performance 32-bit architecture for embedded control * Number of instructions: 74 * 32-bit general registers: 32 * Load/store instructions in long/short format * 3-operand instruction * 5-stage pipeline of 1 clock cycle per stage * Hardware interlock on register/flag hazards * Memory space Program space: 16 MB linear Data space: 4 GB linear * Special instructions * Saturation operation instructions * Bit manipulation instructions * On-chip multiplier executing multiplication in 1 to 2 clocks (16 bits x 16 bits 32 bits) User's Manual U10243EJ7V0UM 17 CHAPTER 1 INTRODUCTION 1.3 Product Development The V850 Family consists of single-chip microcontrollers that use a RISC microprocessor core. The V850 Family includes the V851, V852, V853, V854, V850/SA1, V850/SB1, V850/SB2, V850/SF1, and V850/ SV1 which incorporate the V850 CPU, and the V850E/MS1TM, V850E/MS2TM, V850E/MA1TM, V850E/MA2TM, V850E/ IA1TM, V850E/IA2TM, and V850E/xxx which incorporate the V850E CPU. The products incorporating the V850 CPU are single-chip control-system microcontrollers, and the products incorporating the V850E CPU are single-chip microcontrollers that have enhanced external bus interface performance and that support not only the control-system but also data processing. Figure 1-1. V850 Family Product Development Performance Under development V850 CPU core Note V850E/MA1 V850E/IA1 Enhanced memory Inverter control controller and with CAN support of SDRAM Highperformance V850E/xxx V850E/MS1 V850 CPU Core V851 Internal flash V853 V852 V854 Memory controller Compact version added ASSP V850E/MS2 V850E/MA2 V850E/IA2 Compact version Compact version V850/SV1 3V, low-power version with many pins VCR servo control V850/Sxx 5V, low-power version with many pins V850/SB1 Ultra-low power V850/SA1 consumption 3V, low-power version 5V, low-power version V850/Sxx V850/SF1 5V, low-power version with CAN 5V, low-power version with many pins and IEBus V850/SB2 5V, low-power version with IEBus V850/Sxx 5V, low-power version with many pins and CAN Year of development Note For details of the V850E CPU core architecture, refer to V850E/MS1 User's Manual Architecture (U12197E) and V850E1 User's Manual Architecture (U14559E). 18 User's Manual U10243EJ7V0UM CHAPTER 1 INTRODUCTION 1.4 CPU Internal Configuration Figure 1-2 shows the internal configuration of the V850 Family. Figure 1-2. Internal Configuration Internal ROM CPU BCU ROM/ PROM/ flash memory PC 32-bit barrel shifter Multiplier 16 x 16 32 Instruction queue Internal peripheral I/O System register Internal RAM General register 32 bits x 32 Prefetch control ALU Bus control Internal bus The function of each hardware block is as follows: CPU ********************************* Executes almost all instructions such as address calculation, arithmetic and logical operation, and data transfer in one clock by using a 5-stage pipeline. Contains dedicated hardware such as a multiplier (16 x 16 bits) and a barrel shifter (32 bits/clock) to execute complicated instructions at high speeds. Internal ROM ******************* ROM, EPROM, or flash memory mapped from address 00000000H. Can be accessed by the CPU in one clock during instruction fetch. Internal RAM ******************* RAM mapped to a space preceding address FFFFEFFFH. Can be accessed by the CPU in one clock during data access. Internal peripheral I/O ***** Peripheral I/O area mapped from address FFFFF000H. BCU ********************************* Starts the required bus cycle based on a physical address obtained by the CPU. If the CPU does not issue a request for starting a bus cycle, the BCU generates a prefetch address, and prefetches an instruction code. The prefetched instruction code is loaded to an internal instruction queue. User's Manual U10243EJ7V0UM 19 CHAPTER 2 REGISTER SET The register sets of the V850 Family can be classified into two types: program register sets that can be used for general programming, and system register sets that can control the execution environment. All the registers are 32 bits wide. 2.1 Program Registers 2.1.1 Program register set (1) General registers The V850 Family has thirty-two general registers, r0 through r31. All these registers can be used for data or address storage. However, r0 and r30 are implicitly used by instructions, and care must be exercised in using these registers. r0 is a register that always holds 0, and is used for operations and offset 0 addressing. r30 is used as a base pointer when accessing memory using the SLD and SST instructions. r1, r3, r4, r5, and r31 are implicitly used by the assembler and C compiler. Before using these registers, therefore, their contents must be saved so that they are not lost. The contents must be restored to the registers after the registers have been used. r2 may be used by the real-time OS. If the real-time OS used does not use r2, r2 can be used as a register for variable. 20 User's Manual U10243EJ7V0UM CHAPTER 2 REGISTER SET Figure 2-1. Program Register List 31 r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 Element Pointer (EP) Link pointer (LP) Stack Pointer (SP) Global Pointer (GP) Text Pointer (TP) Zero Register Reserved for Address Generation 0 PC Program Counter User's Manual U10243EJ7V0UM 21 CHAPTER 2 REGISTER SET Figure 2-2. List of Program Register Operations Name r0 r1 r2 r3 Usage Zero register Assembler-reserved register Always holds 0. Operation Used as working register for address generation. Address/data variable register (if real-time OS used does not use r2) Stack pointer Used for stack frame generation when function is called. Used to access global variable in data area. Used as register for pointing start address of text areaNote. r4 r5 Global pointer Text pointer r6 to r29 r30 Address/data variable registers Element pointer Used as base pointer for address generation when memory is accessed. Used when compiler calls function. Holds instruction address during program execution. r31 PC Link pointer Program counter Note Text area: Area where program code is placed. Remark For detailed descriptions of r1, r3 to r5, and r31 used by the assembler and C compiler, refer to C Compiler Package (CA850) User's Manual. (2) Program counter This register holds an instruction address during program execution. The lower 24 bits of this register are valid, and bits 31 through 24 are reserved fields (fixed to 0). If a carry occurs from bit 23 to 24, it is ignored. Bit 0 is always fixed to 0, and execution cannot branch to an odd address. 31 PC RFU 24 23 10 0 Remark RFU: Reserved field (Reserved for Future Use) 22 User's Manual U10243EJ7V0UM CHAPTER 2 REGISTER SET 2.2 System Registers The system registers control the status of the V850 Family and hold information on interrupts. Figure 2-3. System Registers 31 EIPC EIPSW Exception/Interrupt PC Exception/Interrupt PSW 0 FEPC FEPSW Fatal Error PC Fatal Error PSW ECR Exception Cause Register PSW Program Status Word 2.2.1 Interrupt status saving registers Two interrupt status saving registers are provided: EIPC and EIPSW. The contents of the PC and PSW are respectively saved in these registers if an exception or interrupt occurs. If an NMI occurs, however, the contents of the PC and PSW are saved to NMI status saving registers. When an exception or interrupt occurs, the address of the following instruction is saved to the EIPC register. If an interrupt occurs while a division (DIVH) instruction is executed, the address of the division instruction currently being executed is saved. The current value of the PSW is saved to the EIPSW. Because only one pair of interrupt status saving registers is provided, the contents of these registers must be saved by program when multiple interrupts are enabled. Bits 24 through 31 of the EIPC and bits 8 through 31 of the EIPSW are fixed to 0. 31 EIPC PC 0 31 EIPSW PSW 0 User's Manual U10243EJ7V0UM 23 CHAPTER 2 REGISTER SET 2.2.2 NMI status saving registers The V850 Family is provided with two NMI status saving registers: FEPC and FEPSW. The contents of the PC and PSW are respectively saved in these registers when an NMI occurs. The value saved to the FEPC is, like the EIPC, the address of the instruction next to the one executed when the NMI has occurred (if the NMI occurs while a division (DIVH) instruction is executed, the address of the division instruction under execution is saved). The current value of the PSW is saved to the FEPSW. Bits 24 through 31 of the FEPC and bits 8 through 31 of the FEPSW are fixed to 0. 31 FEPC PC 0 31 FEPSW PSW 0 2.2.3 Exception cause register The exception cause register (ECR) holds the cause information of an exception, maskable interrupt, or NMI when any of these events occur. The ECR holds a code which identifies each interrupt source. This is a read-only register, therefore no data can be written to it using the LDSR instruction. 31 ECR FECC 16 15 EICC 0 Bit Position 31 to 16 Field FECC Fatal Error Cause Code NMI code Exception/Interrupt Cause Code Exception/interrupt code Function 15 to 0 EICC 24 User's Manual U10243EJ7V0UM CHAPTER 2 REGISTER SET 2.2.4 Program status word The program status word is a collection of flags that indicate the status of the program (result of instruction execution) and the status of the CPU. If the contents of the PSW register are modified by the LDSR instruction, the PSW will assume the new value immediately after the LDSR instruction has been executed. In setting the ID flag to 1, however, interrupts are already disabled even while the LDSR instruction is under execution. (1/2) 31 PSW RFU 876543210 NE I SCO SZ A PPDTYV Bit Position 31 to 8 7 RFU NP Flag Reserved for Future Use Reserved field (fixed to 0). Function NMI Pending Indicates that NMI processing is in progress. This flag is set when an NMI is granted. The NMI request is then masked, and multiple interrupts are disabled. NP = 0: NMI processing is not in progress NP = 1: NMI processing is in progress Exception Pending Indicates that exception processing is in progress. This flag is set when an exception occurs. EP = 0: Exception processing is not in progress EP = 1: Exception processing is in progress Interrupt Disable Indicates whether external interrupt request can be accepted. ID = 0: Interrupt can be accepted ID = 1: Interrupt cannot be accepted Saturated Indicates that an overflow has occurred in a saturation operation and the result is saturated. This is a cumulative flag. Once the result is saturated, the flag is set to 1 and is not reset to 0 even if the next result does not saturate. To reset this flag, load data to PSW. This flag is neither set to 1 nor reset to 0 by a general arithmetic operation instruction. SAT = 0: Not saturated SAT = 1: Saturated Carry Indicates whether a carry or borrow occurred as a result of the operation. CY = 0: Carry or borrow did not occur CY = 1: Carry or borrow occurred Overflow Indicates whether an overflow occurred as a result of the operation. OV = 0: Overflow did not occur OV = 1: Overflow occurred Sign Indicates whether the result of the operation is negative S = 0: Result is positive or zero S = 1: Result is negative Zero Indicates whether the result of the operation is zero Z = 0: Result is not zero Z = 1: Result is zero 6 EP 5 ID 4 SATNote 3 CY 2 OVNote 1 SNote 0 Z Remark Description of Note is given on the next page. User's Manual U10243EJ7V0UM 25 CHAPTER 2 REGISTER SET (2/2) Note In the case of saturation instructions, the SAT, S, and OV flags will be set accordingly by the result of the operation as shown in the table below. Note that the SAT flag is set to 1 only when the OV flag has been set due to an overflow condition caused by a saturation instruction. Status of Operation Result Maximum positive value is exceeded Maximum negative value is exceeded Other SAT-S-OV 1 0 1 Result of Saturation Processing 7FFFFFFFH 1 1 x 1 80000000H 0 0 Operation result 2.2.5 System register number Data in the system registers is accessed by using the load/store system register instructions, LDSR and STSR. Each register is assigned a unique number which is referenced by the LDSR and STSR instructions. Table 2-1. System Register Number Operand Specification LDSR 0 1 2 3 4 5 6 to 31 EIPC EIPSW FEPC FEPSW ECR PSW Reserved -- STSR Number System Register --: : Accessing prohibited Accessing enabled Reserved: Accessing registers in this range is prohibited and will lead to undefined results. Caution When using the LDSR instruction with the EIPC and FEPC registers, only even address values should be specified. After interrupt servicing has ended with the RETI instruction, bit 0 in the EIPC and FEPC registers will be ignored and assumed to be zero when the PC is restored. 26 User's Manual U10243EJ7V0UM CHAPTER 3 DATA TYPE 3.1 Data Format The V850 Family supports the following data types: * Integer (8, 16, 32 bits) * Unsigned integer (8, 16, 32 bits) * Bit 3.1.1 Data type and addressing The V850 Family supports three types of data lengths: word (32 bits), half-word (16 bits), and byte (8 bits). Byte 0 of any data is always the least significant byte (this is called little endian) and shown at the rightmost position in figures throughout this manual. The following paragraphs describe the data format where data of a fixed length is in memory. (1) Byte (BYTE) A byte is 8-bit contiguous data that starts from any byte boundaryNote. Each bit is assigned a number from 0 to 7. The LSB (Least Significant Bit) is bit 0 and the MSB (Most Significant Bit) is bit 7. A byte is specified by its address A. 7 0 Data A Address (2) Half-word (HALF-WORD) A half-word is 2-byte (16-bit) contiguous data that starts from any half-word boundaryNote. Each bit is assigned a number from 0 to 15. The LSB is bit 0 and the MSB is bit 15. A half-word is specified by its address A (with the lowest bit fixed to 0), and occupies 2 bytes A and A+1. 15 87 0 Data A+1 A Address User's Manual U10243EJ7V0UM 27 CHAPTER 3 DATA TYPE (3) Word (WORD) A word is 4-byte (32-bit) contiguous data that starts from any word boundaryNote. Each bit is assigned a number from 0 to 31. The LSB is bit 0 and the MSB is bit 31. A word is specified by its address A (with the 2 lowest bits fixed to 0), and occupies 4 bytes A, A+1, A+2, and A+3. 31 24 23 16 15 87 0 Data A+3 A+2 A+1 A Address (4) Bit (BIT) A bit is 1-bit data at the nth bit position in 8-bit data that starts from any byte boundaryNote. A bit is specified by its address A and bit number n. Note See 3.3 Data Alignment. 7 Byte of address A * * * * * * * * * * * * * * * * * * * * * * * * n 0 Bit number Data A Address 3.2 Data Representation 3.2.1 Integer With the V850 Family, an integer is expressed as a binary number of 2's complement and is 8, 16, or 32 bits long. Regardless of its length, bit 0 of an integer is the least significant bit. The higher the bit number, the more significant the bit. Because 2's complement is used, the most significant bit is used as a sign bit. Data Length Byte Half-word Word 8 bits 16 bits 32 bits Range -128 to +127 -32,768 to +32,767 -2,147,483,648 to +2,147,483,647 28 User's Manual U10243EJ7V0UM CHAPTER 3 DATA TYPE 3.2.2 Unsigned integer While an integer is data that can take either a positive or a negative value, an unsigned integer is an integer that is not negative. Like an integer, an unsigned integer is also expressed as 2's complement and is 8, 16, or 32 bits long. Regardless of its length, bit 0 of an unsigned integer is the least significant bit, and the higher the bit number, the more significant the bit. However, no sign bit is used. Data Length Byte Half-word Word 8 bits 16 bits 32 bits Range 0 to 255 0 to 65,535 0 to 4,294,967,295 3.2.3 Bit The V850 Family can handle 1-bit data that can take a value of 0 (cleared) or 1 (set). Bit manipulation can be performed only on 1-byte data in the memory space in the following four ways: * * * * Set Clear Invert Test 3.3 Data Alignment With the V850 Family, word data to be allocated in memory must be aligned at an appropriate boundary. Therefore, word data must be aligned at a word boundary (the lower 2 bits of the address are 0), and half-word data must be aligned at a half-word boundary (the lowest bit of the address is 0). If data is not aligned at a boundary, the data is accessed with the lowest bit(s) of the address (lower 2 bits in the case of word data and lowest 1 bit in the case of half-word data) automatically masked. Byte data can be placed at any address. Note that the process of aligning is called alignment. User's Manual U10243EJ7V0UM 29 CHAPTER 4 ADDRESS SPACE The V850 Family supports a 4-GB linear address space. Both memory and I/O are mapped to this address space (memory-mapped I/O). The V850 Family outputs 32-bit addresses to the memory and I/O. The maximum address is 232-1. Byte ordering is little endian. Byte data allocated at each address is defined with bit 0 as LSB and bit 7 as MSB. In regards to multiple-byte data, the byte with the lowest address value is defined to have the LSB and the byte with the highest address value is defined to have the MSB (little endian). Data consisting of 2 bytes is called a half-word, and 4-byte data is called a word. In this User's Manual, data consisting of 2 or more bytes is illustrated as below, with the lower address shown on the right and the higher address on the left. 7 Byte of address A *************************************** **************** A 15 Half-word at address A ************************************* A+1 31 Word at address A * * * * * * * * * * * * * * A+3 A+2 A+1 A 24 23 16 15 87 A 87 0 Data Address 0 Data Address 0 Data Address 30 User's Manual U10243EJ7V0UM CHAPTER 4 ADDRESS SPACE 4.1 Memory Map The V850 Family employs a 32-bit architecture and supports a linear address space (data space) of up to 4 GB. It supports a linear address space (program space) of up to 16 MB for instruction addressing. Figure 4-1 shows the memory map of the V850 Family. The capacity of the on-chip ROM and RAM depends on each product. For details, refer to the memory map section in the User's Manual Hardware of each product. Figure 4-1. Memory Map FFFFFFFFH Peripheral I/O FFFFEFFFH Internal RAM Internal ROM/PROM/ flash memory 00000000H 4 GB linear User's Manual U10243EJ7V0UM 31 CHAPTER 4 ADDRESS SPACE 4.2 Addressing Modes The CPU generates two types of addresses: instruction addresses used for instruction fetch and branch operations; and operand addresses used for data access. 4.2.1 Instruction address An instruction address is determined by the contents of the program counter (PC), and is automatically incremented (+2) according to the number of bytes of an instruction to be fetched each time an instruction has been executed. When a branch instruction is executed, the branch destination address is loaded into the PC using one of the following two addressing modes: (1) Relative address (PC relative) The signed 9- or 22-bit data of an instruction code (displacement: disp) is added to the value of the program counter (PC). At this time, the displacement is treated as 2's complement data with bits 8 and 21 serving as sign bits. This addressing is used for the Bcond disp9, JR disp22, and JARL disp22, reg2 instructions. Figure 4-2. Relative Addressing (JR disp22/JARL disp22, reg2) 31 24 23 PC 0 0 00000000 31 Sign extension 22 21 S disp22 0 0 31 24 23 PC 0 0 00000000 Memory to be manipulated 32 User's Manual U10243EJ7V0UM CHAPTER 4 ADDRESS SPACE Figure 4-3. Relative Addressing (Bcond disp9) 31 24 23 PC 0 0 00000000 31 Sign extension 98 S disp9 0 0 31 24 23 PC 0 0 00000000 Memory to be manipulated User's Manual U10243EJ7V0UM 33 CHAPTER 4 ADDRESS SPACE (2) Register addressing (register indirect) The contents of a general register (r0 to r31) specified by an instruction are transferred to the program counter (PC). This addressing is applied to the JMP [reg1] instruction. Figure 4-4. Register Addressing (JMP [reg1]) 31 rn 0 31 24 23 PC 0 0 00000000 Memory to be manipulated 34 User's Manual U10243EJ7V0UM CHAPTER 4 ADDRESS SPACE 4.2.2 Operand address When an instruction is executed, the register or memory area to be accessed is specified in one of the following four addressing modes: (1) Register addressing The general register (or system register) specified in the general register specification field is accessed as an operand. This addressing mode applies to instructions using the operand format reg1, reg2, or regID. (2) Immediate addressing The 5-bit or 16-bit data for manipulation is contained directly in the instruction. This addressing mode applies to instructions using the operand format imm5, imm16, vector, or cccc. Remark vector: Operand that is 5-bit immediate data to specify the trap vector (00H to 1FH), and is used by the TRAP instruction. cccc: Operand consisting of 4-bit data used by the SETF instruction to specify the condition code. Assigned as part of the instruction code as 5-bit immediate data by appending 1-bit 0 above highest bit. (3) Based addressing The following two types of based addressing are supported: (a) Type 1 The address of the data memory location to be accessed is determined by adding the value in the specified general register to the 16-bit displacement value contained in the instruction. This addressing mode applies to instructions using the operand format disp16 [reg1]. Figure 4-5. Based Addressing (Type 1) 31 reg1 0 31 Sign extension 16 15 disp16 0 Memory to be manipulated User's Manual U10243EJ7V0UM 35 CHAPTER 4 ADDRESS SPACE (b) Type 2 The address of the data memory location to be accessed is determined by adding the value in the 32-bit element pointer (r30) to the 7- or 8-bit displacement value contained in the instruction. This addressing mode applies to SLD and SST instructions. Figure 4-6. Based Addressing (Type 2) 31 r30 (element pointer) 0 31 000000000000000000000000 (Zero extension) 7 disp8 or disp7 0 Memory to be manipulated Byte access = disp7 Half-word access and word access = disp8 36 User's Manual U10243EJ7V0UM CHAPTER 4 ADDRESS SPACE (4) Bit addressing This addressing is used to access 1 bit (specified with bit#3 of 3-bit data) among 1 byte of the memory space to be manipulated by using an operand address which is the sum of the contents of a general register and a 16bit displacement sign-extended to a word length. This addressing mode applies only to bit manipulation instructions. Figure 4-7. Bit Addressing 31 reg1 0 31 Sign extension 16 15 disp16 0 Memory to be manipulated n Remark n: Bit position specified with 3-bit data (bit#3) (n = 0 to 7) User's Manual U10243EJ7V0UM 37 CHAPTER 5 INSTRUCTIONS 5.1 Instruction Format The V850 Family has two types of instruction formats: 16-bit and 32-bit. The 16-bit instructions include binary operation, control, and conditional branch instructions, and the 32-bit instructions include load/store, jump, and instructions that handle 16-bit immediate data. Some instructions have an unused field (RFU). This field is reserved for future expansion and must be fixed to 0. An instruction is actually stored in memory as follows: * Lower bytes of instruction (including bit 0) lower address * Higher bytes of instruction (including bit 15 or 31) higher address (1) reg-reg instruction (Format I) A 16-bit instruction format having a 6-bit op code field and two general register specification fields for operand specification. 15 reg2 11 10 opcode 5 4 reg1 0 (2) imm-reg instruction (Format II) A 16-bit instruction format having a 6-bit op code field, 5-bit immediate field, and a general register specification field. 15 reg2 11 10 opcode 5 4 imm 0 (3) Conditional branch instruction (Format III) A 16-bit instruction format having a 4-bit op code field, 4-bit condition code, and an 8-bit displacement. 15 disp 11 10 opcode 7 6 disp 4 3 cond 0 38 User's Manual U10243EJ7V0UM CHAPTER 5 INSTRUCTIONS (4) 16-bit load/store instruction (Format IV) A 16-bit instruction format having a 4-bit op code field, a general register specification field, and a 7-bit displacement (or 6-bit displacement + 1-bit sub-op code). 15 reg2 11 10 opcode 7 6 5 disp 1 0 disp/sub-opcode (5) Jump instruction (Format V) A 32-bit instruction format having a 5-bit op code field, a general register specification field, and a 22-bit displacement. 15 reg2 11 10 opcode 65 0 31 disp 17 16 0 (6) 3-operand instruction (Format VI) A 32-bit instruction format having a 6-bit op code field, two general register specification fields, and a 16-bit immediate field. 15 reg2 11 10 opcode 54 reg1 0 31 imm 16 0 (7) 32-bit load/store instruction (Format VII) A 32-bit instruction format having a 6-bit op code field, two general register specification fields, and a 16-bit displacement (or 15-bit displacement + 1-bit sub-op code). 15 reg2 11 10 opcode 54 reg1 0 31 disp 17 16 disp/sub-opcode User's Manual U10243EJ7V0UM 39 CHAPTER 5 INSTRUCTIONS (8) Bit manipulation instruction (Format VIII) A 32-bit instruction format having a 6-bit op code field, 2-bit sub-op code, 3-bit bit specification field, a general register specification field, and a 16-bit displacement. 15 14 13 sub 11 10 bit # opcode 54 reg1 0 31 disp 16 (9) Extended instruction format 1 (Format IX) A 32-bit instruction format having a 6-bit op code field, 6-bit sub-op code, and two general register specification fields (one field may be regID or cond). 15 reg2 11 10 opcode 54 0 31 RFU 27 26 sub-opcode 21 20 RFU 16 reg1/regID/cond (10) Extended instruction format 2 (Format X) A 32-bit instruction format having a 6-bit op code field and 6-bit sub op code. 15 13 12 11 10 RFU opcode 54 0 31 RFU 27 26 sub-opcode 21 20 RFU 16 RFU/sub-opcode RFU/immediate/vector Remark RFU: Reserved field (Reserved for Future Use) 40 User's Manual U10243EJ7V0UM CHAPTER 5 INSTRUCTIONS 5.2 Outline of Instructions Load/store instructions ...................... Transfer data from memory to a register or from a register to memory. Table 5-1. Load/Store Instructions SLD LD SST ST Arithmetic operation instructions ..... Add, subtract, multiply, divide, transfer, or compare data between registers. Table 5-2. Arithmetic Operation Instructions MOV MOVHI MOVEA ADD ADDI SUB SUBR MULH MULHI DIVH CMP SETF User's Manual U10243EJ7V0UM 41 CHAPTER 5 INSTRUCTIONS Saturated operation instructions ...... Execute saturation addition or subtraction. If the result of the operation exceeds the maximum positive value (7FFFFFFFH), 7FFFFFFFH is returned. If the result exceeds the negative value (80000000H), 80000000H is returned. Table 5-3. Saturated Operation Instructions SATADD SATSUB SATSUBI SATSUBR Logical operation instructions .......... These instructions include logical operation instructions and shift instructions. The shift instructions include arithmetic shift and logical shift instructions. Operands can be shifted by two or more bit positions in one clock cycle by the universal barrel shifter. Table 5-4. Logical Operation Instructions TST OR ORI AND ANDI XOR XORI NOT SHL SHR SAR 42 User's Manual U10243EJ7V0UM CHAPTER 5 INSTRUCTIONS Branch instructions ...................... Branch operations include unconditional branch along with conditional branch instructions which alter the flow of control, depending on the status of conditional flags in the PSW. Program control can be transferred to the address specified by a branch instruction. Table 5-5. Branch Instructions JMP JR JARL BGT BGE BLT BLE BH BNL BL BNH BE BNE BV BNV BN BP BC BNC BZ BNZ BR BSA User's Manual U10243EJ7V0UM 43 CHAPTER 5 INSTRUCTIONS Bit manipulation instructions ...... Execute a logical operation to bit data in memory. Only a specified bit is affected as a result of executing a bit manipulation instruction. Table 5-6. Bit Manipulation Instructions SET1 CLR1 NOT1 TST1 Special instructions ...................... These instructions are special in that they do not fall in any of the categories of instructions described above. Table 5-7. Special Instructions LDSR STSR TRAP RETI HALT DI EI NOP 44 User's Manual U10243EJ7V0UM CHAPTER 5 INSTRUCTIONS 5.3 Instruction Set Example of instruction description Mnemonic of instruction Meaning of instruction Instruction format Indicates the description and operand of the instruction. The following symbols are used in description of an operand: Symbol reg1 reg2 Meaning General register (used as source register) General register (mainly used as destination register. Some are also used as source registers) 3-bit data for specification bit number x-bit immediate x-bit displacement System register number 5-bit data for trap vector (00H to 1FH) specification 4-bit data for condition code specification Element pointer (r30) bit#3 immx dispx regID vector cccc ep User's Manual U10243EJ7V0UM 45 CHAPTER 5 INSTRUCTIONS Operation Describes the function of the instruction. The following symbols are used: Symbol GR [ ] SR [ ] zero-extend (n) sign-extend (n) load-memory (a, b) store-memory (a, b, c) load-memory-bit (a, b) store-memory-bit (a, b, c) saturated (n) Assignment General register System register Zero-extends n to word Sign-extends n to word Reads data of size b from address a Writes data b of size c to address a Reads bit b from address a Writes c to bit b of address a Performs saturation processing of n. If n 7FFFFFFFH as result of calculation, 7FFFFFFFH. If n 80000000H as result of calculation, 80000000H. Reflects result on flag Byte (8 bits) Half-word (16 bits) Word (32 bits) Add Subtract Bit concatenation Multiply Divide And Or Exclusive Or Logical negate Logical left shift Logical right shift Arithmetic right shift Meaning result Byte Halfword Word + - || x / AND OR XOR NOT logically shift left by logically shift right by arithmetically shift right by Format Indicates instruction format number. 46 User's Manual U10243EJ7V0UM CHAPTER 5 INSTRUCTIONS Op code Describes the separate bit fields of the instruction opcode. The following symbols are used: Symbol R r d i cccc bbb Meaning 1-bit data of code specifying reg1 or regID 1-bit data of code specifying reg2 1-bit data of displacement 1-bit data of immediate 4-bit data for condition code specification 3-bit data for bit number specification Flag Indicates the flags which are altered after executing the instruction. CY OV S Z - 0 1 - Indicates that the flag is not affected. Indicates that the flag is cleared to 0. Indicates that the flag is set to 1. SAT - Instruction Explanation Remark Caution Describes the function of the instruction. Explains the operation of the instruction. Supplementary information on the instruction Important cautions regarding use of this instruction User's Manual U10243EJ7V0UM 47 CHAPTER 5 INSTRUCTIONS Instruction List Mnemonic Function Load/Store instructions SLD.B SLD.H SLD.W LD.B LD.H LD.W SST.B SST.H SST.W ST.B ST.H ST.W Load Byte Load Half-Word Load Word Load Byte Load Half-Word Load Word Store Byte Store Half-Word Store Word Store Byte Store Half-Word Store Word Arithmetic instructions MOV MOVHI MOVEA ADD ADDI SUB SUBR MULH MULHI DIVH CMP SETF Move Move High Half-Word Move Effective Address Add Add Immediate Subtract Subtract Reverse Multiply Half-Word Multiply Half-Word Immediate Divide Half-Word Compare Set Flag Condition Saturate instructions SATADD SATSUB SATSUBI SATSUBR Saturated Add Saturated Subtract Saturated Subtract Immediate Saturated Subtract Reverse LDSR STSR TRAP RETI HALT DI EI NOP SET1 CLR1 NOT1 TST1 JMP JR JARL Bcond TST OR ORI AND ANDI XOR XORI NOT SHL SHR SAR Mnemonic Function Logical operation instructions Test Or Or Immediate And And Immediate Exclusive-Or Exclusive-Or Immediate Not Shift Logical Left Shift Logical Right Shift Arithmetic Right Branch instructions Jump Jump Relative Jump and Register Link Branch on Condition Code Bit manipulation instructions Set Bit Clear Bit Not Bit Test Bit Special instructions Load System Register Store System Register Trap Return from Trap or Interrupt Halt Disable Interrupt Enable Interrupt No Operation Most of these mnemonics are acronyms of functions. 48 User's Manual U10243EJ7V0UM CHAPTER 5 INSTRUCTIONS ADD Add Instruction format (1) ADD (2) ADD reg1, reg2 imm5, reg2 Operation (1) GR [reg2] GR [reg2] + GR [reg1] (2) GR [reg2] GR [reg2] + sign-extend (imm5) Format (1) Format I (2) Format II Op code (1) 15 0 rrrrr001110RRRRR 15 0 (2) rrrrr010010iiiii Flag CY OV S Z SAT 1 if a carry occurs from MSB; otherwise, 0. 1 if an overflow occurs; otherwise, 0. 1 if the result of an operation is negative; otherwise, 0. 1 if the result of an operation is 0; otherwise 0. - Add Register Add Immediate (5-bit) Instruction (1) ADD (2) ADD Explanation (1) Adds the word data of general register reg1 to the word data of general register reg2, and stores the result in general register reg2. The data of general register reg1 is not affected. (2) Adds 5-bit immediate data, sign-extended to word length, to the word data of general register reg2, and stores the result in general register reg2. User's Manual U10243EJ7V0UM 49 CHAPTER 5 INSTRUCTIONS ADDI Add Immediate Instruction format Operation Format Op code ADDI imm16, reg1, reg2 GR [reg2] GR [reg1] + sign-extend (imm16) Format VI 15 0 31 16 rrrrr110000RRRRR iiiiiiiiiiiiiiii Flag CY OV S Z SAT Instruction Explanation 1 if a carry occurs from MSB; otherwise, 0. 1 if an overflow occurs; otherwise, 0. 1 if the result of an operation is negative; otherwise, 0. 1 if the result of an operation is 0; otherwise 0. - ADDI Add Immediate Adds 16-bit immediate data, sign-extended to word length, to the word data of general register reg1, and stores the result in general register reg2. The data of general register reg1 is not affected. 50 User's Manual U10243EJ7V0UM CHAPTER 5 INSTRUCTIONS AND And Instruction format Operation Format Op code AND reg1, reg2 GR [reg2] GR [reg2] AND GR [reg1] Format I 15 0 rrrrr001010RRRRR Flag CY OV S Z SAT Instruction Explanation - 0 1 if the result of an operation is negative; otherwise, 0. 1 if the result of an operation is 0; otherwise 0. - AND And ANDs the word data of general register reg2 with the word data of general register reg1, and stores the result in general register reg2. The data of general register reg1 is not affected. User's Manual U10243EJ7V0UM 51 CHAPTER 5 INSTRUCTIONS ANDI And Immediate Instruction format Operation Format Op code ANDI imm16, reg1, reg2 GR [reg2] GR [reg1] AND zero-extend (imm16) Format VI 15 0 31 16 rrrrr110110RRRRR iiiiiiiiiiiiiiii Flag CY OV S Z SAT Instruction Explanation - 0 0 1 if the result of an operation is 0; otherwise 0. - ANDI And Immediate (16-Bit) ANDs the word data of general register reg1 with the value of the 16-bit immediate data, zeroextended to word length, and stores the result in general register reg2. The data of general register reg1 is not affected. 52 User's Manual U10243EJ7V0UM CHAPTER 5 INSTRUCTIONS Bcond Branch on Condition Code Instruction format Operation Bcond disp9 if conditions are satisfied then PC PC + sign-extend (disp9) Format Op code Format III 15 0 ddddd1011dddcccc dddddddd is the higher 8 bits of disp9. Flag CY OV S Z SAT Instruction Explanation Bcond - - - - - Branch on Condition Code with 9-Bit Displacement Tests a condition flag specified by the instruction. Branches if a specified condition is satisfied; otherwise, executes the next instruction. The branch destination PC holds the sum of the current PC value and 9-bit displacement, which is 8-bit immediate shifted 1 bit and signextended to word length. Remark Bit 0 of the 9-bit displacement is masked to 0. The current PC value used for calculation is the address of the first byte of this instruction. If the displacement value is 0, therefore, the branch destination is this instruction itself. User's Manual U10243EJ7V0UM 53 CHAPTER 5 INSTRUCTIONS Table 5-8. List of Conditional Branch Instructions Condition Code (cccc) 1111 1110 0110 0111 1011 1001 0001 0011 0010 1010 0000 1000 0100 1100 0001 1001 0010 1010 0101 1101 Instruction Signed integer BGT BGE BLT BLE Unsigned integer BH BNL BL BNH Common BE BNE Others BV BNV BN BP BC BNC BZ BNZ BR BSA Status of Condition Flag ( (S xor OV) or Z) = 0 (S xor OV) = 0 (S xor OV) = 1 ( (S xor OV) or Z) = 1 (CY or Z) = 0 CY = 0 CY = 1 (CY or Z) = 1 Z=1 Z=0 OV = 1 OV = 0 S=1 S=0 CY = 1 CY = 0 Z=1 Z=0 - SAT = 1 Branch Condition Greater than signed Greater than or equal signed Less than signed Less than or equal signed Higher (Greater than) Not lower (Greater than or equal) Lower (Less than) Not higher (Less than or equal) Equal Not equal Overflow No overflow Negative Positive Carry No carry Zero Not zero Always (unconditional) Saturated Caution If executing a conditional branch instruction of a signed integer (BGT, BGE, BLT, or BLE) when the SAT flag is set to 1 as a result of executing a saturated operation instruction, the branch condition loses its meaning. In ordinary arithmetic operations, if an overflow condition occurs, the S flag is inverted (0 1 or 1 0). This is because the result is a negative value if it exceeds the maximum positive value and it is a positive value if it exceeds the maximum negative value. However, when a saturated operation instruction is executed, and if the result exceeds the maximum positive value, the result is saturated with a positive value; if the result exceeds the maximum negative value, the result is saturated with a negative value. Unlike the ordinary operation, therefore, the S flag is not inverted even if an overflow occurs. Hence, the S flag of the PSW is affected differently when the instruction is a saturate operation, as opposed to an ordinary arithmetic operation. A branch condition which is an XOR of S and OV flags will therefore, have no meaning. 54 User's Manual U10243EJ7V0UM CHAPTER 5 INSTRUCTIONS CLR1 Clear Bit Instruction format Operation CLR1 bit#3, disp16 [reg1] adr GR [reg1] + sign-extend (disp16) Z flag Not (Load-memory-bit (adr, bit#3)) Store-memory-bit (adr, bit#3, 0) Format Op code Format VIII 15 0 31 16 10bbb111110RRRRR dddddddddddddddd Flag CY OV S Z SAT Instruction Explanation - - - 1 if bit NO.bit#3 of memory disp16 [reg1] = 0. 0 if bit NO.bit#3 of memory disp16 [reg1] = 1. - CLR1 Clear Bit Adds the data of general register reg1 to the 16-bit displacement, sign-extended to word length, to generate a 32-bit address. Then clears the bit, specified by the bit number of 3 bits, of the byte data referenced by the generated address. Not specified bit is not affected. Remark The Z flag of the PSW indicates whether the specified bit was a 0 or 1 before this instruction is executed. It does not indicate the content of the specified bit after this instruction has been executed. User's Manual U10243EJ7V0UM 55 CHAPTER 5 INSTRUCTIONS CMP Compare Instruction format (1) CMP reg1, reg2 (2) CMP imm5, reg2 Operation (1) result GR [reg2] - GR [reg1] (2) result GR [reg2] - sign-extend (imm5) Format (1) Format I (2) Format II Op code (1) 15 0 rrrrr001111RRRRR 15 0 (2) Flag CY OV S Z SAT Instruction rrrrr010011iiiii 1 if a borrow to MSB occurs; otherwise, 0. 1 if an overflow occurs; otherwise 0. 1 if the result of the operation is negative; otherwise, 0. 1 if the result of the operation is 0; otherwise, 0. - (1) CMP Compare Register (2) CMP Compare Immediate (5-Bit) Explanation (1) Compares the word data of general register reg2 with the word data of general register reg1, and indicates the result by using the condition flags. To compare, the contents of general register reg1 are subtracted from the word data of general register reg2. The data of general registers reg1 and reg2 is not affected. (2) Compares the word data of general register reg2 with 5-bit immediate data, sign-extended to word length, and indicates the result by using the condition flags. To compare, the contents of the sign-extended immediate data is subtracted from the word data of general register reg2. The data of general register reg2 is not affected. 56 User's Manual U10243EJ7V0UM CHAPTER 5 INSTRUCTIONS DI Disable Interrupt Instruction format Operation Format Op code DI PSW.ID 1 (Disables maskable interrupt) Format X 15 0 31 16 0000011111100000 0000000101100000 Flag CY OV S Z SAT ID Instruction Explanation - - - - - 1 DI Disable Interrupt Sets the ID flag of the PSW to 1 to disable the acknowledgement of maskable interrupts during executing this instruction. Remark Interrupts are not sampled during execution of this instruction. The ID flag actually becomes valid at the start of the next instruction. But because interrupts are not sampled during instruction execution, interrupts are immediately disabled. Non-maskable interrupts (NMI) are not affected by this instruction. User's Manual U10243EJ7V0UM 57 CHAPTER 5 INSTRUCTIONS DIVH Divide Half-Word Instruction format Operation Format Op code DIVH reg1, reg2 GR [reg2] GR [reg2] / GR [reg1] Format I 15 0 rrrrr000010RRRRR Flag CY OV S Z SAT Instruction Explanation - 1 if an overflow occurs; otherwise, 0. 1 if the result of an operation is negative; otherwise, 0. 1 if the result of an operation is 0; otherwise, 0. - DIVH Divide Half-Word Divides the word data of general register reg2 by the lower half-word data of general register reg1, and stores the quotient in general register reg2. If the data is divided by 0, Overflow occurs, and the quotient is undefined. The data of general register reg1 is not affected. Remark The remainder is not stored. Overflow occurs when the maximum negative value (80000000H) is divided by -1 (in which case the quotient is 80000000H) and when data is divided by 0 (in which case the quotient is undefined). If an interrupt occurs while this instruction is executed, division is aborted, and the interrupt is processed. Upon returning from the interrupt, the division is restarted from the beginning, with the return address being the address of this instruction. Also, general registers reg1 and reg2 will retain their original values prior to the start of execution. The higher 16 bits of general register reg1 are ignored when division is executed. 58 User's Manual U10243EJ7V0UM CHAPTER 5 INSTRUCTIONS EI Enable Interrupt Instruction format Operation Format Op code EI PSW.ID 0 (enables maskable interrupt) Format X 15 0 31 16 1000011111100000 0000000101100000 Flag CY OV S Z SAT ID Instruction Explanation - - - - - 0 EI Enable Interrupt Resets the ID flag of the PSW to 0 and enables the acknowledgement of maskable interrupts beginning at the next instruction. Remark Interrupts are not sampled during instruction execution. User's Manual U10243EJ7V0UM 59 CHAPTER 5 INSTRUCTIONS HALT Halt Instruction format Operation Format Op code HALT Halts Format X 15 0 31 16 0000011111100000 0000000100100000 Flag CY OV S Z SAT Instruction Explanation Remark - - - - - HALT Halt Stops the operating clock of the CPU and places the CPU in the HALT mode. The HALT mode is exited by any of the following three events: * RESET input * NMI input * Maskable interrupt (when ID of PSW = 0) If an interrupt is acknowledged during the HALT mode, the address of the following instruction is stored in EIPC or FEPC. 60 User's Manual U10243EJ7V0UM CHAPTER 5 INSTRUCTIONS JARL Jump and Register Link Instruction format Operation JARL disp22, reg2 GR [reg2] PC + 4 PC PC + sign-extend (disp22) Format Op code Format V 15 0 31 16 rrrrr11110dddddd ddddddddddddddd0 ddddddddddddddddddddd is the higher 21 bits of disp22. Flag CY OV S Z SAT Instruction Explanation - - - - - JARL Jump and Register Link Saves the current PC value plus 4 to general register reg2, adds the current PC value and 22bit displacement, sign-extended to word length, and transfers control to that PC. Bit 0 of the 22-bit displacement is masked to 0. Remark The current PC value used for calculation is the address of the first byte of this instruction. If the displacement value is 0, the branch destination is this instruction itself. This instruction is equivalent to a call subroutine instruction, and saves the PC return address to general register reg2. The JMP instruction, which is equivalent to a subroutine-return instruction, can be used to specify the general register containing the return address saved during the JARL subroutine-call instruction, to restore the program counter. User's Manual U10243EJ7V0UM 61 CHAPTER 5 INSTRUCTIONS JMP Jump Register Instruction format Operation Format Op code JMP [reg1] PC GR [reg1] Format I 15 0 00000000011RRRRR Flag CY OV S Z SAT Instruction Explanation - - - - - JMP Jump Register Transfers control to the address specified by general register reg1. Bit 0 of the address is masked to 0. Remark When using this instruction as the subroutine-return instruction, specify the general register containing the return address saved during the JARL subroutine-call instruction, to restore the program counter. When using the JARL instruction, which is equivalent to the subroutine-call instruction, store the PC return address in general register reg2. 62 User's Manual U10243EJ7V0UM CHAPTER 5 INSTRUCTIONS JR Jump Relative Instruction format Operation Format Op code JR disp22 PC PC + sign-extend (disp22) Format V 15 0 31 16 0000011110dddddd ddddddddddddddd0 ddddddddddddddddddddd is the higher 21 bits of disp22. Flag CY OV S Z SAT Instruction Explanation - - - - - JR Jump Relative Adds the 22-bit displacement, sign-extended to word length, to the current PC value and stores the value in the PC, and then transfers control to that PC. Bit 0 of the 22-bit displacement is masked to 0. Remark The current PC value used for the calculation is the address of the first byte of this instruction itself. Therefore, if the displacement value is 0, the jump destination is this instruction. User's Manual U10243EJ7V0UM 63 CHAPTER 5 INSTRUCTIONS LD Load Instruction format (1) LD.B disp16 [reg1], reg2 (2) LD.H disp16 [reg1], reg2 (3) LD.W disp16 [reg1], reg2 Operation (1) adr GR [reg1] + sign-extend (disp16) GR [reg2] sign-extend (Load-memory (adr, Byte)) (2) adr GR [reg1] + sign-extend (disp16) GR [reg2] sign-extend (Load-memory (adr, Halfword)) (3) adr GR [reg1] + sign-extend (disp16) GR [reg2] Load-memory (adr, Word) Format Op code Format VII 15 (1) 0 31 16 rrrrr111000RRRRR dddddddddddddddd 15 0 31 16 (2) rrrrr111001RRRRR ddddddddddddddd0 ddddddddddddddd is the higher 15 bits of disp16. 15 0 31 16 (3) rrrrr111001RRRRR ddddddddddddddd1 ddddddddddddddd is the higher 15 bits of disp16. Flag CY OV S Z SAT - - - - - Instruction (1) LD.B Load Byte (2) LD.H Load Half-Word (3) LD.W Load Word 64 User's Manual U10243EJ7V0UM CHAPTER 5 INSTRUCTIONS Explanation (1) Adds the data of general register reg1 to a 16-bit displacement, sign-extended to word length, to generate a 32-bit address. Byte data is read from the generated address, signextended to word length, and then stored in general register reg2. (2) Adds the data of general register reg1 to a 16-bit displacement sign-extended to word length to generate a 32-bit address. Half-word data is read from this 32-bit address with its bit 0 masked to 0, sign-extended to word length, and stored in general register reg2. (3) Adds the data of general register reg1 to a 16-bit displacement sign-extended to word length to generate a 32-bit address. Word data is read from this 32-bit address with bits 0 and 1 masked to 0, and stored in general register reg2. Caution When the data of general register reg1 is added to a 16-bit displacement sign-extended to word length, the lower bits of the result may be masked to 0 depending on the type of data to be accessed (half word, word) to generate an address. User's Manual U10243EJ7V0UM 65 CHAPTER 5 INSTRUCTIONS LDSR Load to System Register Instruction format Operation Format Op code LDSR reg2, regID SR [regID] GR [reg2] Format IX 15 0 31 16 rrrrr111111RRRRR 0000000000100000 Remark The fields used to define reg1 and reg2 are swapped in this instruction. Normally, "RRR" is used for reg1 and is the source operand while "rrr" signifies reg2 and is the destination operand. In this instruction, "RRR" is still the source operand, but is represented by reg2, while "rrr" is the special register destination, as labeled below: rrrrr: regID specification RRRRR: reg2 specification Flag CY OV S Z SAT Instruction Explanation - (See Remark below.) - (See Remark below.) - (See Remark below.) - (See Remark below.) - (See Remark below.) LDSR Load to System Register Loads the word data of general register reg2 to a system register specified by the system register number (regID). The data of general register reg2 is not affected. Remark If the system register number (regID) is equal to 5 (PSW register), the values of the corresponding bits of the PSW are set according to the contents of reg2. This only affects the flag bits, the reserved bits remain at 0. Also, interrupts are not sampled when the PSW is being written with a new value. If the ID flag is enabled with this instruction, interrupt disabling begins at the start of execution, even though the ID flag does not become valid until the beginning of the next instruction. Caution The system register number regID is a number which identifies a system register. Accessing system registers which are reserved or write-prohibited is prohibited and will lead to undefined results. 66 User's Manual U10243EJ7V0UM CHAPTER 5 INSTRUCTIONS MOV Move Instruction format (1) MOV reg1, reg2 (2) MOV imm5, reg2 Operation (1) GR [reg2] GR [reg1] (2) GR [reg2] sign-extend (imm5) Format (1) Format I (2) Format II Op code (1) 15 0 rrrrr000000RRRRR 15 0 (2) Flag CY OV S Z SAT Instruction rrrrr010000iiiii - - - - - (1) MOV Move Register (2) MOV Move Immediate (5-Bit) Explanation (1) Transfers the word data of general register reg1 to general register reg2. The data of general register reg1 is not affected. (2) Transfers the value of a 5-bit immediate data, sign-extended to word length, to general register reg2. User's Manual U10243EJ7V0UM 67 CHAPTER 5 INSTRUCTIONS MOVEA Move Effective Address Instruction format Operation Format Op code MOVEA imm16, reg1, reg2 GR [reg2] GR [reg1] + sign-extend (imm16) Format VI 15 0 31 16 rrrrr110001RRRRR iiiiiiiiiiiiiiii Flag CY OV S Z SAT Instruction Explanation - - - - - MOVEA Move Effective Address Adds the 16-bit immediate data, sign-extended to word length, to the word data of general register reg1, and stores the result in general register reg2. The data of general register reg1 is not affected. The flags are not affected by the addition. Remark This instruction calculates a 32-bit address and stores the result without affecting the PSW flags. 68 User's Manual U10243EJ7V0UM CHAPTER 5 INSTRUCTIONS MOVHI Move High Half-Word Instruction format Operation Format Op code MOVHI imm16, reg1, reg2 GR [reg2] GR [reg1] + (imm16 II 016) Format VI 15 0 31 16 rrrrr110010RRRRR iiiiiiiiiiiiiiii Flag CY OV S Z SAT Instruction Explanation - - - - - MOVHI Move High Half-Word Adds a word value, whose higher 16 bits are specified by the 16-bit immediate data and lower 16 bits are 0, to the word data of general register reg1 and stores the result in general register reg2. The data of general register reg1 is not affected. The flags are not affected by the addition. Remark This instruction is used to generate the higher 16 bits of a 32-bit address. User's Manual U10243EJ7V0UM 69 CHAPTER 5 INSTRUCTIONS MULH Multiply Half-Word Instruction format (1) MULH reg1, reg2 (2) MULH imm5, reg2 Operation (1) GR [reg2] (32) GR [reg2] (16) x GR [reg1] (16) (2) GR [reg2] GR [reg2] x sign-extend (imm5) Format (1) Format I (2) Format II Op code (1) 15 0 rrrrr000111RRRRR 15 0 (2) Flag CY OV S Z SAT Instruction rrrrr010111iiiii - - - - - (1) MULH Multiply Half-Word by Register (2) MULH Multiply Half-Word by Immediate (5-Bit) Explanation (1) Multiplies the lower half-word data of general register reg2 by the half-word data of general register reg1, and stores the result in general register reg2 as word data. The data of general register reg1 is not affected. (2) Multiplies the lower half-word data of general register reg2 by a 5-bit immediate data, signextended to half-word length, and stores the result in general register reg2. Remark The higher 16 bits of general registers reg1 and reg2 are ignored in this operation. 70 User's Manual U10243EJ7V0UM CHAPTER 5 INSTRUCTIONS MULHI Multiply Half-Word Immediate Instruction format Operation Format Op code MULHI imm16, reg1, reg2 GR [reg2] GR [reg1] x imm16 Format VI 15 0 31 16 rrrrr110111RRRRR iiiiiiiiiiiiiiii Flag CY OV S Z SAT Instruction Explanation - - - - - MULHI Multiply Half-Word by Immediate (16-Bit) Multiplies the lower half-word data of general register reg1 by the 16-bit immediate data, and stores the result in general register reg2. The data of general register reg1 is not affected. Remark The higher 16 bits of general register reg1 are ignored in this operation. User's Manual U10243EJ7V0UM 71 CHAPTER 5 INSTRUCTIONS NOP No Operation Instruction format Operation Format Op code NOP Executes nothing and consumes at least one clock. Format I 15 0 0000000000000000 Flag CY OV S Z SAT Instruction Explanation Remark - - - - - NOP No Operation Executes nothing and consumes at least one clock cycle. The contents of the PC are incremented by two. The op code is the same as that of MOV r0, r0. 72 User's Manual U10243EJ7V0UM CHAPTER 5 INSTRUCTIONS NOT Not Instruction format Operation Format Op code NOT reg1, reg2 GR [reg2] NOT (GR [reg1]) Format I 15 0 rrrrr000001RRRRR Flag CY OV S Z SAT Instruction Explanation - - 1 if the result of an operation is negative; otherwise, 0. 1 if the result of an operation is 0; otherwise, 0. - NOT Not Logically negates (takes the 1's complement of) the word data of general register reg1, and stores the result in general register reg2. The data of general register reg1 is not affected. User's Manual U10243EJ7V0UM 73 CHAPTER 5 INSTRUCTIONS NOT1 Not Bit Instruction format Operation NOT1 bit#3, disp16 [reg1] adr GR [reg1] + sign-extend (disp16) Z flag Not (Load-memory-bit (adr, bit#3)) Store-memory-bit (adr, bit#3, Z flag) Format Op code Format VIII 15 0 31 16 01bbb111110RRRRR dddddddddddddddd Flag CY OV S Z SAT Instruction Explanation - - - 1 if bit NO.bit#3 of memory disp16 [reg1] = 0. 0 if bit NO.bit#3 of memory disp16 [reg1] = 1. - NOT1 Not Bit Adds the data of general register reg1 to a 16-bit displacement, sign-extended to word length to generate a 32-bit address. The bit, specified by the 3-bit field "bbb", is inverted at the byte data location referenced by the generated address. The bits other than the specified bit are not affected. Remark The Z flag of the PSW indicates whether the specified bit was 0 or 1 before this instruction is executed, and does not indicate the content of the specified bit after this instruction has been executed. 74 User's Manual U10243EJ7V0UM CHAPTER 5 INSTRUCTIONS OR Or Instruction format Operation Format Op code OR reg1, reg2 GR [reg2] GR [reg2] OR GR [reg1] Format I 15 0 rrrrr001000RRRRR Flag CY OV S Z SAT Instruction Explanation OR Or ORs the word data of general register reg2 with the word data of general register reg1, and stores the result in general register reg2. The data of general register reg1 is not affected. - 0 1 if the result of an operation is negative; otherwise, 0. 1 if the result of an operation is 0; otherwise, 0. - User's Manual U10243EJ7V0UM 75 CHAPTER 5 INSTRUCTIONS ORI Or Immediate Instruction format Operation Format Op code ORI imm16, reg1, reg2 GR [reg2] GR [reg1] OR zero-extend (imm16) Format VI 15 0 31 16 rrrrr110100RRRRR iiiiiiiiiiiiiiii Flag CY OV S Z SAT Instruction Explanation - 0 1 if the result of an operation is negative; otherwise, 0. 1 if the result of an operation is 0; otherwise, 0. - OR Or Immediate (16-Bit) ORs the word data of general register reg1 with the value of the 16-bit immediate data, zeroextended to word length, and stores the result in general register reg2. The data of general register reg1 is not affected. 76 User's Manual U10243EJ7V0UM CHAPTER 5 INSTRUCTIONS RETI Return from Trap or Interrupt Instruction format Operation RETI if PSW.EP = 1 then PC EIPC PSW EIPSW else if PSW.NP = 1 then PC else PC FEPC EIPC PSW FEPSW PSW EIPSW Format Op code Format X 15 0 31 16 0000011111100000 0000000101000000 Flag CY OV S Z SAT Instruction Explanation Value read from FEPSW or EIPSW is set. Value read from FEPSW or EIPSW is set. Value read from FEPSW or EIPSW is set. Value read from FEPSW or EIPSW is set. Value read from FEPSW or EIPSW is set. RETI Return from Trap or Interrupt This instruction restores the restore PC and PSW from the appropriate system register and returns from an exception or interrupt routine. The operations of this instruction are as follows: (1) If the EP flag of the PSW is 1, the restore PC and PSW are read from the EIPC and EIPSW, regardless of the status of the NP flag of the PSW. If the EP flag of the PSW is 0 and the NP flag of the PSW is 1, the restore PC and PSW are read from the FEPC and FEPSW. If the EP flag of the PSW is 0 and the NP flag of the PSW is 0, the restore PC and PSW are read from the EIPC and EIPSW. (2) Once the PC and PSW are restored to the return values, control is transferred to the return address. User's Manual U10243EJ7V0UM 77 CHAPTER 5 INSTRUCTIONS Caution When restoring from an NMI or exception processing using the RETI instruction, the PSW.NP and PSW.EP flags must be set accordingly to restore the PC and PSW: * When returning from non-maskable interrupt processing using the RETI instruction: PSW.NP = 1 and PSW.EP = 0 * When restoring from an exception processing using the RETI instruction: PSW.EP = 1 Use the LDSR instruction for setting the flags. Interrupts are not accepted in the latter half of the ID stage during LDSR execution because of the operation of the interrupt controller. 78 User's Manual U10243EJ7V0UM CHAPTER 5 INSTRUCTIONS SAR Shift Arithmetic Right Instruction format (1) SAR reg1, reg2 (2) SAR imm5, reg2 Operation (1) GR [reg2] GR [reg2] arithmetically shift right by GR [reg1] (2) GR [reg2] GR [reg2] arithmetically shift right by zero-extend Format (1) Format IX (2) Format II Op code (1) 15 0 31 16 rrrrr111111RRRRR 0000000010100000 15 0 (2) Flag CY OV S Z SAT Instruction rrrrr010101iiiii 1 if the bit shifted out last is 1; otherwise, 0. However, if the number of shifts is 0, the result is 0. 0 1 if the result of an operation is negative; otherwise, 0. 1 if the result of an operation is 0; otherwise, 0. - (1) SAR Shift Arithmetic Right by Register (2) SAR Shift Arithmetic Right by Immediate (5-Bit) Explanation (1) Arithmetically shifts the word data of general register reg2 to the right by `n' positions, where `n' is a value from 0 to +31, specified by the lower 5 bits of general register reg1 (after the shift, the MSB prior to shift execution is copied and set as the new MSB value), and then writes the result to general register reg2. If the number of shifts is 0, general register reg2 retains the same value prior to instruction execution. The data of general register reg1 is not affected. (2) Arithmetically shifts the word data of general register reg2 to the right by `n' positions, where `n' is a value from 0 to +31, specified by the 5-bit immediate data, zero-extended to word length (after the shift, the MSB prior to shift execution is copied and set as the new MSB value), and then writes the result to general register reg2. If the number of shifts is 0, general register reg2 retains the same value prior to instruction execution. User's Manual U10243EJ7V0UM 79 CHAPTER 5 INSTRUCTIONS SATADD Saturated Add Instruction format (1) SATADD reg1, reg2 (2) SATADD imm5, reg2 Operation (1) GR [reg2] saturated (GR [reg2] + GR [reg1]) (2) GR [reg2] saturated (GR [reg2] + sign-extend (imm5)) Format (1) Format I (2) Format II Op code (1) 15 0 rrrrr000110RRRRR 15 0 (2) Flag CY OV S Z SAT Instruction rrrrr010001iiiii 1 if a carry occurs from MSB; otherwise, 0. 1 if an overflow occurs; otherwise, 0. 1 if the result of the saturated operation is negative; otherwise, 0. 1 if the result of the saturated operation is 0; otherwise, 0. 1 if OV = 1; otherwise, not affected. (1) SATADD Saturated Add Register (2) SATADD Saturated Add Immediate (5-Bit) Explanation (1) Adds the word data of general register reg1 to the word data of general register reg2, and stores the result in general register reg2. However, if the result exceeds the maximum positive value 7FFFFFFFH, 7FFFFFFFH is stored in reg2; if the result exceeds the maximum negative value 80000000H, 80000000H is stored in reg2. The SAT flag is set to 1. The data of general register reg1 is not affected. (2) Adds a 5-bit immediate data, sign-extended to word length, to the word data of general register reg2, and stores the result in general register reg2. However, if the result exceeds the maximum positive value 7FFFFFFFH, 7FFFFFFFH is stored in reg2; if the result exceeds the maximum negative value 80000000H, 80000000H is stored in reg2. The SAT flag is set to 1. Remark The SAT flag is a cumulative flag. Once the result of the saturated operation instruction has been saturated, this flag is set to 1 and is not reset to 0 even if the result of the subsequent operation is not saturated. Even if the SAT flag is set to 1, the saturated operation instruction is executed normally. Caution To reset the SAT flag to 0, load data to the PSW by using the LDSR instruction. 80 User's Manual U10243EJ7V0UM CHAPTER 5 INSTRUCTIONS SATSUB Saturated Subtract Instruction format Operation Format Op code SATSUB reg1, reg2 GR [reg2] saturated (GR [reg2] - GR [reg1]) Format I 15 0 rrrrr000101RRRRR Flag CY OV S Z SAT Instruction Explanation 1 if a borrow to MSB occurs; otherwise, 0. 1 if an overflow occurs; otherwise, 0. 1 if the result of the saturated operation is negative; otherwise, 0. 1 if the result of the saturated operation is 0; otherwise, 0. 1 if OV = 1; otherwise, not affected. SATSUB Saturated Subtract Subtracts the word data of general register reg1 from the word data of general register reg2, and stores the result in general register reg2. However, if the result exceeds the maximum positive value 7FFFFFFFH, 7FFFFFFFH is stored in reg2; if the result exceeds the maximum negative value 80000000H, 80000000H is stored in reg2. The SAT flag is set to 1. The data of general register reg1 is not affected. Remark The SAT flag is a cumulative flag. Once the result of the operation of the saturated operation instruction has been saturated, this flag is set to 1 and is not reset to 0 even if the result of the subsequent operations is not saturated. Even if the SAT flag is set to 1, the saturated operation instruction is executed normally. Caution To reset the SAT flag to 0, load data to the PSW by using the LDSR instruction. User's Manual U10243EJ7V0UM 81 CHAPTER 5 INSTRUCTIONS SATSUBI Saturated Subtract Immediate Instruction format Operation Format Op code SATSUBI imm16, reg1, reg2 GR [reg2] saturated (GR [reg1] - sign-extend (imm16)) Format VI 15 0 31 16 rrrrr110011RRRRR iiiiiiiiiiiiiiii Flag CY OV S Z SAT Instruction Explanation 1 if a borrow to MSB occurs; otherwise, 0. 1 if an overflow occurs; otherwise, 0. 1 if the result of the saturated operation is negative; otherwise, 0. 1 if the result of the saturated operation is 0; otherwise, 0. 1 if OV = 1; otherwise, not affected. SATSUBI Saturated Subtract Immediate Subtracts the 16-bit immediate data, sign-extended to word length, from the word data of general register reg1, and stores the result in general register reg2. However, if the result exceeds the maximum positive value 7FFFFFFFH, 7FFFFFFFH is stored in reg2; if the result exceeds the maximum negative value 80000000H, 80000000H is stored in reg2. The SAT flag is set to 1. The data of general register reg1 is not affected. Remark The SAT flag is a cumulative flag. Once the result of the operation of the saturated operation instruction has been saturated, this flag is set to 1 and is not reset to 0 even if the result of the subsequent operations is not saturated. Even if the SAT flag is set to 1, the saturated operation instruction is executed normally. Caution To reset the SAT flag to 0, load data to the PSW by using the LDSR instruction. 82 User's Manual U10243EJ7V0UM CHAPTER 5 INSTRUCTIONS SATSUBR Saturated Subtract Reverse Instruction format Operation Format Op code SATSUBR reg1, reg2 GR [reg2] saturated (GR [reg1] - GR [reg2]) Format I 15 0 rrrrr000100RRRRR Flag CY OV S Z SAT Instruction Explanation 1 if a borrow to MSB occurs; otherwise, 0. 1 if an overflow occurs; otherwise, 0. 1 if the result of the saturated operation is negative; otherwise, 0. 1 if the result of the saturated operation is 0; otherwise, 0. 1 if OV = 1; otherwise, not affected. SATSUBR Saturated Subtract Reverse Subtracts the word data of general register reg2 from the word data of general register reg1, and stores the result in general register reg2. However, if the result exceeds the maximum positive value 7FFFFFFFH, 7FFFFFFFH is stored in reg2; if the result exceeds the maximum negative value 80000000H, 80000000H is stored in reg2. The SAT flag is set to 1. The data of general register reg1 is not affected. Remark The SAT flag is a cumulative flag. Once the result of the operation of the saturated operation instruction has been saturated, this flag is set to 1 and is not reset to 0 even if the result of the subsequent operations is not saturated. Even if the SAT flag is set to 1, the saturated operation instruction is executed normally. Caution To reset the SAT flag to 0, load data to the PSW by using the LDSR instruction. User's Manual U10243EJ7V0UM 83 CHAPTER 5 INSTRUCTIONS SETF Set Flag Condition Instruction format Operation SETF cccc, reg2 if conditions are satisfied then GR [reg2] 00000001H else GR [reg2] 00000000H Format Op code Format IX 15 0 31 16 rrrrr1111110cccc 0000000000000000 Flag CY OV S Z SAT Instruction Explanation - - - - - SETF Set Flag Condition The general register reg2 is set to 1 if a condition specified by condition code "cccc" is satisfied; otherwise, 0 are stored in the register. One of the codes shown in Table 5-9 should be specified as the condition code "cccc". Remark Here are some examples of using this instruction: (1) Translation of two or more condition clauses: If A of statement if (A) in C language consists of two or more condition clauses (a1, a2, a3, and so on), it is usually translated to a sequence of if (a1) then, if (a2) then. The object code executes "conditional branch" by checking the result of evaluation equivalent to an. A pipeline processor takes more time to execute "condition judgment" + "branch" than to execute an ordinary operation, the result of evaluating each condition clause if (an) is stored to register Ra. By performing a logical operation to Ran after all the condition clauses have been evaluated, the delay due to the pipeline can be prevented. (2) Double-length operation: To execute a double-length operation such as Add with Carry, the result of the CY flag can be stored to general register reg2. Therefore, a carry from the lower bits can be expressed as a numeric value. 84 User's Manual U10243EJ7V0UM CHAPTER 5 INSTRUCTIONS Table 5-9. Condition Codes Condition Code (cccc) 0000 1000 0001 1001 0010 1010 0011 1011 0100 1100 0101 1101 0110 1110 0111 1111 Condition Name V NV C/L NC/NL Z NZ NH H S/N NS/P T SA LT GE LE GT OV = 1 OV = 0 CY = 1 CY = 0 Z=1 Z=0 Condition Expression (CY or Z) = 1 (CY or Z) = 0 S=1 S=0 always SAT = 1 (S xor OV) = 1 (S xor OV) = 0 ((S xor OV) or Z) = 1 ((S xor OV) or Z) = 0 User's Manual U10243EJ7V0UM 85 CHAPTER 5 INSTRUCTIONS SET1 Set Bit Instruction format Operation SET1 bit#3, disp16 [reg1] adr GR [reg1] + sign-extend (disp16) Z flag Not (Load-memory-bit (adr, bit#3)) Store-memory-bit (adr, bit#3, 1) Format Op code Format VIII 15 0 31 16 00bbb111110RRRRR dddddddddddddddd Flag CY OV S Z SAT Instruction Explanation - - - 1 when bit NO.bit#3 of memory disp16 [reg1] = 0. 0 when bit NO.bit#3 of memory disp16 [reg1] = 1 - SET1 Set Bit Adds the 16-bit displacement, sign-extended to word length, to the data of general register reg1 to generate a 32-bit address. The bit, specified by the 3-bit field "bbb", is set at the byte data location referenced by the generated address. The bits other than the specified bit are not affected. Remark The Z flag of the PSW indicates whether the specified bit was 0 or 1 before this instruction is executed, and does not indicate the content of the specified bit after this instruction has been executed. 86 User's Manual U10243EJ7V0UM CHAPTER 5 INSTRUCTIONS SHL Shift Logical Left Instruction format (1) SHL reg1, reg2 (2) SHL imm5, reg2 Operation (1) GR [reg2] GR [reg2] logically shift left by (2) GR [reg2] GR [reg2] logically shift left by GR [reg1] zero-extend (imm5) Format (1) Format IX (2) Format II Op code (1) 15 0 31 16 rrrrr111111RRRRR 0000000011000000 15 0 (2) Flag CY OV S Z SAT Instruction rrrrr010110iiiii 1 if the bit shifted out last is 1; otherwise, 0. However, if the number of shifts is 0, the result is 0. 0 1 if the result of an operation is negative; otherwise, 0. 1 if the result of an operation is 0; otherwise, 0. - (1) SHL Shift Logical Left by Register (2) SHL Shift Logical Left by Immediate (5-Bit) Explanation (1) Logically shifts the word data of general register reg2 to the left by `n' positions, where `n' is a value from 0 to +31, specified by the lower 5 bits of general register reg1 (0 is shifted to the LSB side), and then writes the result to general register reg2. If the number of shifts is 0, general register reg2 retains the same value prior to instruction execution. The data of general register reg1 is not affected. (2) Logically shifts the word data of general register reg2 to the left by `n' positions, where `n' is a value from 0 to +31, specified by the 5-bit immediate data, zero-extended to word length (0 is shifted to the LSB side), and then writes the result to general register reg2. If the number of shifts is 0, general register reg2 retains the value prior to instruction execution. User's Manual U10243EJ7V0UM 87 CHAPTER 5 INSTRUCTIONS SHR Shift Logical Right Instruction format (1) SHR reg1, reg2 (2) SHR imm5, reg2 Operation (1) GR [reg2] GR [reg2] logically shift right by GR [reg1] (2) GR [reg2] GR [reg2] logically shift right by zero-extend (imm5) Format (1) Format IX (2) Format II Op code (1) 15 0 31 16 rrrrr111111RRRRR 0000000010000000 15 0 (2) Flag CY OV S Z SAT Instruction rrrrr010100iiiii 1 if the bit shifted out last is 1; otherwise, 0. However, if the number of shifts is 0, the result is 0. 0 1 if the result of an operation is negative; otherwise, 0. 1 if the result of an operation is 0; otherwise, 0. - (1) SHR Shift Logical Right by Register (2) SHR Shift Logical Right by Immediate (5-Bit) Explanation (1) Logically shifts the word data of general register reg2 to the right by `n' positions where `n' is a value from 0 to +31, specified by the lower 5 bits of general register reg1 (0 is shifted to the MSB side). This instruction then writes the result to general register reg2. If the number of shifts is 0, general register reg2 retains the same value prior to instruction execution. The data of general register reg1 is not affected. (2) Logically shifts the word data of general register reg2 to the right by `n' positions, where `n' is a value from 0 to +31, specified by the 5-bit immediate data, zero-extended to word length (0 is shifted to the MSB side). This instruction then writes the result to general register reg2. If the number of shifts is 0, general register reg2 retains the same value prior to instruction execution. 88 User's Manual U10243EJ7V0UM CHAPTER 5 INSTRUCTIONS SLD Load Instruction format (1) SLD.B disp7 [ep], reg2 (2) SLD.H disp8 [ep], reg2 (3) SLD.W disp8 [ep], reg2 Operation (1) adr ep + zero-extend (disp7) GR [reg2] sign-extend (Load-memory (adr, Byte)) (2) adr ep + zero-extend (disp8) GR [reg2] sign-extend (Load-memory (adr, Halfword)) (2) adr ep + zero-extend (disp8) GR [reg2] Load-memory (adr, Word) Format Op code Format IV 15 (1) 0 rrrrr0110ddddddd 15 0 (2) rrrrr1000ddddddd ddddddd is the higher 7 bits of disp8. 15 0 (3) rrrrr1010dddddd0 dddddd is the higher 6 bits of disp8. Flag CY OV S Z SAT - - - - - Instruction (1) SLD.B Short format Load Byte (2) SLD.H Short format Load Half-Word (3) SLD.W Short format Load Word User's Manual U10243EJ7V0UM 89 CHAPTER 5 INSTRUCTIONS Explanation (1) Adds the 7-bit displacement, zero-extended to word length, to the element pointer to generate a 32-bit address. Byte data is read from the generated address, sign-extended to word length, and stored in reg2. (2) Adds the 8-bit displacement, zero-extended to word length, to the element pointer to generate a 32-bit address. Half-word data is read from this 32-bit address with bit 0 masked to 0, sign-extended to word length, and stored in reg2. (3) Adds the 8-bit displacement, zero-extended to word length, to the element pointer to generate a 32-bit address. Word data is read from this 32-bit address with bits 0 and 1 masked to 0, and stored in reg2. Caution When the element pointer is added to the 8-bit displacement zero extended to word length, the lower bits of the result may be masked to 0 depending on the type of data to be accessed (half word, word). 90 User's Manual U10243EJ7V0UM CHAPTER 5 INSTRUCTIONS SST Store Instruction format (1) SST.B reg2, disp7 [ep] (2) SST.H reg2, disp8 [ep] (3) SST.W reg2, disp8 [ep] Operation (1) adr ep + zero-extend (disp7) Store-memory (adr, GR [reg2], Byte) (2) adr ep + zero-extend (disp8) Store-memory (adr, GR [reg2], Halfword) (2) adr ep + zero-extend (disp8) Store-memory (adr, GR [reg2], Word) Format Op code Format IV 15 (1) 0 rrrrr0111ddddddd 15 0 (2) rrrrr1001ddddddd ddddddd is the higher 7 bits of disp8. 15 0 (3) rrrrr1010dddddd1 dddddd is the higher 6 bits of disp8. Flag CY OV S Z SAT - - - - - Instruction (1) SST.B Short format Store Byte (2) SST.H Short format Store Half-Word (3) SST.W Short format Store Word User's Manual U10243EJ7V0UM 91 CHAPTER 5 INSTRUCTIONS Explanation (1) Adds the 7-bit displacement, zero-extended to word length, to the element pointer to generate a 32-bit address, and stores the data of the lowest byte of reg2 at the generated address. (2) Adds the 8-bit displacement, zero-extended to word length, to the element pointer to generate a 32-bit address, and stores the lower half-word data of reg2 at the generated 32-bit address with bit 0 masked to 0. (3) Adds the 8-bit displacement, zero-extended to word length, to the element pointer to generate a 32-bit address, and stores the word data of reg2 at the generated 32-bit address with bits 0 and 1 masked to 0. Caution When the element pointer is added to the 8-bit displacement zero-extended to word length, the lower bits of the result may be masked to 0 depending on the type of data to be accessed (half word, word). 92 User's Manual U10243EJ7V0UM CHAPTER 5 INSTRUCTIONS ST Store Instruction format (1) ST.B reg2, disp16 [reg1] (2) ST.H reg2, disp16 [reg1] (3) ST.W reg2, disp16 [reg1] Operation (1) adr GR [reg1] + sign-extend (disp16) Store-memory (adr, GR [reg2], Byte) (2) adr GR [reg1] + sign-extend (disp16) Store-memory (adr, GR [reg2], Halfword) (2) adr GR [reg1] + sign-extend (disp16) Store-memory (adr, GR [reg2], Word) Format Op code Format VII 15 (1) 0 31 16 rrrrr111010RRRRR dddddddddddddddd 15 0 31 16 (2) rrrrr111011RRRRR ddddddddddddddd0 ddddddddddddddd is the higher 15 bits of disp16. 15 0 31 16 (3) rrrrr111011RRRRR ddddddddddddddd1 ddddddddddddddd is the higher 15 bits of disp16. Flag CY OV S Z SAT - - - - - Instruction (1) ST.B Store Byte (2) ST.H Store Half-Word (3) ST.W Store Word User's Manual U10243EJ7V0UM 93 CHAPTER 5 INSTRUCTIONS Explanation (1) Adds the 16-bit displacement, sign-extended to word length, to the data of general register reg1 to generate a 32-bit address, and stores the lowest byte data of general register reg2 at the generated address. (2) Adds the 16-bit displacement, sign-extended to word length, to the data of general register reg1 to generate a 32-bit address, and stores the lower half-word data of general register reg2 at the generated 32-bit address with bit 0 masked to 0. Therefore, stored data is automatically aligned on a half-word boundary. (3) Adds the 16-bit displacement, sign-extended to word length, to the data of general register reg1 to generate a 32-bit address, and stores the word data of general register reg2 at the generated 32-bit address with bits 0 and 1 masked to 0. Therefore, stored data is automatically aligned on a word boundary. Caution When the data of general register reg1 is added to a 16-bit displacement sign-extended to word length, the lower bits of the result may be masked to 0 depending on the type of data to be accessed (half word, word) to generate an address. 94 User's Manual U10243EJ7V0UM CHAPTER 5 INSTRUCTIONS STSR Store Contents of System Register Instruction format Operation Format Op code STSR regID, reg2 GR [reg2] SR [regID] Format IX 15 0 31 16 rrrrr111111RRRRR 0000000001000000 Flag CY OV S Z SAT Instruction Explanation - - - - - STSR Store Contents of System Register Stores the contents of a system register specified by system register number (regID) in general register reg2. The contents of the system register are not affected. Remark The system register number regID is a number which identifies a system register. Accessing system register which is reserved is prohibited and will lead to undefined results. User's Manual U10243EJ7V0UM 95 CHAPTER 5 INSTRUCTIONS SUB Subtract Instruction format Operation Format Op code SUB reg1, reg2 GR [reg2] GR [reg2] - [reg1] Format I 15 0 rrrrr001101RRRRR Flag CY OV S Z SAT Instruction Explanation 1 if a borrow to MSB occurs; otherwise, 0. 1 if an overflow occurs; otherwise, 0. 1 if the result of an operation is negative; otherwise, 0. 1 if the result of an operation is 0; otherwise, 0. - SUB Subtract Subtracts the word data of general register reg1 from the word data of general register reg2, and stores the result in general register reg2. The data of general register reg1 is not affected. 96 User's Manual U10243EJ7V0UM CHAPTER 5 INSTRUCTIONS SUBR Subtract Reverse Instruction format Operation Format Op code SUBR reg1, reg2 GR [reg2] GR [reg1] - GR [reg2] Format I 15 0 rrrrr001100RRRRR Flag CY OV S Z SAT Instruction Explanation 1 if a borrow to MSB occurs; otherwise, 0. 1 if an overflow occurs; otherwise, 0. 1 if the result of an operation is negative; otherwise, 0. 1 if the result of an operation is 0; otherwise, 0. - SUBR Subtract Reverse Subtracts the word data of general register reg2 from the word data of general register reg1, and stores the result in general register reg2. The data of general register reg1 is not affected. User's Manual U10243EJ7V0UM 97 CHAPTER 5 INSTRUCTIONS TRAP Software Trap Instruction format Operation TRAP vector EIPC EIPSW ECR.EICC PSW.EP PSW.ID PC PC + 4 (restore PC) PSW interrupt code 1 1 00000040H (vector = 00H to 0FH) 00000050H (vector = 10H to 1FH) Format Op code Format X 15 0 31 16 00000111111iiiii 0000000100000000 Flag CY OV S Z SAT Instruction Explanation - - - - - TRAP Trap Saves the restore PC and PSW to EIPC and EIPSW, respectively; sets the exception code (EICC of ECR) and the flags of the PSW (EP and ID flags); jumps to the address of the trap handler corresponding to the trap vector specified by vector number (0 to 31), and starts exception processing. The condition flags are not affected. The restore PC is the address of the instruction following the TRAP instruction. 98 User's Manual U10243EJ7V0UM CHAPTER 5 INSTRUCTIONS TST Test Instruction format Operation Format Op code TST reg1, reg2 result GR [reg2] AND GR [reg1] Format I 15 0 rrrrr001011RRRRR Flag CY OV S Z SAT Instruction Explanation - 0 1 if the result of an operation is negative; otherwise, 0. 1 if the result of an operation is 0; otherwise, 0. - TST Test ANDs the word data of general register reg2 with the word data of general register reg1. The result is not stored, and only the flags are changed. The data of general registers reg1 and reg2 are not affected. User's Manual U10243EJ7V0UM 99 CHAPTER 5 INSTRUCTIONS TST1 Test Bit Instruction format Operation TST1 bit#3, disp16 [reg1] adr GR [reg1] + sign-extend (disp16) Z flag Not (Load-memory-bit (adr,bit#3)) Format Op code Format VIII 15 0 31 16 11bbb111110RRRRR dddddddddddddddd Flag CY OV S Z SAT Instruction Explanation - - - 1 if bit NO.bit#3 of memory disp16 [reg1] = 0. 0 if bit NO.bit#3 of memory disp16 [reg1] = 1. - TST1 Test Bit Adds the data of general register reg1 to a 16-bit displacement, sign-extended to word length, to generate a 32-bit address. Performs the test on the bit, specified by the 3-bit field "bbb", at the byte data location referenced by the generated address. If the specified bit is 0, the Z flag is set to 1; if the bit is 1, the Z flag is reset to 0. The byte data, including the specified bit, is not affected. 100 User's Manual U10243EJ7V0UM CHAPTER 5 INSTRUCTIONS XOR Exclusive Or Instruction format Operation Format Op code XOR reg1, reg2 GR [reg2] GR [reg2] XOR GR [reg1] Format I 15 0 rrrrr001001RRRRR Flag CY OV S Z SAT Instruction Explanation - 0 1 if the result of an operation is negative; otherwise, 0. 1 if the result of an operation is 0; otherwise, 0. - XOR Exclusive Or Exclusively ORs the word data of general register reg2 with the word data of general register reg1, and stores the result in general register reg2. The data of general register reg1 is not affected. User's Manual U10243EJ7V0UM 101 CHAPTER 5 INSTRUCTIONS XORI Exclusive Or Immediate Instruction format Operation Format Op code XORI imm16, reg1, reg2 GR [reg2] GR [reg1] XOR zero-extend (imm16) Format VI 15 0 31 16 rrrrr110101RRRRR iiiiiiiiiiiiiiii Flag CY OV S Z SAT Instruction Explanation - 0 1 if the result of an operation is negative; otherwise, 0. 1 if the result of an operation is 0; otherwise, 0. - XORI Exclusive Or Immediate (16-Bit) Exclusively ORs the word data of general register reg1 with a 16-bit immediate data, zeroextended to word length, and stores the result in general register reg2. The data of general register reg1 is not affected. 102 User's Manual U10243EJ7V0UM CHAPTER 5 INSTRUCTIONS 5.4 Number of Instruction Execution Clock Cycles The number of instruction execution clock cycles differs depending on the combination of instructions. For details, see CHAPTER 8 PIPELINE. Table 5-10 shows a list of the number of instruction execution clock cycles. Table 5-10. List of Number of Instruction Execution Clock Cycles (1/3) Execution clock i-r-l Load/store SLD.B SLD.H SLD.W SST.B SST.H SST.W LD.B LD.H LD.W ST.B ST.H ST.W Arithmetic operation MOV MOV MOVEA MOVHI DIVH MULH MULH MULHI ADD ADD ADDI CMP CMP SUBR SUB SETF Saturated operation SATSUBR SATSUB SATADD SATADD SATSUBI disp7 [ep], r disp8 [ep], r disp8 [ep], r r, disp7 [ep] r, disp8 [ep] r, disp8 [ep] disp16 [R], r disp16 [R], r disp16 [R], r r, disp16 [R] r, disp16 [R] r, disp16 [R] R, r imm5, r imm16, R, r imm16, R, r R, r R, r imm5, r imm16, R, r R, r imm5, r imm16, R, r R, r imm5, r R, r R, r cccc, r R, r R, r R, r imm5, r imm16, R, r 2 2 2 2 2 2 4 4 4 4 4 4 2 2 4 4 2 2 2 4 2 2 4 2 2 2 2 4 2 2 2 2 4 1-1-2 1-1-2 1-1-2 1-1-1 1-1-1 1-1-1 1-1-2 1-1-2 1-1-2 1-1-1 1-1-1 1-1-1 1-1-1 1-1-1 1-1-1 1-1-1 36 - 36 - 36 1-1-2 1-1-2 1-1-2 1-1-1 1-1-1 1-1-1 1-1-1 1-1-1 1-1-1 1-1-1 1-1-1 1-1-1 1-1-1 1-1-1 1-1-1 1-1-1 Instructions Mnemonic Operand Byte User's Manual U10243EJ7V0UM 103 CHAPTER 5 INSTRUCTIONS Table 5-10. List of Number of Instruction Execution Clock Cycles (2/3) Execution clock i-r-l Logical operation NOT OR XOR AND TST SHR SAR SHL ORI XORI ANDI SHR SAR SHL Branch JMP JR JARL Bcond R, r R, r R, r R, r R, r imm5, r imm5, r imm5, r imm16, R, r imm16, R, r imm16, R, r R, r R, r R, r [R] disp22 disp22, r disp9 When condition is satisfied When condition is not satisfied Bit manipulation SET1 CLR1 NOT1 TST1 Special LDSR STSR NOP DI EI TRAP HALT RETI bit#3, disp16 [R] bit#3, disp16 [R] bit#3, disp16 [R] bit#3, disp16 [R] R, SR SR, r - - - vector - - 2 2 2 2 2 2 2 2 4 4 4 4 4 4 2 4 4 2 2 4 4 4 4 4 4 2 4 4 4 4 4 4 1-1-1 1-1-1 1-1-1 1-1-1 1-1-1 1-1-1 1-1-1 1-1-1 1-1-1 1-1-1 1-1-1 1-1-1 1-1-1 1-1-1 3-3-3 3-3-3 3-3-3 3-3-3 1-1-1 4-4-4 4-4-4 4-4-4 3-3-3 1 - 1 -Note 1-1-1 1-1-1 1-1-1 1-1-1 4-4-4 1-1-1 4-4-4 4-4-4 Instructions Mnemonic Operand Byte Undefined instruction code trap Note When accessing EIPC, FEPC: 3 When accessing EIPSW, FEPSW, PSW: 1 104 User's Manual U10243EJ7V0UM CHAPTER 5 INSTRUCTIONS Table 5-10. List of Number of Instruction Execution Clock Cycles (3/3) Operand Symbol R: reg1 r: reg2 SR: System Register immx: immediate dispx: displacement bit#3: bit number ep: Element Pointer B: Byte H: Halfword W: Word cccc: conditions vector Meaning General register (used as source register) General register (mainly used as destination register) System register x-bit immediate x-bit displacement 3-bit data for bit number specification Element pointer Byte (8 bits) Half-word (16 bits) Word (32 bits) 4-bit data condition code specification 5-bit data for trap vector (00H to 1FH) specification Execution clock Symbol i: issue r: repeat Meaning When other instruction is executed immediately after executing an instruction When the same instruction is repeatedly executed immediately after the instruction has been executed If result of instruction execution is quoted by immediately subsequent instruction l: latency User's Manual U10243EJ7V0UM 105 CHAPTER 6 INTERRUPTS AND EXCEPTIONS Interrupts are events that occur independently of the program execution and are divided into two types: maskable and non-maskable interrupts. In contrast, an exception is an event whose occurrence is dependent on the program execution. There is no major difference between interrupts and exceptions in terms of control flow. The V850 Family can process various interrupt requests from the on-chip peripheral hardware and external sources. In addition, exception processing can be started by an instruction (TRAP instruction) and by the occurrence of an exception event (exception trap). The interrupts and exceptions supported in the V850 Family are described below. When an interrupt or exception is deleted, control is transferred to a handler whose address is determined by the source of the interrupt or exception. The source of the event is specified by the exception code that is stored in the exception cause register (ECR). Each handler analyzes the exception cause register (ECR) and performs appropriate interrupt servicing or exception handling. The restore PC and PSW are written to the status saving registers (EIPC, EIPSW/FEPC, FEPSW). To restore execution from interrupt or exception processing, use the RETI instruction. Read the restore PC and PSW from the status saving register, and transfer control to the restore PC. * Types of interrupt/exception processing The V850 Family handles the following four types of interrupts/exceptions: * Non-maskable interrupt * Maskable interrupt * Software exception * Exception trap 106 User's Manual U10243EJ7V0UM CHAPTER 6 INTERRUPTS AND EXCEPTIONS Table 6-1. List of Interrupt/Exception Codes Interrupt/Exception Cause Name NMI Maskable interrupt TRAP0n (n = 0 to FH) TRAP1n (n = 0 to FH) ILGOP Trigger NMI input Note 1 TRAP instruction TRAP instruction Illegal op code Interrupt Interrupt Exception Exception Exception 0010H Note 1 004nH 005nH 0060H 00000010H Note 1 00000040H 00000050H 00000060H next PCNote next PCNote next PC next PC next PCNote 3 2 2 Classification Exception Code Handler Address Restore PC Notes 1. Differs depending on the type of the maskable interrupt. 2. If an interrupt is acknowledged during execution of a DIVH (divide) instruction, the restore PC becomes the PC value for the currently executed instruction (DIVH). 3. The execution address of the illegal instruction is obtained by "restore PC-4" when an illegal op code exception occurs. The restore PC is the PC saved to the EIPC or FEPC when interrupt/exception processing is started. "next PC" is the PC that starts processing after interrupt/exception processing. The processing of maskable interrupts is controlled by the user through the INTC unit (interrupt controller). The INTC is different for each device in the V850 Family due to the variations of on-chip peripherals, interrupt/exception causes and exception codes. 6.1 Interrupt Processing 6.1.1 Maskable interrupts A maskable interrupt can be masked by the program status word (PSW). The INTC issues an interrupt request to the CPU, based on the acknowledged interrupt with the highest priority. If a maskable interrupt occurs due to INT input, the processor performs the following steps, and transfers control to the handler routine. (1) Saves restore PC to EIPC. (2) Saves current PSW to EIPSW. (3) Writes exception code to lower half-word of ECR (EICC). (4) Sets ID bit of PSW and clears EP bit. (5) Sets handler address for each interrupt to PC and transfers control. The EIPC and EIPSW are used as the status saving registers. Interrupts are held pending in the interrupt controller (INTC) when one of the following two conditions occurs: when the interrupt input (INT) is masked by its INTC, or when an interrupt processing routine is currently being executed (when the NP bit of the PSW is 1 or when the ID bit of the PSW is 1). New maskable interrupt processing is started by the pending INT input when the mask condition is cleared and the NP and ID bits of the PSW are reset to 0 by the LDSR and RETI instructions. The EIPC and EIPSW must be saved by the program to enable nesting of interrupts because only one set of EIPC and EIPSW is provided. Bits 31 through 24 of the EIPC and bits 31 through 8 of the EIPSW are fixed to 0. Figure 6-1 illustrates how a maskable interrupt is processed. User's Manual U10243EJ7V0UM 107 CHAPTER 6 INTERRUPTS AND EXCEPTIONS Figure 6-1. Maskable Interrupt Processing Format Maskable interrupt (INT) occurs Mask No Yes Interrupt request pending PSW.NP 0 1 PSW.ID 0 EIPC EIPSW ECR.EICC PSW.EP PSW.ID PC 1 Interrupt processing pending Restore PC PSW Exception code 0 1 Handler address Interrupt processing 108 User's Manual U10243EJ7V0UM CHAPTER 6 INTERRUPTS AND EXCEPTIONS 6.1.2 Non-maskable interrupts A non-maskable interrupt cannot be disabled by an instruction and therefore can be always acknowledged. The non-maskable interrupt of the V850 Family is generated by NMI input. When a non-maskable interrupt is generated by NMI input, the processor performs the following steps, and transfers control to the handler routine. (1) Saves restore PC to FEPC. (2) Saves current PSW to FEPSW. (3) Writes exception code to higher half-word of ECR (FECC). (4) Sets NP and ID bits of PSW and clears EP bit. (5) Sets handler address (00000010H) for non-maskable interrupt to PC and transfers control. The FEPC and FEPSW are used as the status saving registers. Non-maskable interrupts are held pending in the INTC when another non-maskable interrupt is currently being executed (when the NP bit of the PSW is 1). New nonmaskable interrupt processing is started by the pending non-maskable interrupt request when the NP bit of the PSW is reset to 0 by the RETI and LDSR instructions. Figure 6-2 illustrates how a non-maskable interrupt is processed. Figure 6-2. Non-maskable Interrupt Processing Format Non-maskable interrupt (NMI) occurs PSW.NP 0 FEPC FEPSW ECR.FECC PSW.NP PSW.EP PSW.ID PC 1 Restore PC PSW Exception code 1 0 1 00000010H Interrupt request pending Interrupt processing User's Manual U10243EJ7V0UM 109 CHAPTER 6 INTERRUPTS AND EXCEPTIONS 6.2 Exception Processing 6.2.1 Software exceptions A software exception is generated when the CPU executes the TRAP instruction and is always acknowledged. If a software exception occurs, the CPU performs the following steps,and transfers control to the handler routine. (1) Saves restore PC to EIPC. (2) Saves current PSW to EIPSW. (3) Writes exception code to lower 16 bits (EICC) of ECR (interrupt cause). (4) Sets EP and ID bits of PSW. (5) Sets handler address (00000040H or 00000050H) for software exception to PC and transfers control. Figure 6-3 illustrates how the software exception is processed. Figure 6-3. Software Exception Processing Format Software exception (TRAP instruction) occurs EIPC EIPSW ECR.EICC PSW.EP PSW.ID PC Restore PC PSW Exception code 1 1 Handler address Exception processing Handler address: 00000040H (vector = 0nH) 00000050H (vector = 1nH) 110 User's Manual U10243EJ7V0UM CHAPTER 6 INTERRUPTS AND EXCEPTIONS 6.2.2 Exception trap An exception trap is an interrupt requested when an instruction is illegally executed. The exception trap of the V850 Family is generated by an illegal op code instruction code trap (ILGOP: ILleGal OPcode trap). An illegal op code instruction has an instruction code with an op code (bits 5 through 10) of 111111B and a subop code (bits 23 through 26) of 0011B through 1111B. When this kind of an illegal op code instruction is executed, an illegal op code instruction code trap occurs. Figure 6-4. Illegal Instruction Code 15 13 12 11 10 5 4 0 31 27 26 00 to 11 1 1 23 22 21 20 1 1 17 16 xxx xx111111xxxxxxxxxx xxxxxxx Remark x : don't care : Op code/sub-op code position If an exception trap occurs, the CPU performs the following steps, and transfers control to the handler routine. (1) Saves restore PC to EIPC. (2) Saves current PSW to EIPSW. (3) Writes exception code to lower 16 bits (EICC) of ECR. (4) Sets NP, EP, and ID bits of PSW. (5) Sets handler address (00000060H) for exception trap to PC and transfers control. Figure 6-5 illustrates how the exception trap is processed. Figure 6-5. Exception Trap Processing Format Exception trap (ILGOP) occurs EIPC EIPSW ECR.EICC PSW.NP PSW.EP PSW.ID PC Restore PC PSW Exception code 1 1 1 00000060H Exception processing The execution address of the illegal instruction is obtained by "restore PC - 4" when an exception trap occurs. Caution The operation is not guaranteed when an instruction that has not been defined either as an instruction or an illegal instruction is executed. User's Manual U10243EJ7V0UM 111 CHAPTER 6 INTERRUPTS AND EXCEPTIONS 6.3 Restoring from Interrupt/Exception All restoration from interrupt/exception processing is executed by the RETI instruction. With the RETI instruction, the processor performs the following steps,and transfers control to the address of the restore PC. (1) If the EP bit of the PSW is 0 and the NP bit of the PSW is 1, the restore PC and PSW are read from the FEPC and FEPSW; otherwise, the restore PC and PSW are read from the EIPC and EIPSW. (2) Control is transferred to the address of the restored PC and PSW. When execution has returned from exception processing or non-maskable interrupt processing, the NP and EP bits of the PSW must be set to the following values by using the LDSR instruction immediately before the RETI instruction, in order to restore the PC and PSW normally: To restore from non-maskable interrupt ******************* PSW's NP bit = 1, EP bit = 0 To restore from exception processing *********************** PSW's EP bit = 1 Figure 6-6 illustrates how restoring from interrupt/exception is performed. Figure 6-6. Restoring from Interrupt/Exception RETI instruction 1 PSW.EP 0 Restore from exception PSW.NP 0 1 Restore from maskable interrupt Restore from non-maskable interrupt PC PSW EIPC EIPSW PC PSW FEPC FEPSW Jump to PC 112 User's Manual U10243EJ7V0UM CHAPTER 7 RESET When a low-level signal is input to the RESET pin, the system is reset, and all on-chip hardware is initialized. 7.1 Initialization When a low-level signal is input to the RESET pin, the system is reset, and each hardware register is set in the status shown in Table 7-1. When the RESET signal goes high, program execution begins. If necessary, re-initialize the contents of each register by program control. Table 7-1. Register Status after Reset Hardware (Symbol) Program counter Interrupt status saving register PC EIPC EIPSW FEPC FEPSW Exception cause register (ECR) FECC EICC PSW r0 r1 to r31 Status after Reset 00000000H Undefined Undefined Undefined Undefined 0000H 0000H 00000020H Fixed to 00000000H Undefined NMI status saving register Program status word General register 7.2 Start Up All devices in the V850 Family begin program execution from address 00000000H after reset. After reset, no immediate interrupt requests are acknowledged. To enable interrupts, clear the ID bit of the program status word (PSW) to 0. User's Manual U10243EJ7V0UM 113 CHAPTER 8 PIPELINE The V850 Family is based on the RISC architecture and executes almost all the instructions in one clock cycle under control of a 5-stage pipeline. The processor uses a 5-stage pipeline. The operation to be performed in each stage is as follows: IF (instruction fetch) ............................................................ ID (instruction decode) ........................................................ EX (execution of ALU, multiplier, and barrel shifter) ......... MEM (memory access) ....................................................... WB (write back) ................................................................... Instruction is fetched and fetch pointer is incremented. Instruction is decoded, immediate data is generated, and register is read. The instruction is executed. Memory at specified address is accessed. Result of execution is written to register. 8.1 Outline of Operation The instruction execution sequence of the V850 Family consists of five stages including fetch and write back stages. The execution time of each stage differs depending on the type of the instruction and the type of the memory to be accessed. As an example of pipeline operation, Figure 8-1 shows the processing of the CPU when nine standard instructions are executed in succession. Figure 8-1. Example of Executing Nine Standard Instructions Time flow (state) System clock Processing CPU performs simultaneously 1 Instruction 1 IF Instruction 2 Instruction 3 Instruction 4 Instruction 5 Instruction 6 Instruction 7 Instruction 8 Instruction 9 2 3 4 5 6 7 8 9 10 11 12 13 ID IF EX ID IF MEM EX ID IF WB MEM EX ID IF WB MEM EX ID IF WB MEM EX ID IF WB MEM EX ID IF End of instruction 4 WB MEM EX ID IF End of instruction 5 WB MEM WB EX MEM WB ID EX MEM WB End of instruction 6 End of instruction 7 End of instruction 8 End of instruction 9 End of instruction 1 End of End of ionstruc- instruction 2 tion 3 1 through 13 in the figure above indicate the states of the CPU. In each state, write back of instruction n, memory access of instruction n+1, execution of instruction n+2, decoding of instruction n+3, and fetching of instruction n+4 are simultaneously performed. It takes five clock cycles to process a standard instruction, including fetching and write back. Because five instructions can be processed at the same time, however, a standard instruction can be executed in 1 clock cycle on average. 114 User's Manual U10243EJ7V0UM Executes instruction every 1 clock cycle CHAPTER 8 PIPELINE 8.2 Pipeline Flow During Execution of Instructions This section explains the pipeline flow during the execution of instructions. During instruction fetch (IF stage) and memory access (MEM stage), the internal ROM/PROM and the internal RAM are accessed, respectively. In this case, the IF and MEM stages are processed in 1 clock. In all other cases, the required time for access consists of the fixed access time, with the addition in some cases of a path wait time. Access times are shown in Figure 8-2 below. Table 8-1. Access Times (in Clocks) Resource (Bus Width) Stage Instruction fetch Memory access (MEM) Internal ROM/PROM (32 Bits) 1 3 Internal RAM (32 Bits) 3 1 Internal Peripheral I/O (8/16 Bits) Impossible 3+n External Memory (16 Bits) 3+n 3+n Remark n: Wait number 8.2.1 Load instructions [Instructions] [Pipeline] LD, SLD 1 Load instruction Next instruction IF ID IF 2 3 EX ID 4 MEM EX 5 WB MEM 6 WB [Description] The pipeline consists of 5 stages, IF, ID, EX, MEM, and WB. If an instruction using the execution result is placed immediately after the load instruction, data wait time occurs. For details, see 8.3 Pipeline Disorder. 8.2.2 Store instructions [Instructions] [Pipeline] ST, SST 1 Store instruction Next instruction IF ID IF 2 3 EX ID 4 MEM EX 5 WB MEM 6 WB [Description] The pipeline consists of 5 stages, IF, ID, EX, MEM and WB. However, no operation is performed in the WB stage, because no data is written to registers. 8.2.3 Arithmetic operation instructions (excluding multiply and divide instructions) [Instructions] [Pipeline] MOV, MOVEA, MOVHI, ADD, ADDI, CMP, SUB, SUBR, SETF 1 Arithmetic operation instruction Next instruction IF ID IF 2 3 EX ID 4 MEM EX 5 WB MEM 6 WB [Description] The pipeline consists of 5 stages, IF, ID, EX, MEM and WB. However, no operation is performed in the MEM stage, because memory is not accessed. User's Manual U10243EJ7V0UM 115 CHAPTER 8 PIPELINE 8.2.4 Multiply instructions [Instructions] [Pipeline] MULH, MULHI (1) When the next instruction is not a multiply instruction 1 Multiply instruction Next instruction IF ID IF 2 3 EX1 ID 4 EX2 EX 5 WB MEM 6 WB (2) When the next instruction is a multiply instruction 1 Multiply instruction 1 IF Multiply instruction 2 ID IF 2 3 EX1 ID 4 EX2 EX1 5 WB EX2 6 WB [Description] The pipeline consists of 5 stages, IF, ID, EX1, EX2, and WB. There is no MEM stage. The EX stage requires 2 clocks, but the EX1 and EX2 stages can operate independently. Therefore, the number of clocks for instruction execution is always 1, even if several multiply instructions are executed in a row. However, if an instruction using the execution result is placed immediately after a multiply instruction, data wait time occurs. For details, see 8.3 Pipeline Disorder. 8.2.5 Divide instructions [Instructions] [Pipeline] Divide instruction Next instruction DIVH 1 IF ID IF 2 3 EX1 - 4 EX2 - 37 EX35 - 38 EX36 ID IF 39 MEM EX ID 40 WB MEM EX 41 WB MEM 42 Next to next instruction WB - : Idle inserted for wait [Description] The pipeline consists of 40 stages, IF, ID, EX1 to EX36, MEM, and WB. The EX stage requires 36 clocks. No operation is performed in the MEM stage, because memory is not accessed. 8.2.6 Logical operation instructions [Instructions] [Pipeline] NOT, OR, ORI, XOR, XORI, AND, ANDI, TST, SHR, SAR, SHL 1 Logical operation instruction Next instruction IF ID IF 2 3 EX ID 4 MEM EX 5 WB MEM 6 WB [Description] The pipeline consists of 5 stages, IF, ID, EX, MEM, and WB. No operation is performed in the MEM stage, because memory is not accessed. 116 User's Manual U10243EJ7V0UM CHAPTER 8 PIPELINE 8.2.7 Saturation operation instructions [Instructions] [Pipeline] SATADD, SATSUB, SATSUBI, SATSUBR 1 Saturation operation instruction Next instruction IF ID IF 2 3 EX ID 4 MEM EX 5 WB MEM 6 WB [Description] The pipeline consists of 5 stages, IF, ID, EX, MEM, and WB. However, no operation is performed in the MEM stage, because memory is not accessed. 8.2.8 Branch instructions (1) Conditional branch instructions [Instructions] Bcond instructions (BGT, BGE, BLT, BLE, BH, BNL, BL, BNH, BE, BNE, BV, BNV, BN, BP, BC, BNC, BZ, BNZ, BSA): Except BR instruction [Pipeline] (a) When the condition is not realized 1 Conditional branch instruction Next instruction IF ID IF 2 EX ID 3 4 MEM EX 5 WB MEM 6 WB (b) When the condition is realized 1 Conditional branch IF instruction Next instruction Next to next instruction Branch destination instruction 2 ID IF x 3 EX ID x IF x 4 MEM 5 WB 6 7 8 IF ID EX MEM WB IF x: Instruction fetch that is not executed ID x: Instruction decode that is not executed [Description] The pipeline consists of 5 stages, IF, ID, EX, MEM, and WB. However, no operation is performed in the MEM and WB stages, because memory is not accessed and no data is written to registers. (a) When the condition is not realized The number of execution clocks for the branch instruction is 1. (b) When the condition is realized The number of execution clocks for the branch instruction is 3. The IF stage of the next instruction and next to next instruction of the branch instruction is not executed. User's Manual U10243EJ7V0UM 117 CHAPTER 8 PIPELINE (2) Unconditional branch instructions [Instructions] [Pipeline] JMP, JR, JARL, BR 1 Unconditional branch IF instruction Next instruction Branch destination instruction 2 ID IF x 3 EX 4 MEM IF 5 WB * ID EX MEM WB 6 7 8 IF x: Instruction fetch that is not executed instruction, and BR instruction, but in the case of the JARL instruction, data is written to the restore PC. WB *: No operation is performed in the case of the JMP instruction, JR [Description] The pipeline consists of 5 stages, IF, ID, EX, MEM, and WB. However, no operation is performed in the MEM and WB stages, because memory is not accessed and no data is written to registers. However, in the case of the JARL instruction, data is written to the restore PC in the WB stage. Also, the IF stage of the next instruction of the branch instruction is not executed. 8.2.9 Bit manipulation instructions (1) SET1, CLR1, NOT1 [Pipeline] 1 SET1, CLR1, NOT1 IF instruction Next instruction Next to next instruction ID IF 2 3 EX1 - 4 MEM - 5 EX2 - 6 EX3 ID IF 7 MEM EX ID 8 WB MEM EX 9 WB MEM 10 WB - : Idle inserted for wait [Description] The pipeline consists of 8 stages, IF, ID, EX1, MEM, EX2, EX3, MEM, and WB. However, no operation is performed in the WB stage, because no data is written to registers. In the case of these instructions, the memory access is read modify write, and the EX and MEM stages require 3 and 2 clocks, respectively. 118 User's Manual U10243EJ7V0UM CHAPTER 8 PIPELINE (2) TST1 1 2 ID IF 3 EX1 - 4 MEM - 5 EX2 - 6 EX3 ID IF 7 MEM EX ID 8 WB MEM EX 9 WB MEM 10 [Pipeline] IF TST1 instruction Next instruction Next to next instruction WB - : Idle inserted for wait [Description] The pipeline consists of 8 stages, IF, ID, EX1, MEM, EX2, EX3, MEM, and WB. However, no operation is performed in the second MEM and WB stages, because there is no second memory access nor data write to registers. In the case of this instruction, the memory access is read modify write, and the EX and MEM stage require 3 and 2 clocks, respectively. 8.2.10 Special instructions (1) LDSR, STSR 1 2 ID IF 3 EX ID 4 MEM EX 5 WB MEM 6 WB [Pipeline] LDSR, STSR instruction IF Next instruction [Description] The pipeline consists of 5 stages, IF, ID, EX, MEM, and WB. However, no operation is performed in the MEM stage, because memory is not accessed. Also, if the STSR instruction using the EIPC and FEPC system registers is placed immediately after the LDSR instruction setting these registers, data wait time occurs. For details, see 8.3 Pipeline Disorder. (2) NOP 1 2 ID IF 3 EX ID 4 MEM EX 5 WB MEM 6 WB [Pipeline] NOP instruction Next instruction IF [Description] The pipeline consists of 5 stages, IF, ID, EX, MEM, and WB. However, no operation is performed in the EX, MEM and WB stages, because no operation and no memory access is executed, and no data is written to registers. (3) EI, DI 1 2 ID IF 3 EX ID 4 MEM EX 5 WB MEM 6 WB [Pipeline] EI, DI instruction Next instruction IF [Description] The pipeline consists of 5 stages, IF, ID, EX, MEM, and WB. However, no operation is performed in the MEM and WB stages, because memory is not accessed and data is not written to registers. User's Manual U10243EJ7V0UM 119 CHAPTER 8 PIPELINE (4) HALT [Pipeline] 1 2 HALT ID instruction IF Next IF instruction Next to next instruction 3 EX - 4 MEM - 5 WB - - 6 - HALT release ID IF EX ID MEM EX WB MEM WB - : Idle inserted for wait [Description] The pipeline consists of 5 stages, IF, ID, EX, MEM and WB. No operation is performed in the MEM and WB stages, because memory is not accessed and no data is written to registers. Also, for the next instruction, the ID stage is delayed until the HALT state is released. (5) TRAP 1 2 ID1 IF x 3 ID2 EX 4 5 MEM IF 6 WB ID EX MEM WB 7 8 9 [Pipeline] TRAP instruction Next instruction IF Jump destination instruction IF x: Instruction fetch that is not executed ID1: Trap code detect ID2: Address generate [Description] The pipeline consists of 6 stages, IF, ID1, ID2, EX, MEM, and WB. However, no operation is performed in the MEM stage, because memory is not accessed. The ID stage requires 2 clocks. Also, the IF stage of the next instruction and next to next instruction is not executed. (6) RETI 1 2 ID1 IF x 3 ID2 EX 4 5 MEM IF 6 WB ID EX MEM WB 7 8 9 [Pipeline] RETI instruction Next instruction IF Jump destination instruction IF x: Instruction fetch that is not executed ID1: Register select ID2: Read EIPC/FEPC [Description] The pipeline consists of 6 stages, IF, ID1, ID2, EX, MEM, and WB. However, no operation is performed in the MEM and WB stages, because memory is not accessed and no data is written to registers. The ID stage requires 2 clocks. Also, the IF stage of the next instruction and next to next instruction is not executed. 120 User's Manual U10243EJ7V0UM CHAPTER 8 PIPELINE 8.3 Pipeline Disorder The pipeline consists of 5 stages from IF (Instruction Fetch) to WB (Write Back). Each stage basically requires 1 clock for processing, but the pipeline may become disordered, causing the number of execution clocks to increase. This section describes the main causes of pipeline disorder. 8.3.1 Alignment hazard If the branch destination instruction address is not word aligned (A1=1, A0=0) and is 4 bytes in length, it is necessary to repeat IF twice in order to align instructions in word units. This is called an align hazard. For example, the instructions a to e are placed from address X0H, and that instruction b consists of 4 bytes, and the other instructions each consist of 2 bytes. In this case, instruction b is placed at X2H (A1=1, A0=0), and is not word aligned (A1=0, A0=0). Therefore, when this instruction b becomes the branch destination instruction, an align hazard occurs. When an align hazard occurs, the number of execution clocks of the branch instruction becomes 4. Figure 8-2. Align Hazard Example (a) Memory map 32 bits X8H X4H X0H Instruc- Instruction d tion e Instruc- Instruction b tion c Instruc- Instruction a tion b (b) Pipeline 1 2 3 4 5 WB 6 7 8 9 10 Branch instruction IF ID EX MEM Next instruction IF x - Next to next instruction IF x Branch destination instruction (instruction b) IF1 Branch destination's next instruction (instruction c) IF2 ID IF EX ID MEM EX WB MEM WB IF x: Instruction fetch that is not executed Address of branch destination instruction (instruction b) -: Idle inserted for wait fetch that fetches the 2 bytes on the lower address of instruction b. IF1: First instruction fetch that occurs during align hazard. It is a 2-byte IF2: Second instruction fetch that occurs during align hazard. It is normally a 4-byte fetch that fetches the 2 bytes on the upper address of instruction b in addition to instruction c (2-byte length). Align hazards can be prevented through the following handling in order to obtain faster instruction execution. * Use 2-byte branch destination instruction. * Use 4-byte instructions placed at word boundaries (A1=0, A0=0) for branch destination instructions. User's Manual U10243EJ7V0UM 121 CHAPTER 8 PIPELINE 8.3.2 Referencing execution result of load instruction For load instructions (LD, SLD), data read in the MEM stage is saved during the WB stage. Therefore, if the contents of the same register are used by the instruction immediately after the load instruction, it is necessary to delay the use of the register by this later instruction until the load instruction has ended using that register. This is called a hazard. The V850 Family has an interlock function that causes the CPU to automatically handle this hazard by delaying the ID stage of the next instruction. The V850 Family also has a short path that allows the data read during the MEM stage to be used in the ID stage of the next instruction. This short path allows data to be read with the load instruction during the MEM stage and the use of this data in the ID stage of the next instruction with the same timing. As a result of the above, when using the execution result in the instruction following immediately after, the number of execution clocks of the load instruction is 2. Figure 8-3. Example of Execution Result of Load Instruction 1 Load instruction 1 IF (LD [R4], R6) Instruction 2 (ADD 2, R6) Instruction 3 Instruction 4 2 ID IF EX IL IF 3 4 MEM ID - 5 WB EX ID IF 6 MEM EX ID 7 WB MEM EX 8 9 WB MEM WB IL: Idle inserted for data wait by interlock function -: Idle inserted for wait : Short path As described in Figure 8-3, when an instruction placed immediately after a load instruction uses its execution result, a data wait time occurs due to the interlock function, and the execution speed is lowered. This drop in execution speed can be avoided by placing instructions that use the execution result of a load instruction at least 2 instructions after the load instruction. 8.3.3 Referencing execution result of multiply instruction For multiply instructions (MULH, MULHI), the operation result is saved to the register in the WB stage. Therefore, if the contents of the same register are used by the instruction immediately after the multiply instruction, it is necessary to delay the use of the register by this later instruction until the multiply instruction has ended using that register (occurrence of hazard). The V850 Family's interlock function delays the ID stage of the instruction following immediately after. A short path is also provided that allows the EX2 stage of the multiply instruction and the multiply instruction's operation result to be used in the ID stage of the instruction following immediately after with the same timing. Figure 8-4. Example of Execution Result of Multiply Instruction 1 Multiply instruction 1 IF (MULH 3, R6) Instruction 2 (ADD 2, R6) Instruction 3 Instruction 4 2 ID IF 3 EX1 IL IF 4 EX2 ID - 5 WB EX ID IF 6 MEM EX ID 7 WB MEM EX 8 9 WB MEM WB IL: Idle inserted for data wait by interlock function -: Idle inserted for wait : Short path 122 User's Manual U10243EJ7V0UM CHAPTER 8 PIPELINE As described in Figure 8-4, when an instruction placed immediately after a multiply instruction uses its execution result, a data wait time occurs due to the interlock function, and the execution speed is lowered. This drop in execution speed can be avoided by placing instructions that use the execution result of a multiply instruction at least 2 instructions after the multiply instruction. 8.3.4 Referencing execution result of LDSR instruction for EIPC and FEPC When using the LDSR instruction to set the data of the EIPC and FEPC system registers, and immediately after referencing the same system registers with the STSR instruction, the use of the system registers for the STSR instruction is delayed until the setting of the system registers with the LDSR instruction is completed (occurrence of hazard). The V850 Family's interlock function delays the ID stage of the STSR instruction immediately after. As a result of the above, when using the execution result of the LDSR instruction for EIPC and FEPC for an STSR instruction following immediately after, the number of execution clocks of the LDSR instruction becomes 3. Figure 8-5. Example of Execution Result of LDSR Instruction for EIPC and FEPC LDSR instruction (LDSR R6, 0) Note IF STSR instruction (STSR 0, R7) Note Next instruction Next to next instruction 1 ID IF 2 EX IL IF 3 4 MEM IL - 5 WB ID - EX ID IF 6 7 MEM EX ID 8 WB MEM EX 9 10 WB MEM WB IL: -: Idle inserted for data wait by interlock function Idle inserted for wait Note System register 0 used for the LDSR and STSR instructions designates EIPC. As described in Figure 8-5, when an STSR instruction is placed immediately after an LDSR instruction that uses the operand EIPC or FEPC, and that STSR instruction uses the LDSR instruction execution result, the interlock function causes a data wait time to occur, and the execution speed is lowered. This drop in execution speed can be avoided by placing STSR instructions that reference the execution result of the preceding LDSR instruction at least 3 instructions after the LDSR instruction. 8.3.5 Cautions when creating programs When creating programs, pipeline disorder can be avoided and instruction execution speed can be raised by observing the following cautions. * Place instructions that use the execution result of load instructions (LD, SLD) at least 2 instructions after the load instruction. * Place instructions that use the execution result of multiply instructions (MULH, MULHI) at least 2 instructions after the multiply instruction. * If using the STSR instruction to read the setting results written to the EIPC or FEPC registers with the LDSR instruction, place the STSR instruction at least 3 instructions after the LDSR instruction. * For the first branch destination instruction, use a 2-byte instruction, or a 4-byte instruction placed at the word boundary. User's Manual U10243EJ7V0UM 123 CHAPTER 8 PIPELINE 8.4 Additional Items Related to Pipeline 8.4.1 Harvard architecture The V850 Family uses the Harvard architecture to operate an instruction fetch path from internal ROM and a memory access path to internal RAM independently. This eliminates path arbitration conflicts between the IF and MEM stages and allows orderly pipeline operation. (1) V850 Family (Harvard architecture) The MEM stage of instruction 1 and the IF stage of instruction 4, as well as the MEM stage of instruction 2 and the IF stage of instruction 5 can be executed simultaneously with orderly pipeline operation. 1 Instruction 1 Instruction 2 Instruction 3 Instruction 4 Instruction 5 IF ID IF 2 3 EX ID IF 4 MEM EX ID IF 5 WB MEM EX ID IF 6 WB MEM EX ID 7 8 9 WB MEM EX WB MEM WB (2) Not V850 Family (Other than Harvard architecture) The MEM stage of instruction 1 and the IF stage of instruction 4, in addition to the MEM stage of instruction 2 and the IF stage of instruction 5 are in contention, causing path waiting to occur and slower execution time due to disorderly pipeline operation. 1 Instruction 1 Instruction 2 Instruction 3 Instruction 4 Instruction 5 IF ID IF 2 3 EX ID IF 4 MEM - - 5 WB EX ID IF 6 MEM - - 7 WB EX ID IF 8 9 10 11 MEM EX ID WB MEM EX WB MEM WB -: Idle inserted for wait 124 User's Manual U10243EJ7V0UM CHAPTER 8 PIPELINE 8.4.2 Short path The V850 Family provides on chip a short path that allows the use of the execution result of the preceding instruction by the following instruction before write back (WB) is completed for the previous instruction. Example 1. Execution result of arithmetic operation instruction and logical operation used by instruction following immediately after * V850 Family (on-chip short path) The execution result of the preceding instruction can be used for the ID stage of the instruction following immediately after as soon as the result is out (EX stage), without having to wait for write back to be completed. 1 ADD 2, R6 MOV R6, R7 IF ID IF 2 EX ID 3 4 MEM EX 5 WB MEM 6 WB * Not V850 Family (No short path) The ID stage of the instruction following immediately after is delayed until write back of the previous instruction is completed. 1 ADD 2, R6 MOV R6, R7 IF ID IF 2 EX - 3 4 MEM - 5 WB ID EX 6 7 MEM 8 WB -: Idle inserted for wait : Short path User's Manual U10243EJ7V0UM 125 CHAPTER 8 PIPELINE Example 2. Data read from memory by the load instruction used by instruction following immediately after * V850 Family (on-chip short path) The execution result of the preceding instruction can be used for the ID stage of the instruction following immediately after as soon as the result is out (MEM stage), without having to wait for write back to be completed. 1 IF LD [R4], R6 ADD 2, R6 Next instruction Next to next instruction ID IF 2 EX IL IF 3 4 MEM ID - 5 WB EX ID IF 6 MEM EX ID 7 WB MEM EX 8 9 WB MEM WB * Not V850 Family (No short path) The ID stage of the instruction following immediately after is delayed until write back of the previous instruction is completed. 1 IF LD [R4], R6 ADD 2, R6 Next instruction Next to next instruction ID IF 2 EX - 3 4 MEM - 5 WB ID IF EX ID IF 6 7 MEM EX ID 8 WB MEM EX 9 10 WB MEM WB IL: Idle inserted for data wait by interlock function -: Idle inserted for wait : Short path 126 User's Manual U10243EJ7V0UM APPENDIX A INSTRUCTION MNEMONIC (IN ALPHABETICAL ORDER) This appendix summarizes the instruction mnemonic list described previously. Instructions are listed in the alphabetical order of their mnemonics. The illustration and table shown below indicates how to read this appendix and what each symbol and word means. Instruction Mnemonic Operand Format CY OV S Z SAT Convention ADD reg1, reg2 I - * * * * Instruction mnemonic Operand name Indicates instruction format Describes movements of flags Name reg1 reg2 Meaning General register (used as source register) General register (mainly used as destination register. Some are also used as source registers) 3-bit data for bit number specification x-bit immediate x-bit displacement System register number Trap handler address corresponding to trap vector 4-bit data for 4-bit condition code specification bit#3 immx dispx regID vector cccc Identifier 0 * - Reset to 0 Meaning Set to 1 or reset to 0 according to instruction execution result No change User's Manual U10243EJ7V0UM 127 APPENDIX A INSTRUCTION MNEMONIC (IN ALPHABETICAL ORDER) Table A-1. Instruction Mnemonic (In Alphabetical Order) (1/7) Instruction Mnemonic ADD ADD Operand Format CY OV S Z SAT Instruction Function reg1, reg2 imm5, reg2 I II * * * * * * * * - - Add. Adds the word data of reg1 to the word data of reg2, and stores the result in reg2. Add. Adds the 5-bit immediate data, signextended to word length, to the word data of reg2, and stores the result in reg2. Add. Adds the 16-bit immediate data, signextended to word length, to the word data of reg1, and stores the result in reg2. AND. ANDs the word data of reg2 with the word data of reg1, and stores the result in reg2. AND. ANDs the word data of reg1 with the 16-bit immediate data, zero-extended to word length, and stores the result in reg2. Conditional branch (if Carry). Tests a condition flag specified by an instruction. Branches if a specified condition is satisfied; otherwise, executes the next instruction. The branch destination PC holds the sum of the current PC value and 9-bit displacement which is the 8-bit immediate shifted 1 bit and sign-extended to word length. Bit clear. Adds the data of reg1 to 16-bit displacement, sign-extended to word length, to generate a 32-bit address. Then clears the bit, specified by the instruction bit field, of the byte data referenced by the generated address. Compare. Compares the word data of reg2 with the word data of reg1, and indicates the result by using the condition flags. To compare, the contents of reg1 are subtracted from the word data of reg2. Compare. Compares the word data of reg2 with the 5-bit immediate data, sign-extended to word length, and indicates the result by using the condition flags. To compare, the contents of the sign-extended immediate data are subtracted from the word data of reg2. Disables maskable interrupt. Sets the ID flag of the PSW to 1 to disable the acknowledgement of maskable interrupts from acceptance; interrupts are immediately disabled at the start of this instruction execution. ADDI imm16, reg1, reg2 VI * * * * - AND reg1, reg2 I - 0 * * - ANDI imm16, reg1, reg2 VI - 0 * * - Bcond disp9 III - - - - - CLR1 bit#3, disp16 [reg1] VIII - - - * - CMP reg1, reg2 I * * * * - CMP imm5, reg2 II * * * * - DI - X - - - - - 128 User's Manual U10243EJ7V0UM APPENDIX A INSTRUCTION MNEMONIC (IN ALPHABETICAL ORDER) Table A-1. Instruction Mnemonic (In Alphabetical Order) (2/7) Instruction Mnemonic DIVH Operand Format CY OV S Z SAT Instruction Function reg1, reg2 I - * * * - Signed divide. Divides the word data of reg2 by the lower half-word data of reg1, and stores the quotient to reg2. Enables maskable interrupt. Resets the ID flag of the PSW to 0 and enables the acknowledgement of maskable interrupts at the beginning of next instruction. CPU halt. Stops the operating clock of the CPU and places the CPU in the HALT mode. Jump and register link. Saves the current PC value plus 4 to general register reg2, adds a 22bit displacement, sign-extended to word length, to the current PC value, and transfers control to the PC. Bit 0 of the 22-bit displacement is masked to 0. Register indirect unconditional branch. Transfers control to the address specified by reg1. Bit 0 of the address is masked to 0. Unconditional branch. Adds a 22-bit displacement, sign-extended to word length, to the current PC value, and transfers control to the PC. Bit 0 of the 22-bit displacement is masked to 0. Byte load. Adds the data of reg1 to a 16-bit displacement, sign-extended to word length, to generate a 32-bit address. Byte data is read from the generated address, sign-extended to word length, and then stored in reg2. EI - X - - - - - HALT - X - - - - - JARL disp22, reg2 V - - - - - JMP [reg1] I - - - - - JR disp22 V - - - - - LD.B disp16 [reg1], reg2 VII - - - - - LD.H disp16 [reg1], reg2 VII - - - - - Half-word load. Adds the data of reg1 to a 16-bit displacement, sign-extended to word length, to generate a 32-bit address. Half-word data is read from this 32-bit address with its bit 0 masked to 0, sign-extended to word length, and stored in reg2. Word load. Adds the data of reg1 to a 16-bit displacement, sign-extended to word length, to generate a 32-bit address. Word data is read from this 32-bit address with bits 0 and 1 masked to 0, and stored in reg2. LD.W disp16 [reg1], reg2 VII - - - - - User's Manual U10243EJ7V0UM 129 APPENDIX A INSTRUCTION MNEMONIC (IN ALPHABETICAL ORDER) Table A-1. Instruction Mnemonic (In Alphabetical Order) (3/7) Instruction Mnemonic LDSR Operand Format CY OV S Z SAT Instruction Function reg2, regID IX - - - - - Load to system register. Set the word data of reg2 to a system register specified by regID. If regID is PSW, the values of the corresponding bits of reg2 are set to the respective flags of the PSW. Moves data. Transfers the word data of reg1 to reg2. Moves data. Transfers the value of a 5-bit immediate data, sign-extended to word length, to reg2. Moves effective address. Adds a 16-bit immediate data, sign-extended to word length, to the word data of reg1, and stores the result in reg2. Moves higher half-word. Adds word data, in which the higher 16 bits are defined by the 16-bit immediate data while the lower 16 bits are set to 0, to the word data of reg1 and stores the result in reg2. Signed multiply. Multiplies the lower half-word data of reg2 by the lower half-word data of reg1, and stores the result in reg2 as word data. Signed multiply. Multiplies the lower half-word data of reg2 by a 5-bit immediate data, signextended to half-word length, and stores the result in reg2 as word data. Signed multiply. Multiplies the lower half-word data of reg1 by a 16-bit immediate data, and stores the result in reg2. No operation. Logical not. Logically negates (takes 1's complement of) the word data of reg1, and stores the result in reg2. Bit not. First, adds the data of reg1 to a 16-bit displacement, sign-extended to word length, to generate a 32-bit address. The bit specified by the 3-bit field "bbb" is inverted at the byte data location referenced by the generated address. Logical sum. ORs the word data of reg2 with the word data of reg1, and stores the result in reg2. MOV reg1, reg2 I - - - - - MOV imm5, reg2 II - - - - - MOVEA imm16, reg1, reg2 VI - - - - - MOVHI imm16, reg1, reg2 VI - - - - - MULH reg1, reg2 I - - - - - MULH imm5, reg2 II - - - - - MULHI imm16, reg1, reg2 VI - - - - - NOP NOT - reg1, reg2 I I - - - 0 - * - * - - NOT1 bit#3, disp16 [reg1] VIII - - - * - OR reg1, reg2 I - 0 * * - 130 User's Manual U10243EJ7V0UM APPENDIX A INSTRUCTION MNEMONIC (IN ALPHABETICAL ORDER) Table A-1. Instruction Mnemonic (In Alphabetical Order) (4/7) Instruction Mnemonic ORI Operand Format CY OV S Z SAT Instruction Function imm16, reg1, reg2 VI - 0 * * - Logical sum. ORs the word data of reg1 with the 16-bit immediate data, zero-extended to word length, and stores the result in reg2. Returns from exception or interrupt routine. Restores the restore PC and PSW from the appropriate system register, and restores from exception or interrupt routine. Arithmetic right shift. Arithmetically shifts the word data of reg2 to the right by `n' positions, where `n' is specified by the lower 5 bits of reg1 (the MSB prior to shift execution is copied and set as the new MSB), and then writes the result to reg2. Arithmetic right shift. Arithmetically shifts the word data of reg2 to the right by `n' positions specified by the 5-bit immediate data, zero-extended to word length (the MSB prior to shift execution is copied and set as the new MSB), and then writes the result to reg2. Saturated add. Adds the word data of reg1 to the word data of reg2, and stores the result in reg2. However, if the result exceeds the maximum positive value, the maximum positive value is stored in reg2; if the result exceeds the maximum negative value, the maximum negative value is stored in reg2. The SAT flag is set to 1. Saturated add. Adds the 5-bit immediate data, sign-extended to word length, to the word data of reg2, and stores the result in general register reg2. However, if the result exceeds the positive maximum value, the maximum positive value is stored in reg2; if the result exceeds the maximum negative value, the maximum negative value is stored in reg2. The SAT flag is set to 1. Saturated subtract. Subtracts the word data of reg1 from the word data of reg2, and stores the result in reg2. However, if the result exceeds the maximum positive value, the maximum positive value is stored in reg2; if the result exceeds the maximum negative value, the maximum negative value is stored in reg2. The SAT flag is set to 1. RETI - X * * * * * SAR reg1, reg2 IX * 0 * * - SAR imm5, reg2 II * 0 * * - SATADD reg1, reg2 I * * * * * SATADD imm5, reg2 II * * * * * SATSUB reg1, reg2 I * * * * * User's Manual U10243EJ7V0UM 131 APPENDIX A INSTRUCTION MNEMONIC (IN ALPHABETICAL ORDER) Table A-1. Instruction Mnemonic (In Alphabetical Order) Instruction Mnemonic SATSUBI Operand Format CY OV S Z SAT (5/7) Instruction Function imm16, reg1, reg2 VI * * * * * Saturated subtract. Subtracts a 16-bit immediate sign-extended to word length from the word data of reg1, and stores the result in reg2. However, if the result exceeds the maximum positive value, the maximum positive value is stored in reg2; if the result exceeds the maximum negative value, the maximum negative value is stored in reg2. The SAT flag is set to 1. Saturated subtract reverse. Subtracts the word data of reg2 from the word data of reg1, and stores the result in reg2. However, if the result exceeds the maximum positive value, the maximum positive value is stored in reg2; if the result exceeds the maximum negative value, the maximum negative value is stored in reg2. The SAT flag is set to 1. Set flag condition. The reg2 is set to 1 if a condition specified by condition code "cccc" is satisfied; otherwise, a 0 is stored in the register. Bit set. First, adds a 16-bit displacement, signextended to word length, to the data of reg1 to generate a 32-bit address. The bits, specified by the 3-bit bit field "bbb" is set at the byte data location specified by the generated address. Logical left shift. Logically shifts the word data of reg2 to the left by `n' positions (0 is shifted to the LSB side), where `n' is specified by the lower 5 bits of reg1, and writes the result to reg2. Logical left shift. Logically shifts the word data of reg2 to the left by `n' positions (0 is shifted to the LSB side), where `n' is specified by a 5-bit immediate data, zero-extended to word length, and writes the result to reg2. Logical right shift. Logically shifts the word data of reg2 to the right by `n' positions (0 is shifted to the MSB side), where `n' is specified by the lower 5 bits of reg1, and writes the result to reg2. Logical right shift. Logically shifts the word data of reg2 to the right by `n' positions (0 is shifted to the MSB side), where `n' is specified by a 5-bit immediate data, zero-extended to word length, and writes the result to reg2. SATSUBR reg1, reg2 I * * * * * SETF cccc, reg2 IX - - - - - SET1 bit#3, disp16 [reg1] VIII - - - * - SHL reg1, reg2 IX * 0 * * - SHL imm5, reg2 II * 0 * * - SHR reg1, reg2 IX * 0 * * - SHR imm5, reg2 II * 0 * * - 132 User's Manual U10243EJ7V0UM APPENDIX A INSTRUCTION MNEMONIC (IN ALPHABETICAL ORDER) Table A-1. Instruction Mnemonic (In Alphabetical Order) (6/7) Instruction Mnemonic SLD.B Operand Format CY OV S Z SAT Instruction Function disp7 [ep], reg2 IV - - - - - Byte load. Adds the 7-bit displacement, zeroextended to word length, to the element pointer to generate a 32-bit address. Byte data is read from the generated address, sign-extended to word length, and stored in reg2. Half-word load. Adds the 8-bit displacement, zero-extended to word length, to the element pointer to generate a 32-bit address. Half-word data is read from this 32-bit address with bit 0 masked to 0, sign-extended to word length, and stored in reg2. Word load. Adds the 8-bit displacement, zeroextended to word length, to the element pointer to generate a 32-bit address. Word data is read from this 32-bit address with bits 0 and 1 masked to 0, and stored in reg2. Byte store. Adds the 7-bit displacement, zeroextended to word length, to the element pointer to generate a 32-bit address, and stores the data of the lowest byte of reg2 at the generated address. Half-word store. Adds the 8-bit displacement, zero-extended to word length, to the element pointer to generate a 32-bit address, and stores the lower half-word of reg2 at the generated 32bit address with bit 0 masked to 0. Word store. Adds the 8-bit displacement, zeroextended to word length, to the element pointer to generate a 32-bit address, and stores the word data of reg2 at the generated 32-bit address with bits 0 and 1 masked to 0. Byte store. Adds the 16-bit displacement, signextended to word length, to the data of reg1 to generate a 32-bit address, and stores the lowest byte data of reg2 at the generated address. Half-word store. Adds the 16-bit displacement, sign-extended to word length, to the data of reg1 to generate a 32-bit address, and stores the lower half-word of reg2 at the generated 32-bit address with bit 0 masked to 0. SLD.H disp8 [ep], reg2 IV - - - - - SLD.W disp8 [ep], reg2 IV - - - - - SST.B reg2, disp7 [ep] IV - - - - - SST.H reg2, disp8 [ep] IV - - - - - SST.W reg2, disp8 [ep] IV - - - - - ST.B reg2, disp16 [reg1] VII - - - - - ST.H reg2, disp16 [reg1] VII - - - - - User's Manual U10243EJ7V0UM 133 APPENDIX A INSTRUCTION MNEMONIC (IN ALPHABETICAL ORDER) Table A-1. Instruction Mnemonic (In Alphabetical Order) (7/7) Instruction Mnemonic ST.W Operand Format CY OV S Z SAT Instruction Function reg2, disp16 [reg1] VII - - - - - Word store. Adds the 16-bit displacement, signextended to word length, to the data of reg1 to generate a 32-bit address, and stores the word data of reg2 at the generated 32-bit address with bits 0 and 1 masked to 0. Stores contents of system register. Stores the contents of a system register specified by regID in reg2. Subtract. Subtracts the word data of reg1 from the word data of reg2, and stores the result in reg2. Subtract reverse. Subtracts the word data of reg2 from the word data of reg1, and stores the result in reg2. Software trap. Saves the restore PC and PSW to the system register; sets the exception code and the flags of the PSW; jumps to the address of the trap handler corresponding to the trap vector specified by vector number, and starts exception processing. Test. ANDs the word data of reg2 with the word data of reg1. The result is not stored, and only the flags are changed. Bit test. Adds the data of reg1 to a 16-bit displacement, sign-extended to word length, to generate a 32-bit address. Performs the test on the bit, specified by the 3-bit field "bbb", at the byte data location referenced by the generated address. If the specified bit is 0, the Z flag is set to 1; if the bit is 1, the Z flag is reset to 0. Exclusive OR. Exclusively ORs the word data of reg2 with the word data of reg1, and stores the result in reg2. Exclusive OR immediate. Exclusively ORs the word data of reg1 with a 16-bit immediate data, zero-extended to word length, and stores the result in reg2. STSR regID, reg2 IX - - - - - SUB reg1, reg2 I * * * * - SUBR reg1, reg2 I * * * * - TRAP vector X - - - - - TST reg1, reg2 I - 0 * * - TST1 bit#3, disp16 [reg1] VIII - - - * - XOR reg1, reg2 I - 0 * * - XORI imm16, reg1, reg2 VI - 0 * * - 134 User's Manual U10243EJ7V0UM APPENDIX B INSTRUCTION LIST Table B-1. Mnemonic List Mnemonic Load/store LD.B LD.H LD.W SLD.B SLD.H SLD.W ST.B ST.H ST.W SST.B SST.H SST.W Load Byte Load Halfword Lord Word Load Byte Load Halfword Load Word Store Byte Store Halfword Store Word Store Byte Store Halfword Store Word Integer arithmetic operation/logical operation/saturated operation (2-operand register) MOV ADD SUB SUBR MULH DIVH CMP SATADD SATSUB SATSUBR TST OR AND XOR NOT SHL SHR SAR Move Add Subtract Subtract Reverse Multiply Halfword Divide Halfword Compare Saturated Add Saturated Subtract Saturated Subtract Reverse Test Or And Exclusive Or Not Shift Logical Left Shift Logical Right Shift Arithmetic Right (2-operand immediate) MOV ADD CMP SATADD SETF SHL SHR SAR Move Add Compare Saturated Add Set Flag Condition Shift Logical Left Shift Logical Right Shift Arithmetic Right MOVHI MOVEA ADDI MULHI SATSUBI ORI ANDI XORI Function Mnemonic (3-operand) Move High Halfword Move Effective Address Add Immediate Multiply Halfword Immediate Saturated Subtract Immediate Or Immediate And Immediate Exclusive Or Immediate Branch JMP JR JARL Bcond Jump Register Jump Relative Jump and Register Link Branch on condition code Bit manipulation SET1 CLR1 NOT1 TST1 Set Bit Clear Bit Not Bit Test Bit Special LDSR STSR TRAP RETI HALT DI EI NOP Load System Register Store System Register Trap Return from Trap or Interrupt Halt Disable Interrupt Enable Interrupt No operation Function User's Manual U10243EJ7V0UM 135 APPENDIX B INSTRUCTION LIST Table B-2. Instruction Set Instruction Code b10 * * * * b5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 0 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 x x x x x x 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 x x x x x x 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 MOV NOT DIVH JMP SATSUBR SATSUB SATADD MULH OR XOR AND TST SUBR SUB ADD CMP MOV SATADD ADD CMP SHR SAR SHL MULH SLD.B SST.B SLD.H SST.H SLD.W SST.W Bcond ADDI MOVEA MOVHI SATSUBI ORI XORI ANDI MULHI LD.B LD.H LD.W ST.B ST.H ST.W JARL SET1 CLR1 NOT1 TST1 SETF LDSR STSR SHR SAR SHL Instruction Format reg1, reg2 reg1, reg2 reg1, reg2 [reg1] reg1, reg2 reg1, reg2 reg1, reg2 reg1, reg2 reg1, reg2 reg1, reg2 reg1, reg2 reg1, reg2 reg1, reg2 reg1, reg2 reg1, reg2 reg1, reg2 imm5, imm5, imm5, imm5, imm5, imm5, imm5, imm5, reg2 reg2 reg2 reg2 reg2 reg2 reg2 reg2 Format I Remarks When reg1, reg2 = 0, NOP II disp7 [ep], reg2 reg2, disp7 [ep] disp8, [ep], reg2 reg2, disp8 [ep] disp8 [ep], reg2 reg2, disp8 [ep] disp9 imm16, imm16, imm16, imm16, imm16, imm16, imm16, imm16, reg1, reg1, reg1, reg1, reg1, reg1, reg1, reg1, reg2 reg2 reg2 reg2 reg2 reg2 reg2 reg2 IV 1011xx III VI disp16 [reg1], reg2 disp16 [reg1], reg2 disp16 [reg1], reg2 reg2, disp16 [reg1] reg2, disp16 [reg1] reg2, disp16 [reg1] disp22, reg2 bit#3, bit#3, bit#3, bit#3, disp16 disp16 disp16 disp16 [reg1] [reg1] [reg1] [reg1] VII 11110x V VIII When reg2 = r0, JR disp22 cccc, reg2 reg2, regID regID, reg2 reg1, reg2 reg1, reg2 reg1, reg2 IX TRAP vector HALT RETI DI EI Undefined instruction X 136 User's Manual U10243EJ7V0UM APPENDIX C INSTRUCTION OP CODE MAP The following tables (a) through (f) show the op code maps corresponding to instruction codes. Instruction code * 16-bit length instruction format 15 11 10 54 0 Sub op code (see (b)) Op code (see (a)) * 32-bit length instruction format 15 14 13 12 11 10 54 0 31 27 26 21 20 17 16 Op code (see (a)) Sub-op code (see (f)) Sub-op code (see (d)) Sub-op code (see (c)) Sub-op code (see (e)) (a) Op code Bits 6 to 5 Bits 10 to 7 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 ADDI ORI LD.B MOVEA XORI LD.H/LD.W JARL Note 2 00 MOV/NOP SATSUBR OR SUBR MOV imm5, r SHR imm5, r 01 NOT SATSUB XOR SUB SATADD SAR imm5, r SLD.B SST.B SLD.H SST.H 10 DIVH SATADD AND ADD R, r ADD imm5, r SHL imm5, r 11 JMP MULH TST CMP R,r CMP imm5, r MULH Format I II IV SLD.W/SST.WNote 1 Bcond MOVHI ANDI ST.B Bit manipulation Note 3 III SATSUBI MULHI ST.H/ST.WNote Extension 1 2 VI V/VII/VIII/IX/X Note 4 Notes 1. See (b). 2. See (c). 3. See (d). 4. See (e). User's Manual U10243EJ7V0UM 137 APPENDIX C INSTRUCTION OP CODE MAP (b) Short format load/store instruction (displacement/sub-op code) Bit 0 Bits 10 to 7 0110 0111 1000 1001 1010 SLD.W SLD.B SST.B SLD.H SST.H SST.W 0 1 (c) Load/store instruction (displacement/sub-op code) Bit 16 Bits 6 to 5 00 01 10 11 ST.H LD.H ST.B ST.W LD.B LD.W 0 1 (d) Bit manipulation instruction (sub-op code) Bit 14 Bit 15 0 1 SET1 CLR1 NOT1 TST1 0 1 (e) Extension 1 (sub-op code) Bits 22 to 21 Bits 26 to 23 0000 0001 0010 0011 to 1111 SETF SHR R, r TRAP LDSR SAR R, r HALT STSR SHL R, r RETI Undefined Undefined Extension 2Note 00 01 10 11 Illegal instruction Note See (f). (f) Extension 2 (sub-op code) Bits 14 to 13 Bit 15 0 1 DI EI Undefined 00 01 10 11 138 User's Manual U10243EJ7V0UM APPENDIX D INDEX [A] ADD ........................................................................ 49 Add .......................................................................... 49 ADDI ....................................................................... 50 Add immediate ....................................................... 50 Address space ........................................................ 30 Addressing modes ................................................. 32 Alignment hazard ................................................. 121 AND .................................................................. 46, 51 And .......................................................................... 51 ANDI ....................................................................... 52 And immediate ....................................................... 52 Arithmetic operation instructions ................... 41, 115 arithmetically shift right by ..................................... 46 Assembler-reserved register ................................. 22 [B] Based addressing .................................................. 35 bbb .......................................................................... 47 BC ........................................................................... 54 Bcond ...................................................................... 53 BE ........................................................................... 54 BGE ........................................................................ 54 BGT ......................................................................... 54 BH ........................................................................... 54 Bit ............................................................................ 28 BIT .......................................................................... 28 Bit addressing ........................................................ 37 Bit manipulation instructions .......................... 44, 118 bit#3 ........................................................................ 45 BL ............................................................................ 54 BLE ......................................................................... 54 BLT ......................................................................... 54 BN ........................................................................... 54 BNC ........................................................................ 54 BNE ......................................................................... 54 BNH ........................................................................ 54 BNL ......................................................................... 54 BNV ......................................................................... 54 BNZ ......................................................................... 54 BP ........................................................................... 54 BR ........................................................................... 54 Branch instructions ........................................ 43, 117 Branch on condition code ...................................... 53 BSA ......................................................................... 54 BV ........................................................................... 54 BYTE ....................................................................... 27 Byte ................................................................... 27, 46 BZ ........................................................................... 54 [C] cccc ................................................................... 45, 47 Clear bit .................................................................. 55 CLR1 ....................................................................... 55 CMP ........................................................................ 56 Compare ................................................................. 56 Conditional branch instructions ........................... 117 CPU internal configuration ..................................... 19 CY ........................................................................... 25 [D] Data alignment ....................................................... 29 Data format ............................................................. 27 Data representation ............................................... 28 Data type ................................................................ 27 Data type and addressing ..................................... 27 DI ............................................................................ 57 Disable interrupt ..................................................... 57 dispx ............................................................................... 45 DIVH ....................................................................... 58 Divide half-word ..................................................... 58 Divide instructions ................................................ 116 [E] ECR ........................................................................ 23 EI ............................................................................. 59 EICC ....................................................................... 24 EIPC ........................................................................ 23 EIPSW .................................................................... 23 Element pointer ...................................................... 22 Enable interrupt ...................................................... 59 EP ........................................................................... 25 ep ............................................................................ 45 Exception .............................................................. 106 Exception cause register ....................................... 23 Exception processing ........................................... 110 Exception trap ...................................................... 111 Exclusive or .......................................................... 101 User's Manual U10243EJ7V0UM 139 APPENDIX D INDEX Exclusive or immediate ........................................ 102 [F] FECC ...................................................................... 24 FEPC ...................................................................... 24 FEPSW ................................................................... 24 Flag ......................................................................... 47 Format .................................................................... 46 [G] General registers .................................................... 20 Global pointer ......................................................... 22 GR [ ] ...................................................................... 46 [H] Half word ................................................................ 27 HALT ....................................................................... 60 Halt .......................................................................... 60 Harvard architecture ............................................ 124 [I] i ............................................................................... 47 ID ............................................................................ 25 Illegal instruction code ......................................... 111 Immediate addressing ............................................ 35 immx ............................................................................... 45 Initialization ........................................................... 113 Instruction address ................................................. 32 Instruction format ................................................... 45 Instruction list ....................................................... 135 Instruction mnemonic ........................................... 127 Instruction op code map ...................................... 137 Instruction set ......................................................... 45 Integer ..................................................................... 28 Interrupt ................................................................ 106 Interrupt status saving registers ............................ 23 Interrupt processing ............................................. 107 Introduction ............................................................. 16 [J] JARL ....................................................................... 61 JMP ......................................................................... 62 JR ............................................................................ 63 Jump and register link ........................................... 61 Jump register .......................................................... 62 Jump relative .......................................................... 63 [L] LD ........................................................................... 64 LDSR ...................................................................... 66 Link pointer ............................................................. 22 List of conditional branch instruction .................... 54 List of interrupt/exception codes ......................... 107 List of program register operaitons ....................... 22 Load .................................................................. 64, 89 Load instruction .................................................... 115 Load to system register ......................................... 66 load-memory (a, b) ................................................. 46 load-memory-bit (a, b) ........................................... 46 Load/store instruction ............................................ 41 Logical operation instructions ........................ 42, 116 logically shift left by ................................................ 46 logically shift right by ............................................. 46 [M] Maskable interrupts .............................................. 107 Memory map ........................................................... 31 MOV ........................................................................ 67 Move ....................................................................... 67 MOVEA ................................................................... 68 Move effective address .......................................... 68 Move high half-word .............................................. 69 MOVHI .................................................................... 69 MULH ...................................................................... 70 MULHI ..................................................................... 71 Multiply half-word ................................................... 70 Multiply half-word immediate ................................. 71 Multiply instructions .............................................. 116 [N] NMI status saving registers ................................... 24 No operation ........................................................... 72 Non-maskable interrupts ...................................... 109 NOP ........................................................................ 72 Not .......................................................................... 73 NOT ........................................................................ 73 Not bit ..................................................................... 74 NOT1 ...................................................................... 74 NP ........................................................................... 25 Number of instruction execution clock cycles .... 103 [O] Op code .................................................................. 47 Operand address ................................................... 35 Operation ................................................................ 46 140 User's Manual U10243EJ7V0UM APPENDIX D INDEX OR ..................................................................... 46, 75 Or ............................................................................ 75 ORI .......................................................................... 76 Or immediate .......................................................... 76 Outline of instructions ............................................ 41 OV ........................................................................... 25 [P] PC ........................................................................... 22 PC relative .............................................................. 32 Pipeline ................................................................. 114 Pipeline disorder .................................................. 121 Product development ............................................. 18 Program counter .................................................... 22 Program status word .............................................. 24 Program registers ................................................... 20 Program register list ............................................... 21 Program register set .............................................. 20 PSW ........................................................................ 24 [R] R .............................................................................. 47 r ............................................................................... 47 r0 to r31 .................................................................. 22 Register addressing ......................................... 34, 35 Register indirect ..................................................... 34 Register set ............................................................ 20 reg1 ......................................................................... 45 reg2 ......................................................................... 45 regID ....................................................................... 45 Relative addressing ............................................... 32 Reset ..................................................................... 113 Restoring from interrupt/exception ...................... 112 result ....................................................................... 46 RETI ........................................................................ 77 Return from trap or interrupt ................................. 77 Saturated subtract .................................................. 81 Saturated subtract immediate ............................... 82 Saturated subtract reverse .................................... 83 Set bit ..................................................................... 86 SET1 ....................................................................... 86 SETF ....................................................................... 84 Set flag condition ................................................... 84 Shift arithmetic right ............................................... 79 Shift logical left ....................................................... 87 Shift logical right .................................................... 88 SHL ......................................................................... 87 SHR ........................................................................ 88 Short path ............................................................. 125 sign-extend (n) ....................................................... 46 SLD ......................................................................... 89 Software exceptions ............................................. 110 Software trap .......................................................... 98 Special instructions ........................................ 44, 119 SR[ ] ........................................................................ 46 SST ......................................................................... 91 ST ........................................................................... 93 Stack pointer .......................................................... 22 Starting up ............................................................ 113 Store ................................................................. 91, 93 Store contents of system register ......................... 95 Store instructions ................................................. 115 store-memory (a, b, c) ........................................... 46 store-memory-bit (a, b, c) ...................................... 46 STSR ...................................................................... 95 SUB ......................................................................... 96 SUBR ...................................................................... 97 Subtract .................................................................. 96 Subtract reverse ..................................................... 97 System registers .................................................... 23 System register number ......................................... 26 [T] [S] S .............................................................................. 25 SAR ......................................................................... 79 SAT ......................................................................... 25 SATADD ................................................................. 80 SATSUB ................................................................. 81 SATSUBI ................................................................ 72 SATSUBR ............................................................... 83 saturated (n) ........................................................... 46 Saturated add ......................................................... 80 Saturated operation instructions ................... 42, 117 Test ......................................................................... 99 Test bit .................................................................. 100 Text pointer ............................................................ 22 TRAP ...................................................................... 98 TST ......................................................................... 99 TST1 ..................................................................... 100 [U] Unsigned integer .................................................... 29 Unconditional branch instructions ....................... 118 User's Manual U10243EJ7V0UM 141 APPENDIX D INDEX [V] vector ...................................................................... 45 [W] WORD ..................................................................... 28 Word ....................................................................... 28 [X] XOR ................................................................ 46, 101 XOR1 .................................................................... 102 [Z] zero-extend (n) ....................................................... 46 Zero register ........................................................... 22 142 User's Manual U10243EJ7V0UM Facsimile Message From: Name Company Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that errors may occur. Despite all the care and precautions we've taken, you may encounter problems in the documentation. Please complete this form whenever you'd like to report errors or suggest improvements to us. Tel. FAX Address Thank you for your kind support. North America Hong Kong, Philippines, Oceania NEC Electronics Inc. NEC Electronics Hong Kong Ltd. Corporate Communications Dept. Fax: +852-2886-9022/9044 Fax: +1-800-729-9288 +1-408-588-6130 Korea Europe NEC Electronics Hong Kong Ltd. NEC Electronics (Europe) GmbH Seoul Branch Technical Documentation Dept. Fax: +82-2-528-4411 Fax: +49-211-6503-274 South America NEC do Brasil S.A. Fax: +55-11-6462-6829 Taiwan NEC Electronics Taiwan Ltd. Fax: +886-2-2719-5951 Asian Nations except Philippines NEC Electronics Singapore Pte. Ltd. Fax: +65-250-3583 Japan NEC Semiconductor Technical Hotline Fax: +81- 44-435-9608 I would like to report the following error/make the following suggestion: Document title: Document number: Page number: If possible, please fax the referenced page or drawing. Document Rating Clarity Technical Accuracy Organization CS 01.2 Excellent Good Acceptable Poor |
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