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PRELIMINARY DATA SHEET
BIPOLAR ANALOG INTEGRATED CIRCUIT
PC8126K
900 MHz BAND DIRECT QUADRATURE MODULATOR IC FOR DIGITAL MOBILE COMMUNICATION SYSTEMS
DESCRIPTION
The PC8126K is a silicon monolithic integrated circuit designed as quadrature modulator for digital mobile communication systems. This IC integrates a pre-mixer for local signals plus a quadrature modulator operating from 889 MHz to 960 MHz. The chip which has been conventionally packaged in 20-pin SSOP is packaged in 28-pin QFN and therefore is suitable for higher density mounting. In addition, the IC has power save function and can operate 2.7 to 3.6 V supply voltage. Consequently the PC8126K can contribute to make RF blocks smaller size, higher performance and lower power consumption.
FEATURES
* Directly modulate in 889 MHz to 960 MHz * Built-in pre-mixer for local signals * External IF filter can be applied between modulator output and pre-mixer input terminal. * Current consumption ICC = 35 mA TYP. @ VCC = 3.0 V * Equipped with power save function. * 28-pin QFN suitable for higher density mounting.
APPLICATIONS
* Digital cellular phones: PDC800M
ORDERING INFORMATION
Part Number Package 28-pin plastic QFN (5.1 x 5.5 x 0.95 mm) Supplying Form Embossed tape 12 mm wide. QTY 2.5 kp/reel. Pins 1 through 10 are in pull-out direction.
PC8126K-E1
Remark To order evaluation samples, please contact your local NEC sales office . (Part number for sample order: PC8126K)
Caution Electro-static sensitive device
The information in this document is subject to change without notice.
Document No. P13488EJ1V0DS00 (1st edition) Date Published February 1999 N CP(K) Printed in Japan
(c)
1999
PC8126K
INTERNAL BLOCK DIAGRAM AND PIN CONNECTIONS (Top View)
MODout IF-LOin
N. C.
22
21
20
19
18
17
16
15
N. C.
23
N. C.
GND
VCC3
VPS2
N.C.
14
GND
GND
24 LO Pre-Mix
13
Q
RF-LOin
25 /2 I/Q-Mix
12
Qb
VCC1
26 LOx2 Phase Shifter LO Buffer
11
Ib
MIXout
27
10
I
GND
28
9
GND
1
N. C.
2
LOinb
3
N. C.
4
LOin
5
N. C.
6
VCC2
7
VPS1
8
N. C.
2
Preliminary Data Sheet P13488EJ1V0DS00
PC8126K
QUADRATURE MODULATOR SERIES PRODUCT
ICC (mA) fLO1in (MHz) fMODout Up-Converter (MHz) fRFout (MHz) External Phase Shifter F/F
Part Number
Functions 150 MHz Quad.Mod RF Up-Converter + IF Quad.Mod 400 MHz Quad.Mod
Package
Application
PC8101GR PC8104GR PC8105GR PC8110GR PC8125GR PC8126GR PC8126K PC8129GR
15/@2.7 V 100 to 300 50 to 150 28/@3.0 V 100 to 400
20-pin CT-2 etc. SSOP (225 mil) 900 to 1 900 Doubler Digital Comm. + F/F External 16-pin SSOP (225 mil) 20-pin PDC800 MHz, etc. SSOP (225 mil) PHS
16/@3.0 V
100 to 400
1 GHz Direct Quad.Mod RF Up-Converter + IF Quad.Mod + AGC
24/@3.0 V 36/@3.0 V
800 to 1 000 220 to 270
Direct 1 800 to 2 000
900 MHz Direct Quad.Mod 35/@3.0 V with Offset-Mixer
915 to 960
915 to 960 (LO pre-mixer) 889 to 960 F/F 28-pin QFN
PDC800 MHz
889 to 960 x2LO IF Quad. Mod+RF Up-Converter
28/@3.0 V 200 to 800 100 to 400 800 to 1 900
20-pin GSM, SSOP (225 mil) DCS1800, etc. 30-pin PHS TSSOP (225 mil)
PC8139GR-7JH Transceiver IC (1.9 GHz Indirect Quad. Mod + RX-IF + IF VCO)
PC8158K
RF Up-Converter + IF Quad.Mod + AGC
TX: 32.5 RX: 4.8 /@3.0 V 28/@3.0 V
220 to 270
1 800 to 2 000
CR
100 to 300
800 to 1 500
28-pin QFN
PDC800 M/1.5 G
Remark For outline of the quadrature modulator series, please refer to the application note Usage of PC8101, 8104, 8105, 8125, 8129 (Document No. P13251E) and so on.
Preliminary Data Sheet P13488EJ1V0DS00
3
PC8126K
APPLICATION EXAMPLE [PDC800 MHz]
SUB ANT LNA SW RSSI MAIN ANT SW SW 1st LO PLL1 PLL2 2nd LO 1st MIX 2nd MIX TO DEMOD RSSI OUT
I 0
(/2)
PA AGC 90
x2
Filter
Q
PC8126 K
This block diagram presents the IC's location example applied in the system. The system block construction herein is an example.
4
Preliminary Data Sheet P13488EJ1V0DS00
PC8126K
ABSOLUTE MAXIMUM RATINGS
Parameter Supply Voltage Power Save Control Voltage Power Dissipation Operating Ambient Temperature Storage Temperature Symbol VCC VPS PD TA Tstg Test Conditions TA = +25 C TA = +25 C TA = +85 C
Note
Rating 4.0 4.0 430 -40 to +85 -55 to +150
Unit V V mW C C
Note Mounted on a 50 x 50 x 1.6 mm double sided copper clad epoxy glass PWB. RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage Operating Ambient Temperature Pre-Mix. RF Input Frequency Pre-Mix. RF Input Power Pre-Mix. IF Input Frequency Pre-Mix. IF Input Power Pre-Mix. Output Frequency (Modulator Output Frequency, Modulator LO Input Frequency) Modulator LO Input Power I/Q Input Frequency I/Q Input Amplitude Symbol VCC TA fRFin PRFin fIFin PIFin fMIXout (fMODout, fLOin) fIFin = 200 MHz fIFin = 135 MHz P (fIF x 7) -65 dBc Test Conditions MIN. 2.7 -25 689 -13 120 -14 889 915 -21.5 DC Single ended Input Differential Input - - TYP. 3.0 +25 - -11 135 -12 - - -18.5 - - - MAX. 3.6 +75 1 200 -9 270 -10 898 960 -15.5 10 500 250 Unit V C MHz dBm MHz dBm MHz MHz dBm MHz mVP-P
PLOin fI/Qin VI/Qin
Preliminary Data Sheet P13488EJ1V0DS00
5
PC8126K
ELECTRICAL CHARACTERISTICS (TA = +25C, VCC1 = VCC2 = VCC3 = 3.0 V, VPS1, VPS2 2.2 V unless otherwise specified)
Parameter Symbol Test Conditions MIN. TYP. MAX. Unit
MODULATOR + PRE-MIXER TOTAL (TEST CIRCUIT 1 unless otherwise specified) Total Circuit Current Total Circuit Current at Sleep Mode ICC (TOTAL) ICC (PS) TOTAL No Input Signals VPS 0.5 V (Low), No Input Signals fIFin = 135 MHz, PIFin = -12 dBm fRFin = 813 MHz, PRFin = -11 dBm fMODout = 948 MHz + fI/Q fI/Qin = 2.625 kHz VI/Qin = 500 mVP-P (Single ended) I/Q (DC) = Ib/Qb (DC) = VCC/2 Data Rate: 42 kbps, RNYQ: = 0.5 MOD Pattern: All Zero VPS: Low to High, TEST CIRCUIT 2 VPS: High to Low, TEST CIRCUIT 2 fIFin = 135 MHz, PIFin = -12 dBm fRFin = 813 MHz, PRFin = -11 dBm fMODout = 948 MHz + fI/Q fI/Qin = 2.625 kHz VI/Qin = 500 mVP-P (Single ended) I/Q (DC) = Ib/Qb (DC) = VCC/2 Data Rate: 42 kbps, RNYQ: = 0.5 MOD Pattern: PN9 (Pseudorandom pattern) No Input Signals No Input Signals 24 - 35 0 44 15 mA
A
dBm dBc dBc dBc dBc
Modulator Output Power Local Oscillator Leakage Image Rejection I/Q 3rd Order Intermodulation fIF-LO x 7 Harmonics Power Save Response Time Rise Time Fall Time
PMODout LOL
Note
-12 - - - - - - -
-9 -35 -40 -45 - 3 3 1.6
-6 -30 -30 -30 -65 5 5 3.5
ImR IM3 (I/Q) P (fIF x 7) TPS (RISE) TPS (FALL) EVM
s s
%rms
Error Vector Magnitude
Adjacent Channel Power
ACP (f = 50 kHz)
-
-65
-60
dBc
Port Current-7 pin Port Current-17 pin
IPS (7 pin) IPS (17 pin)
- -
- -
620 400
A A
Note fLOL = fIFin + fRFin
6
Preliminary Data Sheet P13488EJ1V0DS00
PC8126K
STANDARD CHARACTERISTICS FOR REFERENCE (TA = +25C, VCC1 = VCC2 = VCC3 = 3.0 V, VPS1, VPS2 2.2 V unless otherwise specified)
Parameter MODULATOR (TEST CIRCUIT 3) Modulator Circuit Current Modulator Circuit Current at Sleep Mode Input Impedance I and Q Port Modulator Output Port VSWR PRE-MIXER (TEST CIRCUIT 4) Pre-Mixer Circuit Current Pre-Mixer Circuit Current at Sleep Mode Pre-Mixer Conversion Gain Pre-Mixer Output Power ICC (MIX) ICC (PS) (MIX) No Input Signals VPS 0.5 V (Low), No Input Signals fRFin = 813 MHz, PRFin = -11 dBm fIFin = 135 MHz, PIFin = -12 dBm fMIXout = 948 MHz - - 7.5 0 10 5 mA ICC (MOD) ICC (PS) (MOD) No Input Signals VPS 0.5 V (Low), No Input Signals fI/Q = DC to 10 MHz fMODout = 948 MHz - - 27.5 0 34 10 mA Symbol Test Conditions MIN. TYP. MAX. Unit
A
k -
ZI/Qin VSWR (MOD)
90 -
180 1.5:1
- -
A
dB dBm
CG (MIX) Pout (MIX)
-5 -17
-3 -15
-1 -13
Preliminary Data Sheet P13488EJ1V0DS00
7
PC8126K
PIN EXPLANATIONS
Supply Voltage (V) - Pin Voltage (V) @3 V 2.6
Pin No. 2
Symbol
Description
Equivalent Circuit
LOinb
Bypass of LO input for modulator. This pin should be externally grounded through around 33 pF capacitor. LO input for the phase shifter. Connect around 300 between pin 4 and 5 to match to 50 by LC.
4
2
4
LOin
-
2.6
6
VCC2
2.7 to 3.6
-
Supply voltage pin for the phase shifter and IQ Mixer. An internal regulator helps keep the device stable against temperature or VCC variation. Power save control pin for the modulator can control On/Sleep state with bias as follows. VPS (V) 2.2 to 3.6 0 to 0.5 State ON (Active Mode) OFF (Sleep Mode)
-------------
7
VPS1 (Modulator)
VPS
-
7
9
GND (Modulator)
0
-
Ground pin for the modulator. Connect to the ground with minimum inductance. Track length should be kept as short as possible. Input for I signal. This input impedance is 180 k. In case of that I/Q input signals are single ended, amplitude of the signal is 500 mVP-P max. Note Input for I signal. This input impedance is 180 k. In case of that I/Q input signals are single ended, VCC/2 biased DC signal should be input. In case of that I/Q input signals are differential, amplitude of the signal is 250 m VP-P max. Note
-------------
10
I
VCC/2
-
11
Ib
VCC/2
-
10
11
Note Relations between amplitude and VCC/2 bias of input signal are following.
8
Preliminary Data Sheet P13488EJ1V0DS00
PC8126K
Pin No. 12 Supply Voltage (V) VCC/2 Pin Voltage (V) @3 V -
Symbol
Description
Equivalent Circuit
Qb
Input for Q signal. This input impedance is 180 k. In case of that I/Q input signals are single ended, VCC/2 biased DC signal should be input. In case of that I/Q input signals are differential, amplitude of the signal is 250 mVP-P max. Note Input for Q signal. This input impedance is 180 k. In case of that I/Q input signals are single ended, amplitude of the signal is 500 mVP-P max. Note Ground pin for the modulator. Connect to the ground with minimum inductance. Track length should be kept as short as possible. Supply voltage pin for the output buffer amplifier of modulator. An internal regulator helps keep the device stable against temperature or VCC variation. Output pin from the modulator. This is emitter follower output. So this output impedance is low.
12
13
13
Q
VCC/2
-
14
GND (Modulator)
0
-
-------------
16
VCC3
2.7 to 3.6
-
-------------
17
MODout
-
1.6
17
19
GND (Modulator)
0
-
Ground pin for the modulator. Connect to the ground with minimum inductance. Track length should be kept as short as possible. Power save control pin can control the On/Sleep state with bias as follows. VPS (V) 2.2 to 3.6 0 to 0.5 State ON (Active Mode) OFF (Sleep Mode)
-------------
20
VPS2 (Pre-Mix)
VPS
-
20
Note Relations between amplitude and VCC/2 bias of input signal are following.
Preliminary Data Sheet P13488EJ1V0DS00
9
PC8126K
Pin No. 21 Supply Voltage (V) - Pin Voltage (V) @3 V 1.3
Symbol
Description
Equivalent Circuit
IF-LOin
IF input pin for the Pre-Mixer. This pin is biased internally. Capacitor should be connected in series, and grounded through 51 .
21
24
GND (Pre-Mix)
0
-
Ground pin for Pre-Mixer. Connect to the ground with minimum inductance. Track length should be kept as short as possible. RF input pin for the Pre-Mixer. This pin is biased internally. Capacitor should be connected in series, and grounded through 51 .
-------------
25
RF-LOin
-
2.3
25
26
VCC1 (Pre-Mix)
2.7 to 3.6
-
Supply voltage pin for the Pre-Mixer. An internal regulator helps keep the device stable against temperature or VCC variation. Output from the Pre-Mixer. This pin is designed as open collector. Due to the high impedance output, this pin should be externally equipped with LC matching circuit to next stage.
-------------
27
Pre-Mixout
2.7 to 3.6
-
27
28
GND (Modulator)
0
-
Ground pin for the modulator. Connect to the ground with minimum inductance. Track length should be kept as short as possible. Non connection pins.
-------------
1, 3, 5, 8, 15, 18, 22, 23
N.C.
-
-
-------------
10
Preliminary Data Sheet P13488EJ1V0DS00
PC8126K
RELATION BETWEEN I/Q PIN INPUT DC VOLTAGE AND AMPLITUDE
I/Q input signal (mVP-P) Supply Voltage (V) VCC 2.7 to 3.6 I/Q DC Voltage (V) VCC/2 = I = Ib = Q = Qb 1.35 to 1.8 Single ended input I=Q 500 Differential input I = Ib = Q = Qb 250
EXPLANATION OF INTERNAL FUNCTION
Block 90 PHASE SHIFTER Function/Operation Input signal from LO is send to digital circuit of T-type flip-flop through frequency doubler. Output signal from T-type F/F is changed to same frequency as LO input and that have quadrature phase shift, 0, 90 , 180, 270. These circuits have function of self phase correction to make correctly quadrature signals. Block Diagram
from LOin x2
/2F/F
BUFFER AMP.
Buffer amplifiers for each phase signals to send to each mixers.
MIXER
Each signals from buffer amp. are quadrature modulated with two double-balanced mixers. High accurate phase and amplitude inputs are realized to good performance for image rejection.
I Ib Qb Q
ADDER
Output signals from each mixers are added with adder and send to final amplifier.
to MODout
Preliminary Data Sheet P13488EJ1V0DS00
11
PC8126K
TEST CIRCUIT 1 Pre-mixer + Quadrature modulator (except Power save response time)
Spectrum Analyzer Signal Generator
Voltage Source
Signal Generator VPS2 (Pre Mix) BPF
Voltage Source
VCC3 (MOD) 100 pF 1 000 pF 33 pF 0.22 F
MODout IFin
RFin VCC1 (Pre Mix) 100 pF 51 1 000 pF 33 pF 0.22E F Mixout 7 pF 5.6 nH 1 pF 18 nH 15 nH
51 1 000 pF
22 21 20 19 18 17 16 15 23 24 25 26 27 28 1 7 pF 33 pF 6.8 nH 2 pF 33 pF 0.22 F
Voltage Source
14 13 PreMixer TFF I/Q Mixer Frequency Doubler I/Q Mixer 2 3 300 1 000 pF 4 5 6 100 pF 7 8 12 11 10 9 Qin Qb Ib Iin
I/Q Singnal Generator
VPS1 (MOD)
2.5 pF
6.8 nH Filter
10 nH
18 nH
VCC2 (MOD)
12
Preliminary Data Sheet P13488EJ1V0DS00
PC8126K
TEST CIRCUIT 2 Pre-mixer + Quadrature modulator (for Power save response time)
Spectrum Analyzer Signal Generator
Voltage Source
Signal Generator VPS2 (Pre Mix) BPF
Voltage Source
VCC3 (MOD) 100 pF 1 000 pF 33 pF 0.22 F
MODout IFin 51 1 000 pF 51 23 22 21 20 19 18 17 16 15 14 13 PreMixer TFF I/Q Mixer Frequency Doubler I/Q Mixer 1 2 3 300 33 pF 1 000 pF 33 pF 0.22 F
Voltage Source
RFin VCC1 (Pre Mix) 100 pF 1 000 pF 33 pF 0.22 F Mixout 7 pF 5.6 nH 1 pF 18 nH 15 nH 27 28 24 25 26
I/Q Singnal Generator Qin Qb Ib Iin Palse Pattern Generator
12 11 10 9
4
7 pF
5 6 100 pF
7
8
VPS1 (MOD)
2.5 pF
6.8 nH
6.8 nH Filter 2 pF 10 nH 18 nH VCC2 (MOD)
Preliminary Data Sheet P13488EJ1V0DS00
13
PC8126K
TEST CIRCUIT 3 Quadrature modulator block
Spectrum Analyzer or Network Analyzer
Voltage Source
VCC3 (MOD) 100 pF MODout 1 000 pF 33 pF 0.22 F 17 16 15 14 13 12 11 10 9 1 2 3 300 33 pF 4 5 6 100 pF 7 8 Voltage Source Pulse Pattern Generator I/Q Signal Generator Qin Qb Ib Iin
22 23 24 25 26 27 28
21
20
19
18
33 pF
1 000 pF 6.8 nH 0.22 F
VPS1 (MOD) Voltage Source VCC2 (MOD)
LOinb 2 pF Signal Generator
LOin
In this case, pin 20 to 27 should be opened or grounded.
14
Preliminary Data Sheet P13488EJ1V0DS00
PC8126K
TEST CIRCUIT 4 Pre-mixer block
Signal Generator Signal Generator
Voltage Source Voltage Source IFin VCC1 (Pre Mix) RFin 100 pF 1 000 pF VPS2 (Pre Mix) 22 1 000 pF 0.22 F 51 23 24 33 pF 25 26 Mixout 1 pF 18 nH 15 nH 27 28 Spectrum Analyzer 1 2 21
BPF
51
MODout
VCC3 (MOD)
20
19
18
17
16
15 14 13 12 11 10 9 Qin Qb Ib Iin
3
4
5
6
7
8
LOinb
VPS1 (MOD) LOin VCC2 (MOD)
Preliminary Data Sheet P13488EJ1V0DS00
15
PC8126K
PACKAGE DIMENSIONS
28 pin plastic QFN (UNIT: mm)
4 - 0.5
4 - 0.5
2 x 0.5 = 1
0.5
(5.1 0.1) 0.5
5.1 0.1
1 pin 0.22 0.5 7 x 0.5 = 3.5 5.5 0.1
2 x 0.5 = 1
28 pin
0.22 0.5
(4.7)
1.2
0.125
0.95 0.1
0.5
(0.22)
(5.1)
(4.1)
(5.5 0.1)
(0.22) 0.5 (4.5) 0.5
Bottom View
16
Preliminary Data Sheet P13488EJ1V0DS00
0.3
PC8126K
NOTE ON CORRECT USE
(1) Observe precautions for handling because of electrostatic sensitive devices. (2) Form a ground pattern as widely as possible to minimize ground impedance (to prevent undesired operation). (3) Keep the track length between the ground pins as short as possible. (4) Connect a bypass capacitor (example 1 000 pF) to the VCC pin.
RECOMMENDED SOLDERING CONDITIONS
This product should be soldered under the following recommended condition. For soldering methods and conditions other than those recommended below, contact your NEC sales representative.
Recommended Condition Symbol IR35-00-2
Soldering Method Infrared Reflow
Soldering Conditions Package peak temperature: 235C or below Time: 30 seconds or less (at 210C) Note Count: 2, Exposure limit : None Pin temperature: 300C Time: 3 seconds or less (per side of device) Note Exposure limit : None
Partial Heating
-
Note After opening the dry pack, keep it in a place below 25C and 65% RH for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). For details of recommended soldering conditions for surface mounting, refer to information document SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL (C10535E).
Preliminary Data Sheet P13488EJ1V0DS00
17
PC8126K
[MEMO]
18
Preliminary Data Sheet P13488EJ1V0DS00
PC8126K
[MEMO]
Preliminary Data Sheet P13488EJ1V0DS00
19
PC8126K
The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.
M4 96. 5

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