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IT8281M
K8 Power Sequence Controller
Preliminary Specification V0.1
INTEGRATED TECHNOLOGY EXPRESS, INC.
Specification subject to Change without notice, AS IS and for reference only. For purchasing, please contact sales representatives.
Copyright 2003 ITE, Inc. This is Preliminary document release. All specifications are subject to change without notice. The material contained in this document supersedes all previous documentation issued for the related products included herein. Please contact ITE, Inc. for the latest document(s). All sales are subject to ITE's Standard Terms and Conditions, a copy of which is included in the back of this document. ITE, IT8208M is a trademark of ITE, Inc. All other trademarks are claimed by their respective owners. All specifications are subject to change without notice. Additional copies of this manual or other ITE literature may be obtained from: ITE, Inc. Marketing Department 8F, No. 233-1, Bao Chiao Rd., Hsin Tien, Taipei County 231, Taiwan, R.O.C. ITE (USA) Inc. Marketing Department 1235 Midas Way Sunnyvale, CA 94086 U.S.A. ITE (USA) Inc. Eastern U.S.A. Sales Office 896 Summit St., #105 Round Rock, TX 78664 U.S.A. Phone: Fax: (02) 2912-6889 (02) 2910-2551, 2910-2552
Phone: Fax:
(408) 530-8860 (408) 530-8861
Phone: Fax:
(512) 388-7880 (512) 388-3108
If you have any marketing or sales questions, please contact: Lawrence Liu, at ITE Taiwan: E-mail: lawrence.liu@ite.com.tw, Tel: 886-2-2912-6889 X6071, Fax: 886-2-26578561 David Lin, at ITE U.S.A: E-mail: david.lin@iteusa.com, Tel: (408) 530-8860 X238, Fax: (408) 530-8861 Don Gardenhire, at ITE Eastern USA Office: E-mail: don.gardenhire@iteusa.com Tel: (512) 388-7880, Fax: (512) 388-3108 To find out more about ITE, visit our World Wide Web at: http://www.ite.com.tw http://www.iteusa.com Or e-mail itesupport@ite.com.tw for more product information/services.
Contents Contents
1. Features ......................................................................................................................................................... 1 2. General Description........................................................................................................................................ 3 3. Block Diagram ................................................................................................................................................ 5 4. Pin Configuration............................................................................................................................................ 7 5. IT8281M Pin Descriptions .............................................................................................................................. 9 6. DC Characteristics (VCC = 5.0V5%. Ta=0C to 70C) .............................................................................. 11 7. AC Characteristics........................................................................................................................................ 13 8. Package Information .................................................................................................................................... 15 9. Ordering Information .................................................................................................................................... 17
Figures
Figure 2-1. Application Circuit ............................................................................................................................. 3
Tables
Table 4-1. Pins Listed in Numeric Order ............................................................................................................. 7 Table 5-1. Pin Descriptions of Power Sequence ................................................................................................. 9 Table 5-2. Pin Descriptions of Power-Good Generation ..................................................................................... 9 Table 5-3. Pin Descriptions of Power/Ground Signals ........................................................................................ 9 Table 7-1. AC Timing Parameter....................................................................................................................... 13
i
Features
1. Features
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K8 Power Sequence Controller Built-in enhanced voltage comparator System Power-Good Generation Built-in power-good glue logic Single 5VSB Power Supply 16-pin SOP
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General Description
2. General Description
The IT8281M incorporates glue logics for AMD K8 CPU power sequence application and provides the system power-good request. Outstanding features of this controller IC include special voltage comparators for VLDT, VDDA and VDIMM_STR power detected without the need of any external components. All power-good generation circuits support AMD K8 main board design for saving glue logics cost. The following figure is the application hint.
5VSB VCORE
Power_VCORE Block
VCORE VCORE_GD EN 5VSB
Power_VDIMM_STR Block
GND
VDIMM_STR
VDIMM_STR VDDA_25 VLDT_12 16
VDIMM_STR EN GND
Power_VDDA_25 Block
VDDA_25
1 2 3 4 VCORE 5VSB
VCORE_GD VLDT_12
5VSB
VCORE_EN VDIMM_STR_EN
13 12 14 15
VDDA_25 EN GND VLDT_12
Power_VLDT Block
VDDA_25 VDDA_EN VDIMM_STR VLDT_EN
VLDT_12 EN GND 5VSB
IT8281M
Power Sequence Controller
25VDUAL
K8
CPU_PWRGD ATX_PSON# ATX_PWRGD 5 6 SB_PSON# ACPI_S3 GND CPU_PWRGD SB_PWRGD 9 7 10
ATX Power
PSON# PWRGD
South Bridge
SB_PSON# ACPI_S3 SB_PWRGD
25VDUAL 11
Motherboard designer can use an AND-Gate to AND Panel-Button-Reset Input with either SB_PWRGD or CPU_PWRGD to generate a reset signal.
25VDUAL 14 1 2 7
8
All_Power_Good 3 RSTSW#
Figure 2-1. Application Circuit
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Block Diagram
3. Block Diagram
VCORE_GD
VLDT_12
Detector
VDDA_25
Detector
Delay Logic
PWR_Sequence
VDIMM_STR
Detector
ATX_PWRGD PWRGD ACPI_S3 S/B PS_ON# Delay Logic Logic PS_ON#
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Pin Configuration
4. Pin Configuration
VCORE_GD VLDT_12 VDDA_25 VDIMM_STR SB_PSON# ACPI_S3 ATX_PWRGD GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
5VSB VLDT_EN VDDA_EN VCORE_EN VDIMM_STR_EN CPU_PWRGD SB_PWRGD ATX_PSON#
Pin
1 2 3 4 5 6 7 8
Table 4-1. Pins Listed in Numeric Order Signal Pin Signal
VCORE_GD VLDT_12 VDDA_25 VDIMM_STR SB_PSON# ACPI_S3 ATX_PWRGD GND 9 10 11 12 13 14 15 16 ATX_PSON# SB_PWRGD CPU_PWRGD VDIMM_STR_EN VCORE_EN VDDA_EN VLDT_EN 5VSB
IT8281M
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Pin Descriptions
5. IT8281M Pin Descriptions
Table 5-1. Pin Descriptions of Power Sequence
Pin(s) No. 1 2 3 4 5 Symbol VCORE_GD VLDT_12 VDDA_25 VDIMM_STR SB_PSON# Attribute DI AI AI AI DI Description VCORE Power- Good. Active high. This pin indicates that the power-good signal from the PWM controller for CPU core voltage. VLDT (1.2V) analog inputs. VDDA (2.5V) analog inputs. VDIMM DUAL STR (2.5V) analog inputs. South Bridge PSON#. Active low. This signal is connected to the PSON# signal from the south bridge or Super I/O to control the on/off of ATX power supply. A GPIO pin from S/B. Active high. This pin indicates that the system is in ACPI S3 state. ATX Power PSON#. Active low. The function of this pin is ATX Power Supply On-Off. VDIMM STR Enable. Active high. The function of this pin is to enable the PWM for VDIMM_STR dual voltage. VCORE Enable. Active high. The function of this pin is to enable the PWM for CPU VCORE. VDDA Enable. Active high. The function of this pin is to enable the VDDA power for K8 CPU. VLDT Enable. Active high. The function of this pin is to enable the VLDT voltage.
6 9 12 13 14 15
ACPI_S3 ATX_PSON# VDIMM_STR_ EN VCORE_EN VDDA_EN VLDT_EN
DI DOD8 DOD8 DOD8 DOD8 DOD8
Table 5-2. Pin Descriptions of Power-Good Generation
Pin(s) No. 7 10 11 Symbol ATX_PWRGD SB_PWRGD CPU_PWRGD Attribute DI DOD8 DOD8 Description ATX Power-Good. Active high. Input indicates that ATX power supply power-good is ready. South Bridge Power-Good. Active high. Output indicates that the south bridge power-good is ready. CPU Power-Good. Active high. Output indicates that CPU power-good is ready.
Table 5-3. Pin Descriptions of Power/Ground Signals
Pin(s) No. 8 16 Symbol GND 5VSB Attribute PWR PWR Description Ground +5V Standby Power Supply
IO Cell: DOD8: 8mA Digital Open-Drain Output buffer AI: Analog input DI: Digital Input
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DC Characteristics
6. DC Characteristics (VCC = 5.0V5%. Ta=0C to 70C)
Absolute Maximum Ratings Power Supply (VCC) Input Voltage Output Voltage Storage Temperature -0.5V to 7.0V -0.5V to VCC + 0.5V -0.5V to VCC + 0.5V -55C to 125C *Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied, and exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC Electrical Characteristics (Operation Condition Vcc=5V 5%, Ta = 0C to + 70C) Symbol Parameter Condition Min. Typ. AI Type Buffer Vtrig Trigger point for VDDA_25 and VCC=5V 2.25 VDIMM_STR Vtrig VOL Trigger point for VLDT_12 Output Low Voltage VCC=5V IOL=8mA IOH=8mA 2.4 2.2 IOL=8mA VIN=0 VIN=VCC 2.2 VIN=0 VIN=VCC 1.0 10 10 DOD8 Type Buffer
Max. 0.4 0.8 0.4 -10 20 0.8 -10
Unit V V V V V V V uA uA uA V V uA uA
VOH Output High Voltage DIOD8 Type Buffer VIL Input Low Voltage VIH VOL IIL IIH Input High Voltage Output Low Voltage Low Input Leakage current High Input Leakage current
IOZ Tri-state leakage current DI Type Buffer VIL Input Low Voltage VIH IIL IIH Input High Voltage Input Leakage current High Input Leakage current
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AC Characteristics
7. AC Characteristics
Power on
t0 t1 t2 t3 t4 t5
Enter S3
t11 t6 t7 t8 t9 t0
Exit S3
t1 t3 t4 t5
Power off
t11 t6 t7 t8 t9 t10
ACPI_S3 SB_PSON# ATX_PSON# ATX_PWRGD VDIMM_STR_EN VDDA_EN VCORE_EN VCORE_GD VLDT_EN CPU_PWRGD SB_PWRGD
Table 7-1. AC Timing Parameter Item t0 t1 t2 Max Typ 1us 50us Min 0 50us Description The falling edge of SB_PSON# to the assertion of ATX_PSON#. The rising edge of ATX_PWRGD to the assertion of VDIMM_STR_EN The assertion of VDIMM_STR_EN to the assertion of VDDA_EN. The t_vdimm_gd is the rise time of the VDIMM_STR_EN voltage from 0V to 2.25V. The assertion of VDDA_EN to the assertion of VCORE_EN. The t_vdda_gd is the rise time of the VDDA voltage from 0V to 2.25V. The rising edge of VCORE_GD to the assertion of VLDT_EN. The assertion of VLDT_EN to the assertion of CPU_PWRGD and SB_PWRGD. The t_vldt_gd is the rise time of the vldt voltage from 0V to 1.0V. The de-assertion of CPU_PWRGD and SB_PWRGD to the de-assertion of VLDT_EN. The de-assertion of VLDT_EN to the de-assertion of VCORE_EN. The falling edge of VCORE_GD to the de-assertion of VDDA_EN. The de-assertion of VDDA_EN to the de-assertion of VDIMM_STR_EN or ATX_PSON#. The de-assertion of VDIMM_STR_EN to the de-assertion of ATX_PSON#. The rising edge of SB_PSON# to the de-assertion of CPU_PWRGD and SB_PWRGD.
50us + t_vdimm_gd 50us + t_vdda_gd 50us 50us + t_vldt_gd 50us 10ms 10ms 10ms 50ms 50us
t3 t4 t5
50us
50us
t6 t7 t8 t9 t10 t11
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Package Information
8. Package Information
SOP16L Outline Dimensions unit: inches/mm
16 9
E
HE E
1
b
8
L
Detail F
D
A2 2
y
Seating Plane
D
A1 1
e
A
See Detail F
Symbol A A1 A2 b C D E e HE L L1 y
Dimension in inches Min Nom Max 0.053 0.064 0.069 0.004 0.006 0.010 0.051 0.055 0.059 0.013 0.016 0.020 0.007 0.010 0.386 0.390 0.394 0.150 0.154 0.157 0.050BSC 0.228 0.236 0.244 0.016 0.025 0.050 0.042REF. 0.004 0 8
Dimension in mm Min Nom Max 1.35 1.63 1.75 0.10 0.15 0.25 1.30 1.40 1.50 0.33 0.41 0.51 0.19 0.25 9.80 9.91 10.01 3.80 3.90 4.00 1.27BSC 5.80 6.00 6.20 0.40 0.64 1.27 1.07REF. 0.10 0 8
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C L1
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Ordering Information
9. Ordering Information
Part No. IT8281M Package 16 SOP
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