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RF4E20N50S Data Sheet May 2002 20A, 500V, 0.240 Ohm, N-Channel Power MOSFETs Features * 20A, 500V [ /Title These are N-Channel enhancement mode silicon gate * rDS(ON) = 0.240 (HUF75 power field effect transistors. They are advanced power * Single Pulse Avalanche Energy Rated 337G3, MOSFETs designed, tested, and guaranteed to withstand a * SOA is Power Dissipation Limited HUF753 specified level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for 37P3, * Nanosecond Switching Speeds applications such as switching regulators, switching HUF753 convertors, motor drivers, relay drivers, and drivers for high * Linear Transfer Characteristics 37S3, power bipolar switching transistors requiring high speed and * High Input Impedance HUF753 low gate drive power. These types can be operated directly * Related Literature 37S3S) from integrated circuits. - TB334 "Guidelines for Soldering Surface Mount Compo/Subject Formerly developmental type TA17465. nents to PC Boards" (62A, Ordering Information 55V, Symbol 0.014 PART NUMBER PACKAGE BRAND D Ohm, N- RF4E20N50S TO-268AA RF4E20N50S Channel NOTE: When ordering, use the entire part number. UltraFE G T Power S MOSFETs) /Author () /Keywords (Harris Packaging SemiJEDEC TO-268AA conductor, NDRAIN Channel (TAB) UltraFE T Power GATE MOSSOURCE FETs, TO-247, TO220AB, TO262AA, TO263AB) (c)2002 Fairchild Semiconductor Corporation RF4E20N50S revA1 RF4 E2 0 N50 S Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified RF4E20N50S 500 500 20 12 80 20 250 2.0 960 -55 to 150 300 260 UNITS V V A A A V W W/oC mJ oC oC oC Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulse Avalanche Energy Rating (Note 4). . . . . . . . . . . . . . . . . . . . . . . . EAS Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. Electrical Specifications PARAMETER TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS TEST CONDITIONS ID = 250A, VGS = 0V, (Figure 10) VGS = VDS, ID = 250A VDS = Rated BVDSS, VGS = 0V VDS = 0.8 x Rated BVDSS,, VGS = 0V TJ = 125o MIN 500 2 20 13 VGS = 10V, ID = 20A, VDS = 0.8 x Rated BVDSS, IG(REF) = 1.5mA, (Figures 14, 19, 20) Gate Charge is Essentially Independent of OperatingTemperature TYP 19 23 81 85 65 120 MAX 4 25 250 100 0.240 35 120 130 98 190 UNITS V V A A A nA S ns ns ns ns nC Drain to Source Breakdown Voltage Gate Threshold Voltage Zero Gate Voltage Drain Current On-State Drain Current (Note 2) Gate to Source Leakage Current Drain to Source On Resistance (Note 2) Forward Transconductance (Note 2) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge (Gate to Source + Gate-Drain) Gate to Source Charge Gate to Drain "Miller" Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance ID(ON) IGSS rDS(ON) gfs td(ON) tr td(OFF) tf Qg(TOT) Qgs Qgd CISS COSS CRSS VDS > ID(ON) x rDS(ON)MAX, VGS = 10V VGS = 20V ID = 11A, VGS = 10V, (Figures 8, 9) VDS 50V, IDS > 11A, (Figure 12) VDD = 250V, ID = 20A, RGS = 4.3, RD = 12.5, VGS = 10V, (Figures 17, 18) MOSFET Switching Times are Essentially Independent of Operating Temperature - 18 62 4100 480 84 - nC nC pF pF pF VDS = 25V, VGS = 0V, f = 1MHz, (Figure 10) - RF4 E2 0 N50 S Electrical Specifications PARAMETER Internal Drain Inductance TC = 25oC, Unless Otherwise Specified SYMBOL LD TEST CONDITIONS Measured from the Drain Lead, 6mm (0.25in) from Package to Center of Die Measured from the Source Lead, 6mm (0.25in) from Header to Source Bonding Pad Modified MOSFET Symbol Showing the Internal Device Inductances D LD G LS S MIN - TYP 5.0 MAX - UNITS nH Internal Source Inductance LS - 13 - nH Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient RJC RJA Free Air Operation - - 0.50 30 oC/W oC/W Source to Drain Diode Specifications PARAMETER Continuous Source to Drain Current Pulse Source to Drain Current (Note 3) SYMBOL ISD ISDM TEST CONDITIONS Modified MOSFET Symbol Showing the Integral Reverse P-N Junction Rectifier G D MIN - TYP - MAX 20 80 UNITS A A S Source to Drain Diode Voltage (Note 2) Reverse Recovery Time Reverse Recovery Charge NOTES: VSD trr QRR TJ TJ TJ = 25oC, ISD = 20A, VGS = 0V, (Figure 13) = 25oC, ISD = 20A, dISD/dt = 100A/s = 25oC, ISD = 20A, dISD/dt = 100A/s 280 3.8 580 8.1 1.8 1200 18 V ns C 2. Pulse test: pulse width 300s, duty cycle 2%. 3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3). 4. VDD = 50V, starting TJ = 25oC, L = 4.3mH, RGS = 25, Peak IAS = 20A (Figures 15, 16). Typical Performance Curves 1.2 POWER DISSIPATION MULTIPLIER 1.0 ID, DRAIN CURRENT (A) 20 16 0.8 0.6 0.4 0.2 0 12 8 4 0 0 50 100 150 25 50 75 100 125 150 TC, CASE TEMPERATURE (oC) TC, CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE RF4 E2 0 N50 S Typical Performance Curves 1 ZJC, THERMAL IMPEDANCE (oC/W) (Continued) 0.5 0.1 0.2 0.1 0.05 PDM 0.02 10-2 0.01 SINGLE PULSE NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC 10-4 10-3 10-2 0.1 t1, RECTANGULAR PULSE DURATION (S) 1 10 t1 t2 10-3 10-5 FIGURE 3. MAXIMUM TRANSIENT THERMAL IMPEDANCE 103 5 2 ID, DRAIN CURRENT (A) 102 5 2 10 5 2 1 40 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) ID, DRAIN CURRENT (A) 10s 100s 1ms 10ms DC VGS = 10V VGS = 6.0V 32 VGS = 5.5V 24 80s PULSE TEST 16 VGS = 5.0V 5 T = 25oC C T = MAX RATED 2J SINGLE PULSE 0.1 1 2 5 10 8 VGS = 4.5V VGS = 4.0V 2 5 102 2 5 103 0 0 50 100 150 200 250 VDS, DRAIN TO SOURCE VOLTAGE (V) VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. OUTPUT CHARACTERISTICS 40 80s PULSE TEST 32 VGS = 10V VGS = 6.0V ID, DRAIN CURRENT(A) VGS = 5.5V 24 102 VDS 50V 80s PULSE TEST 10 TJ = 150oC 1 TJ = 25oC 0.1 ID, DRAIN CURRENT (A) 16 VGS = 5.0V 8 VGS = 4.5V VGS = 4.0V 0 0 4 8 12 16 20 VDS, DRAIN TO SOURCE VOLTAGE (V) 10-2 0 2 4 6 8 VGS, GATE TO SOURCE VOLTAGE (V) 10 FIGURE 6. SATURATION CHARACTERISTICS FIGURE 7. TRANSFER CHARACTERISTICS RF4 E2 0 N50 S Typical Performance Curves 2.5 80s PULSE TEST NORMALIZED DRAIN TO SOURCE ON RESISTANCE rDS(ON), DRAIN TO SOURCE ON RESISTANCE () 2.0 VGS = 10V 2.4 (Continued) 3.0 VGS = 10V, ID = 11A 1.5 1.8 1.0 1.2 0.5 0.6 VGS = 20V 0 0 0 20 40 60 ID, DRAIN CURRENT (A) 80 100 -40 0 40 80 120 160 TJ , JUNCTION TEMPERATURE (oC) FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 1.25 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE ID = 250A C, CAPACITANCE (pF) 1.15 10000 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS = CDS + CGD 8000 CISS 6000 COSS 4000 1.05 0.95 0.85 2000 CRSS 0.75 -40 0 40 80 120 160 TJ , JUNCTION TEMPERATURE (oC) 0 1 2 5 10 2 5 VDS, DRAIN TO SOURCE VOLTAGE (V) 102 FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 40 gfs, TRANSCONDUCTANCE (S) ISD, SOURCE TO DRAIN CURRENT (A) VDS 50V 80s PULSE TEST 102 5 2 10 5 2 1 5 2 0.1 0 0.4 0.8 1.2 1.6 2.0 TJ = 150oC TJ = 25oC 32 TJ = 25oC 24 16 TJ = 150oC 8 0 0 8 16 24 ID, DRAIN CURRENT (A) 32 40 VSD, SOURCE TO DRAIN VOLTAGE (V) FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE RF4 E2 0 N50 S Typical Performance Curves 20 (Continued) ID = 20A VDS = 400V VDS = 250V VDS = 100V VGS, GATE TO SOURCE (V) 16 12 8 4 0 0 40 80 120 160 200 Qg(TOT), TOTAL GATE CHARGE (nC) FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE Test Circuits and Waveforms VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD + 0V IAS 0.01 0 tAV FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS tON td(ON) tr RL VDS + tOFF td(OFF) tf 90% 90% RG DUT - VDD 0 10% 90% 10% VGS VGS 0 10% 50% PULSE WIDTH 50% FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS RF4 E2 0 N50 S Test Circuits and Waveforms VDS RL VDD VDS VGS = 20V VGS + (Continued) Qg(TOT) Qg(10) VDD VGS VGS = 2V 0 Qg(TH) IG(REF) 0 VGS = 10V DUT IG(REF) FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORM TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx Bottomless CoolFET CROSSVOLT DenseTrench DOME EcoSPARK E2CMOSTM EnSignaTM FACT FACT Quiet Series DISCLAIMER FAST a FASTr FRFET GlobalOptoisolator GTO HiSeC I2C ISOPLANAR LittleFET MicroFET MicroPak MICROWIRE OPTOLOGIC a OPTOPLANAR PACMAN POP Power247 PowerTrench a QFET QS QT Optoelectronics Quiet Series SILENT SWITCHER a UHC SMART START UltraFET a SPM VCX STAR*POWER Stealth SuperSOT-3 SuperSOT-6 SuperSOT-8 SyncFET TinyLogic TruTranslation STAR*POWER is used under license FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component is any component of a life 1. Life support devices or systems are devices or support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Preliminary No Identification Needed Full Production Obsolete Not In Production Rev. H5 |
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