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8 Mbit (x8) Multi-Purpose Flash
SST39VF088
SST39VF0882.7V 8Mb (x8) MPF memory
Preliminary Specifications
FEATURES:
* Organized as 1M x8 * Single Voltage Read and Write Operations - 2.7-3.6V * Superior Reliability - Endurance: 100,000 Cycles (typical) - Greater than 100 years Data Retention * Low Power Consumption (typical values at 5 MHz) - Active Current: 12 mA (typical) - Standby Current: 4 A (typical) * Sector-Erase Capability - Uniform 4 KByte sectors * Block-Erase Capability - Uniform 64 KByte blocks * Fast Read Access Time: - 70 and 90 ns * Latched Address and Data * Fast Erase and Byte-Program - Sector-Erase Time: 18 ms (typical) - Block-Erase Time: 18 ms (typical) - Chip-Erase Time: 70 ms (typical) - Byte-Program Time: 14 s (typical) - Chip Rewrite Time: 15 seconds (typical) * Automatic Write Timing - Internal VPP Generation * End-of-Write Detection - Toggle Bit - Data# Polling * CMOS I/O Compatibility * JEDEC Standard - Flash EEPROM Pinouts and command sets * Packages Available - 48-lead TSOP (12mm x 20mm)
PRODUCT DESCRIPTION
The SST39VF088 device is a 1M x8 CMOS Multi-Purpose Flash (MPF) manufactured with SST's proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39VF088 writes (Program or Erase) with a 2.7-3.6V power supply. It conforms to JEDEC standard pinouts for x8 memories. Featuring high performance Byte-Program, the SST39VF088 device provides a typical Byte-Program time of 14 sec. The devices use Toggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inadvertent write, they have on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with a guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 100 years. The SST39VF088 device is suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, they significantly improve performance and reliability, while lowering power consumption. They inherently use less energy during Erase and Program than alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time of application. Since
(c)2003 Silicon Storage Technology, Inc. S71227-04-000 11/03 1 The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MPF is a trademark of Silicon Storage Technology, Inc. These specifications are subject to change without notice.
for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. They also improve flexibility while lowering the cost for program, data, and configuration storage applications. The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. To meet high density, surface mount requirements, the SST39VF088 is offered in 48-lead TSOP packaging. See Figure 1 for pin assignments.
8 Mbit Multi-Purpose Flash SST39VF088
Preliminary Specifications
Device Operation
Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocessor write sequences. A command is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first.
Read
The Read operation of the SST39VF088 is controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 2).
sequence with Block-Erase command (30H) and block address (BA) in the last bus cycle. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or 50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-ofErase operation can be determined using either Data# Polling or Toggle Bit methods. See Figures 8 and 9 for timing waveforms. Any commands issued during the Sectoror Block-Erase operation are ignored.
Chip-Erase Operation
The SST39VF088 provides a Chip-Erase operation, which allows the user to erase the entire memory array to the "1" state. This is useful when the entire device must be quickly erased. The Chip-Erase operation is initiated by executing a sixbyte command sequence with Chip-Erase command (10H) at address AAAH in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 4 for the command sequence, Figure 7 for timing diagram, and Figure 16 for the flowchart. Any commands issued during the Chip-Erase operation are ignored.
Byte-Program Operation
The SST39VF088 is programmed on a byte-by-byte basis. Before programming, the sector where the byte exists must be fully erased. The Program operation is accomplished in three steps. The first step is the three-byte load sequence for Software Data Protection. The second step is to load byte address and byte data. During the Byte-Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed within 20 s. See Figures 3 and 4 for WE# and CE# controlled Program operation timing diagrams and Figure 13 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands issued during the internal Program operation are ignored.
Write Operation Status Detection
The SST39VF088 provides two software means to detect the completion of a write (Program or Erase) cycle, in order to optimize the system Write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid.
Sector/Block-Erase Operation
The Sector- (or Block-) Erase operation allows the system to erase the device on a sector-by-sector (or block-byblock) basis. The SST39VF088 offers both Sector-Erase and Block-Erase mode. The sector architecture is based on uniform sector size of 4 KByte. The Block-Erase mode is based on uniform block size of 64 KByte. The SectorErase operation is initiated by executing a six-byte command sequence with Sector-Erase command (50H) and sector address (SA) in the last bus cycle. The Block-Erase operation is initiated by executing a six-byte command
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8 Mbit Multi-Purpose Flash SST39VF088
Preliminary Specifications
Data# Polling (DQ7)
When the SST39VF088 is in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. Note that even though DQ7 may have valid data immediately following the completion of an internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 s. During internal Erase operation, any attempt to read DQ7 will produce a `0'. Once the internal Erase operation is completed, DQ7 will produce a `1'. The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 5 for Data# Polling timing diagram and Figure 14 for a flowchart.
Data Protection
The SST39VF088 provides both hardware and software features to protect nonvolatile data from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a Write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V. Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down.
Software Data Protection (SDP)
The SST39VF088 provides the JEDEC approved Software Data Protection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of the three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte sequence. The SST39VF088 device is shipped with the Software Data Protection permanently enabled. See Table 4 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to Read mode within TRC.
Toggle Bit (DQ6)
During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating 1s and 0s, i.e., toggling between 1 and 0. When the internal Program or Erase operation is completed, the DQ6 bit will stop toggling. The device is then ready for the next operation. The Toggle Bit is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block-, or Chip-Erase, the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 6 for Toggle Bit timing diagram and Figure 14 for a flowchart.
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8 Mbit Multi-Purpose Flash SST39VF088
Preliminary Specifications
Product Identification
The Product Identification mode identifies the device as the SST39VF088 and manufacturer as SST. This mode may be accessed by software operations. Users may use the Software Product Identification operation to identify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, see Table 4 for software operation, Figure 10 for the Software ID Entry and Read timing diagram and Figure 15 for the Software ID Entry command sequence flowchart. TABLE 1: PRODUCT IDENTIFICATION
Address Manufacturer's ID Device ID SST39VF088 0001H D8H
T1.0 1227
Product Identification Mode Exit
In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to the Read operation. This command may also be used to reset the device to the Read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. Please note that the Software ID Exit command is ignored during an internal Program or Erase operation. See Table 4 for software command codes and Figure 15 for a flowchart.
Data BFH
0000H
FUNCTIONAL BLOCK DIAGRAM
X-Decoder
SuperFlash Memory
Memory Address
Address Buffer & Latches Y-Decoder
CE# OE# WE# DQ7 - DQ0
1227 B1.0
Control Logic
I/O Buffers and Data Latches
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8 Mbit Multi-Purpose Flash SST39VF088
Preliminary Specifications
A16 A15 A14 A13 A12 A11 A10 A9 NC NC WE# NC NC NC NC A19 A18 A8 A7 A6 A5 A4 A3 A2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Standard Pinout Top View Die Up
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
A17 NC VSS A0 DQ7 NC DQ6 NC DQ5 NC DQ4 VDD NC DQ3 NC DQ2 NC DQ1 NC DQ0 OE# VSS CE# A1
1227 48-tsop P01.0
FIGURE 1: PIN ASSIGNMENTS FOR 48-LEAD TSOP TABLE 2: PIN DESCRIPTION
Symbol AMS1-A0 DQ7-DQ0 Pin Name Address Inputs Data Input/output Functions To provide memory addresses. During Sector-Erase AMS-A12 address lines will select the sector. During Block-Erase AMS-A16 address lines will select the block. To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is high. To activate the device when CE# is low. To gate the data output buffers. To control the Write operations. To provide power supply voltage: Unconnected pins.
T2.0 1227
CE# OE# WE# VDD VSS NC
Chip Enable Output Enable Write Enable Power Supply Ground No Connection
2.7-3.6V for SST39VF088
1. AMS = Most significant address AMS = A19 for SST39VF088
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8 Mbit Multi-Purpose Flash SST39VF088
Preliminary Specifications TABLE 3: OPERATION MODES SELECTION
Mode Read Program Erase Standby Write Inhibit Product Identification Software Mode VIL VIL VIH See Table 4
T3.0 1227
CE# VIL VIL VIL VIH X X
OE# VIL VIH VIH X VIL X
WE# VIH VIL VIL X X VIH
DQ DOUT DIN X1 High Z High Z/ DOUT High Z/ DOUT
Address AIN AIN Sector or Block address, XXH for Chip-Erase X X X
1. X can be VIL or VIH, but no other value.
TABLE 4: SOFTWARE COMMAND SEQUENCE
Command Sequence Byte-Program Block-Erase Sector-Erase Chip-Erase Software ID Entry4,5 Software ID Exit6 1st Bus Write Cycle Addr1 AAAH AAAH AAAH AAAH AAAH XXH Data AAH AAH AAH AAH AAH F0H
T4.1 1227
2nd Bus Write Cycle Addr1 555H 555H 555H 555H 555H Data 55H 55H 55H 55H 55H
3rd Bus Write Cycle Addr1 AAAH AAAH AAAH AAAH AAAH Data A0H 80H 80H 80H 90H
4th Bus Write Cycle Addr1 WA2 AAAH AAAH AAAH Data Data AAH AAH AAH
5th Bus Write Cycle Addr1 555H 555H 555H Data 55H 55H 55H
6th Bus Write Cycle Addr1 BAX3 SAX3 AAAH Data 30H 50H 10H
1. Address format A14-A0 (Hex), Addresses A19-A15 can be VIL or VIH, but no other value, for the Command sequence. 2. WA = Program Byte address 3. SAX for Sector-Erase; uses AMS-A12 address lines BAX for Block-Erase; uses AMS-A16 address lines AMS = Most significant address AMS = A19 for SST39VF088 4. The device does not remain in Software Product ID mode if powered down. 5. With AMS-A1 = 0; SST Manufacturer's ID = BFH, is read with A0 = 0 SST39VF088 Device ID = D8H, is read with A0 = 1 6. Both Software ID Exit operations are equivalent
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8 Mbit Multi-Purpose Flash SST39VF088
Preliminary Specifications Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V Package Power Dissipation Capability (Ta = 25C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240C Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Outputs shorted for no more than one second. No more than one output shorted at a time.
OPERATING RANGE
Range Commercial Industrial
FOR
SST39VF088
VDD 2.7-3.6V 2.7-3.6V 0C to +70C
Ambient Temp -40C to +85C
OF
AC CONDITIONS
TEST
Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns Output Load . . . . . . . . . . . . . . . . . . . . CL = 100 pF See Figures 11 and 12
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8 Mbit Multi-Purpose Flash SST39VF088
Preliminary Specifications TABLE 5: DC OPERATING CHARACTERISTICS VDD = 2.7-3.6V1
Limits Symbol IDD Parameter Power Supply Current Read2 Program and Erase ISB ILI ILO VIL VILC VIH VIHC VOL VOH Standby VDD Current Input Leakage Current Output Leakage Current Input Low Voltage Input Low Voltage (CMOS) Input High Voltage Input High Voltage (CMOS) Output Low Voltage Output High Voltage VDD-0.2 0.7VDD VDD-0.3 0.2 15 30 20 1 10 0.8 0.3 mA mA A A A V V V V V V Min Max Units Test Conditions Address input=VILT/VIHT, at f=5 MHz, VDD=VDD Max CE#=VIL, OE#=WE#=VIH, all I/Os open CE#=WE#=VIL, OE#=VIH CE#=VIHC, VDD=VDD Max VIN=GND to VDD, VDD=VDD Max VOUT=GND to VDD, VDD=VDD Max VDD=VDD Min VDD=VDD Max VDD=VDD Max VDD=VDD Max IOL=100 A, VDD=VDD Min IOH=-100 A, VDD=VDD Min
T5.1 1227
1. Typical conditions for the Active Current shown on the front page of the data sheet are average values at 25C (room temperature), and VDD = 3V. Not 100% tested. 2. The IDD current listed is typically less than 2mA/MHz, with OE# at VIH. Typical VDD is 3V.
TABLE 6: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol TPU-READ1 TPU-WRITE
1
Parameter Power-up to Read Operation Power-up to Program/Erase Operation
Minimum 100 100
Units s s
T6.0 1227
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 7: CAPACITANCE
Parameter CI/O
1
(Ta = 25C, f=1 Mhz, other pins open)
Description I/O Pin Capacitance Input Capacitance
Test Condition VI/O = 0V VIN = 0V
Maximum 12 pF 6 pF
T7.0 1227
CIN1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 8: RELIABILITY CHARACTERISTICS
Symbol NEND1,2 TDR1 ILTH1 Parameter Endurance Data Retention Latch Up Minimum Specification 10,000 100 100 + IDD Units Cycles Years mA Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard 78
T8.0 1227
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 2. NEND endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would result in a higher minimum specification.
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8 Mbit Multi-Purpose Flash SST39VF088
Preliminary Specifications
AC CHARACTERISTICS
TABLE 9: READ CYCLE TIMING PARAMETERS VDD = 2.7-3.6V
SST39VF088-70 Symbol TRC TCE TAA TOE TCLZ1 TOLZ1 TCHZ TOH
1 1
SST39VF088-90 Min 90 Max 90 90 45 0 0 Units ns ns ns ns ns ns 30 30 0 ns ns ns
T9.0 1227
Parameter Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time CE# Low to Active Output OE# Low to Active Output CE# High to High-Z Output OE# High to High-Z Output Output Hold from Address Change
Min 70
Max 70 70 35
0 0 20 20 0
TOHZ1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 10: PROGRAM/ERASE CYCLE TIMING PARAMETERS
Symbol TBP TAS TAH TCS TCH TOES TOEH TCP TWP TWPH1 TCPH TDS TDH TSE TBE TSCE
1 1
Parameter Byte-Program Time Address Setup Time Address Hold Time WE# and CE# Setup Time WE# and CE# Hold Time OE# High Setup Time OE# High Hold Time CE# Pulse Width WE# Pulse Width WE# Pulse Width High CE# Pulse Width High Data Setup Time Data Hold Time Software ID Access and Exit Time Sector-Erase Block-Erase Chip-Erase
Min 0 30 0 0 0 10 40 40 30 30 30 0
Max 20
Units s ns ns ns ns ns ns ns ns ns ns ns ns
TIDA1
150 25 25 100
ns ms ms ms
T10.0 1227
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
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8 Mbit Multi-Purpose Flash SST39VF088
Preliminary Specifications
TRC ADDRESS AMS-0
TAA
CE#
TCE
OE# VIH WE# TOLZ
TOE
TOHZ TCHZ HIGH-Z DATA VALID
DQ7-0
HIGH-Z
TCLZ
TOH DATA VALID
Note: AMS = Most significant address AMS = A19 for SST39VF088
1227 F02.1
FIGURE 2: READ CYCLE TIMING DIAGRAM
INTERNAL PROGRAM OPERATION STARTS TBP ADDRESS AMS-0 AAA TAH TWP WE# TAS OE# TCH CE# TCS DQ7-0 AA SW0 55 SW1 A0 SW2 DATA BYTE (ADDR/DATA) TWPH TDS 555 AAA ADDR TDH
1227 F03.2
Note: AMS = Most significant address AMS = A19 for SST39VF088
FIGURE 3: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
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8 Mbit Multi-Purpose Flash SST39VF088
Preliminary Specifications
INTERNAL PROGRAM OPERATION STARTS TBP ADDRESS AMS-0 AAA TAH TCP CE# TAS OE# TCH WE# TCS DQ7-0 AA SW0 55 SW1 A0 SW2 DATA BYTE (ADDR/DATA) TCPH TDS 555 AAA ADDR TDH
1227 F04.2
Note: AMS = Most significant address AMS = A19 for SST39VF088
FIGURE 4: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
ADDRESS AMS-0 TCE CE# TOEH OE# TOE WE# TOES
DQ7
DATA
DATA#
DATA#
DATA
1227 F05.1
Note: AMS = Most significant address AMS = A19 for SST39VF088
FIGURE 5: DATA# POLLING TIMING DIAGRAM
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8 Mbit Multi-Purpose Flash SST39VF088
Preliminary Specifications
ADDRESS AMS-0 TCE CE# TOEH OE# TOE TOES
WE#
DQ6
TWO READ CYCLES WITH SAME OUTPUTS
1227 F06.1
Note: AMS = Most significant address AMS = A19 for SST39VF088
FIGURE 6: TOGGLE BIT TIMING DIAGRAM
Six-byte Code for Chip-Erase ADDRESS AMS-0 AAA 555 AAA AAA 555 AAA
TSCE
CE#
OE# TWP WE#
DQ7-0
AA SW0
55 SW1
80 SW2
AA SW3
55 SW4
10 SW5
1227 F07.2
Note: The device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are interchangeable as long as minimum timings are met. (See Table 10) AMS = Most significant address AMS = A19 for SST39VF088
FIGURE 7: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM
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8 Mbit Multi-Purpose Flash SST39VF088
Preliminary Specifications
Six-Byte Code for Block-Erase ADDRESS AMS-0 AAA 555 AAA AAA 555 BAX
TBE
CE#
OE# TWP WE#
DQ7-0
AA SW0
55 SW1
80 SW2
AA SW3
55 SW4
30 SW5
Note: The device also supports CE# controlled Block-Erase operation. The WE# and CE# signals are interchangeable as long as minimum timings are met. (See Table 10) AMS = Most significant address AMS = A19 for SST39VF088
1227 F08.2
FIGURE 8: WE# CONTROLLED BLOCK-ERASE TIMING DIAGRAM
Six-byte Code for Sector-Erase ADDRESS AMS-0 AAA 555 AAA AAA 555 SAX
TSE
CE#
OE# TWP WE#
DQ7-0
AA SW0
55 SW1
80 SW2
AA SW3
55 SW4
50 SW5
1227 F09.2
Note: The device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are interchangeable as long as minimum timings are met. (See Table 10) AMS = Most significant address AMS = A19 for SST39VF088
FIGURE 9: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM
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8 Mbit Multi-Purpose Flash SST39VF088
Preliminary Specifications
THREE-BYTE SEQUENCE FOR SOFTWARE ID ENTRY ADDRESS A14-0 AAA 555 AAA 0000 0001
CE#
OE# TWP WE# TWPH DQ7-0 AA SW0 55 SW1 90 SW2
1227 F10.1
TIDA
TAA BF Device ID
Note: Device ID = D8H for SST39VF088
FIGURE 10: SOFTWARE ID ENTRY
AND
READ
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8 Mbit Multi-Purpose Flash SST39VF088
Preliminary Specifications
VIHT
INPUT
VIT
REFERENCE POINTS
VOT
OUTPUT
VILT
1227 F12.0
AC test inputs are driven at VIHT (0.9 VDD) for a logic "1" and VILT (0.1 VDD) for a logic "0". Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% 90%) are <5 ns.
Note: VIT - VINPUT Test VOT - VOUTPUT Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test
FIGURE 11: AC INPUT/OUTPUT REFERENCE WAVEFORMS
TO TESTER
TO DUT CL
1227 F13.0
FIGURE 12: A TEST LOAD EXAMPLE
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8 Mbit Multi-Purpose Flash SST39VF088
Preliminary Specifications
Start
Load data: AAH Address: AAAH
Load data: 55H Address: 555H
Load data: A0H Address: AAAH
Load Byte Address/Byte Data
Wait for end of Program (TBP, Data# Polling bit, or Toggle bit operation) Program Completed
1227 F14.0
FIGURE 13: BYTE-PROGRAM ALGORITHM
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8 Mbit Multi-Purpose Flash SST39VF088
Preliminary Specifications
Internal Timer Program/Erase Initiated
Toggle Bit Program/Erase Initiated
Data# Polling Program/Erase Initiated
Wait TBP, TSCE, TSE or TBE
Read byte
Read DQ7
Program/Erase Completed
Read same byte
No
Is DQ7 = true data? Yes
No
Does DQ6 match? Yes Program/Erase Completed
Program/Erase Completed
1227 F15.0
FIGURE 14: WAIT OPTIONS
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17
8 Mbit Multi-Purpose Flash SST39VF088
Preliminary Specifications
Software Product ID Entry Command Sequence
Software ID Exit Command Sequence
Load data: AAH Address: AAAH
Load data: F0H Address: XXH
Load data: 55H Address: 555H
Wait TIDA
Load data: 90H Address: AAAH
Return to normal operation
Wait TIDA
1227 F16.1
Read Software ID
FIGURE 15: SOFTWARE ID COMMAND FLOWCHARTS
(c)2003 Silicon Storage Technology, Inc.
S71227-04-000
11/03
18
8 Mbit Multi-Purpose Flash SST39VF088
Preliminary Specifications
Chip-Erase Command Sequence Load data: AAH Address: AAAH
Sector-Erase Command Sequence Load data: AAH Address: AAAH
Block-Erase Command Sequence Load data: AAH Address: AAAH
Load data: 55H Address: 555H
Load data: 55H Address: 555H
Load data: 55H Address: 555H
Load data: 80H Address: AAAH
Load data: 80H Address: AAAH
Load data: 80H Address: AAAH
Load data: AAH Address: AAAH
Load data: AAH Address: AAAH
Load data: AAH Address: AAAH
Load data: 55H Address: 555H
Load data: 55H Address: 555H
Load data: 55H Address: 555H
Load data: 10H Address: AAAH
Load data: 50H Address: SAX
Load data: 30H Address: BAX
Wait TSCE
Wait TSE
Wait TBE
Chip erased to FFH
Sector erased to FFH
Block erased to FFH
1227 F17.0
FIGURE 16: ERASE COMMAND SEQUENCE
(c)2003 Silicon Storage Technology, Inc.
S71227-04-000
11/03
19
8 Mbit Multi-Purpose Flash SST39VF088
Preliminary Specifications
PRODUCT ORDERING INFORMATION
SST 39 XX VF 088 XX XXXX - 70 - XXX 4C XX EK - XXX E X Environmental Attribute E = non-Pb Package Modifier K = 48 leads Package Type E = TSOP (type 1, die up, 12mm x 20mm) Temperature Range C = Commercial = 0C to +70C I = Industrial = -40C to +85C Minimum Endurance 4 = 10,000 cycles Read Access Speed 70 = 70 ns 90 = 90 ns Device Density 088 = 8 Mbit Voltage V = 2.7-3.6V Product Series 39 = Multi-Purpose Flash
Valid combinations for SST39VF088 SST39VF088-70-4C-EK SST39VF088-70-4C-EKE SST39VF088-90-4C-EK SST39VF088-90-4C-EKE SST39VF088-70-4I-EK SST39VF088-70-4I-EKE SST39VF088-90-4I-EK SST39VF088-90-4I-EKE
Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations.
(c)2003 Silicon Storage Technology, Inc.
S71227-04-000
11/03
20
8 Mbit Multi-Purpose Flash SST39VF088
Preliminary Specifications
PACKAGING DIAGRAMS
1.05 0.95 Pin # 1 Identifier 0.50 BSC
12.20 11.80
0.27 0.17
18.50 18.30
0.15 0.05
DETAIL 1.20 max. 0.70 0.50 20.20 19.80 0- 5 Note: 1. Complies with JEDEC publication 95 MO-142 DD dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (max/min). 3. Coplanarity: 0.1 mm 4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads. 0.70 0.50
1mm 48-tsop-EK-8
48-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 12MM SST PACKAGE CODE: EK
X
20MM
TABLE 11: REVISION HISTORY
Number 00 01 02 03 04 Description Date Mar 2003 Apr 2003 Jun 2003 Aug 2003 Nov 2003
* * * * *
Initial Release Corrected Byte-Program 3rd Cycle Data from 20H to A0H in Table 4 on page 6 Corrected Byte-Program 3rd Cycle Data from 20H to A0H in Figures 3 and 4 Auto Low Power feature references removed. (CE# toggled high achieves same effect.) 2004 Data Book
(c)2003 Silicon Storage Technology, Inc.
S71227-04-000
11/03
21
8 Mbit Multi-Purpose Flash SST39VF088
Preliminary Specifications
Silicon Storage Technology, Inc. * 1171 Sonora Court * Sunnyvale, CA 94086 * Telephone 408-735-9110 * Fax 408-735-9036 www.SuperFlash.com or www.sst.com
(c)2003 Silicon Storage Technology, Inc. S71227-04-000 11/03
22

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