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DG406/407
Vishay Siliconix
16-Ch/Dual 8-Ch High-Performance CMOS Analog Multiplexers
FEATURES
D D D D D D Low On-Resistance--rDS(on): 50 W Low Charge Injection--Q: 15 pC Fast Transition Time--tTRANS: 200 ns Low Power: 0.2 mW Single Supply Capability 44-V Supply Max Rating
BENEFITS
D D D D D D Higher Accuracy Reduced Glitching Improved Data Throughput Reduced Power Consumption Increased Ruggedness Wide Supply Ranges: "5 V to "20 V
APPLICATIONS
D D D D D D D Data Acquisition Systems Audio Signal Routing Medical Instrumentation ATE Systems Battery Powered Systems High-Rel Systems Single Supply Systems
DESCRIPTION
The DG406 is a 16-channel single-ended analog multiplexer designed to connect one of sixteen inputs to a common output as determined by a 4-bit binary address. The DG407 selects one of eight differential inputs to a common differential output. Break-before-make switching action protects against momentary shorting of inputs. An on channel conducts current equally well in both directions. In the off state each channel blocks voltages up to the power supply rails. An enable (EN) function allows the user to reset the multiplexer/demultiplexer to all switches off for stacking several devices. All control inputs, address (Ax) and enable (EN) are TTL compatible over the full specified operating temperature range. Applications for the DG406/407 include high speed data acquisition, audio signal switching and routing, ATE systems, and avionics. High performance and low power dissipation make them ideal for battery operated and remote instrumentation applications. For additional application information order Faxback document numbers 70601 and 70604. Designed in the 44-V silicon-gate CMOS process, the absolute maximum voltage rating is extended to 44 volts, allowing operation with "20-V supplies. Additionally single (12-V) supply operation is allowed. An epitaxial layer prevents latchup. For applications information please request FaxBack documents 70601 and 70604.
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
DG406
V+ NC NC S16 S15 S14 S13 S12 S11 S10 S9 GND NC A3
Dual-In-Line and SOIC Wide-Body 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Top View Decoders/Drivers 28 27 26 25 24 23 22 21 20 19 18 17 16 15 D V- S8 S7 S6 S5 S4 S3 S2 S1 EN A0 A1 A2
DG407
V+ Db NC S8b S7b S6b S5b S4b S3b S2b S1b GND NC NC 1 2 3 4 5 6 7 8 9
Dual-In-Line and SOIC Wide-Body 28 27 26 25 24 23 22 21 20 19 18 Decoders/Drivers 17 16 15 Top View Da V- S8a S7a S6a S5a S4a S3a S2a S1a EN A0 A1 A2
10 11 12 13 14
Document Number: 70061 S-00399--Rev. H, 13-Sep-99
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DG406/407
Vishay Siliconix
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
DG406
S 16 NC PLCC and LCC NC S8 V+ V- D
DG407
S 8b
PLCC and LCC S 8a Db Da NC V+ V-
4
3
2
1
28 27 26
4
3
2
1
28 27 26
S15 S14 S13 S12 S11 S10 S9
5 6 7 8 9 10 11 Decoders/Drivers 12 13 14 15 16 17 18 GND A3 A2 A1 A0 NC EN
25 24 23 22 21 20 19
S7 S6 S5 S4 S3 S2 S1
S7b S6b S5b S4b S3b S2b S1b
5 6 7 8 9 10 11 Decoders/Drivers 12 13 14 15 16 17 18 GND A2 A1 A0 NC NC EN
25 24 23 22 21 20 19
S7a S6a S5a S4a S3a S2a S1a
Top View
Top View
TRUTH TABLE
A3
X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
DG406
EN
0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
TRUTH TABLE
A2
X 0 0 0 0 1 1 1 1
DG407
On Switch Pair
None 1 2 3 4 5 6 7 8 0 1 1 1 1 1 1 1 1
A2
X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
A1
X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
A0
X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
On Switch
None 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
A1
X 0 0 1 1 0 0 1 1
A0
X 0 1 0 1 0 1 0 1
EN
Logic "0" = Logic "1" = X = Don't Care
VAL v 0.8 V VAH w 2.4 V
ORDERING INFORMATION
Temp Range
-40 to 85_C
DG406
Part Number
DG406DJ DG406DN DG406DW DG406AK/883, 5962-9562301QXA DG406AZ/883, 5962-9562301Q3A
ORDERING INFORMATION
Temp Range
-40 to 85_C
DG407
Part Number
DG407DJ DG407DN DG407DW DG407AK/883' 5962-9562302QXA DG407AZ/883 5962-9562302Q3A
Package
28-Pin Plastic DIP 28-Pin PLCC 28-Pin Widebody SOIC 28-Pin CerDIP
Package
28-Pin Plastic DIP 28-Pin PLCC 28-Pin Widebody SOIC 28-Pin CerDIP
-55 to 125_C _ LCC-28
-55 to 125_C _ LCC-28
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Document Number: 70061 S-00399--Rev. H, 13-Sep-99
DG406/407
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS
Voltages Referenced to V- V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 V GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 V Digital Inputsa, VS, VD . . . . . . . . . . . . . . . . . . . . . . . . (V-) -2 V to (V+) +2 V or 20 mA, whichever occurs first Current (Any Terminal,) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA Peak Current, S or D (Pulsed at 1 ms, 10% Duty Cycle Max) . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Storage Temperature (AK, AZ Suffix) . . . . . . . . . . . . . . -65 to 150_C (DJ, DN Suffix) . . . . . . . . . . . . . . -65 to 125_C Power Dissipation (Package)b 28-Pin Plastic DIPc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625 mW 28-Pin CerDIPd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 W 28-Pin Plastic PLCCc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 mW LCC-28e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.35 W 28-Pin Widebody SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 mW Notes: a. Signals on SX, DX or INX exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings. b. All leads soldered or welded to PC board. c. Derate 6 mW/_C above 75_C d. Derate 12 mW/_C above 75_C e. Derate 13.5 mW/_C above 75_C
SPECIFICATIONSa
Test Conditions Unless Otherwise Specified Parameter Analog Switch
Analog Signal Rangee Drain-Source On-Resistance rDS(on) Matching Between Channelsg Source Off Leakage Current Drain Off Leakage Current VANALOG rDS(on) DrDS(on) IS(off) VEN = 0 V VD = "10 V VS = #10 V DG406 DG407 VS = VD = "10 V Sequence Each Switch On DG406 DG407 VD = "10 V, IS = -10 mA Sequence Each Switch On VD = "10 V Full Room Full Room Room Full Room Full Room Full Room Full Room Full 50 5 0.01 0.04 0.04 0.04 0.04 -0.5 -50 -1 -200 -1 -100 -1 -200 -1 -100 0.5 50 1 200 1 100 1 200 1 100 -0.5 -5 -1 -40 -1 -20 -1 -40 -1 -20 0.5 5 1 40 1 20 1 40 1 20 nA -15 15 100 125 -15 15 100 125 V W %
A Suffix
-55 to 125_C
D Suffix
-40 to 85_C
Symbol
V+ = 15 V, V- = -15 V VAL = 0.8 V, VAH = 2.4 Vf
Tempb
Typc
Mind
Maxd
Mind
Maxd
Unit
ID(off)
Drain On Leakage Current
ID(on)
Digital Control
Logic High Input Voltage Logic Low Input Voltage Logic High Input Current Logic Low Input Current Logic Input Capacitance VINH VINL IAH IAL Cin VA = 2.4 V, 15 V VEN = 0 V, 2.4 V, VA = 0 V f = 1 MHz Full Full Full Full Room 7 -1 -1 2.4 0.8 1 1 -1 -1 2.4 0.8 1 1 V mA m pF
Dynamic Characteristics
Transition Time Break-Before-Make Interval Enable Turn-On Time Enable Turn-Off Time Charge Injection Off Isolationh Source Off Capacitance Drain Off Capacitance tTRANS tOPEN tON(EN) See Figure 3 tOFF(EN) Q OIRR CS(off) CD(off) VEN = 0 V, VD = 0 V f = 1 MHz Drain On Capacitance CD(on) CL = 1 nF, VS = 0 V, Rs = 0 W VEN = 0 V, RL = 1 kW f = 100 kHz VEN = 0 V, VS = 0 V, f = 1 MHz DG407 DG406 DG407 See Figure 2 See Figure 4 Room Full Room Full Room Full Room Full Room Room Room Room Room Room Room 200 50 150 70 15 -69 8 130 65 140 70 pF 25 10 200 400 150 300 350 450 25 10 200 400 150 300 pC dB ns 350 450
Document Number: 70061 S-00399--Rev. H, 13-Sep-99
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DG406/407
Vishay Siliconix
SPECIFICATIONSa
Test Conditions Unless Otherwise Specified Parameter Power Supplies
Positive Supply Current Negative Supply Current Positive Supply Current Negative Supply Current I+ VEN = VA = 0 or 5 V I- I+ VEN = 2.4 V, VA = 0 V I- Room Full Room Full Room Full Room Full 13 -0.01 50 -0.01 -20 -20 -1 -10 500 900 -20 -20 30 75 -1 -10 500 700 30 75
A Suffix
-55 to 125_C
D Suffix
-40 to 85_C
Symbol
V+ = 15 V, V- = -15 V VAL = 0.8 V, VAH = 2.4 Vf
Tempb
Typc
Mind
Maxd
Mind
Maxd
Unit
mA m
SPECIFICATIONSa FOR SINGLE SUPPLY
Test Conditions Unless Otherwise Specified Parameter Analog Switch
Analog Signal Rangee Drain-Source On-Resistance rDS(on) Matching Between Channelsg Source Off Leakage Current Drain Off Leakage Current Drain On Leakage Current VANALOG rDS(on) DrDS(on) IS(off) ID(off) ID(on) VD = 3 V, 10 V, IS = - 1 mA Sequence Each Switch On Full Room Room Room DG406 DG407 VS = VD = "10 V Sequence Each Switch On DG406 DG407 Room Room Room Room 90 5 0.01 0.04 0.04 0.04 0.04 nA 0 12 120 0 12 120 V W %
A Suffix
-55 to 125_C
D Suffix
-40 to 85_C
Symbol
V+ = 12 V, V- = 0 V VAL = 0.8 V, VAH = 2.4 Vf
Tempb
Typc
Mind Maxd
Mind
Maxd
Unit
VEN = 0 V VD = 10 V or 0.5 V VS = 0.5 V or 10 V
Dynamic Characteristics
Switching Time of Multiplexer Enable Turn-On Time Enable Turn-Off Time Charge Injection tTRANS tON(EN) tOFF(EN) Q VS1 = 8 V, VS8 = 0 V, VIN = 2.4 V VINH = 2.4 V, VINL = 0 V VS1 = 5 V CL = 1 nF, VS= 6 V, RS = 0 Room Room Room Room 300 250 150 20 450 600 300 450 600 300 pC ns
Power Supplies
Positive Supply Current Negative Supply Current I+ VEN = 0 V or 5 V, VA = 0 V or 5 V I- Room Full Room Full 13 -0.01 -20 -20 30 75 -20 -20 30 75 mA m
Notes: a. Refer to PROCESS OPTION FLOWCHART. b. Room = 25_C, Full = as determined by the operating temperature suffix. c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. e. Guaranteed by design, not subject to production test. f. VIN = input voltage to perform proper function. g. DrDS(on) = rDS(on) MAX - rDS(on) MIN. h. Worst case isolation occurs on Channel 4 due to proximity to the drain pin.
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Document Number: 70061 S-00399--Rev. H, 13-Sep-99
DG406/407
Vishay Siliconix
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
rDS(on) vs. VD and Supply
160 80 70 r DS(on)- On-Resistance ( W ) r DS(on)- On-Resistance ( W ) 120 60 50 40 30 20 10 0 -20 -12 -4 4 VD - Drain Voltage (V) 12 20 0 -15 125_C 85_C 25_C 0_C -40_C -55_C V+ = 15 V V- = -15 V -10 -5 0 5 VD - Drain Voltage (V) 10 15
rDS(on) vs. VD and Temperature
"5 V
80 "8 V "10 V "12 V "15 V "20 V
40
rDS(on) vs. VD and Supply
120 240 r DS(on)- On-Resistance ( W ) V+ = 7.5 V 200 I D, I S - Current (pA) 40 160 10 V 120 80 40 0 0 4 8 12 VD - Drain Voltage (V) 16 20 12 V 15 V 20 V 22 V V- = 0 V 80
ID , IS Leakage Currents vs. Analog Voltage
V+ = 15 V V- = -15 V VS = -VD for ID(off) VD = VS(open) for ID(on)
IS(off) 0
-40
DG406 ID(on), ID(off) DG407 ID(on), ID(off)
-80
-120 -15
-10
-5 0 5 10 VS , VD - Source Drain Voltage (V)
15
ID , IS Leakages vs. Temperature
100 nA 10 nA V+ = 15 V V- = -15 V VD = "14 V 350 300 250 1 nA I D, I S - Current Time (ns) ID(on), ID(off) 200
Switching Times vs. Bipolar Supplies
tTRANS
100 pA IS(off)
tON(EN) 150 100 tOFF(EN)
10 pA
1 pA 0.1 pA -55 -35 -15 5 25 45 65 85 105 125 Temperature (_C)
50 0 "5 "10 "15 "20 VSUPPLY - Supply Voltage (V)
Document Number: 70061 S-00399--Rev. H, 13-Sep-99
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DG406/407
Vishay Siliconix
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
Switching Times vs. Single Supply
700 V- = 0 V 600 500 Time (ns) 400 300 tON(EN) 200 100 0 5 10 15 20 V+ - Supply Voltage (V) 20 10 0 -15 V+ = 15 V, V- = -15 V tTRANS 60 50 40 30 70
Charge Injection vs. Analog Voltage
Q (pC)
V+ = 12 V, V- = 0 V
tOFF(EN)
-10
-5
0
5
10
15
VS - Source Voltage (V)
Off-Isolation vs. Frequency
-140 -120 6 -100 I - Current (mA) ISOL (dB) -80 -60 -40 -20 -8 0 100 1k 10 k 100 k 1M 10 M -10 10 4 2 0 -2 -4 -6 10 8
Supply Currents vs. Switching Frequency
EN = 5 V AX = 0 or 5 V I+
IGND I-
100
1k
10 k
100 k
1M
10 M
f - Frequency (Hz)
f - Frequency (Hz)
tON/tOFF vs. Temperature
300 V+ = 15 V V- = -15 V 3
Switching Threshold vs. Supply Voltage
260
220 Time (ns) V TH (V) tTRANS 180 tON(EN)
2
140
1
100 tOFF(EN) 60 -55 -35 -15 5 25 45 65 85 105 125 0 0
Temperature (_C)
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CCCCCCCCCC CCCCCCCCCC CCCCCCCCCC CCCCCCCCCC CCCCCCCCCC CCCCCCCCCC
5 10 15 20 VSUPPLY - Supply Voltage (V) Document Number: 70061 S-00399--Rev. H, 13-Sep-99
DG406/407
Vishay Siliconix
SCHEMATIC DIAGRAM (TYPICAL CHANNEL)
V+ GND VREF D A0 V+ AX Level Shift Decode/ Drive V-
S1 V+ EN Sn V-
FIGURE 1.
TEST CIRCUITS
+15 V +2.4 V EN A3 A2 A1 A0 GND 50 W -15 V Switch Output +15 V +2.4 V V+ VO "10 V 0V 90% VS8 tTRANS S1 ON VO 35 pF S8 ON tTRANS V- 300 W 35 pF VS1 90% V+ S1 S2 - S15 "10 V tr <20 ns tf <20 ns 50% 0V
DG406
S16 D
#10 V VO
Logic Input
3V
EN A2 A1 A0 GND 50 W
S1b
*
DG407
S8b Db V- 300 W -15 V #10 V
* = S1a - S8a, S2b - S7b, Da
FIGURE 2. Transition Time
Document Number: 70061 S-00399--Rev. H, 13-Sep-99
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DG406/407
Vishay Siliconix
TEST CIRCUITS
+15 V V+ A3 A2 A1 A0 EN GND 50 W -15 V V- 300 W 35 pF S1 S2 - S16 -5 V
DG406
D VO Logic Input 3V 50% 0V tON(EN) +15 V V+ S1b S1a - S8a S2b - S8b -5 V Switch Output VO VO 90% 90% 0V tOFF(EN)
tr <20 ns tf <20 ns
A2 A1 A0
DG407
EN GND 50 W -15 V Da and Db V- 300 W 35 pF VO
FIGURE 3. Enable Switching Time
+15 V Logic Input +5 V 3V 50% 0V tr <20 ns tf <20 ns
V+ +2.4 V EN A3 A2 A1 A0 GND 50 W All S and Da
DG406 DG407
D,Db V- 300 W -15 V 35 pF VO Switch Output VO 0V tOPEN VS 80%
FIGURE 4. Break-Before-Make Interval
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Document Number: 70061 S-00399--Rev. H, 13-Sep-99
DG406/407
Vishay Siliconix
APPLICATION HINTS
Sampling speed is limited by two consecutive events: the transition time of the multiplexer, and the settling time of the sampled signal at the output. tTRANS is given on the data sheet. Settling time at the load depends on several parameters: rDS(on) of the multiplexer, source impedance, multiplexer and load capacitances, charge injection of the multiplexer and accuracy desired. The settling time for the multiplexer alone can be derived from the model shown in Figure 5. Assuming a low impedance signal source like that presented by an op amp or a buffer amplifier, the settling time of the RC network for a given accuracy is equal to nt: For the DG406 then, at room temp and for 12-bit accuracy, using the maximum limits:
fs + 1 16 (9 x 100 W x 10 -12F) ) 300 x 10 -12 s (2)
or
fs = 694 kHz (3)
% ACCURACY
0.25 0.012 0.0017
# BITS
8 12 15
N
6 9 11
From the sampling theorem, to properly recover the original signal, the sampling frequency should be more than twice the maximum component frequency of the original signal. This assumes perfect bandlimiting. In a real application sampling at three to four times the filter cutoff frequency is a good practice. Therefore from equation 2 above:
fc = 1 4 x fs = 173 kHz (4)
rDS(on) VOUT RS = 0 CD(on)
From this we can see that the DG406 can be used to sample 16 different signals whose maximum component frequency can be as high as 173 kHz. If for example, two channels are used to double sample the same incoming signal then its cutoff frequency can be doubled. The block diagram shown in Figure 6 illustrates a typical data acquisition front end suitable for low-level analog signals. Differential multiplexing of small signals is preferred since this method helps to reject any common mode noise. This is especially important when the sensors are located at a distance and it may eliminate the need for individual amplifiers. A low rDS(on), low leakage multiplexer like the DG407 helps to reduce measurement errors. The low power dissipation of the DG407 minimizes on-chip thermal gradients which can cause errors due to temperature mismatch along the parasitic thermocouple paths. Please refer to Application Note AN203 for additional information.
FIGURE 5. Simplified Model of One Multiplexer Channel
The maximum sampling frequency of the multiplexer is:
1 fs = (1) N (tSETTLING + tTRANS)
where N = number of channels to scan tSETTLING = nt = n x rDS(on) x CD(on)
To Sensor 1 Analog Multiplexer
Inst Amp
S/H 12-Bit A/D Converter
To Sensor 8
DG407
Controller
FIGURE 6. Measuring low-level analog signals is more accurate when using a differential multiplexing technique.
Document Number: 70061 S-00399--Rev. H, 13-Sep-99 www.vishay.com
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