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74ACT299
8 BIT PIPO SHIFT REGISTER WITH ASYNCHRONOUS CLEAR
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HIGH SPEED: fMAX = 240MHz (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 8A(MAX.) at TA=25C COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN.), V IL = 0.8V (MAX.) 50 TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 4.5V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 299 IMPROVED LATCH-UP IMMUNITY
DIP
SOP
TSSOP
ORDER CODES
PACKAGE DIP SOP TSSOP TUBE 74ACT299B 74ACT299M T&R 74ACT299MTR 74ACT299TTR
DESCRIPTION The 74ACT299 is an advanced high-speed CMOS 8-BIT PIPO SHIFT REGISTER (3-STATE) fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. These devices have four modes (HOLD, SHIFT LEFT, SHIFT RIGHT and LOAD DATA). Each mode is chosen by two function select inputs (S0, S1) as shown in the Truth Table. When one or PIN CONNECTION AND IEC LOGIC SYMBOLS
both enable inputs, (G1, G2) are high, the eight input/output terminals are in the high-impedance state; however sequential operation or clearing of the register is not affected. Clear function is asynchronousto clock. The device is designed to interface directly High Speed CMOS systems with TTL, NMOS and CMOS output voltage levels. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.
April 2001
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74ACT299
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No 1, 19 2, 3 7, 13, 6, 14, 5, 15, 4, 16 8, 17 9 11 12 18 10 20 SYMBOL S0, S1 G1, G2 A/QA to H/QH QA' to QH' CLEAR SR CLOCK SL GND VCC NAME AND FUNCTION Mode Select Inputs 3-State Output Enable Inputs (Active LOW) Parallel Data Inputs or 3-State Parallel Outputs (Bus Driver) Serial Outputs (Standard Output) Asyncrhronous Master Reset Input (Active LOW) Serial Data Shift Right Input Clock Input (LOW to HIGH, Edge-triggered) Serial Data Shift Left Input Ground (0V) Positive Supply Voltage
TRUTH TABLE
INPUTS MODE CLEAR Z CLEAR HOLD SHIFT RIGHT SHIFT LEFT LOAD L L L H H H H H H FUNCTION SELECTED S1 H L X L L L H H H S0 H X L L H H L L H OUTPUT CONTROL G1* X L L L L L L L X G2* X L L L L L L L X X X X X INPUTS/OUTPUTS SERIAL CLOCK SL X X X X X X H L X SR X X X X H L X X X Z L L QA0 H L QBn QBn a Z L L QH0 QGn QGn H L h L L L QA0 H L QBn QBn a L L L QH0 QGn QGn H L h A/QA H/QH QA' QH' OUTPUTS
* : When one or both controls are high, the eight input/output terminals are the high impedance state: howewer sequential operation or cleanig of the register is not affected. Z : High Impedance Qn0 : The level of An before the indicated steady state input conditions were established. Qnn : The level of Qn before the most recent active transition indicated by OR a, h : The level of the steadystate inputs A, H, respectively. X : Don't Care
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74ACT299
LOGIC DIAGRAM
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74ACT299
TIMING CHART
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VI VO IIK IOK IO Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current Parameter Value -0.5 to +7 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 20 20 50 400 -65 to +150 300 Unit V V V mA mA mA mA C C
ICC or IGND DC VCC or Ground Current Tstg Storage Temperature TL Lead Temperature (10 sec)
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied.
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VI VO Top dt/dv Supply Voltage Input Voltage Output Voltage Operating Temperature Input Rise and Fall Time VCC = 4.5 to 5.5V (note 1) Parameter Value 4.5 to 5.5 0 to VCC 0 to VCC -55 to 125 8 Unit V V V C ns/V
1) VIN from 0.8V to 2.0V
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74ACT299
DC SPECIFICATIONS
Test Condition Symbol Parameter VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Low Level Output Voltage 4.5 5.5 4.5 5.5 II IOZ Input Leakage Current High Impedance Output Leakege Current Max ICC/Input Quiescent Supply Current Dynamic Output Current (note 1, 2) 5.5 5.5 5.5 5.5 5.5 VO = 0.1 V or VCC-0.1V VO = 0.1 V or VCC-0.1V IO=-50 A IO=-50 A IO=-24 mA IO=-24 mA IO=50 A IO=50 A IO=24 mA IO=24 mA VI = VCC or GND VI = VIH or VIL VO = VCC or GND VI = VCC - 2.1V VI = VCC or GND VOLD = 1.65 V max VOHD = 3.85 V min 0.6 8 4.4 5.4 3.86 4.86 0.001 0.001 0.1 0.1 0.36 0.36 0.1 0.5 TA = 25C Min. 2.0 2.0 Typ. 1.5 1.5 1.5 1.5 4.49 5.49 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44 1 5 1.5 80 75 -75 Max. Value -40 to 85C Min. 2.0 2.0 0.8 0.8 4.4 5.4 3.7 4.7 0.1 0.1 0.5 0.5 1 10 1.6 160 50 -50 A A mA A mA mA V Max. -55 to 125C Min. 2.0 2.0 0.8 0.8 V Max. V Unit
VIH VIL VOH
High Level Input Voltage Low Level Input Voltage High Level Output Voltage
ICCT ICC IOLD IOHD
1) Maximum test duration 2ms, one output loaded at time 2) Incident wave switching is guaranteed on trasmission lines with impedances as low as 50
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74ACT299
AC ELECTRICAL CHARACTERISTICS (C L = 50 pF, RL = 500 , Input tr = tf = 3ns)
Test Condition Symbol Parameter VCC (V) 5.0(*) TA = 25C Min. Typ. 6.5 Max. 10.5 Value -40 to 85C Min. 1.0 Max. 15.0 -55 to 125C Min. 1.0 Max. 16.0 ns Unit
tPLH tPHL tPLH tPHL tPHL
Propagation Delay Time CLOCK to Q'A' Q'H Propagation Delay Time CLOCK to QA - QH Propagation Delay Time CLEAR to Q'A' Q'H Propagation Delay Time CLEAR to QA - QH Output Enable Time Output Disable Time CLEAR Pulse Width, LOW CLOCK pulse Width Setup Time HIGH or LOW(S0 or S1 to CK) Hold Time HIGH or LOW (S0 or S1 to CK) Setup Time HIGH or LOW (SR or SL to CK) Hold Time HIGH or LOW (SR or SL to CK) Recovery Time CLR to CK Maximum Clock Frequency
5.0(*)
6.5
11.4
1.0
15.0
1.0
16.0
ns
5.0(*)
6.4
10.0
1.0
17.5
1.0
18.0
ns
tPHL
5.0(*)
6.6
10.5
1.0
17.5
1.0
18.0
ns
tPZL tPZH tPLZ tPHZ tW tW ts
5.0(*) 5.0(*) 5.0(*) 5.0(*) 5.0(*)
6.4 6.2
11.4 9.6 5.0 5.0 6.0
1.0 1.0
13.5 13.5 5.0 5.0 6.5
1.0 1.0
14.5 14.5 5.0 5.0 6.5
ns ns ns ns ns
th
5.0(*)
0.0
0.0
0.0
ns
ts
5.0(*)
3.5
3.5
3.5
ns
th
5.0(*) 5.0(*) 5.0(*) 80 240
2.0 2.0 80
2.0 2.0 80
2.0 2.0
ns ns MHz
tREM fMAX
(*) Voltage range is 5.0V 0.5V
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74ACT299
CAPACITIVE CHARACTERISTICS
Test Condition Symbol Parameter VCC (V) 5.0 5.0 5.0 fIN = 10MHz TA = 25C Min. Typ. 4 13 160 Max. 10 Value -40 to 85C Min. Max. 10 -55 to 125C Min. Max. 10 pF pF pF Unit
CIN CI/O CPD
Input Capacitance I/O Capacitance Power Dissipation Capacitance (note 1)
1) CPD is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x f IN + ICC/n (per circuit)
TEST CIRCUIT
TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ
CL = 50pF or equivalent (includes jig and probe capacitance) RL = R1 = 500 or equivalent RT = ZOUT of pulse generator (typically 50)
SWITCH Open 2VCC Open
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74ACT299
WAVEFORM 1: PROPAGATION DELAYS (f=1MHz; 50% duty cycle)
WAVEFORM 2: PROPAGATION DELAYS (f=1MHz; 50% duty cycle)
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74ACT299
WAVEFORM 3: PROPAGATION DELAYS (f=1MHz; 50% duty cycle)
WAVEFORM 4: PROPAGATION DELAYS (f=1MHz; 50% duty cycle)
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74ACT299
Plastic DIP-20 (0.25) MECHANICAL DATA
mm MIN. a1 B b b1 D E e e3 F I L Z 3.3 1.34 8.5 2.54 22.86 7.1 3.93 0.130 0.053 0.254 1.39 0.45 0.25 25.4 0.335 0.100 0.900 0.280 0.155 1.65 TYP. MAX. MIN. 0.010 0.055 0.018 0.010 1.000 0.065 inch TYP. MAX.
DIM.
P001J
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74ACT299
SO-20 MECHANICAL DATA
DIM. MIN. A a1 a2 b b1 C c1 D E e e3 F L M S 7.40 0.50 12.60 10.00 1.27 11.43 7.60 1.27 0.75 8 (max.) 0.291 0.19 13.00 10.65 0.35 0.23 0.50 45 (typ.) 0.496 0.393 0.050 0.450 0.299 0.050 0.029 0.512 0.419 0.10 mm TYP. MAX. 2.65 0.20 2.45 0.49 0.32 0.013 0.009 0.020 0.004 MIN. inch TYP. MAX. 0.104 0.007 0.096 0.019 0.012
P013L
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74ACT299
TSSOP20 MECHANICAL DATA
mm MIN. A A1 A2 b c D E E1 e K L 0o 0.50 0.05 0.85 0.19 0.09 6.4 6.25 4.3 6.5 6.4 4.4 0.65 BSC 4o 0.60 8o 0.70 0o 0.020 0.10 0.9 TYP. MAX. 1.1 0.15 0.95 0.30 0.2 6.6 6.5 4.48 0.002 0.335 0.0075 0.0035 0.252 0.246 0.169 0.256 0.252 0.173 0.0256 BSC 4o 0.024 8o 0.028 0.004 0.354 MIN. inch TYP. MAX. 0.433 0.006 0.374 0.0118 0.0079 0.260 0.256 0.176
DIM.
A
A2 A1 b e K c L E
D
E1
PIN 1 IDENTIFICATION
1
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74ACT299
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2001 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom (c) http://www.st.com
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