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IDT74SSTV16859 13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O
INDUSTRIAL TEMPERATURE RANGE
13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O
IDT74SSTV16859
FEATURES:
* * * * * *
2.3V to 2.7V Operation SSTL_2 Class II style data inputs/outputs Differential CLK input RESET control compatible with LVCMOS levels Latch-up performance exceeds 100mA ESD >2000V per MIL-STD-883, Method 3015; >200V using machine model (C = 200pF, R = 0) * Available in 56 pin VFQFPN and 64 pin TSSOP packages
APPLICATIONS:
The SSTV16859 is a 13-bit to 26-bit registered buffer designed for 2.3V2.7V VDD and supports low standby operation. All data inputs and outputs are SSTL_2 level compatible with JEDEC standard for SSTL_2. RESET is an LVCMOS input since it must operate predictably during the power-up phase. RESET, which can be operated independent of CLK and CLK, must be held in the low state during power-up in order to ensure predictable outputs (low state) before a stable clock has been applied. RESET, when in the low state, will disable all input receivers, reset all registers, and force all outputs to a low state, before a stable clock has been applied. With inputs held low and a stable clock applied, outputs will remain low during the Low-to-High transition of RESET.
DESCRIPTION:
* Ideally suited for DIMM DDR registered applications
FUNCTIONAL BLOCK DIAGRAM
RESET 51
CLK CLK
48 49
VREF D1
45 35 1D C1 R 32 Q1B
16
Q1A
TO 12 OTHER CHANNELS
INDUSTRIAL TEMPERATURE RANGE
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c 2003 Integrated Device Technology, Inc.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MARCH 2002
DSC-5947/8
IDT74SSTV16859 13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O
INDUSTRIAL TEMPERATURE RANGE
Q13A Q12A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VDDQ GND D13 D12 VDD VDDQ GND D11 D10 D9 GND D8 D7 RESET GND CLK CLK VDDQ VDD VREF D6 GND D5 D4 D3 GND VDDQ VDD D2 D1 GND VDDQ
PIN CONFIGURATIONS
VDDQ VDDQ VDDQ 56 Q8A GND Q10A Q12A Q11A Q13A VDD Q9A D13 D12 43 D11
Q11A Q10A Q9A VDDQ
Q7A 1 Q6A Q5A Q4A Q3A Q2A Q1A Q13B VDDQ Q12B Q11B Q10B Q9B Q8B 14
42 D10 D9 D8 D7 RESET GND
GND Q8A Q7A Q6A Q5A Q4A Q3A Q2A GND Q1A Q13B VDDQ Q12B
GND
CLK CLK VDDQ VDD VREF D6 D5 29 D4
Q7B 15
D3 28
Q11B Q10B Q9B Q8B Q7B Q6B GND VDDQ
D1
VDDQ
VDDQ
D2
VFQFPN TOP VIEW
ABSOLUTE MAXIMUM RATINGS (1)
Symbol VDD or VDDQ VI(2) VO(3) IIK IOK IO VDD TSTG Description Supply Voltage Range Input Voltage Range Output Voltage Range Input Clamp Current, VI < 0 Output Clamp Current, VO < 0 or VO > VDDQ Continuous Output Current, VO = 0 to VDDQ Continuous Current through each VDD, VDDQ or GND Storage Temperature Range -65 to +150 C
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. The input and output negative voltage ratings may be exceeded if the ratings of the I/P and O/P clamp current are observed. 3. The output current will flow if the following conditions are observed: a) Output in HIGH state b) VO = VDDQ
VDDQ
Q6B
Q3B
Q2B
Q1B
Q5B
Q4B
VDD
Q5B
Max. -0.5 to 3.6 -0.5 to VDD +0.5 -0.5 to VDDQ +0.5 -50 50 50 100
Unit V V V mA mA mA mA RESET H H H L
Q4B Q3B Q2B Q1B
TSSOP TOP VIEW
FUNCTION TABLE (1)
Input CLK L or H X CLK L or H X D L H X X Q Outputs L H Qo(2) L
NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care = LOW to HIGH = HIGH to LOW 2. Qo = Output level before the indicated steady-state conditions were established.
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IDT74SSTV16859 13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O
INDUSTRIAL TEMPERATURE RANGE
PIN DESCRIPTION
Pin Names Q1 - Q13 GND VDDQ VDD RESET VREF CLK CLK D1 - D13 Center PAD Description Data Output Ground Output-stage drain power voltage Logic power voltage Asynchronous reset input - resets registers and disables data and clock differential input recievers Input reference voltage Positive master clock input Negative master clock input Data Input - clocked in on the crossing of the rising edge of CLK and the falling edge of CLK Ground (MLF package only)
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = -40C to +85C, VDD = 2.5V 0.2V, VDDQ = 2.5V 0.2V
Symbol VIK VOH VOL II IDD All Inputs Static Standby Static Operating Dynamic Operating (Clock Only) IDDD Dynamic Operating (Per Each Data Input)(1) rOH rOL rO() CI Output HIGH Output LOW | rOH- rOL| each separate bit Data Inputs CLK and CLK RESET Parameter Control Inputs Test Conditions VDD = 2.3V, II= -18mA VDD = 2.3V to 2.7V, IOH = -100A VDD = 2.3V, IOH = -16mA VDD = 2.3V to 2.7V, IOL = 100A VDD = 2.3V, IOL = 16mA VDD = 2.7V,VI = VDD or GND IO = 0, VDD = 2.7V, RESET = GND IO = 0, VDD = 2.7V, RESET = VDD, VI = VIH (AC) or VIL (AC) IO = 0, VDD = 2.7V, RESET = VDD, VI = VIH (AC) or VIL (AC), CLK and CLK Switching 50% Duty Cycle. IO = 0, VDD = 2.7V, RESET = VDD, VI = VIH (AC) or VIL (AC), CLK and CLK Switching 50% Duty Cycle. One Data Input Switching at Half Clock Frequency, 50% Duty Cycle. VDD = 2.3V to 2.7V, IOH = -20mA VDD = 2.3V to 2.7V, IOH = 20mA VDD = 2.5V, TA = 25C, IOH = -20mA VDD = 2.5V, VI = VREF 310mV VICR = 1.25V, VI (PP) = 360mV VI = VDD or GND 7 7 -- 2 2 2 -- -- -- -- -- -- 20 20 4 3 3 3 pF -- 43 -- Min. -- VDD - 0.2 1.95 -- -- -- -- -- -- Typ. -- -- -- -- -- -- -- -- 6 Max. -1.2 -- -- 0.2 0.35 5 0.01 20 -- A/Clock MHz A/Clock MHz/Data Input A mA V Unit V V
NOTE: 1. Power dissipation levels will allow operation at DDR333 speeds without excessive die temperature.
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IDT74SSTV16859 13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O
INDUSTRIAL TEMPERATURE RANGE
OPERATING CHARACTERISTICS, TA = 25C (1)
Symbol VDD VDDQ VREF VTT VI VIH VIL VIH VIL VIH VIL VICR VI (PP) IOH IOL TA
NOTE: 1. The RESET input of the device must be held at VDD or GND to ensure proper device operation.
Parameter Supply Voltage Output Supply Voltage Reference Voltage (VREF= VDDQ/2) Termination Voltage Input Voltage AC High-Level Input Voltage AC Low-Level Input Voltage DC High-Level Input Voltage DC Low-Level Input Voltage High-Level Input Voltage Low-Level Input Voltage Common-Mode Input Range Peak-to-Peak Input Voltage High-Level Output Current Low-Level Output Current Operating Free-Air Temperature Data Inputs Data Inputs Data Inputs Data Inputs RESET RESET CLK, CLK CLK, CLK
Min. VDDQ 2.3 1.15 VREF- 40mV 0 VREF+ 310mV -- VREF+ 150mV -- 1.7 -- 0.97 360 -- -- - 40
Typ.(1) -- 2.5 1.25 VREF -- -- -- -- -- -- -- -- -- -- -- --
Max. 2.7 2.7 1.35 VREF+ 40mV VDD -- VREF- 310mV -- VREF- 150mV -- 0.7 1.53 -- - 20 20 +85
Unit V V V V V V V V V V V V mV mA C
TIMING REQUIREMENTS OVER RECOMMENDED OPERATING FREE-AIR TEMPERATURE RANGE
VDD = 2.5V 0.2V Symbol
CLOCK
Parameter Clock Frequency Pulse Duration, CLK, CLK HIGH or LOW Differential Inputs Active Time Setup Time, Fast Slew Rate Hold Time, Fast Slew Rate
(1)
Min. -- 2.5 -- -- Data Before CLK, CLK Data Before CLK, CLK 0.75 0.9 0.75 0.9
Max. 200 -- 22 22 -- -- -- --
Unit MHz ns ns ns ns ns ns ns
tw tACT tINACT tSU tN
Differential Inputs Inactive Time(2)
(3, 5)
Setup Time, Slow Slew Rate(4, 5)
(3,5)
Hold Time, Slow Slew Rate(2,5)
NOTES: 1. Data inputs must be low a minimum time of tACT max., after RESET is taken HIGH. 2. Data and clock inputs must be held at valid levels (not floating) a minimum time of tINACT max., after RESET is taken LOW. 3. For data signal input slew rate is 1V/ns. 4. For data signal input slew rate is 0.5V/ns and <1V/ns. 5. CLK, CLK signal input slew rates are 1V/ns.
SWITCHING CHARACTERISTICS OVER RECOMMENDED FREE-AIR OPERATING RANGE (UNLESS OTHERWISE NOTED)
VDD = 2.5V 0.2V Symbol fMAX tPD tPHL Parameter CLK and CLK to Q RESET to Q Min 200 1.1 -- Max. -- 2.8 5 Unit MHz ns ns
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IDT74SSTV16859 13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS (VDD = 2.5V 0.2V)
VTT RL = 50 From Output Under Test Test Point CL = 30 pF (see note 1)
Load Circuit
LVCMOS RESET Input tINACT IDD (see note 2) 10%
VDD VDD/2 VDD/2 tACT 90% 0V
Timing Input tPLH Output
VICR
VICR tPHL
VI(PP)
VOH VTT VTT VOL
Voltage and Current Waveforms Inputs Active and Inactive Times
Voltage Waveforms - Propagation Delay Times
LVCMOS RESET Input VIH VDD/2 VIL tPHL
tW VIH Input VREF VREF Output VIL VOH VTT VOL
Voltage Waveforms - Pulse Duration
Timing Input tSU Input VREF
Voltage Waveforms - Propagation Delay Times
VICR
VI(PP)
tN VIH VREF VIL
Voltage Waveforms - Setup and Hold Times
NOTES: 1. CL includes probe and jig capacitance. 2. IDD tested with clock and data inputs held at VDD or GND, and IO = 0mA. 3. All input pulses are supplied by generators having the following characteristics: PRR 10MHz, ZO = 50, input slew rate = 1 V/ns 20% (unless otherwise specified). 4. The outputs are measured one at a time with one transition per measurement. 5. VTT = VREF = VDDQ/2 6. VIH = VREF + 310mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS input. 7. VIL = VREF - 310mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input. 8. tPLH and tPHL are the same as tPD.
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IDT74SSTV16859 13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT XX XX SSTV Family Temp. Range XXX XX Device Type Package
PA NL 859
Thin Shrink Small Outline Package Thermally Enhanced Plastic Very Fine Pitch Quad Flat No Lead Package 13-Bit to 26-Bit Registered Buffer with SSTL I/O
16 74
Double-Density -40C to +85C
CORPORATE HEADQUARTERS San Jose, CA 95138
for SALES: fax: 408-284-2775 www.idt.com
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