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MX66C1024
5V Low Power CMOS SRAM 128 x 8 Bit
n FEATURES
* Vcc operation voltage : 5V * Low power consumption : 45mA (Max.) write current 2mA (Max.) read current 0.6uA (Typ.) CMOS standby current * High speed access time : -70 70ns (Max.) -10 100ns (Max.) * Input levels are CMOS-compatible * Automatic power down when chip is deselected * Three state outputs * Fully static operation * Data retention supply voltage as low as 1.2V * Easy expansion with CE2, CE1, and OE options
n DESCRIPTION
The MX66C1024 is a high performance, extremely low power CMOS Static Random Access Memory organized as 131,072 words by 8 bits and operates at 5.0V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 0.005uA and maximum access time of 70ns and 100ns Easy memory expansion is provided by an active LOW chip enable (CE1), an active HIGH chip enable (CE2), and active LOW output enable (OE) and three-state output drivers. The MX66C1024 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The MX66C1024 is available in the JEDEC standard 32 pin SOP, STSOP and TSOP.
n PIN CONFIGURATIONS
NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND
n BLOCK DIAGRAM
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 DQ7 DQ6 DQ5 DQ4 DQ3
*
1 2 3 4 5 6 7 8 MX66C1024MC 9 MX66C1024MI 10 11 12 13 14 15 16
A6 A7 A12 A14 A16 A15 A13 A8 A9 A11
Address Input Buffer
20
Row Decoder
1024
Memory Array 1024 x 1024
1024 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 8 Data Input Buffer 8 Column I/O Write Driver Sense Amp 8 128 Column Decoder 14 Control Address Input Buffer
*
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 MX66C1024TC MX66C1024SC MX66C1024TI MX66C1024SI
A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
OE A10 CE1 DQ7 DQ6 DQ5 DQ4 DQ3 GND DQ2 DQ1 DQ0 A0 A1 A2 A3
8
Data Output Buffer
CE2 CE1 WE OE Vdd Gnd
A5 A4 A3 A2 A1 A0 A10
P/N DS00040
1
Rev. 1.0, November 1999
Macronix America Inc., USA 1338 Ridder Park Dr., San Jose, CA 95131 Tel (408)453-8088 Fax (408)451-0876 http: www.macronix.com
MX66C1024
n PIN DESCRIPTIONS
Name
A0-A16 Address Input CE1 Chip Enable 1 Input CE2 Chip Enable 2 Input
Function
These 17 address input select one of the 131,072 x 8-bit words in the RAM
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active to read from or write to the device. If either chip enable is not active, the device is deselected and is in a standby power mode. The DQ pins will be in the high impedance state when the device is deselected.
WE Write Enable Input
The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
DQ0 - DQ7 Data Input/Output Ports Vcc Gnd
These 8 bi-directional ports are used to read data from or write data into the RAM.
Power Supply Ground
n TRUTH TABLE
MODE Not selected (Power Down) Output Disabled Read Write WE X X H H L CE1 H X L L L CE2 X L H H H OE X X H L X I/O OPERATION High Z High Z DOUT DIN Vcc CURRENT ICCSB, ICCSB1 ICC ICC ICC
n ABSOLUTE MAXIMUM RATINGS(1)
SYMBOL VTERM TBIAS TSTG PT IOUT PARAMETER
Terminal Voltage Respect to GND with
n OPERATING RANGE
UNITS
V
O
RATING
-0.5 to +7.0 -40 to +125 -60 to +150 1.0 20
RANGE
Commercial Industrial
AMBIENT TEMPERATURE
0 C to +70 C -40 C to +70 C
O O O O
Temperature Under Bias Storage Temperature Power Dissipation DC Output Current
C C
O
W mA
n CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)
SYMBOL PARAMETER Input Capacitance Input/Output Capacitance CONDITIONS MAX. UNIT
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. P/N DS00040
CIN CDQ
VIN=0V VI/O=0V
6 8
pF pF
1. This parameter is guaranteed and not tested.
2
Rev. 1.0, November 1999
Macronix America Inc., USA 1338 Ridder Park Dr., San Jose, CA 95131 Tel (408)453-8088 Fax (408)451-0876 http: www.macronix.com
MX66C1024
n DC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC )
PARAMETER NAME
VIL VIH IIL IOL VOL VOH ICC ICCSB ICCSB1
PARAMETER
Guaranteed Input Low (2) Voltage Guaranteed Input High (2) Voltage Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Operating Power Supply Current Standby Power Supply Current Power Down Current Supply
TEST CONDITIONS
MIN. TYP. (1) MAX.
-0.5 2.2 --------0.6 0.8 Vcc+0.5 1 1 0.4 -45 2 3
UNITS V V uA uA V V mA mA uA
Vcc = Max, VIN = 0V to Vcc Vcc = Max, CE1= VIH, CE2= VIL, or OE = VIH, VI/O = 0V to Vcc Vcc = Max, IOL = 1mA Vcc = Min, IOH = -0.5mA CE1 = V , or CE2 = V , Vcc = 5.0 V (3) IDQ = 0mA, F = Fmax CE1 = VIH, or CE2 = VIL, Vcc = 5.0 V (3) IDQ = 0mA, F = Fmax > CE1 = Vcc-0.2V, CE2 < 0.2V, = VIN > Vcc-0.2V or VIN < 0.2V = =
IL IH
---2.4 ----
1. Typical characteristics are at TA = 25oC. 2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 3. Fmax = 1/tRC .
n DATA RETENTION CHARACTERISTICS ( TA = 0 to + 70oC )
SYMBOL
VDR
PARAMETER
Vcc for Data Retention
TEST CONDITIONS
CE1 > Vcc - 0.2V, CE2 < 0.2V, = = VIN > Vcc - 0.2V or VIN< 0.2V = = CE1 > Vcc - 0.2V, CE2 < 0.2V, = = VIN > Vcc - 0.2V or VIN < 0.2V = = See Retention Waveform
MIN. TYP. (1) MAX.
1.2 ---
UNITS
V
ICCDR tCDR tR
Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time 25OC
-0 TRC
(2)
0.005 ---
0.2 ---
uA ns ns
1. Vcc = 1.5V, TA = + 2. tRC = Read Cycle Time
n LOW VCC DATA RETENTION WAVEFORM (1)
Vcc
( CE1 Controlled )
Data Retention Mode
Vcc
VDR 1.2V
Vcc
t CDR
VIH
tR
CE Vcc - 0.2V
VIH
CE
n LOW VCC DATA RETENTION WAVEFORM (2)
Vcc
Vcc
( CE2 Controlled )
Data Retention Mode VDR 1.2V
Vcc
t CDR
VIH
tR
CE2 0.2V
VIH
CE2
P/N DS00040
3
Rev. 1.0, November 1999
Macronix America Inc., USA 1338 Ridder Park Dr., San Jose, CA 95131 Tel (408)453-8088 Fax (408)451-0876 http: www.macronix.com
MX66C1024
n AC TEST CONDITIONS
Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Vcc/0V 5ns 0.5Vcc
n KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS MUST BE STEADY MAY CHANGE FROM H TO L
1000
OUTPUTS MUST BE STEADY WILL BE CHANGE FROM H TO L WILL BE CHANGE FROM L TO H CHANGE : STATE UNKNOWN CENTER LINE IS HIGH IMPEDANCE "OFF "STATE
n AC TEST LOADS AND WAVEFORMS
1000
5.0V OUTPUT
100PF
INCLUDING JIG AND SCOPE
5.0V OUTPUT
5PF 1500
INCLUDING JIG AND SCOPE
MAY CHANGE FROM L TO H DON T CARE: ANY CHANGE PERMITTED DOES NOT APPLY
,
1500
FIGURE 1A
THEVENIN EQUIVALENT 600
FIGURE 1B
OUTPUT
ALL INPUT PULSES
0.9V
Vcc GND
10%
90% 90%
10%
5ns
FIGURE 2
n AC ELECTRICAL CHARACTERISTICS (over the operating range)
READ CYCLE
JEDEC PARAMETER NAME PARAMETER NAME DESCRIPTION
Read Cycle Time Address Access Time Chip Select Access Time Chip Select Access Time Output Enable to Output Valid Chip Select to Output Low Z Chip Select to Output Low Z Output Enable to Output in Low Z Chip Deselect to Output in High Z Chip Deselect to Output in High Z Output Disable to Output in High Z Output Disable to Output Address Change (CE1) (CE2) (CE1) (CE2) (CE1) (CE2)
MX66C1024-70 MIN. TYP. MAX. 70 ----10 10 10 0 0 0 10 ------------70 70 70 50 ---40 40 35 --
MX66C1024-10 MIN. TYP. MAX. 100 ----10 10 10 0 0 0 10 ------------100 100 100 50 ---40 40 35 --
UNIT ns ns ns ns ns ns ns ns ns ns ns ns
tAVAX tAVQV tE1LQV tE2HOV tGLQV tE1LQX tE2HOX tGLQX tE1HQZ tE2HQZ tGHQZ tAXOX
tRC tAA tACS1 tACS2 tOE tCLZ1 tCLZ2 tOLZ tCHZ1 tCHZ1 tOHZ tOH
1. Typical characteristics are at Vcc = 5V, TA = 25oC.
P/N DS00040
4
Rev. 1.0, November 1999
Macronix America Inc., USA 1338 Ridder Park Dr., San Jose, CA 95131 Tel (408)453-8088 Fax (408)451-0876 http: www.macronix.com
MX66C1024
n SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1
(1,2,4)
t ADDRESS
RC
t t
D OUT
OH
AA
t OH
READ CYCLE2
CE1
(1,3,4)
t
CE2
(5)
ACS1
t t
CLZ
ACS2
t
(5)
CHZ
D OUT
READ CYCLE3
(1,4)
t ADDRESS
RC
t
OE
AA
t
CE1
(5)
t
OE
OH
t t t
CLZ1
OLZ
ACS1
t OHZ (5) (1,5) t CHZ
CE2
t
(5)
ACS2
t
(2,5)
CHZ
t
D OUT
CLZ2
NOTES: 1. WE is high for read Cycle. 2. Device is continuously selected when CE1 = VIL and CE2= VIH. 3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high. 4. OE = VIL .
5. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested.
P/N DS00040
5
Rev. 1.0, November 1999
Macronix America Inc., USA 1338 Ridder Park Dr., San Jose, CA 95131 Tel (408)453-8088 Fax (408)451-0876 http: www.macronix.com
MX66C1024
n AC ELECTRICAL CHARACTERISTICS (over the operating range)
WRITE CYCLE
JEDEC PARAMETER NAME PARAMETER NAME DESCRIPTION MX66C1024-70 MIN. TYP. MAX. 70 -------------------30 --30 -MX66C1024-10 MIN. TYP. MAX. 100 100 0 10 50 ---30 0 0 5 -------------------30 --30 -UNIT ns ns ns ns ns ns ns ns ns ns ns ns
t tE1LWH tAVWL tAVWH tWLWH tWHAX tE2LAX tWLOZ tDVWH tWHDX tGHOZ tWHQX tCW tAS tAW tWP tWR1 tWR2 tWHZ tDW tDH tOHZ tOW
Chip Select to End of Write Address Set up Time Address Valid to End of Write Write Pulse Width Write Recovery Time Write Recovery Time Write to Output in High Z Data to Write Time Overlap Data Hold from Write Time Output Disable to Output in High Z End of Write to Output Active (CE1, WE) (CE2)
70 0 70 50 0 0 -30 0 0 5
1. Typical characteristics are at Vcc = 5V, TA = 25oC.
n SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1
ADDRESS
(1)
t
WC
t
OE
(3) WR1
(5)
t
(11) CW
CE1
CE2
(5)
(11)
t
t
AW
CW
t
WR2
(3)
WE
t AS
(4,10)
t
WP (2)
t OHZ
D OUT
t
t
DW
DH
D IN P/N DS00040
6
Rev. 1.0, November 1999
Macronix America Inc., USA 1338 Ridder Park Dr., San Jose, CA 95131 Tel (408)453-8088 Fax (408)451-0876 http: www.macronix.com
MX66C1024
WRITE CYCLE2 (1,6)
t ADDRESS
(11) (5) WC
t
CW
CE1
CE2
(5)
(11)
t CW t
WE t AS
(4,10) AW
t
(2)
WR2
t WP
(3)
t
DH
t D OUT
WHZ
(7)
(8)
t DW t
DH (8)
D IN
NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. TWR is measured from the earlier of CE1 or WE going high or CE2 going low at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = VIL ).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address. 9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. 11. TCW is measured from the later of CE1 going low or CE2 going high to the end of write.
P/N DS00040
7
Rev. 1.0, November 1999
Macronix America Inc., USA 1338 Ridder Park Dr., San Jose, CA 95131 Tel (408)453-8088 Fax (408)451-0876 http: www.macronix.com
MX66C1024
n
SPEED (ns)
70 100 70 100 70 100 70 100 70 100 70 100
ORDERING PART NUMBER
MX66C1024MC - 70 MX66C1024MC - 10 MX66C1024MI - 70 MX66C1024MI - 10 MX66C1024TC - 70 MX66C1024TC - 10 MX66C1024TI- 70 MX66C1024TI- 10 MX66C1024SC- 70 MX66C1024SC- 10 MX66C1024SI- 70 MX66C1024SI- 10
PACKAGE
SOP - 32 PIN SOP - 32 PIN SOP - 32 PIN SOP - 32 PIN TSOP - 32 PIN TSOP - 32 PIN TSOP - 32 PIN TSOP - 32 PIN STSOP - 32 PIN STSOP - 32 PIN STSOP - 32 PIN STSOP - 32 PIN
TEMPERATURE RANGE
0O C to + 70O C 0O C to + 70O C -40O C to + 85O C -40O C to + 85O C 0O C to + 70O C 0O C to + 70O C -40O C to + 85O C -40O C to + 85O C 0O C to + 70O C 0O C to + 70O C -40O C to + 85O C -40O C to + 85O C
n PACKAGE DIMENSIONS
P/N DS00040
8
Rev. 1.0, November 1999
Macronix America Inc., USA 1338 Ridder Park Dr., San Jose, CA 95131 Tel (408)453-8088 Fax (408)451-0876 http: www. .com
MX66C1024
n PACKAGE DIMENSIONS (continued)
P/N DS00040
9
Rev. 1.0, November 1999
Macronix America Inc., USA 1338 Ridder Park Dr., San Jose, CA 95131 Tel (408)453-8088 Fax (408)451-0876 http: www.macronix.com
This page is left blank intentionally.
P/N DS00040 Macronix America Inc., USA 1338 Ridder Park Dr., San Jose, CA 95131 Tel (408)453-8088 Fax (408)451-0876 http: www. .com
Rev. 1.0, November 1999

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